xref: /linux/drivers/media/dvb-frontends/drxd_firm.c (revision df7686101956929dcea410971656e34926773b88)
1 /*
2  * drxd_firm.c : DRXD firmware tables
3  *
4  * Copyright (C) 2006-2007 Micronas
5  *
6  * This program is free software; you can redistribute it and/or
7  * modify it under the terms of the GNU General Public License
8  * version 2 only, as published by the Free Software Foundation.
9  *
10  *
11  * This program is distributed in the hope that it will be useful,
12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
14  * GNU General Public License for more details.
15  *
16  * To obtain the license, point your browser to
17  * http://www.gnu.org/copyleft/gpl.html
18  */
19 
20 /* TODO: generate this file with a script from a settings file */
21 
22 /* Contains A2 firmware version: 1.4.2
23  * Contains B1 firmware version: 3.3.33
24  * Contains settings from driver 1.4.23
25 */
26 
27 #include "drxd_firm.h"
28 
29 #define ADDRESS(x)     ((x) & 0xFF), (((x)>>8) & 0xFF), (((x)>>16) & 0xFF), (((x)>>24) & 0xFF)
30 #define LENGTH(x)      ((x) & 0xFF), (((x)>>8) & 0xFF)
31 
32 /* Is written via block write, must be little endian */
33 #define DATA16(x)      ((x) & 0xFF), (((x)>>8) & 0xFF)
34 
35 #define WRBLOCK(a, l) ADDRESS(a), LENGTH(l)
36 #define WR16(a, d) ADDRESS(a), LENGTH(1), DATA16(d)
37 
38 #define END_OF_TABLE      0xFF, 0xFF, 0xFF, 0xFF
39 
40 /* HI firmware patches */
41 
42 #define HI_TR_FUNC_ADDR HI_IF_RAM_USR_BEGIN__A
43 #define HI_TR_FUNC_SIZE 9	/* size of this function in instruction words */
44 
45 u8 DRXD_InitAtomicRead[] = {
46 	WRBLOCK(HI_TR_FUNC_ADDR, HI_TR_FUNC_SIZE),
47 	0x26, 0x00,		/* 0         -> ring.rdy;           */
48 	0x60, 0x04,		/* r0rami.dt -> ring.xba;           */
49 	0x61, 0x04,		/* r0rami.dt -> ring.xad;           */
50 	0xE3, 0x07,		/* HI_RA_RAM_USR_BEGIN -> ring.iad; */
51 	0x40, 0x00,		/* (long immediate)                 */
52 	0x64, 0x04,		/* r0rami.dt -> ring.len;           */
53 	0x65, 0x04,		/* r0rami.dt -> ring.ctl;           */
54 	0x26, 0x00,		/* 0         -> ring.rdy;           */
55 	0x38, 0x00,		/* 0         -> jumps.ad;           */
56 	END_OF_TABLE
57 };
58 
59 /* Pins D0 and D1 of the parallel MPEG output can be used
60    to set the I2C address of a device. */
61 
62 #define HI_RST_FUNC_ADDR (HI_IF_RAM_USR_BEGIN__A + HI_TR_FUNC_SIZE)
63 #define HI_RST_FUNC_SIZE 54	/* size of this function in instruction words */
64 
65 /* D0 Version */
66 u8 DRXD_HiI2cPatch_1[] = {
67 	WRBLOCK(HI_RST_FUNC_ADDR, HI_RST_FUNC_SIZE),
68 	0xC8, 0x07, 0x01, 0x00,	/* MASK      -> reg0.dt;                        */
69 	0xE0, 0x07, 0x15, 0x02,	/* (EC__BLK << 6) + EC_OC_REG__BNK -> ring.xba; */
70 	0xE1, 0x07, 0x12, 0x00,	/* EC_OC_REG_OC_MPG_SIO__A -> ring.xad;         */
71 	0xA2, 0x00,		/* M_BNK_ID_DAT -> ring.iba;                    */
72 	0x23, 0x00,		/* &data     -> ring.iad;                       */
73 	0x24, 0x00,		/* 0         -> ring.len;                       */
74 	0xA5, 0x02,		/* M_RC_CTR_SWAP | M_RC_CTR_READ -> ring.ctl;   */
75 	0x26, 0x00,		/* 0         -> ring.rdy;                       */
76 	0x42, 0x00,		/* &data+1   -> w0ram.ad;                       */
77 	0xC0, 0x07, 0xFF, 0x0F,	/* -1        -> w0ram.dt;                       */
78 	0x63, 0x00,		/* &data+1   -> ring.iad;                       */
79 	0x65, 0x02,		/* M_RC_CTR_SWAP | M_RC_CTR_WRITE -> ring.ctl;  */
80 	0x26, 0x00,		/* 0         -> ring.rdy;                       */
81 	0xE1, 0x07, 0x38, 0x00,	/* EC_OC_REG_OCR_MPG_USR_DAT__A -> ring.xad;    */
82 	0xA5, 0x02,		/* M_RC_CTR_SWAP | M_RC_CTR_READ -> ring.ctl;   */
83 	0x26, 0x00,		/* 0         -> ring.rdy;                       */
84 	0xE1, 0x07, 0x12, 0x00,	/* EC_OC_REG_OC_MPG_SIO__A -> ring.xad;         */
85 	0x23, 0x00,		/* &data     -> ring.iad;                       */
86 	0x65, 0x02,		/* M_RC_CTR_SWAP | M_RC_CTR_WRITE -> ring.ctl;  */
87 	0x26, 0x00,		/* 0         -> ring.rdy;                       */
88 	0x42, 0x00,		/* &data+1   -> w0ram.ad;                       */
89 	0x0F, 0x04,		/* r0ram.dt  -> and.op;                         */
90 	0x1C, 0x06,		/* reg0.dt   -> and.tr;                         */
91 	0xCF, 0x04,		/* and.rs    -> add.op;                         */
92 	0xD0, 0x07, 0x70, 0x00,	/* DEF_DEV_ID -> add.tr;                        */
93 	0xD0, 0x04,		/* add.rs    -> add.tr;                         */
94 	0xC8, 0x04,		/* add.rs    -> reg0.dt;                        */
95 	0x60, 0x00,		/* reg0.dt   -> w0ram.dt;                       */
96 	0xC2, 0x07, 0x10, 0x00,	/* SLV0_BASE -> w0rami.ad;                      */
97 	0x01, 0x00,		/* 0         -> w0rami.dt;                      */
98 	0x01, 0x06,		/* reg0.dt   -> w0rami.dt;                      */
99 	0xC2, 0x07, 0x20, 0x00,	/* SLV1_BASE -> w0rami.ad;                      */
100 	0x01, 0x00,		/* 0         -> w0rami.dt;                      */
101 	0x01, 0x06,		/* reg0.dt   -> w0rami.dt;                      */
102 	0xC2, 0x07, 0x30, 0x00,	/* CMD_BASE  -> w0rami.ad;                      */
103 	0x01, 0x00,		/* 0         -> w0rami.dt;                      */
104 	0x01, 0x00,		/* 0         -> w0rami.dt;                      */
105 	0x01, 0x00,		/* 0         -> w0rami.dt;                      */
106 	0x68, 0x00,		/* M_IC_SEL_PT1 -> i2c.sel;                     */
107 	0x29, 0x00,		/* M_IC_CMD_RESET -> i2c.cmd;                   */
108 	0x28, 0x00,		/* M_IC_SEL_PT0 -> i2c.sel;                     */
109 	0x29, 0x00,		/* M_IC_CMD_RESET -> i2c.cmd;                   */
110 	0xF8, 0x07, 0x2F, 0x00,	/* 0x2F      -> jumps.ad;                       */
111 
112 	WR16((B_HI_IF_RAM_TRP_BPT0__AX + ((2 * 0) + 1)),
113 	     (u16) (HI_RST_FUNC_ADDR & 0x3FF)),
114 	WR16((B_HI_IF_RAM_TRP_BPT0__AX + ((2 * 1) + 1)),
115 	     (u16) (HI_RST_FUNC_ADDR & 0x3FF)),
116 	WR16((B_HI_IF_RAM_TRP_BPT0__AX + ((2 * 2) + 1)),
117 	     (u16) (HI_RST_FUNC_ADDR & 0x3FF)),
118 	WR16((B_HI_IF_RAM_TRP_BPT0__AX + ((2 * 3) + 1)),
119 	     (u16) (HI_RST_FUNC_ADDR & 0x3FF)),
120 
121 	/* Force quick and dirty reset */
122 	WR16(B_HI_CT_REG_COMM_STATE__A, 0),
123 	END_OF_TABLE
124 };
125 
126 /* D0,D1 Version */
127 u8 DRXD_HiI2cPatch_3[] = {
128 	WRBLOCK(HI_RST_FUNC_ADDR, HI_RST_FUNC_SIZE),
129 	0xC8, 0x07, 0x03, 0x00,	/* MASK      -> reg0.dt;                        */
130 	0xE0, 0x07, 0x15, 0x02,	/* (EC__BLK << 6) + EC_OC_REG__BNK -> ring.xba; */
131 	0xE1, 0x07, 0x12, 0x00,	/* EC_OC_REG_OC_MPG_SIO__A -> ring.xad;         */
132 	0xA2, 0x00,		/* M_BNK_ID_DAT -> ring.iba;                    */
133 	0x23, 0x00,		/* &data     -> ring.iad;                       */
134 	0x24, 0x00,		/* 0         -> ring.len;                       */
135 	0xA5, 0x02,		/* M_RC_CTR_SWAP | M_RC_CTR_READ -> ring.ctl;   */
136 	0x26, 0x00,		/* 0         -> ring.rdy;                       */
137 	0x42, 0x00,		/* &data+1   -> w0ram.ad;                       */
138 	0xC0, 0x07, 0xFF, 0x0F,	/* -1        -> w0ram.dt;                       */
139 	0x63, 0x00,		/* &data+1   -> ring.iad;                       */
140 	0x65, 0x02,		/* M_RC_CTR_SWAP | M_RC_CTR_WRITE -> ring.ctl;  */
141 	0x26, 0x00,		/* 0         -> ring.rdy;                       */
142 	0xE1, 0x07, 0x38, 0x00,	/* EC_OC_REG_OCR_MPG_USR_DAT__A -> ring.xad;    */
143 	0xA5, 0x02,		/* M_RC_CTR_SWAP | M_RC_CTR_READ -> ring.ctl;   */
144 	0x26, 0x00,		/* 0         -> ring.rdy;                       */
145 	0xE1, 0x07, 0x12, 0x00,	/* EC_OC_REG_OC_MPG_SIO__A -> ring.xad;         */
146 	0x23, 0x00,		/* &data     -> ring.iad;                       */
147 	0x65, 0x02,		/* M_RC_CTR_SWAP | M_RC_CTR_WRITE -> ring.ctl;  */
148 	0x26, 0x00,		/* 0         -> ring.rdy;                       */
149 	0x42, 0x00,		/* &data+1   -> w0ram.ad;                       */
150 	0x0F, 0x04,		/* r0ram.dt  -> and.op;                         */
151 	0x1C, 0x06,		/* reg0.dt   -> and.tr;                         */
152 	0xCF, 0x04,		/* and.rs    -> add.op;                         */
153 	0xD0, 0x07, 0x70, 0x00,	/* DEF_DEV_ID -> add.tr;                        */
154 	0xD0, 0x04,		/* add.rs    -> add.tr;                         */
155 	0xC8, 0x04,		/* add.rs    -> reg0.dt;                        */
156 	0x60, 0x00,		/* reg0.dt   -> w0ram.dt;                       */
157 	0xC2, 0x07, 0x10, 0x00,	/* SLV0_BASE -> w0rami.ad;                      */
158 	0x01, 0x00,		/* 0         -> w0rami.dt;                      */
159 	0x01, 0x06,		/* reg0.dt   -> w0rami.dt;                      */
160 	0xC2, 0x07, 0x20, 0x00,	/* SLV1_BASE -> w0rami.ad;                      */
161 	0x01, 0x00,		/* 0         -> w0rami.dt;                      */
162 	0x01, 0x06,		/* reg0.dt   -> w0rami.dt;                      */
163 	0xC2, 0x07, 0x30, 0x00,	/* CMD_BASE  -> w0rami.ad;                      */
164 	0x01, 0x00,		/* 0         -> w0rami.dt;                      */
165 	0x01, 0x00,		/* 0         -> w0rami.dt;                      */
166 	0x01, 0x00,		/* 0         -> w0rami.dt;                      */
167 	0x68, 0x00,		/* M_IC_SEL_PT1 -> i2c.sel;                     */
168 	0x29, 0x00,		/* M_IC_CMD_RESET -> i2c.cmd;                   */
169 	0x28, 0x00,		/* M_IC_SEL_PT0 -> i2c.sel;                     */
170 	0x29, 0x00,		/* M_IC_CMD_RESET -> i2c.cmd;                   */
171 	0xF8, 0x07, 0x2F, 0x00,	/* 0x2F      -> jumps.ad;                       */
172 
173 	WR16((B_HI_IF_RAM_TRP_BPT0__AX + ((2 * 0) + 1)),
174 	     (u16) (HI_RST_FUNC_ADDR & 0x3FF)),
175 	WR16((B_HI_IF_RAM_TRP_BPT0__AX + ((2 * 1) + 1)),
176 	     (u16) (HI_RST_FUNC_ADDR & 0x3FF)),
177 	WR16((B_HI_IF_RAM_TRP_BPT0__AX + ((2 * 2) + 1)),
178 	     (u16) (HI_RST_FUNC_ADDR & 0x3FF)),
179 	WR16((B_HI_IF_RAM_TRP_BPT0__AX + ((2 * 3) + 1)),
180 	     (u16) (HI_RST_FUNC_ADDR & 0x3FF)),
181 
182 	/* Force quick and dirty reset */
183 	WR16(B_HI_CT_REG_COMM_STATE__A, 0),
184 	END_OF_TABLE
185 };
186 
187 u8 DRXD_ResetCEFR[] = {
188 	WRBLOCK(CE_REG_FR_TREAL00__A, 57),
189 	0x52, 0x00,		/* CE_REG_FR_TREAL00__A */
190 	0x00, 0x00,		/* CE_REG_FR_TIMAG00__A */
191 	0x52, 0x00,		/* CE_REG_FR_TREAL01__A */
192 	0x00, 0x00,		/* CE_REG_FR_TIMAG01__A */
193 	0x52, 0x00,		/* CE_REG_FR_TREAL02__A */
194 	0x00, 0x00,		/* CE_REG_FR_TIMAG02__A */
195 	0x52, 0x00,		/* CE_REG_FR_TREAL03__A */
196 	0x00, 0x00,		/* CE_REG_FR_TIMAG03__A */
197 	0x52, 0x00,		/* CE_REG_FR_TREAL04__A */
198 	0x00, 0x00,		/* CE_REG_FR_TIMAG04__A */
199 	0x52, 0x00,		/* CE_REG_FR_TREAL05__A */
200 	0x00, 0x00,		/* CE_REG_FR_TIMAG05__A */
201 	0x52, 0x00,		/* CE_REG_FR_TREAL06__A */
202 	0x00, 0x00,		/* CE_REG_FR_TIMAG06__A */
203 	0x52, 0x00,		/* CE_REG_FR_TREAL07__A */
204 	0x00, 0x00,		/* CE_REG_FR_TIMAG07__A */
205 	0x52, 0x00,		/* CE_REG_FR_TREAL08__A */
206 	0x00, 0x00,		/* CE_REG_FR_TIMAG08__A */
207 	0x52, 0x00,		/* CE_REG_FR_TREAL09__A */
208 	0x00, 0x00,		/* CE_REG_FR_TIMAG09__A */
209 	0x52, 0x00,		/* CE_REG_FR_TREAL10__A */
210 	0x00, 0x00,		/* CE_REG_FR_TIMAG10__A */
211 	0x52, 0x00,		/* CE_REG_FR_TREAL11__A */
212 	0x00, 0x00,		/* CE_REG_FR_TIMAG11__A */
213 
214 	0x52, 0x00,		/* CE_REG_FR_MID_TAP__A */
215 
216 	0x0B, 0x00,		/* CE_REG_FR_SQS_G00__A */
217 	0x0B, 0x00,		/* CE_REG_FR_SQS_G01__A */
218 	0x0B, 0x00,		/* CE_REG_FR_SQS_G02__A */
219 	0x0B, 0x00,		/* CE_REG_FR_SQS_G03__A */
220 	0x0B, 0x00,		/* CE_REG_FR_SQS_G04__A */
221 	0x0B, 0x00,		/* CE_REG_FR_SQS_G05__A */
222 	0x0B, 0x00,		/* CE_REG_FR_SQS_G06__A */
223 	0x0B, 0x00,		/* CE_REG_FR_SQS_G07__A */
224 	0x0B, 0x00,		/* CE_REG_FR_SQS_G08__A */
225 	0x0B, 0x00,		/* CE_REG_FR_SQS_G09__A */
226 	0x0B, 0x00,		/* CE_REG_FR_SQS_G10__A */
227 	0x0B, 0x00,		/* CE_REG_FR_SQS_G11__A */
228 	0x0B, 0x00,		/* CE_REG_FR_SQS_G12__A */
229 
230 	0xFF, 0x01,		/* CE_REG_FR_RIO_G00__A */
231 	0x90, 0x01,		/* CE_REG_FR_RIO_G01__A */
232 	0x0B, 0x01,		/* CE_REG_FR_RIO_G02__A */
233 	0xC8, 0x00,		/* CE_REG_FR_RIO_G03__A */
234 	0xA0, 0x00,		/* CE_REG_FR_RIO_G04__A */
235 	0x85, 0x00,		/* CE_REG_FR_RIO_G05__A */
236 	0x72, 0x00,		/* CE_REG_FR_RIO_G06__A */
237 	0x64, 0x00,		/* CE_REG_FR_RIO_G07__A */
238 	0x59, 0x00,		/* CE_REG_FR_RIO_G08__A */
239 	0x50, 0x00,		/* CE_REG_FR_RIO_G09__A */
240 	0x49, 0x00,		/* CE_REG_FR_RIO_G10__A */
241 
242 	0x10, 0x00,		/* CE_REG_FR_MODE__A     */
243 	0x78, 0x00,		/* CE_REG_FR_SQS_TRH__A  */
244 	0x00, 0x00,		/* CE_REG_FR_RIO_GAIN__A */
245 	0x00, 0x02,		/* CE_REG_FR_BYPASS__A   */
246 	0x0D, 0x00,		/* CE_REG_FR_PM_SET__A   */
247 	0x07, 0x00,		/* CE_REG_FR_ERR_SH__A   */
248 	0x04, 0x00,		/* CE_REG_FR_MAN_SH__A   */
249 	0x06, 0x00,		/* CE_REG_FR_TAP_SH__A   */
250 
251 	END_OF_TABLE
252 };
253 
254 u8 DRXD_InitFEA2_1[] = {
255 	WRBLOCK(FE_AD_REG_PD__A, 3),
256 	0x00, 0x00,		/* FE_AD_REG_PD__A          */
257 	0x01, 0x00,		/* FE_AD_REG_INVEXT__A      */
258 	0x00, 0x00,		/* FE_AD_REG_CLKNEG__A      */
259 
260 	WRBLOCK(FE_AG_REG_DCE_AUR_CNT__A, 2),
261 	0x10, 0x00,		/* FE_AG_REG_DCE_AUR_CNT__A */
262 	0x10, 0x00,		/* FE_AG_REG_DCE_RUR_CNT__A */
263 
264 	WRBLOCK(FE_AG_REG_ACE_AUR_CNT__A, 2),
265 	0x0E, 0x00,		/* FE_AG_REG_ACE_AUR_CNT__A */
266 	0x00, 0x00,		/* FE_AG_REG_ACE_RUR_CNT__A */
267 
268 	WRBLOCK(FE_AG_REG_EGC_FLA_RGN__A, 5),
269 	0x04, 0x00,		/* FE_AG_REG_EGC_FLA_RGN__A */
270 	0x1F, 0x00,		/* FE_AG_REG_EGC_SLO_RGN__A */
271 	0x00, 0x00,		/* FE_AG_REG_EGC_JMP_PSN__A */
272 	0x00, 0x00,		/* FE_AG_REG_EGC_FLA_INC__A */
273 	0x00, 0x00,		/* FE_AG_REG_EGC_FLA_DEC__A */
274 
275 	WRBLOCK(FE_AG_REG_GC1_AGC_MAX__A, 2),
276 	0xFF, 0x01,		/* FE_AG_REG_GC1_AGC_MAX__A */
277 	0x00, 0xFE,		/* FE_AG_REG_GC1_AGC_MIN__A */
278 
279 	WRBLOCK(FE_AG_REG_IND_WIN__A, 29),
280 	0x00, 0x00,		/* FE_AG_REG_IND_WIN__A     */
281 	0x05, 0x00,		/* FE_AG_REG_IND_THD_LOL__A */
282 	0x0F, 0x00,		/* FE_AG_REG_IND_THD_HIL__A */
283 	0x00, 0x00,		/* FE_AG_REG_IND_DEL__A     don't care */
284 	0x1E, 0x00,		/* FE_AG_REG_IND_PD1_WRI__A */
285 	0x0C, 0x00,		/* FE_AG_REG_PDA_AUR_CNT__A */
286 	0x00, 0x00,		/* FE_AG_REG_PDA_RUR_CNT__A */
287 	0x00, 0x00,		/* FE_AG_REG_PDA_AVE_DAT__A don't care  */
288 	0x00, 0x00,		/* FE_AG_REG_PDC_RUR_CNT__A */
289 	0x01, 0x00,		/* FE_AG_REG_PDC_SET_LVL__A */
290 	0x02, 0x00,		/* FE_AG_REG_PDC_FLA_RGN__A */
291 	0x00, 0x00,		/* FE_AG_REG_PDC_JMP_PSN__A don't care  */
292 	0xFF, 0xFF,		/* FE_AG_REG_PDC_FLA_STP__A */
293 	0xFF, 0xFF,		/* FE_AG_REG_PDC_SLO_STP__A */
294 	0x00, 0x1F,		/* FE_AG_REG_PDC_PD2_WRI__A don't care  */
295 	0x00, 0x00,		/* FE_AG_REG_PDC_MAP_DAT__A don't care  */
296 	0x02, 0x00,		/* FE_AG_REG_PDC_MAX__A     */
297 	0x0C, 0x00,		/* FE_AG_REG_TGA_AUR_CNT__A */
298 	0x00, 0x00,		/* FE_AG_REG_TGA_RUR_CNT__A */
299 	0x00, 0x00,		/* FE_AG_REG_TGA_AVE_DAT__A don't care  */
300 	0x00, 0x00,		/* FE_AG_REG_TGC_RUR_CNT__A */
301 	0x22, 0x00,		/* FE_AG_REG_TGC_SET_LVL__A */
302 	0x15, 0x00,		/* FE_AG_REG_TGC_FLA_RGN__A */
303 	0x00, 0x00,		/* FE_AG_REG_TGC_JMP_PSN__A don't care  */
304 	0x01, 0x00,		/* FE_AG_REG_TGC_FLA_STP__A */
305 	0x0A, 0x00,		/* FE_AG_REG_TGC_SLO_STP__A */
306 	0x00, 0x00,		/* FE_AG_REG_TGC_MAP_DAT__A don't care  */
307 	0x10, 0x00,		/* FE_AG_REG_FGA_AUR_CNT__A */
308 	0x10, 0x00,		/* FE_AG_REG_FGA_RUR_CNT__A */
309 
310 	WRBLOCK(FE_AG_REG_BGC_FGC_WRI__A, 2),
311 	0x00, 0x00,		/* FE_AG_REG_BGC_FGC_WRI__A */
312 	0x00, 0x00,		/* FE_AG_REG_BGC_CGC_WRI__A */
313 
314 	WRBLOCK(FE_FD_REG_SCL__A, 3),
315 	0x05, 0x00,		/* FE_FD_REG_SCL__A         */
316 	0x03, 0x00,		/* FE_FD_REG_MAX_LEV__A     */
317 	0x05, 0x00,		/* FE_FD_REG_NR__A          */
318 
319 	WRBLOCK(FE_CF_REG_SCL__A, 5),
320 	0x16, 0x00,		/* FE_CF_REG_SCL__A         */
321 	0x04, 0x00,		/* FE_CF_REG_MAX_LEV__A     */
322 	0x06, 0x00,		/* FE_CF_REG_NR__A          */
323 	0x00, 0x00,		/* FE_CF_REG_IMP_VAL__A     */
324 	0x01, 0x00,		/* FE_CF_REG_MEAS_VAL__A    */
325 
326 	WRBLOCK(FE_CU_REG_FRM_CNT_RST__A, 2),
327 	0x00, 0x08,		/* FE_CU_REG_FRM_CNT_RST__A */
328 	0x00, 0x00,		/* FE_CU_REG_FRM_CNT_STR__A */
329 
330 	END_OF_TABLE
331 };
332 
333    /* with PGA */
334 /*   WR16COND( DRXD_WITH_PGA, FE_AG_REG_AG_PGA_MODE__A   , 0x0004), */
335    /* without PGA */
336 /*   WR16COND( DRXD_WITHOUT_PGA, FE_AG_REG_AG_PGA_MODE__A   , 0x0001), */
337 /*   WR16(FE_AG_REG_AG_AGC_SIO__A,  (extAttr -> FeAgRegAgAgcSio), 0x0000 );*/
338 /*   WR16(FE_AG_REG_AG_PWD__A        ,(extAttr -> FeAgRegAgPwd), 0x0000 );*/
339 
340 u8 DRXD_InitFEA2_2[] = {
341 	WR16(FE_AG_REG_CDR_RUR_CNT__A, 0x0010),
342 	WR16(FE_AG_REG_FGM_WRI__A, 48),
343 	/* Activate measurement, activate scale */
344 	WR16(FE_FD_REG_MEAS_VAL__A, 0x0001),
345 
346 	WR16(FE_CU_REG_COMM_EXEC__A, 0x0001),
347 	WR16(FE_CF_REG_COMM_EXEC__A, 0x0001),
348 	WR16(FE_IF_REG_COMM_EXEC__A, 0x0001),
349 	WR16(FE_FD_REG_COMM_EXEC__A, 0x0001),
350 	WR16(FE_FS_REG_COMM_EXEC__A, 0x0001),
351 	WR16(FE_AD_REG_COMM_EXEC__A, 0x0001),
352 	WR16(FE_AG_REG_COMM_EXEC__A, 0x0001),
353 	WR16(FE_AG_REG_AG_MODE_LOP__A, 0x895E),
354 
355 	END_OF_TABLE
356 };
357 
358 u8 DRXD_InitFEB1_1[] = {
359 	WR16(B_FE_AD_REG_PD__A, 0x0000),
360 	WR16(B_FE_AD_REG_CLKNEG__A, 0x0000),
361 	WR16(B_FE_AG_REG_BGC_FGC_WRI__A, 0x0000),
362 	WR16(B_FE_AG_REG_BGC_CGC_WRI__A, 0x0000),
363 	WR16(B_FE_AG_REG_AG_MODE_LOP__A, 0x000a),
364 	WR16(B_FE_AG_REG_IND_PD1_WRI__A, 35),
365 	WR16(B_FE_AG_REG_IND_WIN__A, 0),
366 	WR16(B_FE_AG_REG_IND_THD_LOL__A, 8),
367 	WR16(B_FE_AG_REG_IND_THD_HIL__A, 8),
368 	WR16(B_FE_CF_REG_IMP_VAL__A, 1),
369 	WR16(B_FE_AG_REG_EGC_FLA_RGN__A, 7),
370 	END_OF_TABLE
371 };
372 
373 	/* with PGA */
374 /*      WR16(B_FE_AG_REG_AG_PGA_MODE__A   , 0x0000, 0x0000); */
375        /* without PGA */
376 /*      WR16(B_FE_AG_REG_AG_PGA_MODE__A   ,
377 	     B_FE_AG_REG_AG_PGA_MODE_PFN_PCN_AFY_REN, 0x0000);*/
378 									     /*   WR16(B_FE_AG_REG_AG_AGC_SIO__A,(extAttr -> FeAgRegAgAgcSio), 0x0000 );*//*added HS 23-05-2005 */
379 /*   WR16(B_FE_AG_REG_AG_PWD__A    ,(extAttr -> FeAgRegAgPwd), 0x0000 );*/
380 
381 u8 DRXD_InitFEB1_2[] = {
382 	WR16(B_FE_COMM_EXEC__A, 0x0001),
383 
384 	/* RF-AGC setup */
385 	WR16(B_FE_AG_REG_PDA_AUR_CNT__A, 0x0C),
386 	WR16(B_FE_AG_REG_PDC_SET_LVL__A, 0x01),
387 	WR16(B_FE_AG_REG_PDC_FLA_RGN__A, 0x02),
388 	WR16(B_FE_AG_REG_PDC_FLA_STP__A, 0xFFFF),
389 	WR16(B_FE_AG_REG_PDC_SLO_STP__A, 0xFFFF),
390 	WR16(B_FE_AG_REG_PDC_MAX__A, 0x02),
391 	WR16(B_FE_AG_REG_TGA_AUR_CNT__A, 0x0C),
392 	WR16(B_FE_AG_REG_TGC_SET_LVL__A, 0x22),
393 	WR16(B_FE_AG_REG_TGC_FLA_RGN__A, 0x15),
394 	WR16(B_FE_AG_REG_TGC_FLA_STP__A, 0x01),
395 	WR16(B_FE_AG_REG_TGC_SLO_STP__A, 0x0A),
396 
397 	WR16(B_FE_CU_REG_DIV_NFC_CLP__A, 0),
398 	WR16(B_FE_CU_REG_CTR_NFC_OCR__A, 25000),
399 	WR16(B_FE_CU_REG_CTR_NFC_ICR__A, 1),
400 	END_OF_TABLE
401 };
402 
403 u8 DRXD_InitCPA2[] = {
404 	WRBLOCK(CP_REG_BR_SPL_OFFSET__A, 2),
405 	0x07, 0x00,		/* CP_REG_BR_SPL_OFFSET__A  */
406 	0x0A, 0x00,		/* CP_REG_BR_STR_DEL__A     */
407 
408 	WRBLOCK(CP_REG_RT_ANG_INC0__A, 4),
409 	0x00, 0x00,		/* CP_REG_RT_ANG_INC0__A    */
410 	0x00, 0x00,		/* CP_REG_RT_ANG_INC1__A    */
411 	0x03, 0x00,		/* CP_REG_RT_DETECT_ENA__A  */
412 	0x03, 0x00,		/* CP_REG_RT_DETECT_TRH__A  */
413 
414 	WRBLOCK(CP_REG_AC_NEXP_OFFS__A, 5),
415 	0x32, 0x00,		/* CP_REG_AC_NEXP_OFFS__A   */
416 	0x62, 0x00,		/* CP_REG_AC_AVER_POW__A    */
417 	0x82, 0x00,		/* CP_REG_AC_MAX_POW__A     */
418 	0x26, 0x00,		/* CP_REG_AC_WEIGHT_MAN__A  */
419 	0x0F, 0x00,		/* CP_REG_AC_WEIGHT_EXP__A  */
420 
421 	WRBLOCK(CP_REG_AC_AMP_MODE__A, 2),
422 	0x02, 0x00,		/* CP_REG_AC_AMP_MODE__A    */
423 	0x01, 0x00,		/* CP_REG_AC_AMP_FIX__A     */
424 
425 	WR16(CP_REG_INTERVAL__A, 0x0005),
426 	WR16(CP_REG_RT_EXP_MARG__A, 0x0004),
427 	WR16(CP_REG_AC_ANG_MODE__A, 0x0003),
428 
429 	WR16(CP_REG_COMM_EXEC__A, 0x0001),
430 	END_OF_TABLE
431 };
432 
433 u8 DRXD_InitCPB1[] = {
434 	WR16(B_CP_REG_BR_SPL_OFFSET__A, 0x0008),
435 	WR16(B_CP_COMM_EXEC__A, 0x0001),
436 	END_OF_TABLE
437 };
438 
439 u8 DRXD_InitCEA2[] = {
440 	WRBLOCK(CE_REG_AVG_POW__A, 4),
441 	0x62, 0x00,		/* CE_REG_AVG_POW__A        */
442 	0x78, 0x00,		/* CE_REG_MAX_POW__A        */
443 	0x62, 0x00,		/* CE_REG_ATT__A            */
444 	0x17, 0x00,		/* CE_REG_NRED__A           */
445 
446 	WRBLOCK(CE_REG_NE_ERR_SELECT__A, 2),
447 	0x07, 0x00,		/* CE_REG_NE_ERR_SELECT__A  */
448 	0xEB, 0xFF,		/* CE_REG_NE_TD_CAL__A      */
449 
450 	WRBLOCK(CE_REG_NE_MIXAVG__A, 2),
451 	0x06, 0x00,		/* CE_REG_NE_MIXAVG__A      */
452 	0x00, 0x00,		/* CE_REG_NE_NUPD_OFS__A    */
453 
454 	WRBLOCK(CE_REG_PE_NEXP_OFFS__A, 2),
455 	0x00, 0x00,		/* CE_REG_PE_NEXP_OFFS__A   */
456 	0x00, 0x00,		/* CE_REG_PE_TIMESHIFT__A   */
457 
458 	WRBLOCK(CE_REG_TP_A0_TAP_NEW__A, 3),
459 	0x00, 0x01,		/* CE_REG_TP_A0_TAP_NEW__A       */
460 	0x01, 0x00,		/* CE_REG_TP_A0_TAP_NEW_VALID__A */
461 	0x0E, 0x00,		/* CE_REG_TP_A0_MU_LMS_STEP__A   */
462 
463 	WRBLOCK(CE_REG_TP_A1_TAP_NEW__A, 3),
464 	0x00, 0x00,		/* CE_REG_TP_A1_TAP_NEW__A        */
465 	0x01, 0x00,		/* CE_REG_TP_A1_TAP_NEW_VALID__A  */
466 	0x0A, 0x00,		/* CE_REG_TP_A1_MU_LMS_STEP__A    */
467 
468 	WRBLOCK(CE_REG_FI_SHT_INCR__A, 2),
469 	0x12, 0x00,		/* CE_REG_FI_SHT_INCR__A          */
470 	0x0C, 0x00,		/* CE_REG_FI_EXP_NORM__A          */
471 
472 	WRBLOCK(CE_REG_IR_INPUTSEL__A, 3),
473 	0x00, 0x00,		/* CE_REG_IR_INPUTSEL__A          */
474 	0x00, 0x00,		/* CE_REG_IR_STARTPOS__A          */
475 	0xFF, 0x00,		/* CE_REG_IR_NEXP_THRES__A        */
476 
477 	WR16(CE_REG_TI_NEXP_OFFS__A, 0x0000),
478 
479 	END_OF_TABLE
480 };
481 
482 u8 DRXD_InitCEB1[] = {
483 	WR16(B_CE_REG_TI_PHN_ENABLE__A, 0x0001),
484 	WR16(B_CE_REG_FR_PM_SET__A, 0x000D),
485 
486 	END_OF_TABLE
487 };
488 
489 u8 DRXD_InitEQA2[] = {
490 	WRBLOCK(EQ_REG_OT_QNT_THRES0__A, 4),
491 	0x1E, 0x00,		/* EQ_REG_OT_QNT_THRES0__A        */
492 	0x1F, 0x00,		/* EQ_REG_OT_QNT_THRES1__A        */
493 	0x06, 0x00,		/* EQ_REG_OT_CSI_STEP__A          */
494 	0x02, 0x00,		/* EQ_REG_OT_CSI_OFFSET__A        */
495 
496 	WR16(EQ_REG_TD_REQ_SMB_CNT__A, 0x0200),
497 	WR16(EQ_REG_IS_CLIP_EXP__A, 0x001F),
498 	WR16(EQ_REG_SN_OFFSET__A, (u16) (-7)),
499 	WR16(EQ_REG_RC_SEL_CAR__A, 0x0002),
500 	WR16(EQ_REG_COMM_EXEC__A, 0x0001),
501 	END_OF_TABLE
502 };
503 
504 u8 DRXD_InitEQB1[] = {
505 	WR16(B_EQ_REG_COMM_EXEC__A, 0x0001),
506 	END_OF_TABLE
507 };
508 
509 u8 DRXD_ResetECRAM[] = {
510 	/* Reset packet sync bytes in EC_VD ram */
511 	WR16(EC_OD_DEINT_RAM__A + 0x3b7 + (0 * 17), 0x0000),
512 	WR16(EC_OD_DEINT_RAM__A + 0x3b7 + (1 * 17), 0x0000),
513 	WR16(EC_OD_DEINT_RAM__A + 0x3b7 + (2 * 17), 0x0000),
514 	WR16(EC_OD_DEINT_RAM__A + 0x3b7 + (3 * 17), 0x0000),
515 	WR16(EC_OD_DEINT_RAM__A + 0x3b7 + (4 * 17), 0x0000),
516 	WR16(EC_OD_DEINT_RAM__A + 0x3b7 + (5 * 17), 0x0000),
517 	WR16(EC_OD_DEINT_RAM__A + 0x3b7 + (6 * 17), 0x0000),
518 	WR16(EC_OD_DEINT_RAM__A + 0x3b7 + (7 * 17), 0x0000),
519 	WR16(EC_OD_DEINT_RAM__A + 0x3b7 + (8 * 17), 0x0000),
520 	WR16(EC_OD_DEINT_RAM__A + 0x3b7 + (9 * 17), 0x0000),
521 	WR16(EC_OD_DEINT_RAM__A + 0x3b7 + (10 * 17), 0x0000),
522 
523 	/* Reset packet sync bytes in EC_RS ram */
524 	WR16(EC_RS_EC_RAM__A, 0x0000),
525 	WR16(EC_RS_EC_RAM__A + 204, 0x0000),
526 	END_OF_TABLE
527 };
528 
529 u8 DRXD_InitECA2[] = {
530 	WRBLOCK(EC_SB_REG_CSI_HI__A, 6),
531 	0x1F, 0x00,		/* EC_SB_REG_CSI_HI__A            */
532 	0x1E, 0x00,		/* EC_SB_REG_CSI_LO__A            */
533 	0x01, 0x00,		/* EC_SB_REG_SMB_TGL__A           */
534 	0x7F, 0x00,		/* EC_SB_REG_SNR_HI__A            */
535 	0x7F, 0x00,		/* EC_SB_REG_SNR_MID__A           */
536 	0x7F, 0x00,		/* EC_SB_REG_SNR_LO__A            */
537 
538 	WRBLOCK(EC_RS_REG_REQ_PCK_CNT__A, 2),
539 	0x00, 0x10,		/* EC_RS_REG_REQ_PCK_CNT__A       */
540 	DATA16(EC_RS_REG_VAL_PCK),	/* EC_RS_REG_VAL__A               */
541 
542 	WRBLOCK(EC_OC_REG_TMD_TOP_MODE__A, 5),
543 	0x03, 0x00,		/* EC_OC_REG_TMD_TOP_MODE__A      */
544 	0xF4, 0x01,		/* EC_OC_REG_TMD_TOP_CNT__A       */
545 	0xC0, 0x03,		/* EC_OC_REG_TMD_HIL_MAR__A       */
546 	0x40, 0x00,		/* EC_OC_REG_TMD_LOL_MAR__A       */
547 	0x03, 0x00,		/* EC_OC_REG_TMD_CUR_CNT__A       */
548 
549 	WRBLOCK(EC_OC_REG_AVR_ASH_CNT__A, 2),
550 	0x06, 0x00,		/* EC_OC_REG_AVR_ASH_CNT__A       */
551 	0x02, 0x00,		/* EC_OC_REG_AVR_BSH_CNT__A       */
552 
553 	WRBLOCK(EC_OC_REG_RCN_MODE__A, 7),
554 	0x07, 0x00,		/* EC_OC_REG_RCN_MODE__A          */
555 	0x00, 0x00,		/* EC_OC_REG_RCN_CRA_LOP__A       */
556 	0xc0, 0x00,		/* EC_OC_REG_RCN_CRA_HIP__A       */
557 	0x00, 0x10,		/* EC_OC_REG_RCN_CST_LOP__A       */
558 	0x00, 0x00,		/* EC_OC_REG_RCN_CST_HIP__A       */
559 	0xFF, 0x01,		/* EC_OC_REG_RCN_SET_LVL__A       */
560 	0x0D, 0x00,		/* EC_OC_REG_RCN_GAI_LVL__A       */
561 
562 	WRBLOCK(EC_OC_REG_RCN_CLP_LOP__A, 2),
563 	0x00, 0x00,		/* EC_OC_REG_RCN_CLP_LOP__A       */
564 	0xC0, 0x00,		/* EC_OC_REG_RCN_CLP_HIP__A       */
565 
566 	WR16(EC_SB_REG_CSI_OFS__A, 0x0001),
567 	WR16(EC_VD_REG_FORCE__A, 0x0002),
568 	WR16(EC_VD_REG_REQ_SMB_CNT__A, 0x0001),
569 	WR16(EC_VD_REG_RLK_ENA__A, 0x0001),
570 	WR16(EC_OD_REG_SYNC__A, 0x0664),
571 	WR16(EC_OC_REG_OC_MON_SIO__A, 0x0000),
572 	WR16(EC_OC_REG_SNC_ISC_LVL__A, 0x0D0C),
573 	/* Output zero on monitorbus pads, power saving */
574 	WR16(EC_OC_REG_OCR_MON_UOS__A,
575 	     (EC_OC_REG_OCR_MON_UOS_DAT_0_ENABLE |
576 	      EC_OC_REG_OCR_MON_UOS_DAT_1_ENABLE |
577 	      EC_OC_REG_OCR_MON_UOS_DAT_2_ENABLE |
578 	      EC_OC_REG_OCR_MON_UOS_DAT_3_ENABLE |
579 	      EC_OC_REG_OCR_MON_UOS_DAT_4_ENABLE |
580 	      EC_OC_REG_OCR_MON_UOS_DAT_5_ENABLE |
581 	      EC_OC_REG_OCR_MON_UOS_DAT_6_ENABLE |
582 	      EC_OC_REG_OCR_MON_UOS_DAT_7_ENABLE |
583 	      EC_OC_REG_OCR_MON_UOS_DAT_8_ENABLE |
584 	      EC_OC_REG_OCR_MON_UOS_DAT_9_ENABLE |
585 	      EC_OC_REG_OCR_MON_UOS_VAL_ENABLE |
586 	      EC_OC_REG_OCR_MON_UOS_CLK_ENABLE)),
587 	WR16(EC_OC_REG_OCR_MON_WRI__A,
588 	     EC_OC_REG_OCR_MON_WRI_INIT),
589 
590 /*   CHK_ERROR(ResetECRAM(demod)); */
591 	/* Reset packet sync bytes in EC_VD ram */
592 	WR16(EC_OD_DEINT_RAM__A + 0x3b7 + (0 * 17), 0x0000),
593 	WR16(EC_OD_DEINT_RAM__A + 0x3b7 + (1 * 17), 0x0000),
594 	WR16(EC_OD_DEINT_RAM__A + 0x3b7 + (2 * 17), 0x0000),
595 	WR16(EC_OD_DEINT_RAM__A + 0x3b7 + (3 * 17), 0x0000),
596 	WR16(EC_OD_DEINT_RAM__A + 0x3b7 + (4 * 17), 0x0000),
597 	WR16(EC_OD_DEINT_RAM__A + 0x3b7 + (5 * 17), 0x0000),
598 	WR16(EC_OD_DEINT_RAM__A + 0x3b7 + (6 * 17), 0x0000),
599 	WR16(EC_OD_DEINT_RAM__A + 0x3b7 + (7 * 17), 0x0000),
600 	WR16(EC_OD_DEINT_RAM__A + 0x3b7 + (8 * 17), 0x0000),
601 	WR16(EC_OD_DEINT_RAM__A + 0x3b7 + (9 * 17), 0x0000),
602 	WR16(EC_OD_DEINT_RAM__A + 0x3b7 + (10 * 17), 0x0000),
603 
604 	/* Reset packet sync bytes in EC_RS ram */
605 	WR16(EC_RS_EC_RAM__A, 0x0000),
606 	WR16(EC_RS_EC_RAM__A + 204, 0x0000),
607 
608 	WR16(EC_SB_REG_COMM_EXEC__A, 0x0001),
609 	WR16(EC_VD_REG_COMM_EXEC__A, 0x0001),
610 	WR16(EC_OD_REG_COMM_EXEC__A, 0x0001),
611 	WR16(EC_RS_REG_COMM_EXEC__A, 0x0001),
612 	END_OF_TABLE
613 };
614 
615 u8 DRXD_InitECB1[] = {
616 	WR16(B_EC_SB_REG_CSI_OFS0__A, 0x0001),
617 	WR16(B_EC_SB_REG_CSI_OFS1__A, 0x0001),
618 	WR16(B_EC_SB_REG_CSI_OFS2__A, 0x0001),
619 	WR16(B_EC_SB_REG_CSI_LO__A, 0x000c),
620 	WR16(B_EC_SB_REG_CSI_HI__A, 0x0018),
621 	WR16(B_EC_SB_REG_SNR_HI__A, 0x007f),
622 	WR16(B_EC_SB_REG_SNR_MID__A, 0x007f),
623 	WR16(B_EC_SB_REG_SNR_LO__A, 0x007f),
624 
625 	WR16(B_EC_OC_REG_DTO_CLKMODE__A, 0x0002),
626 	WR16(B_EC_OC_REG_DTO_PER__A, 0x0006),
627 	WR16(B_EC_OC_REG_DTO_BUR__A, 0x0001),
628 	WR16(B_EC_OC_REG_RCR_CLKMODE__A, 0x0000),
629 	WR16(B_EC_OC_REG_RCN_GAI_LVL__A, 0x000D),
630 	WR16(B_EC_OC_REG_OC_MPG_SIO__A, 0x0000),
631 
632 	/* Needed because shadow registers do not have correct default value */
633 	WR16(B_EC_OC_REG_RCN_CST_LOP__A, 0x1000),
634 	WR16(B_EC_OC_REG_RCN_CST_HIP__A, 0x0000),
635 	WR16(B_EC_OC_REG_RCN_CRA_LOP__A, 0x0000),
636 	WR16(B_EC_OC_REG_RCN_CRA_HIP__A, 0x00C0),
637 	WR16(B_EC_OC_REG_RCN_CLP_LOP__A, 0x0000),
638 	WR16(B_EC_OC_REG_RCN_CLP_HIP__A, 0x00C0),
639 	WR16(B_EC_OC_REG_DTO_INC_LOP__A, 0x0000),
640 	WR16(B_EC_OC_REG_DTO_INC_HIP__A, 0x00C0),
641 
642 	WR16(B_EC_OD_REG_SYNC__A, 0x0664),
643 	WR16(B_EC_RS_REG_REQ_PCK_CNT__A, 0x1000),
644 
645 /*   CHK_ERROR(ResetECRAM(demod)); */
646 	/* Reset packet sync bytes in EC_VD ram */
647 	WR16(EC_OD_DEINT_RAM__A + 0x3b7 + (0 * 17), 0x0000),
648 	WR16(EC_OD_DEINT_RAM__A + 0x3b7 + (1 * 17), 0x0000),
649 	WR16(EC_OD_DEINT_RAM__A + 0x3b7 + (2 * 17), 0x0000),
650 	WR16(EC_OD_DEINT_RAM__A + 0x3b7 + (3 * 17), 0x0000),
651 	WR16(EC_OD_DEINT_RAM__A + 0x3b7 + (4 * 17), 0x0000),
652 	WR16(EC_OD_DEINT_RAM__A + 0x3b7 + (5 * 17), 0x0000),
653 	WR16(EC_OD_DEINT_RAM__A + 0x3b7 + (6 * 17), 0x0000),
654 	WR16(EC_OD_DEINT_RAM__A + 0x3b7 + (7 * 17), 0x0000),
655 	WR16(EC_OD_DEINT_RAM__A + 0x3b7 + (8 * 17), 0x0000),
656 	WR16(EC_OD_DEINT_RAM__A + 0x3b7 + (9 * 17), 0x0000),
657 	WR16(EC_OD_DEINT_RAM__A + 0x3b7 + (10 * 17), 0x0000),
658 
659 	/* Reset packet sync bytes in EC_RS ram */
660 	WR16(EC_RS_EC_RAM__A, 0x0000),
661 	WR16(EC_RS_EC_RAM__A + 204, 0x0000),
662 
663 	WR16(B_EC_SB_REG_COMM_EXEC__A, 0x0001),
664 	WR16(B_EC_VD_REG_COMM_EXEC__A, 0x0001),
665 	WR16(B_EC_OD_REG_COMM_EXEC__A, 0x0001),
666 	WR16(B_EC_RS_REG_COMM_EXEC__A, 0x0001),
667 	END_OF_TABLE
668 };
669 
670 u8 DRXD_ResetECA2[] = {
671 
672 	WR16(EC_OC_REG_COMM_EXEC__A, 0x0000),
673 	WR16(EC_OD_REG_COMM_EXEC__A, 0x0000),
674 
675 	WRBLOCK(EC_OC_REG_TMD_TOP_MODE__A, 5),
676 	0x03, 0x00,		/* EC_OC_REG_TMD_TOP_MODE__A      */
677 	0xF4, 0x01,		/* EC_OC_REG_TMD_TOP_CNT__A       */
678 	0xC0, 0x03,		/* EC_OC_REG_TMD_HIL_MAR__A       */
679 	0x40, 0x00,		/* EC_OC_REG_TMD_LOL_MAR__A       */
680 	0x03, 0x00,		/* EC_OC_REG_TMD_CUR_CNT__A       */
681 
682 	WRBLOCK(EC_OC_REG_AVR_ASH_CNT__A, 2),
683 	0x06, 0x00,		/* EC_OC_REG_AVR_ASH_CNT__A       */
684 	0x02, 0x00,		/* EC_OC_REG_AVR_BSH_CNT__A       */
685 
686 	WRBLOCK(EC_OC_REG_RCN_MODE__A, 7),
687 	0x07, 0x00,		/* EC_OC_REG_RCN_MODE__A          */
688 	0x00, 0x00,		/* EC_OC_REG_RCN_CRA_LOP__A       */
689 	0xc0, 0x00,		/* EC_OC_REG_RCN_CRA_HIP__A       */
690 	0x00, 0x10,		/* EC_OC_REG_RCN_CST_LOP__A       */
691 	0x00, 0x00,		/* EC_OC_REG_RCN_CST_HIP__A       */
692 	0xFF, 0x01,		/* EC_OC_REG_RCN_SET_LVL__A       */
693 	0x0D, 0x00,		/* EC_OC_REG_RCN_GAI_LVL__A       */
694 
695 	WRBLOCK(EC_OC_REG_RCN_CLP_LOP__A, 2),
696 	0x00, 0x00,		/* EC_OC_REG_RCN_CLP_LOP__A       */
697 	0xC0, 0x00,		/* EC_OC_REG_RCN_CLP_HIP__A       */
698 
699 	WR16(EC_OD_REG_SYNC__A, 0x0664),
700 	WR16(EC_OC_REG_OC_MON_SIO__A, 0x0000),
701 	WR16(EC_OC_REG_SNC_ISC_LVL__A, 0x0D0C),
702 	/* Output zero on monitorbus pads, power saving */
703 	WR16(EC_OC_REG_OCR_MON_UOS__A,
704 	     (EC_OC_REG_OCR_MON_UOS_DAT_0_ENABLE |
705 	      EC_OC_REG_OCR_MON_UOS_DAT_1_ENABLE |
706 	      EC_OC_REG_OCR_MON_UOS_DAT_2_ENABLE |
707 	      EC_OC_REG_OCR_MON_UOS_DAT_3_ENABLE |
708 	      EC_OC_REG_OCR_MON_UOS_DAT_4_ENABLE |
709 	      EC_OC_REG_OCR_MON_UOS_DAT_5_ENABLE |
710 	      EC_OC_REG_OCR_MON_UOS_DAT_6_ENABLE |
711 	      EC_OC_REG_OCR_MON_UOS_DAT_7_ENABLE |
712 	      EC_OC_REG_OCR_MON_UOS_DAT_8_ENABLE |
713 	      EC_OC_REG_OCR_MON_UOS_DAT_9_ENABLE |
714 	      EC_OC_REG_OCR_MON_UOS_VAL_ENABLE |
715 	      EC_OC_REG_OCR_MON_UOS_CLK_ENABLE)),
716 	WR16(EC_OC_REG_OCR_MON_WRI__A,
717 	     EC_OC_REG_OCR_MON_WRI_INIT),
718 
719 /*   CHK_ERROR(ResetECRAM(demod)); */
720 	/* Reset packet sync bytes in EC_VD ram */
721 	WR16(EC_OD_DEINT_RAM__A + 0x3b7 + (0 * 17), 0x0000),
722 	WR16(EC_OD_DEINT_RAM__A + 0x3b7 + (1 * 17), 0x0000),
723 	WR16(EC_OD_DEINT_RAM__A + 0x3b7 + (2 * 17), 0x0000),
724 	WR16(EC_OD_DEINT_RAM__A + 0x3b7 + (3 * 17), 0x0000),
725 	WR16(EC_OD_DEINT_RAM__A + 0x3b7 + (4 * 17), 0x0000),
726 	WR16(EC_OD_DEINT_RAM__A + 0x3b7 + (5 * 17), 0x0000),
727 	WR16(EC_OD_DEINT_RAM__A + 0x3b7 + (6 * 17), 0x0000),
728 	WR16(EC_OD_DEINT_RAM__A + 0x3b7 + (7 * 17), 0x0000),
729 	WR16(EC_OD_DEINT_RAM__A + 0x3b7 + (8 * 17), 0x0000),
730 	WR16(EC_OD_DEINT_RAM__A + 0x3b7 + (9 * 17), 0x0000),
731 	WR16(EC_OD_DEINT_RAM__A + 0x3b7 + (10 * 17), 0x0000),
732 
733 	/* Reset packet sync bytes in EC_RS ram */
734 	WR16(EC_RS_EC_RAM__A, 0x0000),
735 	WR16(EC_RS_EC_RAM__A + 204, 0x0000),
736 
737 	WR16(EC_OD_REG_COMM_EXEC__A, 0x0001),
738 	END_OF_TABLE
739 };
740 
741 u8 DRXD_InitSC[] = {
742 	WR16(SC_COMM_EXEC__A, 0),
743 	WR16(SC_COMM_STATE__A, 0),
744 
745 #ifdef COMPILE_FOR_QT
746 	WR16(SC_RA_RAM_BE_OPT_DELAY__A, 0x100),
747 #endif
748 
749 	/* SC is not started, this is done in SetChannels() */
750 	END_OF_TABLE
751 };
752 
753 /* Diversity settings */
754 
755 u8 DRXD_InitDiversityFront[] = {
756 	/* Start demod ********* RF in , diversity out **************************** */
757 	WR16(B_SC_RA_RAM_CONFIG__A, B_SC_RA_RAM_CONFIG_FR_ENABLE__M |
758 	     B_SC_RA_RAM_CONFIG_FREQSCAN__M),
759 
760 	WR16(B_SC_RA_RAM_LC_ABS_2K__A, 0x7),
761 	WR16(B_SC_RA_RAM_LC_ABS_8K__A, 0x7),
762 	WR16(B_SC_RA_RAM_IR_COARSE_8K_LENGTH__A, IRLEN_COARSE_8K),
763 	WR16(B_SC_RA_RAM_IR_COARSE_8K_FREQINC__A, 1 << (11 - IRLEN_COARSE_8K)),
764 	WR16(B_SC_RA_RAM_IR_COARSE_8K_KAISINC__A, 1 << (17 - IRLEN_COARSE_8K)),
765 	WR16(B_SC_RA_RAM_IR_FINE_8K_LENGTH__A, IRLEN_FINE_8K),
766 	WR16(B_SC_RA_RAM_IR_FINE_8K_FREQINC__A, 1 << (11 - IRLEN_FINE_8K)),
767 	WR16(B_SC_RA_RAM_IR_FINE_8K_KAISINC__A, 1 << (17 - IRLEN_FINE_8K)),
768 
769 	WR16(B_SC_RA_RAM_IR_COARSE_2K_LENGTH__A, IRLEN_COARSE_2K),
770 	WR16(B_SC_RA_RAM_IR_COARSE_2K_FREQINC__A, 1 << (11 - IRLEN_COARSE_2K)),
771 	WR16(B_SC_RA_RAM_IR_COARSE_2K_KAISINC__A, 1 << (17 - IRLEN_COARSE_2K)),
772 	WR16(B_SC_RA_RAM_IR_FINE_2K_LENGTH__A, IRLEN_FINE_2K),
773 	WR16(B_SC_RA_RAM_IR_FINE_2K_FREQINC__A, 1 << (11 - IRLEN_FINE_2K)),
774 	WR16(B_SC_RA_RAM_IR_FINE_2K_KAISINC__A, 1 << (17 - IRLEN_FINE_2K)),
775 
776 	WR16(B_LC_RA_RAM_FILTER_CRMM_A__A, 7),
777 	WR16(B_LC_RA_RAM_FILTER_CRMM_B__A, 4),
778 	WR16(B_LC_RA_RAM_FILTER_SRMM_A__A, 7),
779 	WR16(B_LC_RA_RAM_FILTER_SRMM_B__A, 4),
780 	WR16(B_LC_RA_RAM_FILTER_SYM_SET__A, 500),
781 
782 	WR16(B_CC_REG_DIVERSITY__A, 0x0001),
783 	WR16(B_EC_OC_REG_OC_MODE_HIP__A, 0x0010),
784 	WR16(B_EQ_REG_RC_SEL_CAR__A, B_EQ_REG_RC_SEL_CAR_PASS_B_CE |
785 	     B_EQ_REG_RC_SEL_CAR_LOCAL_B_CE | B_EQ_REG_RC_SEL_CAR_MEAS_B_CE),
786 
787 	/*    0x2a ), *//* CE to PASS mux */
788 
789 	END_OF_TABLE
790 };
791 
792 u8 DRXD_InitDiversityEnd[] = {
793 	/* End demod *********** combining RF in and diversity in, MPEG TS out **** */
794 	/* disable near/far; switch on timing slave mode */
795 	WR16(B_SC_RA_RAM_CONFIG__A, B_SC_RA_RAM_CONFIG_FR_ENABLE__M |
796 	     B_SC_RA_RAM_CONFIG_FREQSCAN__M |
797 	     B_SC_RA_RAM_CONFIG_DIV_ECHO_ENABLE__M |
798 	     B_SC_RA_RAM_CONFIG_SLAVE__M |
799 	     B_SC_RA_RAM_CONFIG_DIV_BLANK_ENABLE__M
800 /* MV from CtrlDiversity */
801 	    ),
802 #ifdef DRXDDIV_SRMM_SLAVING
803 	WR16(SC_RA_RAM_LC_ABS_2K__A, 0x3c7),
804 	WR16(SC_RA_RAM_LC_ABS_8K__A, 0x3c7),
805 #else
806 	WR16(SC_RA_RAM_LC_ABS_2K__A, 0x7),
807 	WR16(SC_RA_RAM_LC_ABS_8K__A, 0x7),
808 #endif
809 
810 	WR16(B_SC_RA_RAM_IR_COARSE_8K_LENGTH__A, IRLEN_COARSE_8K),
811 	WR16(B_SC_RA_RAM_IR_COARSE_8K_FREQINC__A, 1 << (11 - IRLEN_COARSE_8K)),
812 	WR16(B_SC_RA_RAM_IR_COARSE_8K_KAISINC__A, 1 << (17 - IRLEN_COARSE_8K)),
813 	WR16(B_SC_RA_RAM_IR_FINE_8K_LENGTH__A, IRLEN_FINE_8K),
814 	WR16(B_SC_RA_RAM_IR_FINE_8K_FREQINC__A, 1 << (11 - IRLEN_FINE_8K)),
815 	WR16(B_SC_RA_RAM_IR_FINE_8K_KAISINC__A, 1 << (17 - IRLEN_FINE_8K)),
816 
817 	WR16(B_SC_RA_RAM_IR_COARSE_2K_LENGTH__A, IRLEN_COARSE_2K),
818 	WR16(B_SC_RA_RAM_IR_COARSE_2K_FREQINC__A, 1 << (11 - IRLEN_COARSE_2K)),
819 	WR16(B_SC_RA_RAM_IR_COARSE_2K_KAISINC__A, 1 << (17 - IRLEN_COARSE_2K)),
820 	WR16(B_SC_RA_RAM_IR_FINE_2K_LENGTH__A, IRLEN_FINE_2K),
821 	WR16(B_SC_RA_RAM_IR_FINE_2K_FREQINC__A, 1 << (11 - IRLEN_FINE_2K)),
822 	WR16(B_SC_RA_RAM_IR_FINE_2K_KAISINC__A, 1 << (17 - IRLEN_FINE_2K)),
823 
824 	WR16(B_LC_RA_RAM_FILTER_CRMM_A__A, 7),
825 	WR16(B_LC_RA_RAM_FILTER_CRMM_B__A, 4),
826 	WR16(B_LC_RA_RAM_FILTER_SRMM_A__A, 7),
827 	WR16(B_LC_RA_RAM_FILTER_SRMM_B__A, 4),
828 	WR16(B_LC_RA_RAM_FILTER_SYM_SET__A, 500),
829 
830 	WR16(B_CC_REG_DIVERSITY__A, 0x0001),
831 	END_OF_TABLE
832 };
833 
834 u8 DRXD_DisableDiversity[] = {
835 	WR16(B_SC_RA_RAM_LC_ABS_2K__A, B_SC_RA_RAM_LC_ABS_2K__PRE),
836 	WR16(B_SC_RA_RAM_LC_ABS_8K__A, B_SC_RA_RAM_LC_ABS_8K__PRE),
837 	WR16(B_SC_RA_RAM_IR_COARSE_8K_LENGTH__A,
838 	     B_SC_RA_RAM_IR_COARSE_8K_LENGTH__PRE),
839 	WR16(B_SC_RA_RAM_IR_COARSE_8K_FREQINC__A,
840 	     B_SC_RA_RAM_IR_COARSE_8K_FREQINC__PRE),
841 	WR16(B_SC_RA_RAM_IR_COARSE_8K_KAISINC__A,
842 	     B_SC_RA_RAM_IR_COARSE_8K_KAISINC__PRE),
843 	WR16(B_SC_RA_RAM_IR_FINE_8K_LENGTH__A,
844 	     B_SC_RA_RAM_IR_FINE_8K_LENGTH__PRE),
845 	WR16(B_SC_RA_RAM_IR_FINE_8K_FREQINC__A,
846 	     B_SC_RA_RAM_IR_FINE_8K_FREQINC__PRE),
847 	WR16(B_SC_RA_RAM_IR_FINE_8K_KAISINC__A,
848 	     B_SC_RA_RAM_IR_FINE_8K_KAISINC__PRE),
849 
850 	WR16(B_SC_RA_RAM_IR_COARSE_2K_LENGTH__A,
851 	     B_SC_RA_RAM_IR_COARSE_2K_LENGTH__PRE),
852 	WR16(B_SC_RA_RAM_IR_COARSE_2K_FREQINC__A,
853 	     B_SC_RA_RAM_IR_COARSE_2K_FREQINC__PRE),
854 	WR16(B_SC_RA_RAM_IR_COARSE_2K_KAISINC__A,
855 	     B_SC_RA_RAM_IR_COARSE_2K_KAISINC__PRE),
856 	WR16(B_SC_RA_RAM_IR_FINE_2K_LENGTH__A,
857 	     B_SC_RA_RAM_IR_FINE_2K_LENGTH__PRE),
858 	WR16(B_SC_RA_RAM_IR_FINE_2K_FREQINC__A,
859 	     B_SC_RA_RAM_IR_FINE_2K_FREQINC__PRE),
860 	WR16(B_SC_RA_RAM_IR_FINE_2K_KAISINC__A,
861 	     B_SC_RA_RAM_IR_FINE_2K_KAISINC__PRE),
862 
863 	WR16(B_LC_RA_RAM_FILTER_CRMM_A__A, B_LC_RA_RAM_FILTER_CRMM_A__PRE),
864 	WR16(B_LC_RA_RAM_FILTER_CRMM_B__A, B_LC_RA_RAM_FILTER_CRMM_B__PRE),
865 	WR16(B_LC_RA_RAM_FILTER_SRMM_A__A, B_LC_RA_RAM_FILTER_SRMM_A__PRE),
866 	WR16(B_LC_RA_RAM_FILTER_SRMM_B__A, B_LC_RA_RAM_FILTER_SRMM_B__PRE),
867 	WR16(B_LC_RA_RAM_FILTER_SYM_SET__A, B_LC_RA_RAM_FILTER_SYM_SET__PRE),
868 
869 	WR16(B_CC_REG_DIVERSITY__A, 0x0000),
870 	WR16(B_EQ_REG_RC_SEL_CAR__A, B_EQ_REG_RC_SEL_CAR_INIT),	/* combining disabled */
871 
872 	END_OF_TABLE
873 };
874 
875 u8 DRXD_StartDiversityFront[] = {
876 	/* Start demod, RF in and diversity out, no combining */
877 	WR16(B_FE_CF_REG_IMP_VAL__A, 0x0),
878 	WR16(B_FE_AD_REG_FDB_IN__A, 0x0),
879 	WR16(B_FE_AD_REG_INVEXT__A, 0x0),
880 	WR16(B_EQ_REG_COMM_MB__A, 0x12),	/* EQ to MB out */
881 	WR16(B_EQ_REG_RC_SEL_CAR__A, B_EQ_REG_RC_SEL_CAR_PASS_B_CE |	/* CE to PASS mux */
882 	     B_EQ_REG_RC_SEL_CAR_LOCAL_B_CE | B_EQ_REG_RC_SEL_CAR_MEAS_B_CE),
883 
884 	WR16(SC_RA_RAM_ECHO_SHIFT_LIM__A, 2),
885 
886 	END_OF_TABLE
887 };
888 
889 u8 DRXD_StartDiversityEnd[] = {
890 	/* End demod, combining RF in and diversity in, MPEG TS out */
891 	WR16(B_FE_CF_REG_IMP_VAL__A, 0x0),	/* disable impulse noise cruncher */
892 	WR16(B_FE_AD_REG_INVEXT__A, 0x0),	/* clock inversion (for sohard board) */
893 	WR16(B_CP_REG_BR_STR_DEL__A, 10),	/* apparently no mb delay matching is best */
894 
895 	WR16(B_EQ_REG_RC_SEL_CAR__A, B_EQ_REG_RC_SEL_CAR_DIV_ON |	/* org = 0x81 combining enabled */
896 	     B_EQ_REG_RC_SEL_CAR_MEAS_A_CC |
897 	     B_EQ_REG_RC_SEL_CAR_PASS_A_CC | B_EQ_REG_RC_SEL_CAR_LOCAL_A_CC),
898 
899 	END_OF_TABLE
900 };
901 
902 u8 DRXD_DiversityDelay8MHZ[] = {
903 	WR16(B_SC_RA_RAM_DIVERSITY_DELAY_2K_32__A, 1150 - 50),
904 	WR16(B_SC_RA_RAM_DIVERSITY_DELAY_2K_16__A, 1100 - 50),
905 	WR16(B_SC_RA_RAM_DIVERSITY_DELAY_2K_8__A, 1000 - 50),
906 	WR16(B_SC_RA_RAM_DIVERSITY_DELAY_2K_4__A, 800 - 50),
907 	WR16(B_SC_RA_RAM_DIVERSITY_DELAY_8K_32__A, 5420 - 50),
908 	WR16(B_SC_RA_RAM_DIVERSITY_DELAY_8K_16__A, 5200 - 50),
909 	WR16(B_SC_RA_RAM_DIVERSITY_DELAY_8K_8__A, 4800 - 50),
910 	WR16(B_SC_RA_RAM_DIVERSITY_DELAY_8K_4__A, 4000 - 50),
911 	END_OF_TABLE
912 };
913 
914 u8 DRXD_DiversityDelay6MHZ[] =	/* also used ok for 7 MHz */
915 {
916 	WR16(B_SC_RA_RAM_DIVERSITY_DELAY_2K_32__A, 1100 - 50),
917 	WR16(B_SC_RA_RAM_DIVERSITY_DELAY_2K_16__A, 1000 - 50),
918 	WR16(B_SC_RA_RAM_DIVERSITY_DELAY_2K_8__A, 900 - 50),
919 	WR16(B_SC_RA_RAM_DIVERSITY_DELAY_2K_4__A, 600 - 50),
920 	WR16(B_SC_RA_RAM_DIVERSITY_DELAY_8K_32__A, 5300 - 50),
921 	WR16(B_SC_RA_RAM_DIVERSITY_DELAY_8K_16__A, 5000 - 50),
922 	WR16(B_SC_RA_RAM_DIVERSITY_DELAY_8K_8__A, 4500 - 50),
923 	WR16(B_SC_RA_RAM_DIVERSITY_DELAY_8K_4__A, 3500 - 50),
924 	END_OF_TABLE
925 };
926