1 2 /* 3 Copyright (c), 2004-2005,2007-2010 Trident Microsystems, Inc. 4 All rights reserved. 5 6 Redistribution and use in source and binary forms, with or without 7 modification, are permitted provided that the following conditions are met: 8 9 * Redistributions of source code must retain the above copyright notice, 10 this list of conditions and the following disclaimer. 11 * Redistributions in binary form must reproduce the above copyright notice, 12 this list of conditions and the following disclaimer in the documentation 13 and/or other materials provided with the distribution. 14 * Neither the name of Trident Microsystems nor Hauppauge Computer Works 15 nor the names of its contributors may be used to endorse or promote 16 products derived from this software without specific prior written 17 permission. 18 19 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 20 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 21 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 22 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 23 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 POSSIBILITY OF SUCH DAMAGE. 30 31 DRXJ specific header file 32 33 Authors: Dragan Savic, Milos Nikolic, Mihajlo Katona, Tao Ding, Paul Janssen 34 */ 35 36 #ifndef __DRXJ_H__ 37 #define __DRXJ_H__ 38 /*------------------------------------------------------------------------- 39 INCLUDES 40 -------------------------------------------------------------------------*/ 41 42 #include "drx_driver.h" 43 #include "drx_dap_fasi.h" 44 45 /* Check DRX-J specific dap condition */ 46 /* Multi master mode and short addr format only will not work. 47 RMW, CRC reset, broadcast and switching back to single master mode 48 cannot be done with short addr only in multi master mode. */ 49 #if ((DRXDAP_SINGLE_MASTER == 0) && (DRXDAPFASI_LONG_ADDR_ALLOWED == 0)) 50 #error "Multi master mode and short addressing only is an illegal combination" 51 *; /* Generate a fatal compiler error to make sure it stops here, 52 this is necesarry because not all compilers stop after a #error. */ 53 #endif 54 55 /*------------------------------------------------------------------------- 56 TYPEDEFS 57 -------------------------------------------------------------------------*/ 58 /*============================================================================*/ 59 /*============================================================================*/ 60 /*== code support ============================================================*/ 61 /*============================================================================*/ 62 /*============================================================================*/ 63 64 /*============================================================================*/ 65 /*============================================================================*/ 66 /*== SCU cmd if =============================================================*/ 67 /*============================================================================*/ 68 /*============================================================================*/ 69 70 struct drxjscu_cmd { 71 u16 command; 72 /**< Command number */ 73 u16 parameter_len; 74 /**< Data length in byte */ 75 u16 result_len; 76 /**< result length in byte */ 77 u16 *parameter; 78 /**< General purpous param */ 79 u16 *result; 80 /**< General purpous param */}; 81 82 /*============================================================================*/ 83 /*============================================================================*/ 84 /*== CTRL CFG related data structures ========================================*/ 85 /*============================================================================*/ 86 /*============================================================================*/ 87 88 /* extra intermediate lock state for VSB,QAM,NTSC */ 89 #define DRXJ_DEMOD_LOCK (DRX_LOCK_STATE_1) 90 91 /* OOB lock states */ 92 #define DRXJ_OOB_AGC_LOCK (DRX_LOCK_STATE_1) /* analog gain control lock */ 93 #define DRXJ_OOB_SYNC_LOCK (DRX_LOCK_STATE_2) /* digital gain control lock */ 94 95 /* Intermediate powermodes for DRXJ */ 96 #define DRXJ_POWER_DOWN_MAIN_PATH DRX_POWER_MODE_8 97 #define DRXJ_POWER_DOWN_CORE DRX_POWER_MODE_9 98 #define DRXJ_POWER_DOWN_PLL DRX_POWER_MODE_10 99 100 /* supstition for GPIO FNC mux */ 101 #define APP_O (0x0000) 102 103 /*#define DRX_CTRL_BASE (0x0000)*/ 104 105 #define DRXJ_CTRL_CFG_BASE (0x1000) 106 enum drxj_cfg_type { 107 DRXJ_CFG_AGC_RF = DRXJ_CTRL_CFG_BASE, 108 DRXJ_CFG_AGC_IF, 109 DRXJ_CFG_AGC_INTERNAL, 110 DRXJ_CFG_PRE_SAW, 111 DRXJ_CFG_AFE_GAIN, 112 DRXJ_CFG_SYMBOL_CLK_OFFSET, 113 DRXJ_CFG_ACCUM_CR_RS_CW_ERR, 114 DRXJ_CFG_FEC_MERS_SEQ_COUNT, 115 DRXJ_CFG_OOB_MISC, 116 DRXJ_CFG_SMART_ANT, 117 DRXJ_CFG_OOB_PRE_SAW, 118 DRXJ_CFG_VSB_MISC, 119 DRXJ_CFG_RESET_PACKET_ERR, 120 121 /* ATV (FM) */ 122 DRXJ_CFG_ATV_OUTPUT, /* also for FM (SIF control) but not likely */ 123 DRXJ_CFG_ATV_MISC, 124 DRXJ_CFG_ATV_EQU_COEF, 125 DRXJ_CFG_ATV_AGC_STATUS, /* also for FM ( IF,RF, audioAGC ) */ 126 127 DRXJ_CFG_MPEG_OUTPUT_MISC, 128 DRXJ_CFG_HW_CFG, 129 DRXJ_CFG_OOB_LO_POW, 130 131 DRXJ_CFG_MAX /* dummy, never to be used */}; 132 133 /** 134 * /struct enum drxj_cfg_smart_ant_io * smart antenna i/o. 135 */ 136 enum drxj_cfg_smart_ant_io { 137 DRXJ_SMT_ANT_OUTPUT = 0, 138 DRXJ_SMT_ANT_INPUT 139 }; 140 141 /** 142 * /struct struct drxj_cfg_smart_ant * Set smart antenna. 143 */ 144 struct drxj_cfg_smart_ant { 145 enum drxj_cfg_smart_ant_io io; 146 u16 ctrl_data; 147 }; 148 149 /** 150 * /struct DRXJAGCSTATUS_t 151 * AGC status information from the DRXJ-IQM-AF. 152 */ 153 struct drxj_agc_status { 154 u16 IFAGC; 155 u16 RFAGC; 156 u16 digital_agc; 157 }; 158 159 /* DRXJ_CFG_AGC_RF, DRXJ_CFG_AGC_IF */ 160 161 /** 162 * /struct enum drxj_agc_ctrl_mode * Available AGCs modes in the DRXJ. 163 */ 164 enum drxj_agc_ctrl_mode { 165 DRX_AGC_CTRL_AUTO = 0, 166 DRX_AGC_CTRL_USER, 167 DRX_AGC_CTRL_OFF}; 168 169 /** 170 * /struct struct drxj_cfg_agc * Generic interface for all AGCs present on the DRXJ. 171 */ 172 struct drxj_cfg_agc { 173 enum drx_standard standard; /* standard for which these settings apply */ 174 enum drxj_agc_ctrl_mode ctrl_mode; /* off, user, auto */ 175 u16 output_level; /* range dependent on AGC */ 176 u16 min_output_level; /* range dependent on AGC */ 177 u16 max_output_level; /* range dependent on AGC */ 178 u16 speed; /* range dependent on AGC */ 179 u16 top; /* rf-agc take over point */ 180 u16 cut_off_current; /* rf-agc is accelerated if output current 181 is below cut-off current */}; 182 183 /* DRXJ_CFG_PRE_SAW */ 184 185 /** 186 * /struct struct drxj_cfg_pre_saw * Interface to configure pre SAW sense. 187 */ 188 struct drxj_cfg_pre_saw { 189 enum drx_standard standard; /* standard to which these settings apply */ 190 u16 reference; /* pre SAW reference value, range 0 .. 31 */ 191 bool use_pre_saw; /* true algorithms must use pre SAW sense */}; 192 193 /* DRXJ_CFG_AFE_GAIN */ 194 195 /** 196 * /struct struct drxj_cfg_afe_gain * Interface to configure gain of AFE (LNA + PGA). 197 */ 198 struct drxj_cfg_afe_gain { 199 enum drx_standard standard; /* standard to which these settings apply */ 200 u16 gain; /* gain in 0.1 dB steps, DRXJ range 140 .. 335 */}; 201 202 /** 203 * /struct drxjrs_errors 204 * Available failure information in DRXJ_FEC_RS. 205 * 206 * Container for errors that are received in the most recently finished measurment period 207 * 208 */ 209 struct drxjrs_errors { 210 u16 nr_bit_errors; 211 /**< no of pre RS bit errors */ 212 u16 nr_symbol_errors; 213 /**< no of pre RS symbol errors */ 214 u16 nr_packet_errors; 215 /**< no of pre RS packet errors */ 216 u16 nr_failures; 217 /**< no of post RS failures to decode */ 218 u16 nr_snc_par_fail_count; 219 /**< no of post RS bit erros */ 220 }; 221 222 /** 223 * /struct struct drxj_cfg_vsb_misc * symbol error rate 224 */ 225 struct drxj_cfg_vsb_misc { 226 u32 symb_error; 227 /**< symbol error rate sps */}; 228 229 /** 230 * /enum enum drxj_mpeg_output_clock_rate * Mpeg output clock rate. 231 * 232 */ 233 enum drxj_mpeg_start_width { 234 DRXJ_MPEG_START_WIDTH_1CLKCYC, 235 DRXJ_MPEG_START_WIDTH_8CLKCYC}; 236 237 /** 238 * /enum enum drxj_mpeg_output_clock_rate * Mpeg output clock rate. 239 * 240 */ 241 enum drxj_mpeg_output_clock_rate { 242 DRXJ_MPEGOUTPUT_CLOCK_RATE_AUTO, 243 DRXJ_MPEGOUTPUT_CLOCK_RATE_75973K, 244 DRXJ_MPEGOUTPUT_CLOCK_RATE_50625K, 245 DRXJ_MPEGOUTPUT_CLOCK_RATE_37968K, 246 DRXJ_MPEGOUTPUT_CLOCK_RATE_30375K, 247 DRXJ_MPEGOUTPUT_CLOCK_RATE_25313K, 248 DRXJ_MPEGOUTPUT_CLOCK_RATE_21696K}; 249 250 /** 251 * /struct DRXJCfgMisc_t 252 * Change TEI bit of MPEG output 253 * reverse MPEG output bit order 254 * set MPEG output clock rate 255 */ 256 struct drxj_cfg_mpeg_output_misc { 257 bool disable_tei_handling; /**< if true pass (not change) TEI bit */ 258 bool bit_reverse_mpeg_outout; /**< if true, parallel: msb on MD0; serial: lsb out first */ 259 enum drxj_mpeg_output_clock_rate mpeg_output_clock_rate; 260 /**< set MPEG output clock rate that overwirtes the derived one from symbol rate */ 261 enum drxj_mpeg_start_width mpeg_start_width; /**< set MPEG output start width */}; 262 263 /** 264 * /enum enum drxj_xtal_freq * Supported external crystal reference frequency. 265 */ 266 enum drxj_xtal_freq { 267 DRXJ_XTAL_FREQ_RSVD, 268 DRXJ_XTAL_FREQ_27MHZ, 269 DRXJ_XTAL_FREQ_20P25MHZ, 270 DRXJ_XTAL_FREQ_4MHZ}; 271 272 /** 273 * /enum enum drxj_xtal_freq * Supported external crystal reference frequency. 274 */ 275 enum drxji2c_speed { 276 DRXJ_I2C_SPEED_400KBPS, 277 DRXJ_I2C_SPEED_100KBPS}; 278 279 /** 280 * /struct struct drxj_cfg_hw_cfg * Get hw configuration, such as crystal reference frequency, I2C speed, etc... 281 */ 282 struct drxj_cfg_hw_cfg { 283 enum drxj_xtal_freq xtal_freq; 284 /**< crystal reference frequency */ 285 enum drxji2c_speed i2c_speed; 286 /**< 100 or 400 kbps */}; 287 288 /* 289 * DRXJ_CFG_ATV_MISC 290 */ 291 struct drxj_cfg_atv_misc { 292 s16 peak_filter; /* -8 .. 15 */ 293 u16 noise_filter; /* 0 .. 15 */}; 294 295 /* 296 * struct drxj_cfg_oob_misc */ 297 #define DRXJ_OOB_STATE_RESET 0x0 298 #define DRXJ_OOB_STATE_AGN_HUNT 0x1 299 #define DRXJ_OOB_STATE_DGN_HUNT 0x2 300 #define DRXJ_OOB_STATE_AGC_HUNT 0x3 301 #define DRXJ_OOB_STATE_FRQ_HUNT 0x4 302 #define DRXJ_OOB_STATE_PHA_HUNT 0x8 303 #define DRXJ_OOB_STATE_TIM_HUNT 0x10 304 #define DRXJ_OOB_STATE_EQU_HUNT 0x20 305 #define DRXJ_OOB_STATE_EQT_HUNT 0x30 306 #define DRXJ_OOB_STATE_SYNC 0x40 307 308 struct drxj_cfg_oob_misc { 309 struct drxj_agc_status agc; 310 bool eq_lock; 311 bool sym_timing_lock; 312 bool phase_lock; 313 bool freq_lock; 314 bool dig_gain_lock; 315 bool ana_gain_lock; 316 u8 state; 317 }; 318 319 /* 320 * Index of in array of coef 321 */ 322 enum drxj_cfg_oob_lo_power { 323 DRXJ_OOB_LO_POW_MINUS0DB = 0, 324 DRXJ_OOB_LO_POW_MINUS5DB, 325 DRXJ_OOB_LO_POW_MINUS10DB, 326 DRXJ_OOB_LO_POW_MINUS15DB, 327 DRXJ_OOB_LO_POW_MAX}; 328 329 /* 330 * DRXJ_CFG_ATV_EQU_COEF 331 */ 332 struct drxj_cfg_atv_equ_coef { 333 s16 coef0; /* -256 .. 255 */ 334 s16 coef1; /* -256 .. 255 */ 335 s16 coef2; /* -256 .. 255 */ 336 s16 coef3; /* -256 .. 255 */}; 337 338 /* 339 * Index of in array of coef 340 */ 341 enum drxj_coef_array_index { 342 DRXJ_COEF_IDX_MN = 0, 343 DRXJ_COEF_IDX_FM, 344 DRXJ_COEF_IDX_L, 345 DRXJ_COEF_IDX_LP, 346 DRXJ_COEF_IDX_BG, 347 DRXJ_COEF_IDX_DK, 348 DRXJ_COEF_IDX_I, 349 DRXJ_COEF_IDX_MAX}; 350 351 /* 352 * DRXJ_CFG_ATV_OUTPUT 353 */ 354 355 /** 356 * /enum DRXJAttenuation_t 357 * Attenuation setting for SIF AGC. 358 * 359 */ 360 enum drxjsif_attenuation { 361 DRXJ_SIF_ATTENUATION_0DB, 362 DRXJ_SIF_ATTENUATION_3DB, 363 DRXJ_SIF_ATTENUATION_6DB, 364 DRXJ_SIF_ATTENUATION_9DB}; 365 366 /** 367 * /struct struct drxj_cfg_atv_output * SIF attenuation setting. 368 * 369 */ 370 struct drxj_cfg_atv_output { 371 bool enable_cvbs_output; /* true= enabled */ 372 bool enable_sif_output; /* true= enabled */ 373 enum drxjsif_attenuation sif_attenuation; 374 }; 375 376 /* 377 DRXJ_CFG_ATV_AGC_STATUS (get only) 378 */ 379 /* TODO : AFE interface not yet finished, subject to change */ 380 struct drxj_cfg_atv_agc_status { 381 u16 rf_agc_gain; /* 0 .. 877 uA */ 382 u16 if_agc_gain; /* 0 .. 877 uA */ 383 s16 video_agc_gain; /* -75 .. 1972 in 0.1 dB steps */ 384 s16 audio_agc_gain; /* -4 .. 1020 in 0.1 dB steps */ 385 u16 rf_agc_loop_gain; /* 0 .. 7 */ 386 u16 if_agc_loop_gain; /* 0 .. 7 */ 387 u16 video_agc_loop_gain; /* 0 .. 7 */}; 388 389 /*============================================================================*/ 390 /*============================================================================*/ 391 /*== CTRL related data structures ============================================*/ 392 /*============================================================================*/ 393 /*============================================================================*/ 394 395 /* NONE */ 396 397 /*============================================================================*/ 398 /*============================================================================*/ 399 400 /*========================================*/ 401 /** 402 * /struct struct drxj_data * DRXJ specific attributes. 403 * 404 * Global data container for DRXJ specific data. 405 * 406 */ 407 struct drxj_data { 408 /* device capabilties (determined during drx_open()) */ 409 bool has_lna; /**< true if LNA (aka PGA) present */ 410 bool has_oob; /**< true if OOB supported */ 411 bool has_ntsc; /**< true if NTSC supported */ 412 bool has_btsc; /**< true if BTSC supported */ 413 bool has_smatx; /**< true if mat_tx is available */ 414 bool has_smarx; /**< true if mat_rx is available */ 415 bool has_gpio; /**< true if GPIO is available */ 416 bool has_irqn; /**< true if IRQN is available */ 417 /* A1/A2/A... */ 418 u8 mfx; /**< metal fix */ 419 420 /* tuner settings */ 421 bool mirror_freq_spect_oob;/**< tuner inversion (true = tuner mirrors the signal */ 422 423 /* standard/channel settings */ 424 enum drx_standard standard; /**< current standard information */ 425 enum drx_modulation constellation; 426 /**< current constellation */ 427 s32 frequency; /**< center signal frequency in KHz */ 428 enum drx_bandwidth curr_bandwidth; 429 /**< current channel bandwidth */ 430 enum drx_mirror mirror; /**< current channel mirror */ 431 432 /* signal quality information */ 433 u32 fec_bits_desired; /**< BER accounting period */ 434 u16 fec_vd_plen; /**< no of trellis symbols: VD SER measurement period */ 435 u16 qam_vd_prescale; /**< Viterbi Measurement Prescale */ 436 u16 qam_vd_period; /**< Viterbi Measurement period */ 437 u16 fec_rs_plen; /**< defines RS BER measurement period */ 438 u16 fec_rs_prescale; /**< ReedSolomon Measurement Prescale */ 439 u16 fec_rs_period; /**< ReedSolomon Measurement period */ 440 bool reset_pkt_err_acc; /**< Set a flag to reset accumulated packet error */ 441 u16 pkt_err_acc_start; /**< Set a flag to reset accumulated packet error */ 442 443 /* HI configuration */ 444 u16 hi_cfg_timing_div; /**< HI Configure() parameter 2 */ 445 u16 hi_cfg_bridge_delay; /**< HI Configure() parameter 3 */ 446 u16 hi_cfg_wake_up_key; /**< HI Configure() parameter 4 */ 447 u16 hi_cfg_ctrl; /**< HI Configure() parameter 5 */ 448 u16 hi_cfg_transmit; /**< HI Configure() parameter 6 */ 449 450 /* UIO configuartion */ 451 enum drxuio_mode uio_sma_rx_mode;/**< current mode of SmaRx pin */ 452 enum drxuio_mode uio_sma_tx_mode;/**< current mode of SmaTx pin */ 453 enum drxuio_mode uio_gpio_mode; /**< current mode of ASEL pin */ 454 enum drxuio_mode uio_irqn_mode; /**< current mode of IRQN pin */ 455 456 /* IQM fs frequecy shift and inversion */ 457 u32 iqm_fs_rate_ofs; /**< frequency shifter setting after setchannel */ 458 bool pos_image; /**< Ture: positive image */ 459 /* IQM RC frequecy shift */ 460 u32 iqm_rc_rate_ofs; /**< frequency shifter setting after setchannel */ 461 462 /* ATV configuartion */ 463 u32 atv_cfg_changed_flags; /**< flag: flags cfg changes */ 464 s16 atv_top_equ0[DRXJ_COEF_IDX_MAX]; /**< shadow of ATV_TOP_EQU0__A */ 465 s16 atv_top_equ1[DRXJ_COEF_IDX_MAX]; /**< shadow of ATV_TOP_EQU1__A */ 466 s16 atv_top_equ2[DRXJ_COEF_IDX_MAX]; /**< shadow of ATV_TOP_EQU2__A */ 467 s16 atv_top_equ3[DRXJ_COEF_IDX_MAX]; /**< shadow of ATV_TOP_EQU3__A */ 468 bool phase_correction_bypass;/**< flag: true=bypass */ 469 s16 atv_top_vid_peak; /**< shadow of ATV_TOP_VID_PEAK__A */ 470 u16 atv_top_noise_th; /**< shadow of ATV_TOP_NOISE_TH__A */ 471 bool enable_cvbs_output; /**< flag CVBS ouput enable */ 472 bool enable_sif_output; /**< flag SIF ouput enable */ 473 enum drxjsif_attenuation sif_attenuation; 474 /**< current SIF att setting */ 475 /* Agc configuration for QAM and VSB */ 476 struct drxj_cfg_agc qam_rf_agc_cfg; /**< qam RF AGC config */ 477 struct drxj_cfg_agc qam_if_agc_cfg; /**< qam IF AGC config */ 478 struct drxj_cfg_agc vsb_rf_agc_cfg; /**< vsb RF AGC config */ 479 struct drxj_cfg_agc vsb_if_agc_cfg; /**< vsb IF AGC config */ 480 481 /* PGA gain configuration for QAM and VSB */ 482 u16 qam_pga_cfg; /**< qam PGA config */ 483 u16 vsb_pga_cfg; /**< vsb PGA config */ 484 485 /* Pre SAW configuration for QAM and VSB */ 486 struct drxj_cfg_pre_saw qam_pre_saw_cfg; 487 /**< qam pre SAW config */ 488 struct drxj_cfg_pre_saw vsb_pre_saw_cfg; 489 /**< qam pre SAW config */ 490 491 /* Version information */ 492 char v_text[2][12]; /**< allocated text versions */ 493 struct drx_version v_version[2]; /**< allocated versions structs */ 494 struct drx_version_list v_list_elements[2]; 495 /**< allocated version list */ 496 497 /* smart antenna configuration */ 498 bool smart_ant_inverted; 499 500 /* Tracking filter setting for OOB */ 501 u16 oob_trk_filter_cfg[8]; 502 bool oob_power_on; 503 504 /* MPEG static bitrate setting */ 505 u32 mpeg_ts_static_bitrate; /**< bitrate static MPEG output */ 506 bool disable_te_ihandling; /**< MPEG TS TEI handling */ 507 bool bit_reverse_mpeg_outout;/**< MPEG output bit order */ 508 enum drxj_mpeg_output_clock_rate mpeg_output_clock_rate; 509 /**< MPEG output clock rate */ 510 enum drxj_mpeg_start_width mpeg_start_width; 511 /**< MPEG Start width */ 512 513 /* Pre SAW & Agc configuration for ATV */ 514 struct drxj_cfg_pre_saw atv_pre_saw_cfg; 515 /**< atv pre SAW config */ 516 struct drxj_cfg_agc atv_rf_agc_cfg; /**< atv RF AGC config */ 517 struct drxj_cfg_agc atv_if_agc_cfg; /**< atv IF AGC config */ 518 u16 atv_pga_cfg; /**< atv pga config */ 519 520 u32 curr_symbol_rate; 521 522 /* pin-safe mode */ 523 bool pdr_safe_mode; /**< PDR safe mode activated */ 524 u16 pdr_safe_restore_val_gpio; 525 u16 pdr_safe_restore_val_v_sync; 526 u16 pdr_safe_restore_val_sma_rx; 527 u16 pdr_safe_restore_val_sma_tx; 528 529 /* OOB pre-saw value */ 530 u16 oob_pre_saw; 531 enum drxj_cfg_oob_lo_power oob_lo_pow; 532 533 struct drx_aud_data aud_data; 534 /**< audio storage */}; 535 536 /*------------------------------------------------------------------------- 537 Access MACROS 538 -------------------------------------------------------------------------*/ 539 /** 540 * \brief Compilable references to attributes 541 * \param d pointer to demod instance 542 * 543 * Used as main reference to an attribute field. 544 * Can be used by both macro implementation and function implementation. 545 * These macros are defined to avoid duplication of code in macro and function 546 * definitions that handle access of demod common or extended attributes. 547 * 548 */ 549 550 #define DRXJ_ATTR_BTSC_DETECT(d) \ 551 (((struct drxj_data *)(d)->my_ext_attr)->aud_data.btsc_detect) 552 553 /*------------------------------------------------------------------------- 554 DEFINES 555 -------------------------------------------------------------------------*/ 556 557 /** 558 * \def DRXJ_NTSC_CARRIER_FREQ_OFFSET 559 * \brief Offset from picture carrier to centre frequency in kHz, in RF domain 560 * 561 * For NTSC standard. 562 * NTSC channels are listed by their picture carrier frequency (Fpc). 563 * The function DRX_CTRL_SET_CHANNEL requires the centre frequency as input. 564 * In case the tuner module is not used the DRX-J requires that the tuner is 565 * tuned to the centre frequency of the channel: 566 * 567 * Fcentre = Fpc + DRXJ_NTSC_CARRIER_FREQ_OFFSET 568 * 569 */ 570 #define DRXJ_NTSC_CARRIER_FREQ_OFFSET ((s32)(1750)) 571 572 /** 573 * \def DRXJ_PAL_SECAM_BG_CARRIER_FREQ_OFFSET 574 * \brief Offset from picture carrier to centre frequency in kHz, in RF domain 575 * 576 * For PAL/SECAM - BG standard. This define is needed in case the tuner module 577 * is NOT used. PAL/SECAM channels are listed by their picture carrier frequency (Fpc). 578 * The DRX-J requires that the tuner is tuned to: 579 * Fpc + DRXJ_PAL_SECAM_BG_CARRIER_FREQ_OFFSET 580 * 581 * In case the tuner module is used the drxdriver takes care of this. 582 * In case the tuner module is NOT used the application programmer must take 583 * care of this. 584 * 585 */ 586 #define DRXJ_PAL_SECAM_BG_CARRIER_FREQ_OFFSET ((s32)(2375)) 587 588 /** 589 * \def DRXJ_PAL_SECAM_DKIL_CARRIER_FREQ_OFFSET 590 * \brief Offset from picture carrier to centre frequency in kHz, in RF domain 591 * 592 * For PAL/SECAM - DK, I, L standards. This define is needed in case the tuner module 593 * is NOT used. PAL/SECAM channels are listed by their picture carrier frequency (Fpc). 594 * The DRX-J requires that the tuner is tuned to: 595 * Fpc + DRXJ_PAL_SECAM_DKIL_CARRIER_FREQ_OFFSET 596 * 597 * In case the tuner module is used the drxdriver takes care of this. 598 * In case the tuner module is NOT used the application programmer must take 599 * care of this. 600 * 601 */ 602 #define DRXJ_PAL_SECAM_DKIL_CARRIER_FREQ_OFFSET ((s32)(2775)) 603 604 /** 605 * \def DRXJ_PAL_SECAM_LP_CARRIER_FREQ_OFFSET 606 * \brief Offset from picture carrier to centre frequency in kHz, in RF domain 607 * 608 * For PAL/SECAM - LP standard. This define is needed in case the tuner module 609 * is NOT used. PAL/SECAM channels are listed by their picture carrier frequency (Fpc). 610 * The DRX-J requires that the tuner is tuned to: 611 * Fpc + DRXJ_PAL_SECAM_LP_CARRIER_FREQ_OFFSET 612 * 613 * In case the tuner module is used the drxdriver takes care of this. 614 * In case the tuner module is NOT used the application programmer must take 615 * care of this. 616 */ 617 #define DRXJ_PAL_SECAM_LP_CARRIER_FREQ_OFFSET ((s32)(-3255)) 618 619 /** 620 * \def DRXJ_FM_CARRIER_FREQ_OFFSET 621 * \brief Offset from sound carrier to centre frequency in kHz, in RF domain 622 * 623 * For FM standard. 624 * FM channels are listed by their sound carrier frequency (Fsc). 625 * The function DRX_CTRL_SET_CHANNEL requires the Ffm frequency (see below) as 626 * input. 627 * In case the tuner module is not used the DRX-J requires that the tuner is 628 * tuned to the Ffm frequency of the channel. 629 * 630 * Ffm = Fsc + DRXJ_FM_CARRIER_FREQ_OFFSET 631 * 632 */ 633 #define DRXJ_FM_CARRIER_FREQ_OFFSET ((s32)(-3000)) 634 635 /* Revision types -------------------------------------------------------*/ 636 637 #define DRXJ_TYPE_ID (0x3946000DUL) 638 639 /* Macros ---------------------------------------------------------------*/ 640 641 /* Convert OOB lock status to string */ 642 #define DRXJ_STR_OOB_LOCKSTATUS(x) ( \ 643 (x == DRX_NEVER_LOCK) ? "Never" : \ 644 (x == DRX_NOT_LOCKED) ? "No" : \ 645 (x == DRX_LOCKED) ? "Locked" : \ 646 (x == DRX_LOCK_STATE_1) ? "AGC lock" : \ 647 (x == DRX_LOCK_STATE_2) ? "sync lock" : \ 648 "(Invalid)") 649 650 #endif /* __DRXJ_H__ */ 651