1ca3355a9SDevin Heitmueller /* 2ca3355a9SDevin Heitmueller Copyright (c), 2004-2005,2007-2010 Trident Microsystems, Inc. 3ca3355a9SDevin Heitmueller All rights reserved. 4ca3355a9SDevin Heitmueller 5ca3355a9SDevin Heitmueller Redistribution and use in source and binary forms, with or without 6ca3355a9SDevin Heitmueller modification, are permitted provided that the following conditions are met: 7ca3355a9SDevin Heitmueller 8ca3355a9SDevin Heitmueller * Redistributions of source code must retain the above copyright notice, 9ca3355a9SDevin Heitmueller this list of conditions and the following disclaimer. 10ca3355a9SDevin Heitmueller * Redistributions in binary form must reproduce the above copyright notice, 11ca3355a9SDevin Heitmueller this list of conditions and the following disclaimer in the documentation 12ca3355a9SDevin Heitmueller and/or other materials provided with the distribution. 13ca3355a9SDevin Heitmueller * Neither the name of Trident Microsystems nor Hauppauge Computer Works 14ca3355a9SDevin Heitmueller nor the names of its contributors may be used to endorse or promote 15ca3355a9SDevin Heitmueller products derived from this software without specific prior written 16ca3355a9SDevin Heitmueller permission. 17ca3355a9SDevin Heitmueller 18ca3355a9SDevin Heitmueller THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 19ca3355a9SDevin Heitmueller AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20ca3355a9SDevin Heitmueller IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21ca3355a9SDevin Heitmueller ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 22ca3355a9SDevin Heitmueller LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23ca3355a9SDevin Heitmueller CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24ca3355a9SDevin Heitmueller SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25ca3355a9SDevin Heitmueller INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26ca3355a9SDevin Heitmueller CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27ca3355a9SDevin Heitmueller ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28ca3355a9SDevin Heitmueller POSSIBILITY OF SUCH DAMAGE. 29ca3355a9SDevin Heitmueller */ 30ca3355a9SDevin Heitmueller 3138b2df95SDevin Heitmueller /** 3238b2df95SDevin Heitmueller * \file $Id: drxj.h,v 1.132 2009/12/22 12:13:48 danielg Exp $ 3338b2df95SDevin Heitmueller * 3438b2df95SDevin Heitmueller * \brief DRXJ specific header file 3538b2df95SDevin Heitmueller * 3638b2df95SDevin Heitmueller * \author Dragan Savic, Milos Nikolic, Mihajlo Katona, Tao Ding, Paul Janssen 3738b2df95SDevin Heitmueller */ 3838b2df95SDevin Heitmueller 3938b2df95SDevin Heitmueller #ifndef __DRXJ_H__ 4038b2df95SDevin Heitmueller #define __DRXJ_H__ 4138b2df95SDevin Heitmueller /*------------------------------------------------------------------------- 4238b2df95SDevin Heitmueller INCLUDES 4338b2df95SDevin Heitmueller -------------------------------------------------------------------------*/ 4438b2df95SDevin Heitmueller 4538b2df95SDevin Heitmueller #include "drx_driver.h" 4638b2df95SDevin Heitmueller #include "drx_dap_fasi.h" 4738b2df95SDevin Heitmueller 4838b2df95SDevin Heitmueller #ifdef __cplusplus 4938b2df95SDevin Heitmueller extern "C" { 5038b2df95SDevin Heitmueller #endif 5138b2df95SDevin Heitmueller 5238b2df95SDevin Heitmueller /* Check DRX-J specific dap condition */ 5338b2df95SDevin Heitmueller /* Multi master mode and short addr format only will not work. 5438b2df95SDevin Heitmueller RMW, CRC reset, broadcast and switching back to single master mode 5538b2df95SDevin Heitmueller cannot be done with short addr only in multi master mode. */ 5638b2df95SDevin Heitmueller #if ((DRXDAP_SINGLE_MASTER == 0) && (DRXDAPFASI_LONG_ADDR_ALLOWED == 0)) 5738b2df95SDevin Heitmueller #error "Multi master mode and short addressing only is an illegal combination" 5838b2df95SDevin Heitmueller *; /* Generate a fatal compiler error to make sure it stops here, 5938b2df95SDevin Heitmueller this is necesarry because not all compilers stop after a #error. */ 6038b2df95SDevin Heitmueller #endif 6138b2df95SDevin Heitmueller 6238b2df95SDevin Heitmueller /*------------------------------------------------------------------------- 6338b2df95SDevin Heitmueller TYPEDEFS 6438b2df95SDevin Heitmueller -------------------------------------------------------------------------*/ 6538b2df95SDevin Heitmueller /*============================================================================*/ 6638b2df95SDevin Heitmueller /*============================================================================*/ 6738b2df95SDevin Heitmueller /*== code support ============================================================*/ 6838b2df95SDevin Heitmueller /*============================================================================*/ 6938b2df95SDevin Heitmueller /*============================================================================*/ 7038b2df95SDevin Heitmueller 7138b2df95SDevin Heitmueller /*============================================================================*/ 7238b2df95SDevin Heitmueller /*============================================================================*/ 7338b2df95SDevin Heitmueller /*== SCU cmd if =============================================================*/ 7438b2df95SDevin Heitmueller /*============================================================================*/ 7538b2df95SDevin Heitmueller /*============================================================================*/ 7638b2df95SDevin Heitmueller 7738b2df95SDevin Heitmueller typedef struct { 7843a431e4SMauro Carvalho Chehab u16 command; 79443f18d0SMauro Carvalho Chehab /**< Command number */ 8057afe2f0SMauro Carvalho Chehab u16 parameter_len; 81443f18d0SMauro Carvalho Chehab /**< Data length in byte */ 8257afe2f0SMauro Carvalho Chehab u16 result_len; 83443f18d0SMauro Carvalho Chehab /**< result length in byte */ 8443a431e4SMauro Carvalho Chehab u16 *parameter; 85443f18d0SMauro Carvalho Chehab /**< General purpous param */ 8643a431e4SMauro Carvalho Chehab u16 *result; 87443f18d0SMauro Carvalho Chehab /**< General purpous param */ 8857afe2f0SMauro Carvalho Chehab } drxjscu_cmd_t, *p_drxjscu_cmd_t; 8938b2df95SDevin Heitmueller 9038b2df95SDevin Heitmueller /*============================================================================*/ 9138b2df95SDevin Heitmueller /*============================================================================*/ 9238b2df95SDevin Heitmueller /*== CTRL CFG related data structures ========================================*/ 9338b2df95SDevin Heitmueller /*============================================================================*/ 9438b2df95SDevin Heitmueller /*============================================================================*/ 9538b2df95SDevin Heitmueller 9638b2df95SDevin Heitmueller /* extra intermediate lock state for VSB,QAM,NTSC */ 9738b2df95SDevin Heitmueller #define DRXJ_DEMOD_LOCK (DRX_LOCK_STATE_1) 9838b2df95SDevin Heitmueller 9938b2df95SDevin Heitmueller /* OOB lock states */ 10038b2df95SDevin Heitmueller #define DRXJ_OOB_AGC_LOCK (DRX_LOCK_STATE_1) /* analog gain control lock */ 10138b2df95SDevin Heitmueller #define DRXJ_OOB_SYNC_LOCK (DRX_LOCK_STATE_2) /* digital gain control lock */ 10238b2df95SDevin Heitmueller 10338b2df95SDevin Heitmueller /* Intermediate powermodes for DRXJ */ 10438b2df95SDevin Heitmueller #define DRXJ_POWER_DOWN_MAIN_PATH DRX_POWER_MODE_8 10538b2df95SDevin Heitmueller #define DRXJ_POWER_DOWN_CORE DRX_POWER_MODE_9 10638b2df95SDevin Heitmueller #define DRXJ_POWER_DOWN_PLL DRX_POWER_MODE_10 10738b2df95SDevin Heitmueller 10838b2df95SDevin Heitmueller /* supstition for GPIO FNC mux */ 10938b2df95SDevin Heitmueller #define APP_O (0x0000) 11038b2df95SDevin Heitmueller 11138b2df95SDevin Heitmueller /*#define DRX_CTRL_BASE (0x0000)*/ 11238b2df95SDevin Heitmueller 11338b2df95SDevin Heitmueller #define DRXJ_CTRL_CFG_BASE (0x1000) 11438b2df95SDevin Heitmueller typedef enum { 11538b2df95SDevin Heitmueller DRXJ_CFG_AGC_RF = DRXJ_CTRL_CFG_BASE, 11638b2df95SDevin Heitmueller DRXJ_CFG_AGC_IF, 11738b2df95SDevin Heitmueller DRXJ_CFG_AGC_INTERNAL, 11838b2df95SDevin Heitmueller DRXJ_CFG_PRE_SAW, 11938b2df95SDevin Heitmueller DRXJ_CFG_AFE_GAIN, 12038b2df95SDevin Heitmueller DRXJ_CFG_SYMBOL_CLK_OFFSET, 12138b2df95SDevin Heitmueller DRXJ_CFG_ACCUM_CR_RS_CW_ERR, 12238b2df95SDevin Heitmueller DRXJ_CFG_FEC_MERS_SEQ_COUNT, 12338b2df95SDevin Heitmueller DRXJ_CFG_OOB_MISC, 12438b2df95SDevin Heitmueller DRXJ_CFG_SMART_ANT, 12538b2df95SDevin Heitmueller DRXJ_CFG_OOB_PRE_SAW, 12638b2df95SDevin Heitmueller DRXJ_CFG_VSB_MISC, 12738b2df95SDevin Heitmueller DRXJ_CFG_RESET_PACKET_ERR, 12838b2df95SDevin Heitmueller 12938b2df95SDevin Heitmueller /* ATV (FM) */ 13038b2df95SDevin Heitmueller DRXJ_CFG_ATV_OUTPUT, /* also for FM (SIF control) but not likely */ 13138b2df95SDevin Heitmueller DRXJ_CFG_ATV_MISC, 13238b2df95SDevin Heitmueller DRXJ_CFG_ATV_EQU_COEF, 13338b2df95SDevin Heitmueller DRXJ_CFG_ATV_AGC_STATUS, /* also for FM ( IF,RF, audioAGC ) */ 13438b2df95SDevin Heitmueller 13538b2df95SDevin Heitmueller DRXJ_CFG_MPEG_OUTPUT_MISC, 13638b2df95SDevin Heitmueller DRXJ_CFG_HW_CFG, 13738b2df95SDevin Heitmueller DRXJ_CFG_OOB_LO_POW, 13838b2df95SDevin Heitmueller 13938b2df95SDevin Heitmueller DRXJ_CFG_MAX /* dummy, never to be used */ 14057afe2f0SMauro Carvalho Chehab } drxj_cfg_type_t, *pdrxj_cfg_type_t; 14138b2df95SDevin Heitmueller 14238b2df95SDevin Heitmueller /** 14357afe2f0SMauro Carvalho Chehab * /struct drxj_cfg_smart_ant_io_t 14438b2df95SDevin Heitmueller * smart antenna i/o. 14538b2df95SDevin Heitmueller */ 14657afe2f0SMauro Carvalho Chehab typedef enum drxj_cfg_smart_ant_io_t { 14738b2df95SDevin Heitmueller DRXJ_SMT_ANT_OUTPUT = 0, 14838b2df95SDevin Heitmueller DRXJ_SMT_ANT_INPUT 14957afe2f0SMauro Carvalho Chehab } drxj_cfg_smart_ant_io_t, *pdrxj_cfg_smart_ant_io_t; 15038b2df95SDevin Heitmueller 15138b2df95SDevin Heitmueller /** 15257afe2f0SMauro Carvalho Chehab * /struct drxj_cfg_smart_ant_t 15338b2df95SDevin Heitmueller * Set smart antenna. 15438b2df95SDevin Heitmueller */ 15538b2df95SDevin Heitmueller typedef struct { 15657afe2f0SMauro Carvalho Chehab drxj_cfg_smart_ant_io_t io; 15757afe2f0SMauro Carvalho Chehab u16 ctrl_data; 15857afe2f0SMauro Carvalho Chehab } drxj_cfg_smart_ant_t, *p_drxj_cfg_smart_ant_t; 15938b2df95SDevin Heitmueller 16038b2df95SDevin Heitmueller /** 16138b2df95SDevin Heitmueller * /struct DRXJAGCSTATUS_t 16238b2df95SDevin Heitmueller * AGC status information from the DRXJ-IQM-AF. 16338b2df95SDevin Heitmueller */ 16438b2df95SDevin Heitmueller typedef struct { 16543a431e4SMauro Carvalho Chehab u16 IFAGC; 16643a431e4SMauro Carvalho Chehab u16 RFAGC; 16757afe2f0SMauro Carvalho Chehab u16 digital_agc; 16857afe2f0SMauro Carvalho Chehab } drxj_agc_status_t, *pdrxj_agc_status_t; 16938b2df95SDevin Heitmueller 17038b2df95SDevin Heitmueller /* DRXJ_CFG_AGC_RF, DRXJ_CFG_AGC_IF */ 17138b2df95SDevin Heitmueller 17238b2df95SDevin Heitmueller /** 17357afe2f0SMauro Carvalho Chehab * /struct drxj_agc_ctrl_mode_t 17438b2df95SDevin Heitmueller * Available AGCs modes in the DRXJ. 17538b2df95SDevin Heitmueller */ 17638b2df95SDevin Heitmueller typedef enum { 17738b2df95SDevin Heitmueller DRX_AGC_CTRL_AUTO = 0, 17838b2df95SDevin Heitmueller DRX_AGC_CTRL_USER, 17938b2df95SDevin Heitmueller DRX_AGC_CTRL_OFF 18057afe2f0SMauro Carvalho Chehab } drxj_agc_ctrl_mode_t, *pdrxj_agc_ctrl_mode_t; 18138b2df95SDevin Heitmueller 18238b2df95SDevin Heitmueller /** 18357afe2f0SMauro Carvalho Chehab * /struct drxj_cfg_agc_t 18438b2df95SDevin Heitmueller * Generic interface for all AGCs present on the DRXJ. 18538b2df95SDevin Heitmueller */ 18638b2df95SDevin Heitmueller typedef struct { 18761263c75SMauro Carvalho Chehab enum drx_standard standard; /* standard for which these settings apply */ 18857afe2f0SMauro Carvalho Chehab drxj_agc_ctrl_mode_t ctrl_mode; /* off, user, auto */ 18957afe2f0SMauro Carvalho Chehab u16 output_level; /* range dependent on AGC */ 19057afe2f0SMauro Carvalho Chehab u16 min_output_level; /* range dependent on AGC */ 19157afe2f0SMauro Carvalho Chehab u16 max_output_level; /* range dependent on AGC */ 19243a431e4SMauro Carvalho Chehab u16 speed; /* range dependent on AGC */ 19343a431e4SMauro Carvalho Chehab u16 top; /* rf-agc take over point */ 19457afe2f0SMauro Carvalho Chehab u16 cut_off_current; /* rf-agc is accelerated if output current 19538b2df95SDevin Heitmueller is below cut-off current */ 19657afe2f0SMauro Carvalho Chehab } drxj_cfg_agc_t, *p_drxj_cfg_agc_t; 19738b2df95SDevin Heitmueller 19838b2df95SDevin Heitmueller /* DRXJ_CFG_PRE_SAW */ 19938b2df95SDevin Heitmueller 20038b2df95SDevin Heitmueller /** 20157afe2f0SMauro Carvalho Chehab * /struct drxj_cfg_pre_saw_t 20238b2df95SDevin Heitmueller * Interface to configure pre SAW sense. 20338b2df95SDevin Heitmueller */ 20438b2df95SDevin Heitmueller typedef struct { 20561263c75SMauro Carvalho Chehab enum drx_standard standard; /* standard to which these settings apply */ 20643a431e4SMauro Carvalho Chehab u16 reference; /* pre SAW reference value, range 0 .. 31 */ 20757afe2f0SMauro Carvalho Chehab bool use_pre_saw; /* true algorithms must use pre SAW sense */ 20857afe2f0SMauro Carvalho Chehab } drxj_cfg_pre_saw_t, *p_drxj_cfg_pre_saw_t; 20938b2df95SDevin Heitmueller 21038b2df95SDevin Heitmueller /* DRXJ_CFG_AFE_GAIN */ 21138b2df95SDevin Heitmueller 21238b2df95SDevin Heitmueller /** 21357afe2f0SMauro Carvalho Chehab * /struct drxj_cfg_afe_gain_t 21438b2df95SDevin Heitmueller * Interface to configure gain of AFE (LNA + PGA). 21538b2df95SDevin Heitmueller */ 21638b2df95SDevin Heitmueller typedef struct { 21761263c75SMauro Carvalho Chehab enum drx_standard standard; /* standard to which these settings apply */ 21843a431e4SMauro Carvalho Chehab u16 gain; /* gain in 0.1 dB steps, DRXJ range 140 .. 335 */ 21957afe2f0SMauro Carvalho Chehab } drxj_cfg_afe_gain_t, *p_drxj_cfg_afe_gain_t; 22038b2df95SDevin Heitmueller 22138b2df95SDevin Heitmueller /** 22257afe2f0SMauro Carvalho Chehab * /struct DRXJrs_errors_t 22338b2df95SDevin Heitmueller * Available failure information in DRXJ_FEC_RS. 22438b2df95SDevin Heitmueller * 22538b2df95SDevin Heitmueller * Container for errors that are received in the most recently finished measurment period 22638b2df95SDevin Heitmueller * 22738b2df95SDevin Heitmueller */ 22838b2df95SDevin Heitmueller typedef struct { 22957afe2f0SMauro Carvalho Chehab u16 nr_bit_errors; 230443f18d0SMauro Carvalho Chehab /**< no of pre RS bit errors */ 23157afe2f0SMauro Carvalho Chehab u16 nr_symbol_errors; 232443f18d0SMauro Carvalho Chehab /**< no of pre RS symbol errors */ 23357afe2f0SMauro Carvalho Chehab u16 nr_packet_errors; 234443f18d0SMauro Carvalho Chehab /**< no of pre RS packet errors */ 23557afe2f0SMauro Carvalho Chehab u16 nr_failures; 236443f18d0SMauro Carvalho Chehab /**< no of post RS failures to decode */ 23757afe2f0SMauro Carvalho Chehab u16 nr_snc_par_fail_count; 238443f18d0SMauro Carvalho Chehab /**< no of post RS bit erros */ 23957afe2f0SMauro Carvalho Chehab } DRXJrs_errors_t, *p_drxjrs_errors_t; 24038b2df95SDevin Heitmueller 24138b2df95SDevin Heitmueller /** 24257afe2f0SMauro Carvalho Chehab * /struct drxj_cfg_vsb_misc_t 24338b2df95SDevin Heitmueller * symbol error rate 24438b2df95SDevin Heitmueller */ 24538b2df95SDevin Heitmueller typedef struct { 24657afe2f0SMauro Carvalho Chehab u32 symb_error; 247443f18d0SMauro Carvalho Chehab /**< symbol error rate sps */ 24857afe2f0SMauro Carvalho Chehab } drxj_cfg_vsb_misc_t, *p_drxj_cfg_vsb_misc_t; 24938b2df95SDevin Heitmueller 25038b2df95SDevin Heitmueller /** 25157afe2f0SMauro Carvalho Chehab * /enum drxj_mpeg_output_clock_rate_t 25238b2df95SDevin Heitmueller * Mpeg output clock rate. 25338b2df95SDevin Heitmueller * 25438b2df95SDevin Heitmueller */ 25538b2df95SDevin Heitmueller typedef enum { 25638b2df95SDevin Heitmueller DRXJ_MPEG_START_WIDTH_1CLKCYC, 25738b2df95SDevin Heitmueller DRXJ_MPEG_START_WIDTH_8CLKCYC 25857afe2f0SMauro Carvalho Chehab } drxj_mpeg_start_width_t, *pdrxj_mpeg_start_width_t; 25938b2df95SDevin Heitmueller 26038b2df95SDevin Heitmueller /** 26157afe2f0SMauro Carvalho Chehab * /enum drxj_mpeg_output_clock_rate_t 26238b2df95SDevin Heitmueller * Mpeg output clock rate. 26338b2df95SDevin Heitmueller * 26438b2df95SDevin Heitmueller */ 26538b2df95SDevin Heitmueller typedef enum { 26638b2df95SDevin Heitmueller DRXJ_MPEGOUTPUT_CLOCK_RATE_AUTO, 26738b2df95SDevin Heitmueller DRXJ_MPEGOUTPUT_CLOCK_RATE_75973K, 26838b2df95SDevin Heitmueller DRXJ_MPEGOUTPUT_CLOCK_RATE_50625K, 26938b2df95SDevin Heitmueller DRXJ_MPEGOUTPUT_CLOCK_RATE_37968K, 27038b2df95SDevin Heitmueller DRXJ_MPEGOUTPUT_CLOCK_RATE_30375K, 27138b2df95SDevin Heitmueller DRXJ_MPEGOUTPUT_CLOCK_RATE_25313K, 27238b2df95SDevin Heitmueller DRXJ_MPEGOUTPUT_CLOCK_RATE_21696K 27357afe2f0SMauro Carvalho Chehab } drxj_mpeg_output_clock_rate_t, *pdrxj_mpeg_output_clock_rate_t; 27438b2df95SDevin Heitmueller 27538b2df95SDevin Heitmueller /** 27638b2df95SDevin Heitmueller * /struct DRXJCfgMisc_t 27738b2df95SDevin Heitmueller * Change TEI bit of MPEG output 27838b2df95SDevin Heitmueller * reverse MPEG output bit order 27938b2df95SDevin Heitmueller * set MPEG output clock rate 28038b2df95SDevin Heitmueller */ 28138b2df95SDevin Heitmueller typedef struct { 28257afe2f0SMauro Carvalho Chehab bool disable_tei_handling; /**< if true pass (not change) TEI bit */ 28357afe2f0SMauro Carvalho Chehab bool bit_reverse_mpeg_outout; /**< if true, parallel: msb on MD0; serial: lsb out first */ 28457afe2f0SMauro Carvalho Chehab drxj_mpeg_output_clock_rate_t mpeg_output_clock_rate; 285443f18d0SMauro Carvalho Chehab /**< set MPEG output clock rate that overwirtes the derived one from symbol rate */ 28657afe2f0SMauro Carvalho Chehab drxj_mpeg_start_width_t mpeg_start_width; /**< set MPEG output start width */ 28757afe2f0SMauro Carvalho Chehab } drxj_cfg_mpeg_output_misc_t, *p_drxj_cfg_mpeg_output_misc_t; 28838b2df95SDevin Heitmueller 28938b2df95SDevin Heitmueller /** 29057afe2f0SMauro Carvalho Chehab * /enum drxj_xtal_freq_t 29138b2df95SDevin Heitmueller * Supported external crystal reference frequency. 29238b2df95SDevin Heitmueller */ 29338b2df95SDevin Heitmueller typedef enum { 29438b2df95SDevin Heitmueller DRXJ_XTAL_FREQ_RSVD, 29538b2df95SDevin Heitmueller DRXJ_XTAL_FREQ_27MHZ, 29638b2df95SDevin Heitmueller DRXJ_XTAL_FREQ_20P25MHZ, 29738b2df95SDevin Heitmueller DRXJ_XTAL_FREQ_4MHZ 29857afe2f0SMauro Carvalho Chehab } drxj_xtal_freq_t, *pdrxj_xtal_freq_t; 29938b2df95SDevin Heitmueller 30038b2df95SDevin Heitmueller /** 30157afe2f0SMauro Carvalho Chehab * /enum drxj_xtal_freq_t 30238b2df95SDevin Heitmueller * Supported external crystal reference frequency. 30338b2df95SDevin Heitmueller */ 30438b2df95SDevin Heitmueller typedef enum { 30538b2df95SDevin Heitmueller DRXJ_I2C_SPEED_400KBPS, 30638b2df95SDevin Heitmueller DRXJ_I2C_SPEED_100KBPS 30757afe2f0SMauro Carvalho Chehab } drxji2c_speed_t, *pdrxji2c_speed_t; 30838b2df95SDevin Heitmueller 30938b2df95SDevin Heitmueller /** 31057afe2f0SMauro Carvalho Chehab * /struct drxj_cfg_hw_cfg_t 31138b2df95SDevin Heitmueller * Get hw configuration, such as crystal reference frequency, I2C speed, etc... 31238b2df95SDevin Heitmueller */ 31338b2df95SDevin Heitmueller typedef struct { 31457afe2f0SMauro Carvalho Chehab drxj_xtal_freq_t xtal_freq; 315443f18d0SMauro Carvalho Chehab /**< crystal reference frequency */ 31657afe2f0SMauro Carvalho Chehab drxji2c_speed_t i2c_speed; 317443f18d0SMauro Carvalho Chehab /**< 100 or 400 kbps */ 31857afe2f0SMauro Carvalho Chehab } drxj_cfg_hw_cfg_t, *p_drxj_cfg_hw_cfg_t; 31938b2df95SDevin Heitmueller 32038b2df95SDevin Heitmueller /* 32138b2df95SDevin Heitmueller * DRXJ_CFG_ATV_MISC 32238b2df95SDevin Heitmueller */ 32338b2df95SDevin Heitmueller typedef struct { 32457afe2f0SMauro Carvalho Chehab s16 peak_filter; /* -8 .. 15 */ 32557afe2f0SMauro Carvalho Chehab u16 noise_filter; /* 0 .. 15 */ 32657afe2f0SMauro Carvalho Chehab } drxj_cfg_atv_misc_t, *p_drxj_cfg_atv_misc_t; 32738b2df95SDevin Heitmueller 32838b2df95SDevin Heitmueller /* 32957afe2f0SMauro Carvalho Chehab * drxj_cfg_oob_misc_t 33038b2df95SDevin Heitmueller */ 33138b2df95SDevin Heitmueller #define DRXJ_OOB_STATE_RESET 0x0 33238b2df95SDevin Heitmueller #define DRXJ_OOB_STATE_AGN_HUNT 0x1 33338b2df95SDevin Heitmueller #define DRXJ_OOB_STATE_DGN_HUNT 0x2 33438b2df95SDevin Heitmueller #define DRXJ_OOB_STATE_AGC_HUNT 0x3 33538b2df95SDevin Heitmueller #define DRXJ_OOB_STATE_FRQ_HUNT 0x4 33638b2df95SDevin Heitmueller #define DRXJ_OOB_STATE_PHA_HUNT 0x8 33738b2df95SDevin Heitmueller #define DRXJ_OOB_STATE_TIM_HUNT 0x10 33838b2df95SDevin Heitmueller #define DRXJ_OOB_STATE_EQU_HUNT 0x20 33938b2df95SDevin Heitmueller #define DRXJ_OOB_STATE_EQT_HUNT 0x30 34038b2df95SDevin Heitmueller #define DRXJ_OOB_STATE_SYNC 0x40 34138b2df95SDevin Heitmueller 34238b2df95SDevin Heitmueller typedef struct { 34357afe2f0SMauro Carvalho Chehab drxj_agc_status_t agc; 34457afe2f0SMauro Carvalho Chehab bool eq_lock; 34557afe2f0SMauro Carvalho Chehab bool sym_timing_lock; 34657afe2f0SMauro Carvalho Chehab bool phase_lock; 34757afe2f0SMauro Carvalho Chehab bool freq_lock; 34857afe2f0SMauro Carvalho Chehab bool dig_gain_lock; 34957afe2f0SMauro Carvalho Chehab bool ana_gain_lock; 35043a431e4SMauro Carvalho Chehab u8 state; 35157afe2f0SMauro Carvalho Chehab } drxj_cfg_oob_misc_t, *p_drxj_cfg_oob_misc_t; 35238b2df95SDevin Heitmueller 35338b2df95SDevin Heitmueller /* 35438b2df95SDevin Heitmueller * Index of in array of coef 35538b2df95SDevin Heitmueller */ 35638b2df95SDevin Heitmueller typedef enum { 35738b2df95SDevin Heitmueller DRXJ_OOB_LO_POW_MINUS0DB = 0, 35838b2df95SDevin Heitmueller DRXJ_OOB_LO_POW_MINUS5DB, 35938b2df95SDevin Heitmueller DRXJ_OOB_LO_POW_MINUS10DB, 36038b2df95SDevin Heitmueller DRXJ_OOB_LO_POW_MINUS15DB, 36138b2df95SDevin Heitmueller DRXJ_OOB_LO_POW_MAX 36257afe2f0SMauro Carvalho Chehab } drxj_cfg_oob_lo_power_t, *p_drxj_cfg_oob_lo_power_t; 36338b2df95SDevin Heitmueller 36438b2df95SDevin Heitmueller /* 36538b2df95SDevin Heitmueller * DRXJ_CFG_ATV_EQU_COEF 36638b2df95SDevin Heitmueller */ 36738b2df95SDevin Heitmueller typedef struct { 36843a431e4SMauro Carvalho Chehab s16 coef0; /* -256 .. 255 */ 36943a431e4SMauro Carvalho Chehab s16 coef1; /* -256 .. 255 */ 37043a431e4SMauro Carvalho Chehab s16 coef2; /* -256 .. 255 */ 37143a431e4SMauro Carvalho Chehab s16 coef3; /* -256 .. 255 */ 37257afe2f0SMauro Carvalho Chehab } drxj_cfg_atv_equ_coef_t, *p_drxj_cfg_atv_equ_coef_t; 37338b2df95SDevin Heitmueller 37438b2df95SDevin Heitmueller /* 37538b2df95SDevin Heitmueller * Index of in array of coef 37638b2df95SDevin Heitmueller */ 37738b2df95SDevin Heitmueller typedef enum { 37838b2df95SDevin Heitmueller DRXJ_COEF_IDX_MN = 0, 37938b2df95SDevin Heitmueller DRXJ_COEF_IDX_FM, 38038b2df95SDevin Heitmueller DRXJ_COEF_IDX_L, 38138b2df95SDevin Heitmueller DRXJ_COEF_IDX_LP, 38238b2df95SDevin Heitmueller DRXJ_COEF_IDX_BG, 38338b2df95SDevin Heitmueller DRXJ_COEF_IDX_DK, 38438b2df95SDevin Heitmueller DRXJ_COEF_IDX_I, 38538b2df95SDevin Heitmueller DRXJ_COEF_IDX_MAX 38657afe2f0SMauro Carvalho Chehab } drxj_coef_array_index_t, *pdrxj_coef_array_index_t; 38738b2df95SDevin Heitmueller 38838b2df95SDevin Heitmueller /* 38938b2df95SDevin Heitmueller * DRXJ_CFG_ATV_OUTPUT 39038b2df95SDevin Heitmueller */ 39138b2df95SDevin Heitmueller 39238b2df95SDevin Heitmueller /** 39338b2df95SDevin Heitmueller * /enum DRXJAttenuation_t 39438b2df95SDevin Heitmueller * Attenuation setting for SIF AGC. 39538b2df95SDevin Heitmueller * 39638b2df95SDevin Heitmueller */ 39738b2df95SDevin Heitmueller typedef enum { 39838b2df95SDevin Heitmueller DRXJ_SIF_ATTENUATION_0DB, 39938b2df95SDevin Heitmueller DRXJ_SIF_ATTENUATION_3DB, 40038b2df95SDevin Heitmueller DRXJ_SIF_ATTENUATION_6DB, 40138b2df95SDevin Heitmueller DRXJ_SIF_ATTENUATION_9DB 40257afe2f0SMauro Carvalho Chehab } drxjsif_attenuation_t, *pdrxjsif_attenuation_t; 40338b2df95SDevin Heitmueller 40438b2df95SDevin Heitmueller /** 40557afe2f0SMauro Carvalho Chehab * /struct drxj_cfg_atv_output_t 40638b2df95SDevin Heitmueller * SIF attenuation setting. 40738b2df95SDevin Heitmueller * 40838b2df95SDevin Heitmueller */ 40938b2df95SDevin Heitmueller typedef struct { 41057afe2f0SMauro Carvalho Chehab bool enable_cvbs_output; /* true= enabled */ 41157afe2f0SMauro Carvalho Chehab bool enable_sif_output; /* true= enabled */ 41257afe2f0SMauro Carvalho Chehab drxjsif_attenuation_t sif_attenuation; 41357afe2f0SMauro Carvalho Chehab } drxj_cfg_atv_output_t, *p_drxj_cfg_atv_output_t; 41438b2df95SDevin Heitmueller 41538b2df95SDevin Heitmueller /* 41638b2df95SDevin Heitmueller DRXJ_CFG_ATV_AGC_STATUS (get only) 41738b2df95SDevin Heitmueller */ 41838b2df95SDevin Heitmueller /* TODO : AFE interface not yet finished, subject to change */ 41938b2df95SDevin Heitmueller typedef struct { 42057afe2f0SMauro Carvalho Chehab u16 rf_agc_gain; /* 0 .. 877 uA */ 42157afe2f0SMauro Carvalho Chehab u16 if_agc_gain; /* 0 .. 877 uA */ 42257afe2f0SMauro Carvalho Chehab s16 video_agc_gain; /* -75 .. 1972 in 0.1 dB steps */ 42357afe2f0SMauro Carvalho Chehab s16 audio_agc_gain; /* -4 .. 1020 in 0.1 dB steps */ 42457afe2f0SMauro Carvalho Chehab u16 rf_agc_loop_gain; /* 0 .. 7 */ 42557afe2f0SMauro Carvalho Chehab u16 if_agc_loop_gain; /* 0 .. 7 */ 42657afe2f0SMauro Carvalho Chehab u16 video_agc_loop_gain; /* 0 .. 7 */ 42757afe2f0SMauro Carvalho Chehab } drxj_cfg_atv_agc_status_t, *p_drxj_cfg_atv_agc_status_t; 42838b2df95SDevin Heitmueller 42938b2df95SDevin Heitmueller /*============================================================================*/ 43038b2df95SDevin Heitmueller /*============================================================================*/ 43138b2df95SDevin Heitmueller /*== CTRL related data structures ============================================*/ 43238b2df95SDevin Heitmueller /*============================================================================*/ 43338b2df95SDevin Heitmueller /*============================================================================*/ 43438b2df95SDevin Heitmueller 43538b2df95SDevin Heitmueller /* NONE */ 43638b2df95SDevin Heitmueller 43738b2df95SDevin Heitmueller /*============================================================================*/ 43838b2df95SDevin Heitmueller /*============================================================================*/ 43938b2df95SDevin Heitmueller 44038b2df95SDevin Heitmueller /*========================================*/ 44138b2df95SDevin Heitmueller /** 44257afe2f0SMauro Carvalho Chehab * /struct drxj_data_t 44338b2df95SDevin Heitmueller * DRXJ specific attributes. 44438b2df95SDevin Heitmueller * 44538b2df95SDevin Heitmueller * Global data container for DRXJ specific data. 44638b2df95SDevin Heitmueller * 44738b2df95SDevin Heitmueller */ 44838b2df95SDevin Heitmueller typedef struct { 44957afe2f0SMauro Carvalho Chehab /* device capabilties (determined during drx_open()) */ 45057afe2f0SMauro Carvalho Chehab bool has_lna; /**< true if LNA (aka PGA) present */ 45157afe2f0SMauro Carvalho Chehab bool has_oob; /**< true if OOB supported */ 45257afe2f0SMauro Carvalho Chehab bool has_ntsc; /**< true if NTSC supported */ 45357afe2f0SMauro Carvalho Chehab bool has_btsc; /**< true if BTSC supported */ 45457afe2f0SMauro Carvalho Chehab bool has_smatx; /**< true if mat_tx is available */ 45557afe2f0SMauro Carvalho Chehab bool has_smarx; /**< true if mat_rx is available */ 45657afe2f0SMauro Carvalho Chehab bool has_gpio; /**< true if GPIO is available */ 45757afe2f0SMauro Carvalho Chehab bool has_irqn; /**< true if IRQN is available */ 45838b2df95SDevin Heitmueller /* A1/A2/A... */ 45943a431e4SMauro Carvalho Chehab u8 mfx; /**< metal fix */ 46038b2df95SDevin Heitmueller 46138b2df95SDevin Heitmueller /* tuner settings */ 46257afe2f0SMauro Carvalho Chehab bool mirror_freq_spectOOB;/**< tuner inversion (true = tuner mirrors the signal */ 46338b2df95SDevin Heitmueller 46438b2df95SDevin Heitmueller /* standard/channel settings */ 46561263c75SMauro Carvalho Chehab enum drx_standard standard; /**< current standard information */ 46661263c75SMauro Carvalho Chehab enum drx_modulation constellation; 467443f18d0SMauro Carvalho Chehab /**< current constellation */ 46873f7065bSMauro Carvalho Chehab s32 frequency; /**< center signal frequency in KHz */ 46957afe2f0SMauro Carvalho Chehab enum drx_bandwidth curr_bandwidth; 470443f18d0SMauro Carvalho Chehab /**< current channel bandwidth */ 47161263c75SMauro Carvalho Chehab enum drx_mirror mirror; /**< current channel mirror */ 47238b2df95SDevin Heitmueller 47338b2df95SDevin Heitmueller /* signal quality information */ 47457afe2f0SMauro Carvalho Chehab u32 fec_bits_desired; /**< BER accounting period */ 47557afe2f0SMauro Carvalho Chehab u16 fec_vd_plen; /**< no of trellis symbols: VD SER measurement period */ 47657afe2f0SMauro Carvalho Chehab u16 qam_vd_prescale; /**< Viterbi Measurement Prescale */ 47757afe2f0SMauro Carvalho Chehab u16 qam_vd_period; /**< Viterbi Measurement period */ 47857afe2f0SMauro Carvalho Chehab u16 fec_rs_plen; /**< defines RS BER measurement period */ 47957afe2f0SMauro Carvalho Chehab u16 fec_rs_prescale; /**< ReedSolomon Measurement Prescale */ 48057afe2f0SMauro Carvalho Chehab u16 fec_rs_period; /**< ReedSolomon Measurement period */ 48157afe2f0SMauro Carvalho Chehab bool reset_pkt_err_acc; /**< Set a flag to reset accumulated packet error */ 48257afe2f0SMauro Carvalho Chehab u16 pkt_errAccStart; /**< Set a flag to reset accumulated packet error */ 48338b2df95SDevin Heitmueller 48438b2df95SDevin Heitmueller /* HI configuration */ 48557afe2f0SMauro Carvalho Chehab u16 hi_cfg_timing_div; /**< HI Configure() parameter 2 */ 48657afe2f0SMauro Carvalho Chehab u16 hi_cfg_bridge_delay; /**< HI Configure() parameter 3 */ 48757afe2f0SMauro Carvalho Chehab u16 hi_cfg_wake_up_key; /**< HI Configure() parameter 4 */ 48857afe2f0SMauro Carvalho Chehab u16 hi_cfg_ctrl; /**< HI Configure() parameter 5 */ 48957afe2f0SMauro Carvalho Chehab u16 hi_cfg_transmit; /**< HI Configure() parameter 6 */ 49038b2df95SDevin Heitmueller 49138b2df95SDevin Heitmueller /* UIO configuartion */ 492*1bfc9e15SMauro Carvalho Chehab enum drxuio_mode uio_sma_rx_mode;/**< current mode of SmaRx pin */ 493*1bfc9e15SMauro Carvalho Chehab enum drxuio_mode uio_sma_tx_mode;/**< current mode of SmaTx pin */ 494*1bfc9e15SMauro Carvalho Chehab enum drxuio_mode uio_gpio_mode; /**< current mode of ASEL pin */ 495*1bfc9e15SMauro Carvalho Chehab enum drxuio_mode uio_irqn_mode; /**< current mode of IRQN pin */ 49638b2df95SDevin Heitmueller 49738b2df95SDevin Heitmueller /* IQM fs frequecy shift and inversion */ 49857afe2f0SMauro Carvalho Chehab u32 iqm_fs_rate_ofs; /**< frequency shifter setting after setchannel */ 49957afe2f0SMauro Carvalho Chehab bool pos_image; /**< Ture: positive image */ 50038b2df95SDevin Heitmueller /* IQM RC frequecy shift */ 50157afe2f0SMauro Carvalho Chehab u32 iqm_rc_rate_ofs; /**< frequency shifter setting after setchannel */ 50238b2df95SDevin Heitmueller 50338b2df95SDevin Heitmueller /* ATV configuartion */ 50457afe2f0SMauro Carvalho Chehab u32 atv_cfg_changed_flags; /**< flag: flags cfg changes */ 50557afe2f0SMauro Carvalho Chehab s16 atv_top_equ0[DRXJ_COEF_IDX_MAX]; /**< shadow of ATV_TOP_EQU0__A */ 50657afe2f0SMauro Carvalho Chehab s16 atv_top_equ1[DRXJ_COEF_IDX_MAX]; /**< shadow of ATV_TOP_EQU1__A */ 50757afe2f0SMauro Carvalho Chehab s16 atv_top_equ2[DRXJ_COEF_IDX_MAX]; /**< shadow of ATV_TOP_EQU2__A */ 50857afe2f0SMauro Carvalho Chehab s16 atv_top_equ3[DRXJ_COEF_IDX_MAX]; /**< shadow of ATV_TOP_EQU3__A */ 50957afe2f0SMauro Carvalho Chehab bool phase_correction_bypass;/**< flag: true=bypass */ 51057afe2f0SMauro Carvalho Chehab s16 atv_top_vid_peak; /**< shadow of ATV_TOP_VID_PEAK__A */ 51157afe2f0SMauro Carvalho Chehab u16 atv_top_noise_th; /**< shadow of ATV_TOP_NOISE_TH__A */ 51257afe2f0SMauro Carvalho Chehab bool enable_cvbs_output; /**< flag CVBS ouput enable */ 51357afe2f0SMauro Carvalho Chehab bool enable_sif_output; /**< flag SIF ouput enable */ 51457afe2f0SMauro Carvalho Chehab drxjsif_attenuation_t sif_attenuation; 515443f18d0SMauro Carvalho Chehab /**< current SIF att setting */ 51638b2df95SDevin Heitmueller /* Agc configuration for QAM and VSB */ 51757afe2f0SMauro Carvalho Chehab drxj_cfg_agc_t qam_rf_agc_cfg; /**< qam RF AGC config */ 51857afe2f0SMauro Carvalho Chehab drxj_cfg_agc_t qam_if_agc_cfg; /**< qam IF AGC config */ 51957afe2f0SMauro Carvalho Chehab drxj_cfg_agc_t vsb_rf_agc_cfg; /**< vsb RF AGC config */ 52057afe2f0SMauro Carvalho Chehab drxj_cfg_agc_t vsb_if_agc_cfg; /**< vsb IF AGC config */ 52138b2df95SDevin Heitmueller 52238b2df95SDevin Heitmueller /* PGA gain configuration for QAM and VSB */ 52357afe2f0SMauro Carvalho Chehab u16 qam_pga_cfg; /**< qam PGA config */ 52457afe2f0SMauro Carvalho Chehab u16 vsb_pga_cfg; /**< vsb PGA config */ 52538b2df95SDevin Heitmueller 52638b2df95SDevin Heitmueller /* Pre SAW configuration for QAM and VSB */ 52757afe2f0SMauro Carvalho Chehab drxj_cfg_pre_saw_t qam_pre_saw_cfg; 528443f18d0SMauro Carvalho Chehab /**< qam pre SAW config */ 52957afe2f0SMauro Carvalho Chehab drxj_cfg_pre_saw_t vsb_pre_saw_cfg; 530443f18d0SMauro Carvalho Chehab /**< qam pre SAW config */ 53138b2df95SDevin Heitmueller 53238b2df95SDevin Heitmueller /* Version information */ 53357afe2f0SMauro Carvalho Chehab char v_text[2][12]; /**< allocated text versions */ 534*1bfc9e15SMauro Carvalho Chehab struct drx_version v_version[2]; /**< allocated versions structs */ 535*1bfc9e15SMauro Carvalho Chehab struct drx_version_list v_list_elements[2]; 536443f18d0SMauro Carvalho Chehab /**< allocated version list */ 53738b2df95SDevin Heitmueller 53838b2df95SDevin Heitmueller /* smart antenna configuration */ 53957afe2f0SMauro Carvalho Chehab bool smart_ant_inverted; 54038b2df95SDevin Heitmueller 54138b2df95SDevin Heitmueller /* Tracking filter setting for OOB */ 54257afe2f0SMauro Carvalho Chehab u16 oob_trk_filter_cfg[8]; 54357afe2f0SMauro Carvalho Chehab bool oob_power_on; 54438b2df95SDevin Heitmueller 54538b2df95SDevin Heitmueller /* MPEG static bitrate setting */ 54657afe2f0SMauro Carvalho Chehab u32 mpeg_ts_static_bitrate; /**< bitrate static MPEG output */ 54757afe2f0SMauro Carvalho Chehab bool disable_te_ihandling; /**< MPEG TS TEI handling */ 54857afe2f0SMauro Carvalho Chehab bool bit_reverse_mpeg_outout;/**< MPEG output bit order */ 54957afe2f0SMauro Carvalho Chehab drxj_mpeg_output_clock_rate_t mpeg_output_clock_rate; 550443f18d0SMauro Carvalho Chehab /**< MPEG output clock rate */ 55157afe2f0SMauro Carvalho Chehab drxj_mpeg_start_width_t mpeg_start_width; 552443f18d0SMauro Carvalho Chehab /**< MPEG Start width */ 55338b2df95SDevin Heitmueller 55438b2df95SDevin Heitmueller /* Pre SAW & Agc configuration for ATV */ 55557afe2f0SMauro Carvalho Chehab drxj_cfg_pre_saw_t atv_pre_saw_cfg; 556443f18d0SMauro Carvalho Chehab /**< atv pre SAW config */ 55757afe2f0SMauro Carvalho Chehab drxj_cfg_agc_t atv_rf_agc_cfg; /**< atv RF AGC config */ 55857afe2f0SMauro Carvalho Chehab drxj_cfg_agc_t atv_if_agc_cfg; /**< atv IF AGC config */ 55957afe2f0SMauro Carvalho Chehab u16 atv_pga_cfg; /**< atv pga config */ 56038b2df95SDevin Heitmueller 56157afe2f0SMauro Carvalho Chehab u32 curr_symbol_rate; 56238b2df95SDevin Heitmueller 56338b2df95SDevin Heitmueller /* pin-safe mode */ 56457afe2f0SMauro Carvalho Chehab bool pdr_safe_mode; /**< PDR safe mode activated */ 56557afe2f0SMauro Carvalho Chehab u16 pdr_safe_restore_val_gpio; 56657afe2f0SMauro Carvalho Chehab u16 pdr_safe_restore_val_v_sync; 56757afe2f0SMauro Carvalho Chehab u16 pdr_safe_restore_val_sma_rx; 56857afe2f0SMauro Carvalho Chehab u16 pdr_safe_restore_val_sma_tx; 56938b2df95SDevin Heitmueller 57038b2df95SDevin Heitmueller /* OOB pre-saw value */ 57157afe2f0SMauro Carvalho Chehab u16 oob_pre_saw; 57257afe2f0SMauro Carvalho Chehab drxj_cfg_oob_lo_power_t oob_lo_pow; 57338b2df95SDevin Heitmueller 574*1bfc9e15SMauro Carvalho Chehab struct drx_aud_data aud_data; 575443f18d0SMauro Carvalho Chehab /**< audio storage */ 57638b2df95SDevin Heitmueller 57757afe2f0SMauro Carvalho Chehab } drxj_data_t, *pdrxj_data_t; 57838b2df95SDevin Heitmueller 57938b2df95SDevin Heitmueller /*------------------------------------------------------------------------- 58038b2df95SDevin Heitmueller Access MACROS 58138b2df95SDevin Heitmueller -------------------------------------------------------------------------*/ 58238b2df95SDevin Heitmueller /** 58338b2df95SDevin Heitmueller * \brief Compilable references to attributes 58438b2df95SDevin Heitmueller * \param d pointer to demod instance 58538b2df95SDevin Heitmueller * 58638b2df95SDevin Heitmueller * Used as main reference to an attribute field. 58738b2df95SDevin Heitmueller * Can be used by both macro implementation and function implementation. 58838b2df95SDevin Heitmueller * These macros are defined to avoid duplication of code in macro and function 58938b2df95SDevin Heitmueller * definitions that handle access of demod common or extended attributes. 59038b2df95SDevin Heitmueller * 59138b2df95SDevin Heitmueller */ 59238b2df95SDevin Heitmueller 59338b2df95SDevin Heitmueller #define DRXJ_ATTR_BTSC_DETECT(d) \ 59457afe2f0SMauro Carvalho Chehab (((pdrxj_data_t)(d)->my_ext_attr)->aud_data.btsc_detect) 59538b2df95SDevin Heitmueller 59638b2df95SDevin Heitmueller /** 59738b2df95SDevin Heitmueller * \brief Actual access macros 59838b2df95SDevin Heitmueller * \param d pointer to demod instance 59938b2df95SDevin Heitmueller * \param x value to set or to get 60038b2df95SDevin Heitmueller * 60138b2df95SDevin Heitmueller * SET macros must be used to set the value of an attribute. 60238b2df95SDevin Heitmueller * GET macros must be used to retrieve the value of an attribute. 60338b2df95SDevin Heitmueller * Depending on the value of DRX_USE_ACCESS_FUNCTIONS the macro's will be 60438b2df95SDevin Heitmueller * substituted by "direct-access-inline-code" or a function call. 60538b2df95SDevin Heitmueller * 60638b2df95SDevin Heitmueller */ 60738b2df95SDevin Heitmueller #define DRXJ_GET_BTSC_DETECT(d, x) \ 60838b2df95SDevin Heitmueller do { \ 60938b2df95SDevin Heitmueller (x) = DRXJ_ATTR_BTSC_DETECT((d); \ 61038b2df95SDevin Heitmueller } while (0) 61138b2df95SDevin Heitmueller 61238b2df95SDevin Heitmueller #define DRXJ_SET_BTSC_DETECT(d, x) \ 61338b2df95SDevin Heitmueller do { \ 61438b2df95SDevin Heitmueller DRXJ_ATTR_BTSC_DETECT(d) = (x); \ 61538b2df95SDevin Heitmueller } while (0) 61638b2df95SDevin Heitmueller 61738b2df95SDevin Heitmueller /*------------------------------------------------------------------------- 61838b2df95SDevin Heitmueller DEFINES 61938b2df95SDevin Heitmueller -------------------------------------------------------------------------*/ 62038b2df95SDevin Heitmueller 62138b2df95SDevin Heitmueller /** 62238b2df95SDevin Heitmueller * \def DRXJ_NTSC_CARRIER_FREQ_OFFSET 62338b2df95SDevin Heitmueller * \brief Offset from picture carrier to centre frequency in kHz, in RF domain 62438b2df95SDevin Heitmueller * 62538b2df95SDevin Heitmueller * For NTSC standard. 62638b2df95SDevin Heitmueller * NTSC channels are listed by their picture carrier frequency (Fpc). 62738b2df95SDevin Heitmueller * The function DRX_CTRL_SET_CHANNEL requires the centre frequency as input. 62838b2df95SDevin Heitmueller * In case the tuner module is not used the DRX-J requires that the tuner is 62938b2df95SDevin Heitmueller * tuned to the centre frequency of the channel: 63038b2df95SDevin Heitmueller * 63138b2df95SDevin Heitmueller * Fcentre = Fpc + DRXJ_NTSC_CARRIER_FREQ_OFFSET 63238b2df95SDevin Heitmueller * 63338b2df95SDevin Heitmueller */ 63473f7065bSMauro Carvalho Chehab #define DRXJ_NTSC_CARRIER_FREQ_OFFSET ((s32)(1750)) 63538b2df95SDevin Heitmueller 63638b2df95SDevin Heitmueller /** 63738b2df95SDevin Heitmueller * \def DRXJ_PAL_SECAM_BG_CARRIER_FREQ_OFFSET 63838b2df95SDevin Heitmueller * \brief Offset from picture carrier to centre frequency in kHz, in RF domain 63938b2df95SDevin Heitmueller * 64038b2df95SDevin Heitmueller * For PAL/SECAM - BG standard. This define is needed in case the tuner module 64138b2df95SDevin Heitmueller * is NOT used. PAL/SECAM channels are listed by their picture carrier frequency (Fpc). 64238b2df95SDevin Heitmueller * The DRX-J requires that the tuner is tuned to: 64338b2df95SDevin Heitmueller * Fpc + DRXJ_PAL_SECAM_BG_CARRIER_FREQ_OFFSET 64438b2df95SDevin Heitmueller * 64538b2df95SDevin Heitmueller * In case the tuner module is used the drxdriver takes care of this. 64638b2df95SDevin Heitmueller * In case the tuner module is NOT used the application programmer must take 64738b2df95SDevin Heitmueller * care of this. 64838b2df95SDevin Heitmueller * 64938b2df95SDevin Heitmueller */ 65073f7065bSMauro Carvalho Chehab #define DRXJ_PAL_SECAM_BG_CARRIER_FREQ_OFFSET ((s32)(2375)) 65138b2df95SDevin Heitmueller 65238b2df95SDevin Heitmueller /** 65338b2df95SDevin Heitmueller * \def DRXJ_PAL_SECAM_DKIL_CARRIER_FREQ_OFFSET 65438b2df95SDevin Heitmueller * \brief Offset from picture carrier to centre frequency in kHz, in RF domain 65538b2df95SDevin Heitmueller * 65638b2df95SDevin Heitmueller * For PAL/SECAM - DK, I, L standards. This define is needed in case the tuner module 65738b2df95SDevin Heitmueller * is NOT used. PAL/SECAM channels are listed by their picture carrier frequency (Fpc). 65838b2df95SDevin Heitmueller * The DRX-J requires that the tuner is tuned to: 65938b2df95SDevin Heitmueller * Fpc + DRXJ_PAL_SECAM_DKIL_CARRIER_FREQ_OFFSET 66038b2df95SDevin Heitmueller * 66138b2df95SDevin Heitmueller * In case the tuner module is used the drxdriver takes care of this. 66238b2df95SDevin Heitmueller * In case the tuner module is NOT used the application programmer must take 66338b2df95SDevin Heitmueller * care of this. 66438b2df95SDevin Heitmueller * 66538b2df95SDevin Heitmueller */ 66673f7065bSMauro Carvalho Chehab #define DRXJ_PAL_SECAM_DKIL_CARRIER_FREQ_OFFSET ((s32)(2775)) 66738b2df95SDevin Heitmueller 66838b2df95SDevin Heitmueller /** 66938b2df95SDevin Heitmueller * \def DRXJ_PAL_SECAM_LP_CARRIER_FREQ_OFFSET 67038b2df95SDevin Heitmueller * \brief Offset from picture carrier to centre frequency in kHz, in RF domain 67138b2df95SDevin Heitmueller * 67238b2df95SDevin Heitmueller * For PAL/SECAM - LP standard. This define is needed in case the tuner module 67338b2df95SDevin Heitmueller * is NOT used. PAL/SECAM channels are listed by their picture carrier frequency (Fpc). 67438b2df95SDevin Heitmueller * The DRX-J requires that the tuner is tuned to: 67538b2df95SDevin Heitmueller * Fpc + DRXJ_PAL_SECAM_LP_CARRIER_FREQ_OFFSET 67638b2df95SDevin Heitmueller * 67738b2df95SDevin Heitmueller * In case the tuner module is used the drxdriver takes care of this. 67838b2df95SDevin Heitmueller * In case the tuner module is NOT used the application programmer must take 67938b2df95SDevin Heitmueller * care of this. 68038b2df95SDevin Heitmueller */ 68173f7065bSMauro Carvalho Chehab #define DRXJ_PAL_SECAM_LP_CARRIER_FREQ_OFFSET ((s32)(-3255)) 68238b2df95SDevin Heitmueller 68338b2df95SDevin Heitmueller /** 68438b2df95SDevin Heitmueller * \def DRXJ_FM_CARRIER_FREQ_OFFSET 68538b2df95SDevin Heitmueller * \brief Offset from sound carrier to centre frequency in kHz, in RF domain 68638b2df95SDevin Heitmueller * 68738b2df95SDevin Heitmueller * For FM standard. 68838b2df95SDevin Heitmueller * FM channels are listed by their sound carrier frequency (Fsc). 68938b2df95SDevin Heitmueller * The function DRX_CTRL_SET_CHANNEL requires the Ffm frequency (see below) as 69038b2df95SDevin Heitmueller * input. 69138b2df95SDevin Heitmueller * In case the tuner module is not used the DRX-J requires that the tuner is 69238b2df95SDevin Heitmueller * tuned to the Ffm frequency of the channel. 69338b2df95SDevin Heitmueller * 69438b2df95SDevin Heitmueller * Ffm = Fsc + DRXJ_FM_CARRIER_FREQ_OFFSET 69538b2df95SDevin Heitmueller * 69638b2df95SDevin Heitmueller */ 69773f7065bSMauro Carvalho Chehab #define DRXJ_FM_CARRIER_FREQ_OFFSET ((s32)(-3000)) 69838b2df95SDevin Heitmueller 69938b2df95SDevin Heitmueller /* Revision types -------------------------------------------------------*/ 70038b2df95SDevin Heitmueller 70138b2df95SDevin Heitmueller #define DRXJ_TYPE_ID (0x3946000DUL) 70238b2df95SDevin Heitmueller 70338b2df95SDevin Heitmueller /* Macros ---------------------------------------------------------------*/ 70438b2df95SDevin Heitmueller 70538b2df95SDevin Heitmueller /* Convert OOB lock status to string */ 70638b2df95SDevin Heitmueller #define DRXJ_STR_OOB_LOCKSTATUS(x) ( \ 70738b2df95SDevin Heitmueller (x == DRX_NEVER_LOCK) ? "Never" : \ 70838b2df95SDevin Heitmueller (x == DRX_NOT_LOCKED) ? "No" : \ 70938b2df95SDevin Heitmueller (x == DRX_LOCKED) ? "Locked" : \ 71038b2df95SDevin Heitmueller (x == DRX_LOCK_STATE_1) ? "AGC lock" : \ 71138b2df95SDevin Heitmueller (x == DRX_LOCK_STATE_2) ? "sync lock" : \ 71238b2df95SDevin Heitmueller "(Invalid)") 71338b2df95SDevin Heitmueller 71438b2df95SDevin Heitmueller /*------------------------------------------------------------------------- 71538b2df95SDevin Heitmueller ENUM 71638b2df95SDevin Heitmueller -------------------------------------------------------------------------*/ 71738b2df95SDevin Heitmueller 71838b2df95SDevin Heitmueller /*------------------------------------------------------------------------- 71938b2df95SDevin Heitmueller STRUCTS 72038b2df95SDevin Heitmueller -------------------------------------------------------------------------*/ 72138b2df95SDevin Heitmueller 72238b2df95SDevin Heitmueller /*------------------------------------------------------------------------- 72338b2df95SDevin Heitmueller Exported FUNCTIONS 72438b2df95SDevin Heitmueller -------------------------------------------------------------------------*/ 72538b2df95SDevin Heitmueller 726*1bfc9e15SMauro Carvalho Chehab int drxj_open(struct drx_demod_instance *demod); 727*1bfc9e15SMauro Carvalho Chehab int drxj_close(struct drx_demod_instance *demod); 728*1bfc9e15SMauro Carvalho Chehab int drxj_ctrl(struct drx_demod_instance *demod, 72957afe2f0SMauro Carvalho Chehab u32 ctrl, void *ctrl_data); 73038b2df95SDevin Heitmueller 73138b2df95SDevin Heitmueller /*------------------------------------------------------------------------- 73238b2df95SDevin Heitmueller Exported GLOBAL VARIABLES 73338b2df95SDevin Heitmueller -------------------------------------------------------------------------*/ 734*1bfc9e15SMauro Carvalho Chehab extern struct drx_access_func drx_dap_drxj_funct_g; 735*1bfc9e15SMauro Carvalho Chehab extern struct drx_demod_func drxj_functions_g; 73657afe2f0SMauro Carvalho Chehab extern drxj_data_t drxj_data_g; 73757afe2f0SMauro Carvalho Chehab extern struct i2c_device_addr drxj_default_addr_g; 738*1bfc9e15SMauro Carvalho Chehab extern struct drx_common_attr drxj_default_comm_attr_g; 739*1bfc9e15SMauro Carvalho Chehab extern struct drx_demod_instance drxj_default_demod_g; 74038b2df95SDevin Heitmueller 74138b2df95SDevin Heitmueller /*------------------------------------------------------------------------- 74238b2df95SDevin Heitmueller THE END 74338b2df95SDevin Heitmueller -------------------------------------------------------------------------*/ 74438b2df95SDevin Heitmueller #ifdef __cplusplus 74538b2df95SDevin Heitmueller } 74638b2df95SDevin Heitmueller #endif 74738b2df95SDevin Heitmueller #endif /* __DRXJ_H__ */ 748