xref: /linux/drivers/media/dvb-frontends/drx39xyj/drxj.c (revision bfd5bb6f90af092aa345b15cd78143956a13c2a8)
1 /*
2   Copyright (c), 2004-2005,2007-2010 Trident Microsystems, Inc.
3   All rights reserved.
4 
5   Redistribution and use in source and binary forms, with or without
6   modification, are permitted provided that the following conditions are met:
7 
8   * Redistributions of source code must retain the above copyright notice,
9     this list of conditions and the following disclaimer.
10   * Redistributions in binary form must reproduce the above copyright notice,
11     this list of conditions and the following disclaimer in the documentation
12 	and/or other materials provided with the distribution.
13   * Neither the name of Trident Microsystems nor Hauppauge Computer Works
14     nor the names of its contributors may be used to endorse or promote
15 	products derived from this software without specific prior written
16 	permission.
17 
18   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
19   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21   ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
22   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
23   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
24   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
25   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
26   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
27   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
28   POSSIBILITY OF SUCH DAMAGE.
29 
30   DRXJ specific implementation of DRX driver
31   authors: Dragan Savic, Milos Nikolic, Mihajlo Katona, Tao Ding, Paul Janssen
32 
33   The Linux DVB Driver for Micronas DRX39xx family (drx3933j) was
34   written by Devin Heitmueller <devin.heitmueller@kernellabs.com>
35 
36   This program is free software; you can redistribute it and/or modify
37   it under the terms of the GNU General Public License as published by
38   the Free Software Foundation; either version 2 of the License, or
39   (at your option) any later version.
40 
41   This program is distributed in the hope that it will be useful,
42   but WITHOUT ANY WARRANTY; without even the implied warranty of
43   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
44 
45   GNU General Public License for more details.
46 
47   You should have received a copy of the GNU General Public License
48   along with this program; if not, write to the Free Software
49   Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
50 */
51 
52 /*-----------------------------------------------------------------------------
53 INCLUDE FILES
54 ----------------------------------------------------------------------------*/
55 
56 #define pr_fmt(fmt) KBUILD_MODNAME ":%s: " fmt, __func__
57 
58 #include <linux/module.h>
59 #include <linux/init.h>
60 #include <linux/string.h>
61 #include <linux/slab.h>
62 #include <asm/div64.h>
63 
64 #include <media/dvb_frontend.h>
65 #include "drx39xxj.h"
66 
67 #include "drxj.h"
68 #include "drxj_map.h"
69 
70 /*============================================================================*/
71 /*=== DEFINES ================================================================*/
72 /*============================================================================*/
73 
74 #define DRX39XX_MAIN_FIRMWARE "dvb-fe-drxj-mc-1.0.8.fw"
75 
76 /*
77 * \brief Maximum u32 value.
78 */
79 #ifndef MAX_U32
80 #define MAX_U32  ((u32) (0xFFFFFFFFL))
81 #endif
82 
83 /* Customer configurable hardware settings, etc */
84 #ifndef MPEG_SERIAL_OUTPUT_PIN_DRIVE_STRENGTH
85 #define MPEG_SERIAL_OUTPUT_PIN_DRIVE_STRENGTH 0x02
86 #endif
87 
88 #ifndef MPEG_PARALLEL_OUTPUT_PIN_DRIVE_STRENGTH
89 #define MPEG_PARALLEL_OUTPUT_PIN_DRIVE_STRENGTH 0x02
90 #endif
91 
92 #ifndef MPEG_OUTPUT_CLK_DRIVE_STRENGTH
93 #define MPEG_OUTPUT_CLK_DRIVE_STRENGTH 0x06
94 #endif
95 
96 #ifndef OOB_CRX_DRIVE_STRENGTH
97 #define OOB_CRX_DRIVE_STRENGTH 0x02
98 #endif
99 
100 #ifndef OOB_DRX_DRIVE_STRENGTH
101 #define OOB_DRX_DRIVE_STRENGTH 0x02
102 #endif
103 /*** START DJCOMBO patches to DRXJ registermap constants *********************/
104 /*** registermap 200706071303 from drxj **************************************/
105 #define   ATV_TOP_CR_AMP_TH_FM                                              0x0
106 #define   ATV_TOP_CR_AMP_TH_L                                               0xA
107 #define   ATV_TOP_CR_AMP_TH_LP                                              0xA
108 #define   ATV_TOP_CR_AMP_TH_BG                                              0x8
109 #define   ATV_TOP_CR_AMP_TH_DK                                              0x8
110 #define   ATV_TOP_CR_AMP_TH_I                                               0x8
111 #define     ATV_TOP_CR_CONT_CR_D_MN                                         0x18
112 #define     ATV_TOP_CR_CONT_CR_D_FM                                         0x0
113 #define     ATV_TOP_CR_CONT_CR_D_L                                          0x20
114 #define     ATV_TOP_CR_CONT_CR_D_LP                                         0x20
115 #define     ATV_TOP_CR_CONT_CR_D_BG                                         0x18
116 #define     ATV_TOP_CR_CONT_CR_D_DK                                         0x18
117 #define     ATV_TOP_CR_CONT_CR_D_I                                          0x18
118 #define     ATV_TOP_CR_CONT_CR_I_MN                                         0x80
119 #define     ATV_TOP_CR_CONT_CR_I_FM                                         0x0
120 #define     ATV_TOP_CR_CONT_CR_I_L                                          0x80
121 #define     ATV_TOP_CR_CONT_CR_I_LP                                         0x80
122 #define     ATV_TOP_CR_CONT_CR_I_BG                                         0x80
123 #define     ATV_TOP_CR_CONT_CR_I_DK                                         0x80
124 #define     ATV_TOP_CR_CONT_CR_I_I                                          0x80
125 #define     ATV_TOP_CR_CONT_CR_P_MN                                         0x4
126 #define     ATV_TOP_CR_CONT_CR_P_FM                                         0x0
127 #define     ATV_TOP_CR_CONT_CR_P_L                                          0x4
128 #define     ATV_TOP_CR_CONT_CR_P_LP                                         0x4
129 #define     ATV_TOP_CR_CONT_CR_P_BG                                         0x4
130 #define     ATV_TOP_CR_CONT_CR_P_DK                                         0x4
131 #define     ATV_TOP_CR_CONT_CR_P_I                                          0x4
132 #define   ATV_TOP_CR_OVM_TH_MN                                              0xA0
133 #define   ATV_TOP_CR_OVM_TH_FM                                              0x0
134 #define   ATV_TOP_CR_OVM_TH_L                                               0xA0
135 #define   ATV_TOP_CR_OVM_TH_LP                                              0xA0
136 #define   ATV_TOP_CR_OVM_TH_BG                                              0xA0
137 #define   ATV_TOP_CR_OVM_TH_DK                                              0xA0
138 #define   ATV_TOP_CR_OVM_TH_I                                               0xA0
139 #define     ATV_TOP_EQU0_EQU_C0_FM                                          0x0
140 #define     ATV_TOP_EQU0_EQU_C0_L                                           0x3
141 #define     ATV_TOP_EQU0_EQU_C0_LP                                          0x3
142 #define     ATV_TOP_EQU0_EQU_C0_BG                                          0x7
143 #define     ATV_TOP_EQU0_EQU_C0_DK                                          0x0
144 #define     ATV_TOP_EQU0_EQU_C0_I                                           0x3
145 #define     ATV_TOP_EQU1_EQU_C1_FM                                          0x0
146 #define     ATV_TOP_EQU1_EQU_C1_L                                           0x1F6
147 #define     ATV_TOP_EQU1_EQU_C1_LP                                          0x1F6
148 #define     ATV_TOP_EQU1_EQU_C1_BG                                          0x197
149 #define     ATV_TOP_EQU1_EQU_C1_DK                                          0x198
150 #define     ATV_TOP_EQU1_EQU_C1_I                                           0x1F6
151 #define     ATV_TOP_EQU2_EQU_C2_FM                                          0x0
152 #define     ATV_TOP_EQU2_EQU_C2_L                                           0x28
153 #define     ATV_TOP_EQU2_EQU_C2_LP                                          0x28
154 #define     ATV_TOP_EQU2_EQU_C2_BG                                          0xC5
155 #define     ATV_TOP_EQU2_EQU_C2_DK                                          0xB0
156 #define     ATV_TOP_EQU2_EQU_C2_I                                           0x28
157 #define     ATV_TOP_EQU3_EQU_C3_FM                                          0x0
158 #define     ATV_TOP_EQU3_EQU_C3_L                                           0x192
159 #define     ATV_TOP_EQU3_EQU_C3_LP                                          0x192
160 #define     ATV_TOP_EQU3_EQU_C3_BG                                          0x12E
161 #define     ATV_TOP_EQU3_EQU_C3_DK                                          0x18E
162 #define     ATV_TOP_EQU3_EQU_C3_I                                           0x192
163 #define     ATV_TOP_STD_MODE_MN                                             0x0
164 #define     ATV_TOP_STD_MODE_FM                                             0x1
165 #define     ATV_TOP_STD_MODE_L                                              0x0
166 #define     ATV_TOP_STD_MODE_LP                                             0x0
167 #define     ATV_TOP_STD_MODE_BG                                             0x0
168 #define     ATV_TOP_STD_MODE_DK                                             0x0
169 #define     ATV_TOP_STD_MODE_I                                              0x0
170 #define     ATV_TOP_STD_VID_POL_MN                                          0x0
171 #define     ATV_TOP_STD_VID_POL_FM                                          0x0
172 #define     ATV_TOP_STD_VID_POL_L                                           0x2
173 #define     ATV_TOP_STD_VID_POL_LP                                          0x2
174 #define     ATV_TOP_STD_VID_POL_BG                                          0x0
175 #define     ATV_TOP_STD_VID_POL_DK                                          0x0
176 #define     ATV_TOP_STD_VID_POL_I                                           0x0
177 #define   ATV_TOP_VID_AMP_MN                                                0x380
178 #define   ATV_TOP_VID_AMP_FM                                                0x0
179 #define   ATV_TOP_VID_AMP_L                                                 0xF50
180 #define   ATV_TOP_VID_AMP_LP                                                0xF50
181 #define   ATV_TOP_VID_AMP_BG                                                0x380
182 #define   ATV_TOP_VID_AMP_DK                                                0x394
183 #define   ATV_TOP_VID_AMP_I                                                 0x3D8
184 #define   IQM_CF_OUT_ENA_OFDM__M                                            0x4
185 #define     IQM_FS_ADJ_SEL_B_QAM                                            0x1
186 #define     IQM_FS_ADJ_SEL_B_OFF                                            0x0
187 #define     IQM_FS_ADJ_SEL_B_VSB                                            0x2
188 #define     IQM_RC_ADJ_SEL_B_OFF                                            0x0
189 #define     IQM_RC_ADJ_SEL_B_QAM                                            0x1
190 #define     IQM_RC_ADJ_SEL_B_VSB                                            0x2
191 /*** END DJCOMBO patches to DRXJ registermap *********************************/
192 
193 #include "drx_driver_version.h"
194 
195 /* #define DRX_DEBUG */
196 #ifdef DRX_DEBUG
197 #include <stdio.h>
198 #endif
199 
200 /*-----------------------------------------------------------------------------
201 ENUMS
202 ----------------------------------------------------------------------------*/
203 
204 /*-----------------------------------------------------------------------------
205 DEFINES
206 ----------------------------------------------------------------------------*/
207 #ifndef DRXJ_WAKE_UP_KEY
208 #define DRXJ_WAKE_UP_KEY (demod->my_i2c_dev_addr->i2c_addr)
209 #endif
210 
211 /*
212 * \def DRXJ_DEF_I2C_ADDR
213 * \brief Default I2C address of a demodulator instance.
214 */
215 #define DRXJ_DEF_I2C_ADDR (0x52)
216 
217 /*
218 * \def DRXJ_DEF_DEMOD_DEV_ID
219 * \brief Default device identifier of a demodultor instance.
220 */
221 #define DRXJ_DEF_DEMOD_DEV_ID      (1)
222 
223 /*
224 * \def DRXJ_SCAN_TIMEOUT
225 * \brief Timeout value for waiting on demod lock during channel scan (millisec).
226 */
227 #define DRXJ_SCAN_TIMEOUT    1000
228 
229 /*
230 * \def HI_I2C_DELAY
231 * \brief HI timing delay for I2C timing (in nano seconds)
232 *
233 *  Used to compute HI_CFG_DIV
234 */
235 #define HI_I2C_DELAY    42
236 
237 /*
238 * \def HI_I2C_BRIDGE_DELAY
239 * \brief HI timing delay for I2C timing (in nano seconds)
240 *
241 *  Used to compute HI_CFG_BDL
242 */
243 #define HI_I2C_BRIDGE_DELAY   750
244 
245 /*
246 * \brief Time Window for MER and SER Measurement in Units of Segment duration.
247 */
248 #define VSB_TOP_MEASUREMENT_PERIOD  64
249 #define SYMBOLS_PER_SEGMENT         832
250 
251 /*
252 * \brief bit rate and segment rate constants used for SER and BER.
253 */
254 /* values taken from the QAM microcode */
255 #define DRXJ_QAM_SL_SIG_POWER_QAM_UNKNOWN 0
256 #define DRXJ_QAM_SL_SIG_POWER_QPSK        32768
257 #define DRXJ_QAM_SL_SIG_POWER_QAM8        24576
258 #define DRXJ_QAM_SL_SIG_POWER_QAM16       40960
259 #define DRXJ_QAM_SL_SIG_POWER_QAM32       20480
260 #define DRXJ_QAM_SL_SIG_POWER_QAM64       43008
261 #define DRXJ_QAM_SL_SIG_POWER_QAM128      20992
262 #define DRXJ_QAM_SL_SIG_POWER_QAM256      43520
263 /*
264 * \brief Min supported symbolrates.
265 */
266 #ifndef DRXJ_QAM_SYMBOLRATE_MIN
267 #define DRXJ_QAM_SYMBOLRATE_MIN          (520000)
268 #endif
269 
270 /*
271 * \brief Max supported symbolrates.
272 */
273 #ifndef DRXJ_QAM_SYMBOLRATE_MAX
274 #define DRXJ_QAM_SYMBOLRATE_MAX         (7233000)
275 #endif
276 
277 /*
278 * \def DRXJ_QAM_MAX_WAITTIME
279 * \brief Maximal wait time for QAM auto constellation in ms
280 */
281 #ifndef DRXJ_QAM_MAX_WAITTIME
282 #define DRXJ_QAM_MAX_WAITTIME 900
283 #endif
284 
285 #ifndef DRXJ_QAM_FEC_LOCK_WAITTIME
286 #define DRXJ_QAM_FEC_LOCK_WAITTIME 150
287 #endif
288 
289 #ifndef DRXJ_QAM_DEMOD_LOCK_EXT_WAITTIME
290 #define DRXJ_QAM_DEMOD_LOCK_EXT_WAITTIME 200
291 #endif
292 
293 /*
294 * \def SCU status and results
295 * \brief SCU
296 */
297 #define DRX_SCU_READY               0
298 #define DRXJ_MAX_WAITTIME           100	/* ms */
299 #define FEC_RS_MEASUREMENT_PERIOD   12894	/* 1 sec */
300 #define FEC_RS_MEASUREMENT_PRESCALE 1	/* n sec */
301 
302 /*
303 * \def DRX_AUD_MAX_DEVIATION
304 * \brief Needed for calculation of prescale feature in AUD
305 */
306 #ifndef DRXJ_AUD_MAX_FM_DEVIATION
307 #define DRXJ_AUD_MAX_FM_DEVIATION  100	/* kHz */
308 #endif
309 
310 /*
311 * \brief Needed for calculation of NICAM prescale feature in AUD
312 */
313 #ifndef DRXJ_AUD_MAX_NICAM_PRESCALE
314 #define DRXJ_AUD_MAX_NICAM_PRESCALE  (9)	/* dB */
315 #endif
316 
317 /*
318 * \brief Needed for calculation of NICAM prescale feature in AUD
319 */
320 #ifndef DRXJ_AUD_MAX_WAITTIME
321 #define DRXJ_AUD_MAX_WAITTIME  250	/* ms */
322 #endif
323 
324 /* ATV config changed flags */
325 #define DRXJ_ATV_CHANGED_COEF          (0x00000001UL)
326 #define DRXJ_ATV_CHANGED_PEAK_FLT      (0x00000008UL)
327 #define DRXJ_ATV_CHANGED_NOISE_FLT     (0x00000010UL)
328 #define DRXJ_ATV_CHANGED_OUTPUT        (0x00000020UL)
329 #define DRXJ_ATV_CHANGED_SIF_ATT       (0x00000040UL)
330 
331 /* UIO define */
332 #define DRX_UIO_MODE_FIRMWARE_SMA DRX_UIO_MODE_FIRMWARE0
333 #define DRX_UIO_MODE_FIRMWARE_SAW DRX_UIO_MODE_FIRMWARE1
334 
335 /*
336  * MICROCODE RELATED DEFINES
337  */
338 
339 /* Magic word for checking correct Endianness of microcode data */
340 #define DRX_UCODE_MAGIC_WORD         ((((u16)'H')<<8)+((u16)'L'))
341 
342 /* CRC flag in ucode header, flags field. */
343 #define DRX_UCODE_CRC_FLAG           (0x0001)
344 
345 /*
346  * Maximum size of buffer used to verify the microcode.
347  * Must be an even number
348  */
349 #define DRX_UCODE_MAX_BUF_SIZE       (DRXDAP_MAX_RCHUNKSIZE)
350 
351 #if DRX_UCODE_MAX_BUF_SIZE & 1
352 #error DRX_UCODE_MAX_BUF_SIZE must be an even number
353 #endif
354 
355 /*
356  * Power mode macros
357  */
358 
359 #define DRX_ISPOWERDOWNMODE(mode) ((mode == DRX_POWER_MODE_9) || \
360 				       (mode == DRX_POWER_MODE_10) || \
361 				       (mode == DRX_POWER_MODE_11) || \
362 				       (mode == DRX_POWER_MODE_12) || \
363 				       (mode == DRX_POWER_MODE_13) || \
364 				       (mode == DRX_POWER_MODE_14) || \
365 				       (mode == DRX_POWER_MODE_15) || \
366 				       (mode == DRX_POWER_MODE_16) || \
367 				       (mode == DRX_POWER_DOWN))
368 
369 /* Pin safe mode macro */
370 #define DRXJ_PIN_SAFE_MODE 0x0000
371 /*============================================================================*/
372 /*=== GLOBAL VARIABLEs =======================================================*/
373 /*============================================================================*/
374 /*
375 */
376 
377 /*
378 * \brief Temporary register definitions.
379 *        (register definitions that are not yet available in register master)
380 */
381 
382 /*****************************************************************************/
383 /* Audio block 0x103 is write only. To avoid shadowing in driver accessing    */
384 /* RAM adresses directly. This must be READ ONLY to avoid problems.           */
385 /* Writing to the interface adresses is more than only writing the RAM        */
386 /* locations                                                                  */
387 /*****************************************************************************/
388 /*
389 * \brief RAM location of MODUS registers
390 */
391 #define AUD_DEM_RAM_MODUS_HI__A              0x10204A3
392 #define AUD_DEM_RAM_MODUS_HI__M              0xF000
393 
394 #define AUD_DEM_RAM_MODUS_LO__A              0x10204A4
395 #define AUD_DEM_RAM_MODUS_LO__M              0x0FFF
396 
397 /*
398 * \brief RAM location of I2S config registers
399 */
400 #define AUD_DEM_RAM_I2S_CONFIG1__A           0x10204B1
401 #define AUD_DEM_RAM_I2S_CONFIG2__A           0x10204B2
402 
403 /*
404 * \brief RAM location of DCO config registers
405 */
406 #define AUD_DEM_RAM_DCO_B_HI__A              0x1020461
407 #define AUD_DEM_RAM_DCO_B_LO__A              0x1020462
408 #define AUD_DEM_RAM_DCO_A_HI__A              0x1020463
409 #define AUD_DEM_RAM_DCO_A_LO__A              0x1020464
410 
411 /*
412 * \brief RAM location of Threshold registers
413 */
414 #define AUD_DEM_RAM_NICAM_THRSHLD__A         0x102045A
415 #define AUD_DEM_RAM_A2_THRSHLD__A            0x10204BB
416 #define AUD_DEM_RAM_BTSC_THRSHLD__A          0x10204A6
417 
418 /*
419 * \brief RAM location of Carrier Threshold registers
420 */
421 #define AUD_DEM_RAM_CM_A_THRSHLD__A          0x10204AF
422 #define AUD_DEM_RAM_CM_B_THRSHLD__A          0x10204B0
423 
424 /*
425 * \brief FM Matrix register fix
426 */
427 #ifdef AUD_DEM_WR_FM_MATRIX__A
428 #undef  AUD_DEM_WR_FM_MATRIX__A
429 #endif
430 #define AUD_DEM_WR_FM_MATRIX__A              0x105006F
431 
432 /*============================================================================*/
433 /*
434 * \brief Defines required for audio
435 */
436 #define AUD_VOLUME_ZERO_DB                      115
437 #define AUD_VOLUME_DB_MIN                       -60
438 #define AUD_VOLUME_DB_MAX                       12
439 #define AUD_CARRIER_STRENGTH_QP_0DB             0x4000
440 #define AUD_CARRIER_STRENGTH_QP_0DB_LOG10T100   421
441 #define AUD_MAX_AVC_REF_LEVEL                   15
442 #define AUD_I2S_FREQUENCY_MAX                   48000UL
443 #define AUD_I2S_FREQUENCY_MIN                   12000UL
444 #define AUD_RDS_ARRAY_SIZE                      18
445 
446 /*
447 * \brief Needed for calculation of prescale feature in AUD
448 */
449 #ifndef DRX_AUD_MAX_FM_DEVIATION
450 #define DRX_AUD_MAX_FM_DEVIATION  (100)	/* kHz */
451 #endif
452 
453 /*
454 * \brief Needed for calculation of NICAM prescale feature in AUD
455 */
456 #ifndef DRX_AUD_MAX_NICAM_PRESCALE
457 #define DRX_AUD_MAX_NICAM_PRESCALE  (9)	/* dB */
458 #endif
459 
460 /*============================================================================*/
461 /* Values for I2S Master/Slave pin configurations */
462 #define SIO_PDR_I2S_CL_CFG_MODE__MASTER      0x0004
463 #define SIO_PDR_I2S_CL_CFG_DRIVE__MASTER     0x0008
464 #define SIO_PDR_I2S_CL_CFG_MODE__SLAVE       0x0004
465 #define SIO_PDR_I2S_CL_CFG_DRIVE__SLAVE      0x0000
466 
467 #define SIO_PDR_I2S_DA_CFG_MODE__MASTER      0x0003
468 #define SIO_PDR_I2S_DA_CFG_DRIVE__MASTER     0x0008
469 #define SIO_PDR_I2S_DA_CFG_MODE__SLAVE       0x0003
470 #define SIO_PDR_I2S_DA_CFG_DRIVE__SLAVE      0x0008
471 
472 #define SIO_PDR_I2S_WS_CFG_MODE__MASTER      0x0004
473 #define SIO_PDR_I2S_WS_CFG_DRIVE__MASTER     0x0008
474 #define SIO_PDR_I2S_WS_CFG_MODE__SLAVE       0x0004
475 #define SIO_PDR_I2S_WS_CFG_DRIVE__SLAVE      0x0000
476 
477 /*============================================================================*/
478 /*=== REGISTER ACCESS MACROS =================================================*/
479 /*============================================================================*/
480 
481 /*
482 * This macro is used to create byte arrays for block writes.
483 * Block writes speed up I2C traffic between host and demod.
484 * The macro takes care of the required byte order in a 16 bits word.
485 * x -> lowbyte(x), highbyte(x)
486 */
487 #define DRXJ_16TO8(x) ((u8) (((u16)x) & 0xFF)), \
488 		       ((u8)((((u16)x)>>8)&0xFF))
489 /*
490 * This macro is used to convert byte array to 16 bit register value for block read.
491 * Block read speed up I2C traffic between host and demod.
492 * The macro takes care of the required byte order in a 16 bits word.
493 */
494 #define DRXJ_8TO16(x) ((u16) (x[0] | (x[1] << 8)))
495 
496 /*============================================================================*/
497 /*=== MISC DEFINES ===========================================================*/
498 /*============================================================================*/
499 
500 /*============================================================================*/
501 /*=== HI COMMAND RELATED DEFINES =============================================*/
502 /*============================================================================*/
503 
504 /*
505 * \brief General maximum number of retries for ucode command interfaces
506 */
507 #define DRXJ_MAX_RETRIES (100)
508 
509 /*============================================================================*/
510 /*=== STANDARD RELATED MACROS ================================================*/
511 /*============================================================================*/
512 
513 #define DRXJ_ISATVSTD(std) ((std == DRX_STANDARD_PAL_SECAM_BG) || \
514 			       (std == DRX_STANDARD_PAL_SECAM_DK) || \
515 			       (std == DRX_STANDARD_PAL_SECAM_I) || \
516 			       (std == DRX_STANDARD_PAL_SECAM_L) || \
517 			       (std == DRX_STANDARD_PAL_SECAM_LP) || \
518 			       (std == DRX_STANDARD_NTSC) || \
519 			       (std == DRX_STANDARD_FM))
520 
521 #define DRXJ_ISQAMSTD(std) ((std == DRX_STANDARD_ITU_A) || \
522 			       (std == DRX_STANDARD_ITU_B) || \
523 			       (std == DRX_STANDARD_ITU_C) || \
524 			       (std == DRX_STANDARD_ITU_D))
525 
526 /*-----------------------------------------------------------------------------
527 GLOBAL VARIABLES
528 ----------------------------------------------------------------------------*/
529 /*
530  * DRXJ DAP structures
531  */
532 
533 static int drxdap_fasi_read_block(struct i2c_device_addr *dev_addr,
534 				      u32 addr,
535 				      u16 datasize,
536 				      u8 *data, u32 flags);
537 
538 
539 static int drxj_dap_read_modify_write_reg16(struct i2c_device_addr *dev_addr,
540 						 u32 waddr,
541 						 u32 raddr,
542 						 u16 wdata, u16 *rdata);
543 
544 static int drxj_dap_read_reg16(struct i2c_device_addr *dev_addr,
545 				      u32 addr,
546 				      u16 *data, u32 flags);
547 
548 static int drxdap_fasi_read_reg32(struct i2c_device_addr *dev_addr,
549 				      u32 addr,
550 				      u32 *data, u32 flags);
551 
552 static int drxdap_fasi_write_block(struct i2c_device_addr *dev_addr,
553 				       u32 addr,
554 				       u16 datasize,
555 				       u8 *data, u32 flags);
556 
557 static int drxj_dap_write_reg16(struct i2c_device_addr *dev_addr,
558 				       u32 addr,
559 				       u16 data, u32 flags);
560 
561 static int drxdap_fasi_write_reg32(struct i2c_device_addr *dev_addr,
562 				       u32 addr,
563 				       u32 data, u32 flags);
564 
565 static struct drxj_data drxj_data_g = {
566 	false,			/* has_lna : true if LNA (aka PGA) present      */
567 	false,			/* has_oob : true if OOB supported              */
568 	false,			/* has_ntsc: true if NTSC supported             */
569 	false,			/* has_btsc: true if BTSC supported             */
570 	false,			/* has_smatx: true if SMA_TX pin is available   */
571 	false,			/* has_smarx: true if SMA_RX pin is available   */
572 	false,			/* has_gpio : true if GPIO pin is available     */
573 	false,			/* has_irqn : true if IRQN pin is available     */
574 	0,			/* mfx A1/A2/A... */
575 
576 	/* tuner settings */
577 	false,			/* tuner mirrors RF signal    */
578 	/* standard/channel settings */
579 	DRX_STANDARD_UNKNOWN,	/* current standard           */
580 	DRX_CONSTELLATION_AUTO,	/* constellation              */
581 	0,			/* frequency in KHz           */
582 	DRX_BANDWIDTH_UNKNOWN,	/* curr_bandwidth              */
583 	DRX_MIRROR_NO,		/* mirror                     */
584 
585 	/* signal quality information: */
586 	/* default values taken from the QAM Programming guide */
587 	/*   fec_bits_desired should not be less than 4000000    */
588 	4000000,		/* fec_bits_desired    */
589 	5,			/* fec_vd_plen         */
590 	4,			/* qam_vd_prescale     */
591 	0xFFFF,			/* qamVDPeriod       */
592 	204 * 8,		/* fec_rs_plen annex A */
593 	1,			/* fec_rs_prescale     */
594 	FEC_RS_MEASUREMENT_PERIOD,	/* fec_rs_period     */
595 	true,			/* reset_pkt_err_acc    */
596 	0,			/* pkt_err_acc_start    */
597 
598 	/* HI configuration */
599 	0,			/* hi_cfg_timing_div    */
600 	0,			/* hi_cfg_bridge_delay  */
601 	0,			/* hi_cfg_wake_up_key    */
602 	0,			/* hi_cfg_ctrl         */
603 	0,			/* HICfgTimeout      */
604 	/* UIO configuration */
605 	DRX_UIO_MODE_DISABLE,	/* uio_sma_rx_mode      */
606 	DRX_UIO_MODE_DISABLE,	/* uio_sma_tx_mode      */
607 	DRX_UIO_MODE_DISABLE,	/* uioASELMode       */
608 	DRX_UIO_MODE_DISABLE,	/* uio_irqn_mode       */
609 	/* FS setting */
610 	0UL,			/* iqm_fs_rate_ofs      */
611 	false,			/* pos_image          */
612 	/* RC setting */
613 	0UL,			/* iqm_rc_rate_ofs      */
614 	/* AUD information */
615 /*   false,                  * flagSetAUDdone    */
616 /*   false,                  * detectedRDS       */
617 /*   true,                   * flagASDRequest    */
618 /*   false,                  * flagHDevClear     */
619 /*   false,                  * flagHDevSet       */
620 /*   (u16) 0xFFF,          * rdsLastCount      */
621 
622 	/* ATV configuration */
623 	0UL,			/* flags cfg changes */
624 	/* shadow of ATV_TOP_EQU0__A */
625 	{-5,
626 	 ATV_TOP_EQU0_EQU_C0_FM,
627 	 ATV_TOP_EQU0_EQU_C0_L,
628 	 ATV_TOP_EQU0_EQU_C0_LP,
629 	 ATV_TOP_EQU0_EQU_C0_BG,
630 	 ATV_TOP_EQU0_EQU_C0_DK,
631 	 ATV_TOP_EQU0_EQU_C0_I},
632 	/* shadow of ATV_TOP_EQU1__A */
633 	{-50,
634 	 ATV_TOP_EQU1_EQU_C1_FM,
635 	 ATV_TOP_EQU1_EQU_C1_L,
636 	 ATV_TOP_EQU1_EQU_C1_LP,
637 	 ATV_TOP_EQU1_EQU_C1_BG,
638 	 ATV_TOP_EQU1_EQU_C1_DK,
639 	 ATV_TOP_EQU1_EQU_C1_I},
640 	/* shadow of ATV_TOP_EQU2__A */
641 	{210,
642 	 ATV_TOP_EQU2_EQU_C2_FM,
643 	 ATV_TOP_EQU2_EQU_C2_L,
644 	 ATV_TOP_EQU2_EQU_C2_LP,
645 	 ATV_TOP_EQU2_EQU_C2_BG,
646 	 ATV_TOP_EQU2_EQU_C2_DK,
647 	 ATV_TOP_EQU2_EQU_C2_I},
648 	/* shadow of ATV_TOP_EQU3__A */
649 	{-160,
650 	 ATV_TOP_EQU3_EQU_C3_FM,
651 	 ATV_TOP_EQU3_EQU_C3_L,
652 	 ATV_TOP_EQU3_EQU_C3_LP,
653 	 ATV_TOP_EQU3_EQU_C3_BG,
654 	 ATV_TOP_EQU3_EQU_C3_DK,
655 	 ATV_TOP_EQU3_EQU_C3_I},
656 	false,			/* flag: true=bypass             */
657 	ATV_TOP_VID_PEAK__PRE,	/* shadow of ATV_TOP_VID_PEAK__A */
658 	ATV_TOP_NOISE_TH__PRE,	/* shadow of ATV_TOP_NOISE_TH__A */
659 	true,			/* flag CVBS ouput enable        */
660 	false,			/* flag SIF ouput enable         */
661 	DRXJ_SIF_ATTENUATION_0DB,	/* current SIF att setting       */
662 	{			/* qam_rf_agc_cfg */
663 	 DRX_STANDARD_ITU_B,	/* standard            */
664 	 DRX_AGC_CTRL_AUTO,	/* ctrl_mode            */
665 	 0,			/* output_level         */
666 	 0,			/* min_output_level      */
667 	 0xFFFF,		/* max_output_level      */
668 	 0x0000,		/* speed               */
669 	 0x0000,		/* top                 */
670 	 0x0000			/* c.o.c.              */
671 	 },
672 	{			/* qam_if_agc_cfg */
673 	 DRX_STANDARD_ITU_B,	/* standard            */
674 	 DRX_AGC_CTRL_AUTO,	/* ctrl_mode            */
675 	 0,			/* output_level         */
676 	 0,			/* min_output_level      */
677 	 0xFFFF,		/* max_output_level      */
678 	 0x0000,		/* speed               */
679 	 0x0000,		/* top    (don't care) */
680 	 0x0000			/* c.o.c. (don't care) */
681 	 },
682 	{			/* vsb_rf_agc_cfg */
683 	 DRX_STANDARD_8VSB,	/* standard       */
684 	 DRX_AGC_CTRL_AUTO,	/* ctrl_mode       */
685 	 0,			/* output_level    */
686 	 0,			/* min_output_level */
687 	 0xFFFF,		/* max_output_level */
688 	 0x0000,		/* speed          */
689 	 0x0000,		/* top    (don't care) */
690 	 0x0000			/* c.o.c. (don't care) */
691 	 },
692 	{			/* vsb_if_agc_cfg */
693 	 DRX_STANDARD_8VSB,	/* standard       */
694 	 DRX_AGC_CTRL_AUTO,	/* ctrl_mode       */
695 	 0,			/* output_level    */
696 	 0,			/* min_output_level */
697 	 0xFFFF,		/* max_output_level */
698 	 0x0000,		/* speed          */
699 	 0x0000,		/* top    (don't care) */
700 	 0x0000			/* c.o.c. (don't care) */
701 	 },
702 	0,			/* qam_pga_cfg */
703 	0,			/* vsb_pga_cfg */
704 	{			/* qam_pre_saw_cfg */
705 	 DRX_STANDARD_ITU_B,	/* standard  */
706 	 0,			/* reference */
707 	 false			/* use_pre_saw */
708 	 },
709 	{			/* vsb_pre_saw_cfg */
710 	 DRX_STANDARD_8VSB,	/* standard  */
711 	 0,			/* reference */
712 	 false			/* use_pre_saw */
713 	 },
714 
715 	/* Version information */
716 #ifndef _CH_
717 	{
718 	 "01234567890",		/* human readable version microcode             */
719 	 "01234567890"		/* human readable version device specific code  */
720 	 },
721 	{
722 	 {			/* struct drx_version for microcode                   */
723 	  DRX_MODULE_UNKNOWN,
724 	  (char *)(NULL),
725 	  0,
726 	  0,
727 	  0,
728 	  (char *)(NULL)
729 	  },
730 	 {			/* struct drx_version for device specific code */
731 	  DRX_MODULE_UNKNOWN,
732 	  (char *)(NULL),
733 	  0,
734 	  0,
735 	  0,
736 	  (char *)(NULL)
737 	  }
738 	 },
739 	{
740 	 {			/* struct drx_version_list for microcode */
741 	  (struct drx_version *) (NULL),
742 	  (struct drx_version_list *) (NULL)
743 	  },
744 	 {			/* struct drx_version_list for device specific code */
745 	  (struct drx_version *) (NULL),
746 	  (struct drx_version_list *) (NULL)
747 	  }
748 	 },
749 #endif
750 	false,			/* smart_ant_inverted */
751 	/* Tracking filter setting for OOB  */
752 	{
753 	 12000,
754 	 9300,
755 	 6600,
756 	 5280,
757 	 3700,
758 	 3000,
759 	 2000,
760 	 0},
761 	false,			/* oob_power_on           */
762 	0,			/* mpeg_ts_static_bitrate  */
763 	false,			/* disable_te_ihandling   */
764 	false,			/* bit_reverse_mpeg_outout */
765 	DRXJ_MPEGOUTPUT_CLOCK_RATE_AUTO,	/* mpeg_output_clock_rate */
766 	DRXJ_MPEG_START_WIDTH_1CLKCYC,	/* mpeg_start_width */
767 
768 	/* Pre SAW & Agc configuration for ATV */
769 	{
770 	 DRX_STANDARD_NTSC,	/* standard     */
771 	 7,			/* reference    */
772 	 true			/* use_pre_saw    */
773 	 },
774 	{			/* ATV RF-AGC */
775 	 DRX_STANDARD_NTSC,	/* standard              */
776 	 DRX_AGC_CTRL_AUTO,	/* ctrl_mode              */
777 	 0,			/* output_level           */
778 	 0,			/* min_output_level (d.c.) */
779 	 0,			/* max_output_level (d.c.) */
780 	 3,			/* speed                 */
781 	 9500,			/* top                   */
782 	 4000			/* cut-off current       */
783 	 },
784 	{			/* ATV IF-AGC */
785 	 DRX_STANDARD_NTSC,	/* standard              */
786 	 DRX_AGC_CTRL_AUTO,	/* ctrl_mode              */
787 	 0,			/* output_level           */
788 	 0,			/* min_output_level (d.c.) */
789 	 0,			/* max_output_level (d.c.) */
790 	 3,			/* speed                 */
791 	 2400,			/* top                   */
792 	 0			/* c.o.c.         (d.c.) */
793 	 },
794 	140,			/* ATV PGA config */
795 	0,			/* curr_symbol_rate */
796 
797 	false,			/* pdr_safe_mode     */
798 	SIO_PDR_GPIO_CFG__PRE,	/* pdr_safe_restore_val_gpio  */
799 	SIO_PDR_VSYNC_CFG__PRE,	/* pdr_safe_restore_val_v_sync */
800 	SIO_PDR_SMA_RX_CFG__PRE,	/* pdr_safe_restore_val_sma_rx */
801 	SIO_PDR_SMA_TX_CFG__PRE,	/* pdr_safe_restore_val_sma_tx */
802 
803 	4,			/* oob_pre_saw            */
804 	DRXJ_OOB_LO_POW_MINUS10DB,	/* oob_lo_pow             */
805 	{
806 	 false			/* aud_data, only first member */
807 	 },
808 };
809 
810 /*
811 * \var drxj_default_addr_g
812 * \brief Default I2C address and device identifier.
813 */
814 static struct i2c_device_addr drxj_default_addr_g = {
815 	DRXJ_DEF_I2C_ADDR,	/* i2c address */
816 	DRXJ_DEF_DEMOD_DEV_ID	/* device id */
817 };
818 
819 /*
820 * \var drxj_default_comm_attr_g
821 * \brief Default common attributes of a drxj demodulator instance.
822 */
823 static struct drx_common_attr drxj_default_comm_attr_g = {
824 	NULL,			/* ucode file           */
825 	true,			/* ucode verify switch  */
826 	{0},			/* version record       */
827 
828 	44000,			/* IF in kHz in case no tuner instance is used  */
829 	(151875 - 0),		/* system clock frequency in kHz                */
830 	0,			/* oscillator frequency kHz                     */
831 	0,			/* oscillator deviation in ppm, signed          */
832 	false,			/* If true mirror frequency spectrum            */
833 	{
834 	 /* MPEG output configuration */
835 	 true,			/* If true, enable MPEG ouput    */
836 	 false,			/* If true, insert RS byte       */
837 	 false,			/* If true, parallel out otherwise serial */
838 	 false,			/* If true, invert DATA signals  */
839 	 false,			/* If true, invert ERR signal    */
840 	 false,			/* If true, invert STR signals   */
841 	 false,			/* If true, invert VAL signals   */
842 	 false,			/* If true, invert CLK signals   */
843 	 true,			/* If true, static MPEG clockrate will
844 				   be used, otherwise clockrate will
845 				   adapt to the bitrate of the TS */
846 	 19392658UL,		/* Maximum bitrate in b/s in case
847 				   static clockrate is selected */
848 	 DRX_MPEG_STR_WIDTH_1	/* MPEG Start width in clock cycles */
849 	 },
850 	/* Initilisations below can be omitted, they require no user input and
851 	   are initialy 0, NULL or false. The compiler will initialize them to these
852 	   values when omitted.  */
853 	false,			/* is_opened */
854 
855 	/* SCAN */
856 	NULL,			/* no scan params yet               */
857 	0,			/* current scan index               */
858 	0,			/* next scan frequency              */
859 	false,			/* scan ready flag                  */
860 	0,			/* max channels to scan             */
861 	0,			/* nr of channels scanned           */
862 	NULL,			/* default scan function            */
863 	NULL,			/* default context pointer          */
864 	0,			/* millisec to wait for demod lock  */
865 	DRXJ_DEMOD_LOCK,	/* desired lock               */
866 	false,
867 
868 	/* Power management */
869 	DRX_POWER_UP,
870 
871 	/* Tuner */
872 	1,			/* nr of I2C port to wich tuner is     */
873 	0L,			/* minimum RF input frequency, in kHz  */
874 	0L,			/* maximum RF input frequency, in kHz  */
875 	false,			/* Rf Agc Polarity                     */
876 	false,			/* If Agc Polarity                     */
877 	false,			/* tuner slow mode                     */
878 
879 	{			/* current channel (all 0)             */
880 	 0UL			/* channel.frequency */
881 	 },
882 	DRX_STANDARD_UNKNOWN,	/* current standard */
883 	DRX_STANDARD_UNKNOWN,	/* previous standard */
884 	DRX_STANDARD_UNKNOWN,	/* di_cache_standard   */
885 	false,			/* use_bootloader */
886 	0UL,			/* capabilities */
887 	0			/* mfx */
888 };
889 
890 /*
891 * \var drxj_default_demod_g
892 * \brief Default drxj demodulator instance.
893 */
894 static struct drx_demod_instance drxj_default_demod_g = {
895 	&drxj_default_addr_g,	/* i2c address & device id */
896 	&drxj_default_comm_attr_g,	/* demod common attributes */
897 	&drxj_data_g		/* demod device specific attributes */
898 };
899 
900 /*
901 * \brief Default audio data structure for DRK demodulator instance.
902 *
903 * This structure is DRXK specific.
904 *
905 */
906 static struct drx_aud_data drxj_default_aud_data_g = {
907 	false,			/* audio_is_active */
908 	DRX_AUD_STANDARD_AUTO,	/* audio_standard  */
909 
910 	/* i2sdata */
911 	{
912 	 false,			/* output_enable   */
913 	 48000,			/* frequency      */
914 	 DRX_I2S_MODE_MASTER,	/* mode           */
915 	 DRX_I2S_WORDLENGTH_32,	/* word_length     */
916 	 DRX_I2S_POLARITY_RIGHT,	/* polarity       */
917 	 DRX_I2S_FORMAT_WS_WITH_DATA	/* format         */
918 	 },
919 	/* volume            */
920 	{
921 	 true,			/* mute;          */
922 	 0,			/* volume         */
923 	 DRX_AUD_AVC_OFF,	/* avc_mode        */
924 	 0,			/* avc_ref_level    */
925 	 DRX_AUD_AVC_MAX_GAIN_12DB,	/* avc_max_gain     */
926 	 DRX_AUD_AVC_MAX_ATTEN_24DB,	/* avc_max_atten    */
927 	 0,			/* strength_left   */
928 	 0			/* strength_right  */
929 	 },
930 	DRX_AUD_AUTO_SOUND_SELECT_ON_CHANGE_ON,	/* auto_sound */
931 	/*  ass_thresholds */
932 	{
933 	 440,			/* A2    */
934 	 12,			/* BTSC  */
935 	 700,			/* NICAM */
936 	 },
937 	/* carrier */
938 	{
939 	 /* a */
940 	 {
941 	  42,			/* thres */
942 	  DRX_NO_CARRIER_NOISE,	/* opt   */
943 	  0,			/* shift */
944 	  0			/* dco   */
945 	  },
946 	 /* b */
947 	 {
948 	  42,			/* thres */
949 	  DRX_NO_CARRIER_MUTE,	/* opt   */
950 	  0,			/* shift */
951 	  0			/* dco   */
952 	  },
953 
954 	 },
955 	/* mixer */
956 	{
957 	 DRX_AUD_SRC_STEREO_OR_A,	/* source_i2s */
958 	 DRX_AUD_I2S_MATRIX_STEREO,	/* matrix_i2s */
959 	 DRX_AUD_FM_MATRIX_SOUND_A	/* matrix_fm  */
960 	 },
961 	DRX_AUD_DEVIATION_NORMAL,	/* deviation */
962 	DRX_AUD_AVSYNC_OFF,	/* av_sync */
963 
964 	/* prescale */
965 	{
966 	 DRX_AUD_MAX_FM_DEVIATION,	/* fm_deviation */
967 	 DRX_AUD_MAX_NICAM_PRESCALE	/* nicam_gain */
968 	 },
969 	DRX_AUD_FM_DEEMPH_75US,	/* deemph */
970 	DRX_BTSC_STEREO,	/* btsc_detect */
971 	0,			/* rds_data_counter */
972 	false			/* rds_data_present */
973 };
974 
975 /*-----------------------------------------------------------------------------
976 STRUCTURES
977 ----------------------------------------------------------------------------*/
978 struct drxjeq_stat {
979 	u16 eq_mse;
980 	u8 eq_mode;
981 	u8 eq_ctrl;
982 	u8 eq_stat;
983 };
984 
985 /* HI command */
986 struct drxj_hi_cmd {
987 	u16 cmd;
988 	u16 param1;
989 	u16 param2;
990 	u16 param3;
991 	u16 param4;
992 	u16 param5;
993 	u16 param6;
994 };
995 
996 /*============================================================================*/
997 /*=== MICROCODE RELATED STRUCTURES ===========================================*/
998 /*============================================================================*/
999 
1000 /*
1001  * struct drxu_code_block_hdr - Structure of the microcode block headers
1002  *
1003  * @addr:	Destination address of the data in this block
1004  * @size:	Size of the block data following this header counted in
1005  *		16 bits words
1006  * @CRC:	CRC value of the data block, only valid if CRC flag is
1007  *		set.
1008  */
1009 struct drxu_code_block_hdr {
1010 	u32 addr;
1011 	u16 size;
1012 	u16 flags;
1013 	u16 CRC;
1014 };
1015 
1016 /*-----------------------------------------------------------------------------
1017 FUNCTIONS
1018 ----------------------------------------------------------------------------*/
1019 /* Some prototypes */
1020 static int
1021 hi_command(struct i2c_device_addr *dev_addr,
1022 	   const struct drxj_hi_cmd *cmd, u16 *result);
1023 
1024 static int
1025 ctrl_lock_status(struct drx_demod_instance *demod, enum drx_lock_status *lock_stat);
1026 
1027 static int
1028 ctrl_power_mode(struct drx_demod_instance *demod, enum drx_power_mode *mode);
1029 
1030 static int power_down_aud(struct drx_demod_instance *demod);
1031 
1032 static int
1033 ctrl_set_cfg_pre_saw(struct drx_demod_instance *demod, struct drxj_cfg_pre_saw *pre_saw);
1034 
1035 static int
1036 ctrl_set_cfg_afe_gain(struct drx_demod_instance *demod, struct drxj_cfg_afe_gain *afe_gain);
1037 
1038 /*============================================================================*/
1039 /*============================================================================*/
1040 /*==                          HELPER FUNCTIONS                              ==*/
1041 /*============================================================================*/
1042 /*============================================================================*/
1043 
1044 
1045 /*============================================================================*/
1046 
1047 /*
1048 * \fn u32 frac28(u32 N, u32 D)
1049 * \brief Compute: (1<<28)*N/D
1050 * \param N 32 bits
1051 * \param D 32 bits
1052 * \return (1<<28)*N/D
1053 * This function is used to avoid floating-point calculations as they may
1054 * not be present on the target platform.
1055 
1056 * frac28 performs an unsigned 28/28 bits division to 32-bit fixed point
1057 * fraction used for setting the Frequency Shifter registers.
1058 * N and D can hold numbers up to width: 28-bits.
1059 * The 4 bits integer part and the 28 bits fractional part are calculated.
1060 
1061 * Usage condition: ((1<<28)*n)/d < ((1<<32)-1) => (n/d) < 15.999
1062 
1063 * N: 0...(1<<28)-1 = 268435454
1064 * D: 0...(1<<28)-1
1065 * Q: 0...(1<<32)-1
1066 */
1067 static u32 frac28(u32 N, u32 D)
1068 {
1069 	int i = 0;
1070 	u32 Q1 = 0;
1071 	u32 R0 = 0;
1072 
1073 	R0 = (N % D) << 4;	/* 32-28 == 4 shifts possible at max */
1074 	Q1 = N / D;		/* integer part, only the 4 least significant bits
1075 				   will be visible in the result */
1076 
1077 	/* division using radix 16, 7 nibbles in the result */
1078 	for (i = 0; i < 7; i++) {
1079 		Q1 = (Q1 << 4) | R0 / D;
1080 		R0 = (R0 % D) << 4;
1081 	}
1082 	/* rounding */
1083 	if ((R0 >> 3) >= D)
1084 		Q1++;
1085 
1086 	return Q1;
1087 }
1088 
1089 /*
1090 * \fn u32 log1_times100( u32 x)
1091 * \brief Compute: 100*log10(x)
1092 * \param x 32 bits
1093 * \return 100*log10(x)
1094 *
1095 * 100*log10(x)
1096 * = 100*(log2(x)/log2(10)))
1097 * = (100*(2^15)*log2(x))/((2^15)*log2(10))
1098 * = ((200*(2^15)*log2(x))/((2^15)*log2(10)))/2
1099 * = ((200*(2^15)*(log2(x/y)+log2(y)))/((2^15)*log2(10)))/2
1100 * = ((200*(2^15)*log2(x/y))+(200*(2^15)*log2(y)))/((2^15)*log2(10)))/2
1101 *
1102 * where y = 2^k and 1<= (x/y) < 2
1103 */
1104 
1105 static u32 log1_times100(u32 x)
1106 {
1107 	static const u8 scale = 15;
1108 	static const u8 index_width = 5;
1109 	/*
1110 	   log2lut[n] = (1<<scale) * 200 * log2( 1.0 + ( (1.0/(1<<INDEXWIDTH)) * n ))
1111 	   0 <= n < ((1<<INDEXWIDTH)+1)
1112 	 */
1113 
1114 	static const u32 log2lut[] = {
1115 		0,		/* 0.000000 */
1116 		290941,		/* 290941.300628 */
1117 		573196,		/* 573196.476418 */
1118 		847269,		/* 847269.179851 */
1119 		1113620,	/* 1113620.489452 */
1120 		1372674,	/* 1372673.576986 */
1121 		1624818,	/* 1624817.752104 */
1122 		1870412,	/* 1870411.981536 */
1123 		2109788,	/* 2109787.962654 */
1124 		2343253,	/* 2343252.817465 */
1125 		2571091,	/* 2571091.461923 */
1126 		2793569,	/* 2793568.696416 */
1127 		3010931,	/* 3010931.055901 */
1128 		3223408,	/* 3223408.452106 */
1129 		3431216,	/* 3431215.635215 */
1130 		3634553,	/* 3634553.498355 */
1131 		3833610,	/* 3833610.244726 */
1132 		4028562,	/* 4028562.434393 */
1133 		4219576,	/* 4219575.925308 */
1134 		4406807,	/* 4406806.721144 */
1135 		4590402,	/* 4590401.736809 */
1136 		4770499,	/* 4770499.491025 */
1137 		4947231,	/* 4947230.734179 */
1138 		5120719,	/* 5120719.018555 */
1139 		5291081,	/* 5291081.217197 */
1140 		5458428,	/* 5458427.996830 */
1141 		5622864,	/* 5622864.249668 */
1142 		5784489,	/* 5784489.488298 */
1143 		5943398,	/* 5943398.207380 */
1144 		6099680,	/* 6099680.215452 */
1145 		6253421,	/* 6253420.939751 */
1146 		6404702,	/* 6404701.706649 */
1147 		6553600,	/* 6553600.000000 */
1148 	};
1149 
1150 	u8 i = 0;
1151 	u32 y = 0;
1152 	u32 d = 0;
1153 	u32 k = 0;
1154 	u32 r = 0;
1155 
1156 	if (x == 0)
1157 		return 0;
1158 
1159 	/* Scale x (normalize) */
1160 	/* computing y in log(x/y) = log(x) - log(y) */
1161 	if ((x & (((u32) (-1)) << (scale + 1))) == 0) {
1162 		for (k = scale; k > 0; k--) {
1163 			if (x & (((u32) 1) << scale))
1164 				break;
1165 			x <<= 1;
1166 		}
1167 	} else {
1168 		for (k = scale; k < 31; k++) {
1169 			if ((x & (((u32) (-1)) << (scale + 1))) == 0)
1170 				break;
1171 			x >>= 1;
1172 		}
1173 	}
1174 	/*
1175 	   Now x has binary point between bit[scale] and bit[scale-1]
1176 	   and 1.0 <= x < 2.0 */
1177 
1178 	/* correction for division: log(x) = log(x/y)+log(y) */
1179 	y = k * ((((u32) 1) << scale) * 200);
1180 
1181 	/* remove integer part */
1182 	x &= ((((u32) 1) << scale) - 1);
1183 	/* get index */
1184 	i = (u8) (x >> (scale - index_width));
1185 	/* compute delta (x-a) */
1186 	d = x & ((((u32) 1) << (scale - index_width)) - 1);
1187 	/* compute log, multiplication ( d* (.. )) must be within range ! */
1188 	y += log2lut[i] +
1189 	    ((d * (log2lut[i + 1] - log2lut[i])) >> (scale - index_width));
1190 	/* Conver to log10() */
1191 	y /= 108853;		/* (log2(10) << scale) */
1192 	r = (y >> 1);
1193 	/* rounding */
1194 	if (y & ((u32)1))
1195 		r++;
1196 
1197 	return r;
1198 
1199 }
1200 
1201 /*
1202 * \fn u32 frac_times1e6( u16 N, u32 D)
1203 * \brief Compute: (N/D) * 1000000.
1204 * \param N nominator 16-bits.
1205 * \param D denominator 32-bits.
1206 * \return u32
1207 * \retval ((N/D) * 1000000), 32 bits
1208 *
1209 * No check on D=0!
1210 */
1211 static u32 frac_times1e6(u32 N, u32 D)
1212 {
1213 	u32 remainder = 0;
1214 	u32 frac = 0;
1215 
1216 	/*
1217 	   frac = (N * 1000000) / D
1218 	   To let it fit in a 32 bits computation:
1219 	   frac = (N * (1000000 >> 4)) / (D >> 4)
1220 	   This would result in a problem in case D < 16 (div by 0).
1221 	   So we do it more elaborate as shown below.
1222 	 */
1223 	frac = (((u32) N) * (1000000 >> 4)) / D;
1224 	frac <<= 4;
1225 	remainder = (((u32) N) * (1000000 >> 4)) % D;
1226 	remainder <<= 4;
1227 	frac += remainder / D;
1228 	remainder = remainder % D;
1229 	if ((remainder * 2) > D)
1230 		frac++;
1231 
1232 	return frac;
1233 }
1234 
1235 /*============================================================================*/
1236 
1237 
1238 /*
1239 * \brief Values for NICAM prescaler gain. Computed from dB to integer
1240 *        and rounded. For calc used formula: 16*10^(prescaleGain[dB]/20).
1241 *
1242 */
1243 #if 0
1244 /* Currently, unused as we lack support for analog TV */
1245 static const u16 nicam_presc_table_val[43] = {
1246 	1, 1, 1, 1, 2, 2, 2, 2, 3, 3, 3, 4, 4,
1247 	5, 5, 6, 6, 7, 8, 9, 10, 11, 13, 14, 16,
1248 	18, 20, 23, 25, 28, 32, 36, 40, 45,
1249 	51, 57, 64, 71, 80, 90, 101, 113, 127
1250 };
1251 #endif
1252 
1253 /*============================================================================*/
1254 /*==                        END HELPER FUNCTIONS                            ==*/
1255 /*============================================================================*/
1256 
1257 /*============================================================================*/
1258 /*============================================================================*/
1259 /*==                      DRXJ DAP FUNCTIONS                                ==*/
1260 /*============================================================================*/
1261 /*============================================================================*/
1262 
1263 /*
1264    This layer takes care of some device specific register access protocols:
1265    -conversion to short address format
1266    -access to audio block
1267    This layer is placed between the drx_dap_fasi and the rest of the drxj
1268    specific implementation. This layer can use address map knowledge whereas
1269    dap_fasi may not use memory map knowledge.
1270 
1271    * For audio currently only 16 bits read and write register access is
1272      supported. More is not needed. RMW and 32 or 8 bit access on audio
1273      registers will have undefined behaviour. Flags (RMW, CRC reset, broadcast
1274      single/multi master) will be ignored.
1275 
1276    TODO: check ignoring single/multimaster is ok for AUD access ?
1277 */
1278 
1279 #define DRXJ_ISAUDWRITE(addr) (((((addr)>>16)&1) == 1) ? true : false)
1280 #define DRXJ_DAP_AUDTRIF_TIMEOUT 80	/* millisec */
1281 /*============================================================================*/
1282 
1283 /*
1284 * \fn bool is_handled_by_aud_tr_if( u32 addr )
1285 * \brief Check if this address is handled by the audio token ring interface.
1286 * \param addr
1287 * \return bool
1288 * \retval true  Yes, handled by audio token ring interface
1289 * \retval false No, not handled by audio token ring interface
1290 *
1291 */
1292 static
1293 bool is_handled_by_aud_tr_if(u32 addr)
1294 {
1295 	bool retval = false;
1296 
1297 	if ((DRXDAP_FASI_ADDR2BLOCK(addr) == 4) &&
1298 	    (DRXDAP_FASI_ADDR2BANK(addr) > 1) &&
1299 	    (DRXDAP_FASI_ADDR2BANK(addr) < 6)) {
1300 		retval = true;
1301 	}
1302 
1303 	return retval;
1304 }
1305 
1306 /*============================================================================*/
1307 
1308 int drxbsp_i2c_write_read(struct i2c_device_addr *w_dev_addr,
1309 				 u16 w_count,
1310 				 u8 *wData,
1311 				 struct i2c_device_addr *r_dev_addr,
1312 				 u16 r_count, u8 *r_data)
1313 {
1314 	struct drx39xxj_state *state;
1315 	struct i2c_msg msg[2];
1316 	unsigned int num_msgs;
1317 
1318 	if (w_dev_addr == NULL) {
1319 		/* Read only */
1320 		state = r_dev_addr->user_data;
1321 		msg[0].addr = r_dev_addr->i2c_addr >> 1;
1322 		msg[0].flags = I2C_M_RD;
1323 		msg[0].buf = r_data;
1324 		msg[0].len = r_count;
1325 		num_msgs = 1;
1326 	} else if (r_dev_addr == NULL) {
1327 		/* Write only */
1328 		state = w_dev_addr->user_data;
1329 		msg[0].addr = w_dev_addr->i2c_addr >> 1;
1330 		msg[0].flags = 0;
1331 		msg[0].buf = wData;
1332 		msg[0].len = w_count;
1333 		num_msgs = 1;
1334 	} else {
1335 		/* Both write and read */
1336 		state = w_dev_addr->user_data;
1337 		msg[0].addr = w_dev_addr->i2c_addr >> 1;
1338 		msg[0].flags = 0;
1339 		msg[0].buf = wData;
1340 		msg[0].len = w_count;
1341 		msg[1].addr = r_dev_addr->i2c_addr >> 1;
1342 		msg[1].flags = I2C_M_RD;
1343 		msg[1].buf = r_data;
1344 		msg[1].len = r_count;
1345 		num_msgs = 2;
1346 	}
1347 
1348 	if (state->i2c == NULL) {
1349 		pr_err("i2c was zero, aborting\n");
1350 		return 0;
1351 	}
1352 	if (i2c_transfer(state->i2c, msg, num_msgs) != num_msgs) {
1353 		pr_warn("drx3933: I2C write/read failed\n");
1354 		return -EREMOTEIO;
1355 	}
1356 
1357 #ifdef DJH_DEBUG
1358 	if (w_dev_addr == NULL || r_dev_addr == NULL)
1359 		return 0;
1360 
1361 	state = w_dev_addr->user_data;
1362 
1363 	if (state->i2c == NULL)
1364 		return 0;
1365 
1366 	msg[0].addr = w_dev_addr->i2c_addr;
1367 	msg[0].flags = 0;
1368 	msg[0].buf = wData;
1369 	msg[0].len = w_count;
1370 	msg[1].addr = r_dev_addr->i2c_addr;
1371 	msg[1].flags = I2C_M_RD;
1372 	msg[1].buf = r_data;
1373 	msg[1].len = r_count;
1374 	num_msgs = 2;
1375 
1376 	pr_debug("drx3933 i2c operation addr=%x i2c=%p, wc=%x rc=%x\n",
1377 	       w_dev_addr->i2c_addr, state->i2c, w_count, r_count);
1378 
1379 	if (i2c_transfer(state->i2c, msg, 2) != 2) {
1380 		pr_warn("drx3933: I2C write/read failed\n");
1381 		return -EREMOTEIO;
1382 	}
1383 #endif
1384 	return 0;
1385 }
1386 
1387 /*============================================================================*/
1388 
1389 /*****************************
1390 *
1391 * int drxdap_fasi_read_block (
1392 *      struct i2c_device_addr *dev_addr,      -- address of I2C device
1393 *      u32 addr,         -- address of chip register/memory
1394 *      u16            datasize,     -- number of bytes to read
1395 *      u8 *data,         -- data to receive
1396 *      u32 flags)        -- special device flags
1397 *
1398 * Read block data from chip address. Because the chip is word oriented,
1399 * the number of bytes to read must be even.
1400 *
1401 * Make sure that the buffer to receive the data is large enough.
1402 *
1403 * Although this function expects an even number of bytes, it is still byte
1404 * oriented, and the data read back is NOT translated to the endianness of
1405 * the target platform.
1406 *
1407 * Output:
1408 * - 0     if reading was successful
1409 *                  in that case: data read is in *data.
1410 * - -EIO  if anything went wrong
1411 *
1412 ******************************/
1413 
1414 static int drxdap_fasi_read_block(struct i2c_device_addr *dev_addr,
1415 					 u32 addr,
1416 					 u16 datasize,
1417 					 u8 *data, u32 flags)
1418 {
1419 	u8 buf[4];
1420 	u16 bufx;
1421 	int rc;
1422 	u16 overhead_size = 0;
1423 
1424 	/* Check parameters ******************************************************* */
1425 	if (dev_addr == NULL)
1426 		return -EINVAL;
1427 
1428 	overhead_size = (IS_I2C_10BIT(dev_addr->i2c_addr) ? 2 : 1) +
1429 	    (DRXDAP_FASI_LONG_FORMAT(addr) ? 4 : 2);
1430 
1431 	if ((DRXDAP_FASI_OFFSET_TOO_LARGE(addr)) ||
1432 	    ((!(DRXDAPFASI_LONG_ADDR_ALLOWED)) &&
1433 	     DRXDAP_FASI_LONG_FORMAT(addr)) ||
1434 	    (overhead_size > (DRXDAP_MAX_WCHUNKSIZE)) ||
1435 	    ((datasize != 0) && (data == NULL)) || ((datasize & 1) == 1)) {
1436 		return -EINVAL;
1437 	}
1438 
1439 	/* ReadModifyWrite & mode flag bits are not allowed */
1440 	flags &= (~DRXDAP_FASI_RMW & ~DRXDAP_FASI_MODEFLAGS);
1441 #if DRXDAP_SINGLE_MASTER
1442 	flags |= DRXDAP_FASI_SINGLE_MASTER;
1443 #endif
1444 
1445 	/* Read block from I2C **************************************************** */
1446 	do {
1447 		u16 todo = (datasize < DRXDAP_MAX_RCHUNKSIZE ?
1448 			      datasize : DRXDAP_MAX_RCHUNKSIZE);
1449 
1450 		bufx = 0;
1451 
1452 		addr &= ~DRXDAP_FASI_FLAGS;
1453 		addr |= flags;
1454 
1455 #if ((DRXDAPFASI_LONG_ADDR_ALLOWED == 1) && (DRXDAPFASI_SHORT_ADDR_ALLOWED == 1))
1456 		/* short format address preferred but long format otherwise */
1457 		if (DRXDAP_FASI_LONG_FORMAT(addr)) {
1458 #endif
1459 #if (DRXDAPFASI_LONG_ADDR_ALLOWED == 1)
1460 			buf[bufx++] = (u8) (((addr << 1) & 0xFF) | 0x01);
1461 			buf[bufx++] = (u8) ((addr >> 16) & 0xFF);
1462 			buf[bufx++] = (u8) ((addr >> 24) & 0xFF);
1463 			buf[bufx++] = (u8) ((addr >> 7) & 0xFF);
1464 #endif
1465 #if ((DRXDAPFASI_LONG_ADDR_ALLOWED == 1) && (DRXDAPFASI_SHORT_ADDR_ALLOWED == 1))
1466 		} else {
1467 #endif
1468 #if (DRXDAPFASI_SHORT_ADDR_ALLOWED == 1)
1469 			buf[bufx++] = (u8) ((addr << 1) & 0xFF);
1470 			buf[bufx++] =
1471 			    (u8) (((addr >> 16) & 0x0F) |
1472 				    ((addr >> 18) & 0xF0));
1473 #endif
1474 #if ((DRXDAPFASI_LONG_ADDR_ALLOWED == 1) && (DRXDAPFASI_SHORT_ADDR_ALLOWED == 1))
1475 		}
1476 #endif
1477 
1478 #if DRXDAP_SINGLE_MASTER
1479 		/*
1480 		 * In single master mode, split the read and write actions.
1481 		 * No special action is needed for write chunks here.
1482 		 */
1483 		rc = drxbsp_i2c_write_read(dev_addr, bufx, buf,
1484 					   NULL, 0, NULL);
1485 		if (rc == 0)
1486 			rc = drxbsp_i2c_write_read(NULL, 0, NULL, dev_addr, todo, data);
1487 #else
1488 		/* In multi master mode, do everything in one RW action */
1489 		rc = drxbsp_i2c_write_read(dev_addr, bufx, buf, dev_addr, todo,
1490 					  data);
1491 #endif
1492 		data += todo;
1493 		addr += (todo >> 1);
1494 		datasize -= todo;
1495 	} while (datasize && rc == 0);
1496 
1497 	return rc;
1498 }
1499 
1500 
1501 /*****************************
1502 *
1503 * int drxdap_fasi_read_reg16 (
1504 *     struct i2c_device_addr *dev_addr, -- address of I2C device
1505 *     u32 addr,    -- address of chip register/memory
1506 *     u16 *data,    -- data to receive
1507 *     u32 flags)   -- special device flags
1508 *
1509 * Read one 16-bit register or memory location. The data received back is
1510 * converted back to the target platform's endianness.
1511 *
1512 * Output:
1513 * - 0     if reading was successful
1514 *                  in that case: read data is at *data
1515 * - -EIO  if anything went wrong
1516 *
1517 ******************************/
1518 
1519 static int drxdap_fasi_read_reg16(struct i2c_device_addr *dev_addr,
1520 					 u32 addr,
1521 					 u16 *data, u32 flags)
1522 {
1523 	u8 buf[sizeof(*data)];
1524 	int rc;
1525 
1526 	if (!data)
1527 		return -EINVAL;
1528 
1529 	rc = drxdap_fasi_read_block(dev_addr, addr, sizeof(*data), buf, flags);
1530 	*data = buf[0] + (((u16) buf[1]) << 8);
1531 	return rc;
1532 }
1533 
1534 /*****************************
1535 *
1536 * int drxdap_fasi_read_reg32 (
1537 *     struct i2c_device_addr *dev_addr, -- address of I2C device
1538 *     u32 addr,    -- address of chip register/memory
1539 *     u32 *data,    -- data to receive
1540 *     u32 flags)   -- special device flags
1541 *
1542 * Read one 32-bit register or memory location. The data received back is
1543 * converted back to the target platform's endianness.
1544 *
1545 * Output:
1546 * - 0     if reading was successful
1547 *                  in that case: read data is at *data
1548 * - -EIO  if anything went wrong
1549 *
1550 ******************************/
1551 
1552 static int drxdap_fasi_read_reg32(struct i2c_device_addr *dev_addr,
1553 					 u32 addr,
1554 					 u32 *data, u32 flags)
1555 {
1556 	u8 buf[sizeof(*data)];
1557 	int rc;
1558 
1559 	if (!data)
1560 		return -EINVAL;
1561 
1562 	rc = drxdap_fasi_read_block(dev_addr, addr, sizeof(*data), buf, flags);
1563 	*data = (((u32) buf[0]) << 0) +
1564 	    (((u32) buf[1]) << 8) +
1565 	    (((u32) buf[2]) << 16) + (((u32) buf[3]) << 24);
1566 	return rc;
1567 }
1568 
1569 /*****************************
1570 *
1571 * int drxdap_fasi_write_block (
1572 *      struct i2c_device_addr *dev_addr,    -- address of I2C device
1573 *      u32 addr,       -- address of chip register/memory
1574 *      u16            datasize,   -- number of bytes to read
1575 *      u8 *data,       -- data to receive
1576 *      u32 flags)      -- special device flags
1577 *
1578 * Write block data to chip address. Because the chip is word oriented,
1579 * the number of bytes to write must be even.
1580 *
1581 * Although this function expects an even number of bytes, it is still byte
1582 * oriented, and the data being written is NOT translated from the endianness of
1583 * the target platform.
1584 *
1585 * Output:
1586 * - 0     if writing was successful
1587 * - -EIO  if anything went wrong
1588 *
1589 ******************************/
1590 
1591 static int drxdap_fasi_write_block(struct i2c_device_addr *dev_addr,
1592 					  u32 addr,
1593 					  u16 datasize,
1594 					  u8 *data, u32 flags)
1595 {
1596 	u8 buf[DRXDAP_MAX_WCHUNKSIZE];
1597 	int st = -EIO;
1598 	int first_err = 0;
1599 	u16 overhead_size = 0;
1600 	u16 block_size = 0;
1601 
1602 	/* Check parameters ******************************************************* */
1603 	if (dev_addr == NULL)
1604 		return -EINVAL;
1605 
1606 	overhead_size = (IS_I2C_10BIT(dev_addr->i2c_addr) ? 2 : 1) +
1607 	    (DRXDAP_FASI_LONG_FORMAT(addr) ? 4 : 2);
1608 
1609 	if ((DRXDAP_FASI_OFFSET_TOO_LARGE(addr)) ||
1610 	    ((!(DRXDAPFASI_LONG_ADDR_ALLOWED)) &&
1611 	     DRXDAP_FASI_LONG_FORMAT(addr)) ||
1612 	    (overhead_size > (DRXDAP_MAX_WCHUNKSIZE)) ||
1613 	    ((datasize != 0) && (data == NULL)) || ((datasize & 1) == 1))
1614 		return -EINVAL;
1615 
1616 	flags &= DRXDAP_FASI_FLAGS;
1617 	flags &= ~DRXDAP_FASI_MODEFLAGS;
1618 #if DRXDAP_SINGLE_MASTER
1619 	flags |= DRXDAP_FASI_SINGLE_MASTER;
1620 #endif
1621 
1622 	/* Write block to I2C ***************************************************** */
1623 	block_size = ((DRXDAP_MAX_WCHUNKSIZE) - overhead_size) & ~1;
1624 	do {
1625 		u16 todo = 0;
1626 		u16 bufx = 0;
1627 
1628 		/* Buffer device address */
1629 		addr &= ~DRXDAP_FASI_FLAGS;
1630 		addr |= flags;
1631 #if (((DRXDAPFASI_LONG_ADDR_ALLOWED) == 1) && ((DRXDAPFASI_SHORT_ADDR_ALLOWED) == 1))
1632 		/* short format address preferred but long format otherwise */
1633 		if (DRXDAP_FASI_LONG_FORMAT(addr)) {
1634 #endif
1635 #if ((DRXDAPFASI_LONG_ADDR_ALLOWED) == 1)
1636 			buf[bufx++] = (u8) (((addr << 1) & 0xFF) | 0x01);
1637 			buf[bufx++] = (u8) ((addr >> 16) & 0xFF);
1638 			buf[bufx++] = (u8) ((addr >> 24) & 0xFF);
1639 			buf[bufx++] = (u8) ((addr >> 7) & 0xFF);
1640 #endif
1641 #if (((DRXDAPFASI_LONG_ADDR_ALLOWED) == 1) && ((DRXDAPFASI_SHORT_ADDR_ALLOWED) == 1))
1642 		} else {
1643 #endif
1644 #if ((DRXDAPFASI_SHORT_ADDR_ALLOWED) == 1)
1645 			buf[bufx++] = (u8) ((addr << 1) & 0xFF);
1646 			buf[bufx++] =
1647 			    (u8) (((addr >> 16) & 0x0F) |
1648 				    ((addr >> 18) & 0xF0));
1649 #endif
1650 #if (((DRXDAPFASI_LONG_ADDR_ALLOWED) == 1) && ((DRXDAPFASI_SHORT_ADDR_ALLOWED) == 1))
1651 		}
1652 #endif
1653 
1654 		/*
1655 		   In single master mode block_size can be 0. In such a case this I2C
1656 		   sequense will be visible: (1) write address {i2c addr,
1657 		   4 bytes chip address} (2) write data {i2c addr, 4 bytes data }
1658 		   (3) write address (4) write data etc...
1659 		   Address must be rewriten because HI is reset after data transport and
1660 		   expects an address.
1661 		 */
1662 		todo = (block_size < datasize ? block_size : datasize);
1663 		if (todo == 0) {
1664 			u16 overhead_size_i2c_addr = 0;
1665 			u16 data_block_size = 0;
1666 
1667 			overhead_size_i2c_addr =
1668 			    (IS_I2C_10BIT(dev_addr->i2c_addr) ? 2 : 1);
1669 			data_block_size =
1670 			    (DRXDAP_MAX_WCHUNKSIZE - overhead_size_i2c_addr) & ~1;
1671 
1672 			/* write device address */
1673 			st = drxbsp_i2c_write_read(dev_addr,
1674 						  (u16) (bufx),
1675 						  buf,
1676 						  (struct i2c_device_addr *)(NULL),
1677 						  0, (u8 *)(NULL));
1678 
1679 			if ((st != 0) && (first_err == 0)) {
1680 				/* at the end, return the first error encountered */
1681 				first_err = st;
1682 			}
1683 			bufx = 0;
1684 			todo =
1685 			    (data_block_size <
1686 			     datasize ? data_block_size : datasize);
1687 		}
1688 		memcpy(&buf[bufx], data, todo);
1689 		/* write (address if can do and) data */
1690 		st = drxbsp_i2c_write_read(dev_addr,
1691 					  (u16) (bufx + todo),
1692 					  buf,
1693 					  (struct i2c_device_addr *)(NULL),
1694 					  0, (u8 *)(NULL));
1695 
1696 		if ((st != 0) && (first_err == 0)) {
1697 			/* at the end, return the first error encountered */
1698 			first_err = st;
1699 		}
1700 		datasize -= todo;
1701 		data += todo;
1702 		addr += (todo >> 1);
1703 	} while (datasize);
1704 
1705 	return first_err;
1706 }
1707 
1708 /*****************************
1709 *
1710 * int drxdap_fasi_write_reg16 (
1711 *     struct i2c_device_addr *dev_addr, -- address of I2C device
1712 *     u32 addr,    -- address of chip register/memory
1713 *     u16            data,    -- data to send
1714 *     u32 flags)   -- special device flags
1715 *
1716 * Write one 16-bit register or memory location. The data being written is
1717 * converted from the target platform's endianness to little endian.
1718 *
1719 * Output:
1720 * - 0     if writing was successful
1721 * - -EIO  if anything went wrong
1722 *
1723 ******************************/
1724 
1725 static int drxdap_fasi_write_reg16(struct i2c_device_addr *dev_addr,
1726 					  u32 addr,
1727 					  u16 data, u32 flags)
1728 {
1729 	u8 buf[sizeof(data)];
1730 
1731 	buf[0] = (u8) ((data >> 0) & 0xFF);
1732 	buf[1] = (u8) ((data >> 8) & 0xFF);
1733 
1734 	return drxdap_fasi_write_block(dev_addr, addr, sizeof(data), buf, flags);
1735 }
1736 
1737 /*****************************
1738 *
1739 * int drxdap_fasi_read_modify_write_reg16 (
1740 *      struct i2c_device_addr *dev_addr,   -- address of I2C device
1741 *      u32 waddr,     -- address of chip register/memory
1742 *      u32 raddr,     -- chip address to read back from
1743 *      u16            wdata,     -- data to send
1744 *      u16 *rdata)     -- data to receive back
1745 *
1746 * Write 16-bit data, then read back the original contents of that location.
1747 * Requires long addressing format to be allowed.
1748 *
1749 * Before sending data, the data is converted to little endian. The
1750 * data received back is converted back to the target platform's endianness.
1751 *
1752 * WARNING: This function is only guaranteed to work if there is one
1753 * master on the I2C bus.
1754 *
1755 * Output:
1756 * - 0     if reading was successful
1757 *                  in that case: read back data is at *rdata
1758 * - -EIO  if anything went wrong
1759 *
1760 ******************************/
1761 
1762 static int drxdap_fasi_read_modify_write_reg16(struct i2c_device_addr *dev_addr,
1763 						    u32 waddr,
1764 						    u32 raddr,
1765 						    u16 wdata, u16 *rdata)
1766 {
1767 	int rc = -EIO;
1768 
1769 #if (DRXDAPFASI_LONG_ADDR_ALLOWED == 1)
1770 	if (rdata == NULL)
1771 		return -EINVAL;
1772 
1773 	rc = drxdap_fasi_write_reg16(dev_addr, waddr, wdata, DRXDAP_FASI_RMW);
1774 	if (rc == 0)
1775 		rc = drxdap_fasi_read_reg16(dev_addr, raddr, rdata, 0);
1776 #endif
1777 
1778 	return rc;
1779 }
1780 
1781 /*****************************
1782 *
1783 * int drxdap_fasi_write_reg32 (
1784 *     struct i2c_device_addr *dev_addr, -- address of I2C device
1785 *     u32 addr,    -- address of chip register/memory
1786 *     u32            data,    -- data to send
1787 *     u32 flags)   -- special device flags
1788 *
1789 * Write one 32-bit register or memory location. The data being written is
1790 * converted from the target platform's endianness to little endian.
1791 *
1792 * Output:
1793 * - 0     if writing was successful
1794 * - -EIO  if anything went wrong
1795 *
1796 ******************************/
1797 
1798 static int drxdap_fasi_write_reg32(struct i2c_device_addr *dev_addr,
1799 					  u32 addr,
1800 					  u32 data, u32 flags)
1801 {
1802 	u8 buf[sizeof(data)];
1803 
1804 	buf[0] = (u8) ((data >> 0) & 0xFF);
1805 	buf[1] = (u8) ((data >> 8) & 0xFF);
1806 	buf[2] = (u8) ((data >> 16) & 0xFF);
1807 	buf[3] = (u8) ((data >> 24) & 0xFF);
1808 
1809 	return drxdap_fasi_write_block(dev_addr, addr, sizeof(data), buf, flags);
1810 }
1811 
1812 /*============================================================================*/
1813 
1814 /*
1815 * \fn int drxj_dap_rm_write_reg16short
1816 * \brief Read modify write 16 bits audio register using short format only.
1817 * \param dev_addr
1818 * \param waddr    Address to write to
1819 * \param raddr    Address to read from (usually SIO_HI_RA_RAM_S0_RMWBUF__A)
1820 * \param wdata    Data to write
1821 * \param rdata    Buffer for data to read
1822 * \return int
1823 * \retval 0 Succes
1824 * \retval -EIO Timeout, I2C error, illegal bank
1825 *
1826 * 16 bits register read modify write access using short addressing format only.
1827 * Requires knowledge of the registermap, thus device dependent.
1828 * Using DAP FASI directly to avoid endless recursion of RMWs to audio registers.
1829 *
1830 */
1831 
1832 /* TODO correct define should be #if ( DRXDAPFASI_SHORT_ADDR_ALLOWED==1 )
1833    See comments drxj_dap_read_modify_write_reg16 */
1834 #if (DRXDAPFASI_LONG_ADDR_ALLOWED == 0)
1835 static int drxj_dap_rm_write_reg16short(struct i2c_device_addr *dev_addr,
1836 					      u32 waddr,
1837 					      u32 raddr,
1838 					      u16 wdata, u16 *rdata)
1839 {
1840 	int rc;
1841 
1842 	if (rdata == NULL)
1843 		return -EINVAL;
1844 
1845 	/* Set RMW flag */
1846 	rc = drxdap_fasi_write_reg16(dev_addr,
1847 					      SIO_HI_RA_RAM_S0_FLG_ACC__A,
1848 					      SIO_HI_RA_RAM_S0_FLG_ACC_S0_RWM__M,
1849 					      0x0000);
1850 	if (rc == 0) {
1851 		/* Write new data: triggers RMW */
1852 		rc = drxdap_fasi_write_reg16(dev_addr, waddr, wdata,
1853 						      0x0000);
1854 	}
1855 	if (rc == 0) {
1856 		/* Read old data */
1857 		rc = drxdap_fasi_read_reg16(dev_addr, raddr, rdata,
1858 						     0x0000);
1859 	}
1860 	if (rc == 0) {
1861 		/* Reset RMW flag */
1862 		rc = drxdap_fasi_write_reg16(dev_addr,
1863 						      SIO_HI_RA_RAM_S0_FLG_ACC__A,
1864 						      0, 0x0000);
1865 	}
1866 
1867 	return rc;
1868 }
1869 #endif
1870 
1871 /*============================================================================*/
1872 
1873 static int drxj_dap_read_modify_write_reg16(struct i2c_device_addr *dev_addr,
1874 						 u32 waddr,
1875 						 u32 raddr,
1876 						 u16 wdata, u16 *rdata)
1877 {
1878 	/* TODO: correct short/long addressing format decision,
1879 	   now long format has higher prio then short because short also
1880 	   needs virt bnks (not impl yet) for certain audio registers */
1881 #if (DRXDAPFASI_LONG_ADDR_ALLOWED == 1)
1882 	return drxdap_fasi_read_modify_write_reg16(dev_addr,
1883 							  waddr,
1884 							  raddr, wdata, rdata);
1885 #else
1886 	return drxj_dap_rm_write_reg16short(dev_addr, waddr, raddr, wdata, rdata);
1887 #endif
1888 }
1889 
1890 
1891 /*============================================================================*/
1892 
1893 /*
1894 * \fn int drxj_dap_read_aud_reg16
1895 * \brief Read 16 bits audio register
1896 * \param dev_addr
1897 * \param addr
1898 * \param data
1899 * \return int
1900 * \retval 0 Succes
1901 * \retval -EIO Timeout, I2C error, illegal bank
1902 *
1903 * 16 bits register read access via audio token ring interface.
1904 *
1905 */
1906 static int drxj_dap_read_aud_reg16(struct i2c_device_addr *dev_addr,
1907 					 u32 addr, u16 *data)
1908 {
1909 	u32 start_timer = 0;
1910 	u32 current_timer = 0;
1911 	u32 delta_timer = 0;
1912 	u16 tr_status = 0;
1913 	int stat = -EIO;
1914 
1915 	/* No read possible for bank 3, return with error */
1916 	if (DRXDAP_FASI_ADDR2BANK(addr) == 3) {
1917 		stat = -EINVAL;
1918 	} else {
1919 		const u32 write_bit = ((dr_xaddr_t) 1) << 16;
1920 
1921 		/* Force reset write bit */
1922 		addr &= (~write_bit);
1923 
1924 		/* Set up read */
1925 		start_timer = jiffies_to_msecs(jiffies);
1926 		do {
1927 			/* RMW to aud TR IF until request is granted or timeout */
1928 			stat = drxj_dap_read_modify_write_reg16(dev_addr,
1929 							     addr,
1930 							     SIO_HI_RA_RAM_S0_RMWBUF__A,
1931 							     0x0000, &tr_status);
1932 
1933 			if (stat != 0)
1934 				break;
1935 
1936 			current_timer = jiffies_to_msecs(jiffies);
1937 			delta_timer = current_timer - start_timer;
1938 			if (delta_timer > DRXJ_DAP_AUDTRIF_TIMEOUT) {
1939 				stat = -EIO;
1940 				break;
1941 			}
1942 
1943 		} while (((tr_status & AUD_TOP_TR_CTR_FIFO_LOCK__M) ==
1944 			  AUD_TOP_TR_CTR_FIFO_LOCK_LOCKED) ||
1945 			 ((tr_status & AUD_TOP_TR_CTR_FIFO_FULL__M) ==
1946 			  AUD_TOP_TR_CTR_FIFO_FULL_FULL));
1947 	}			/* if ( DRXDAP_FASI_ADDR2BANK(addr)!=3 ) */
1948 
1949 	/* Wait for read ready status or timeout */
1950 	if (stat == 0) {
1951 		start_timer = jiffies_to_msecs(jiffies);
1952 
1953 		while ((tr_status & AUD_TOP_TR_CTR_FIFO_RD_RDY__M) !=
1954 		       AUD_TOP_TR_CTR_FIFO_RD_RDY_READY) {
1955 			stat = drxj_dap_read_reg16(dev_addr,
1956 						  AUD_TOP_TR_CTR__A,
1957 						  &tr_status, 0x0000);
1958 			if (stat != 0)
1959 				break;
1960 
1961 			current_timer = jiffies_to_msecs(jiffies);
1962 			delta_timer = current_timer - start_timer;
1963 			if (delta_timer > DRXJ_DAP_AUDTRIF_TIMEOUT) {
1964 				stat = -EIO;
1965 				break;
1966 			}
1967 		}		/* while ( ... ) */
1968 	}
1969 
1970 	/* Read value */
1971 	if (stat == 0)
1972 		stat = drxj_dap_read_modify_write_reg16(dev_addr,
1973 						     AUD_TOP_TR_RD_REG__A,
1974 						     SIO_HI_RA_RAM_S0_RMWBUF__A,
1975 						     0x0000, data);
1976 	return stat;
1977 }
1978 
1979 /*============================================================================*/
1980 
1981 static int drxj_dap_read_reg16(struct i2c_device_addr *dev_addr,
1982 				      u32 addr,
1983 				      u16 *data, u32 flags)
1984 {
1985 	int stat = -EIO;
1986 
1987 	/* Check param */
1988 	if ((dev_addr == NULL) || (data == NULL))
1989 		return -EINVAL;
1990 
1991 	if (is_handled_by_aud_tr_if(addr))
1992 		stat = drxj_dap_read_aud_reg16(dev_addr, addr, data);
1993 	else
1994 		stat = drxdap_fasi_read_reg16(dev_addr, addr, data, flags);
1995 
1996 	return stat;
1997 }
1998 /*============================================================================*/
1999 
2000 /*
2001 * \fn int drxj_dap_write_aud_reg16
2002 * \brief Write 16 bits audio register
2003 * \param dev_addr
2004 * \param addr
2005 * \param data
2006 * \return int
2007 * \retval 0 Succes
2008 * \retval -EIO Timeout, I2C error, illegal bank
2009 *
2010 * 16 bits register write access via audio token ring interface.
2011 *
2012 */
2013 static int drxj_dap_write_aud_reg16(struct i2c_device_addr *dev_addr,
2014 					  u32 addr, u16 data)
2015 {
2016 	int stat = -EIO;
2017 
2018 	/* No write possible for bank 2, return with error */
2019 	if (DRXDAP_FASI_ADDR2BANK(addr) == 2) {
2020 		stat = -EINVAL;
2021 	} else {
2022 		u32 start_timer = 0;
2023 		u32 current_timer = 0;
2024 		u32 delta_timer = 0;
2025 		u16 tr_status = 0;
2026 		const u32 write_bit = ((dr_xaddr_t) 1) << 16;
2027 
2028 		/* Force write bit */
2029 		addr |= write_bit;
2030 		start_timer = jiffies_to_msecs(jiffies);
2031 		do {
2032 			/* RMW to aud TR IF until request is granted or timeout */
2033 			stat = drxj_dap_read_modify_write_reg16(dev_addr,
2034 							     addr,
2035 							     SIO_HI_RA_RAM_S0_RMWBUF__A,
2036 							     data, &tr_status);
2037 			if (stat != 0)
2038 				break;
2039 
2040 			current_timer = jiffies_to_msecs(jiffies);
2041 			delta_timer = current_timer - start_timer;
2042 			if (delta_timer > DRXJ_DAP_AUDTRIF_TIMEOUT) {
2043 				stat = -EIO;
2044 				break;
2045 			}
2046 
2047 		} while (((tr_status & AUD_TOP_TR_CTR_FIFO_LOCK__M) ==
2048 			  AUD_TOP_TR_CTR_FIFO_LOCK_LOCKED) ||
2049 			 ((tr_status & AUD_TOP_TR_CTR_FIFO_FULL__M) ==
2050 			  AUD_TOP_TR_CTR_FIFO_FULL_FULL));
2051 
2052 	}			/* if ( DRXDAP_FASI_ADDR2BANK(addr)!=2 ) */
2053 
2054 	return stat;
2055 }
2056 
2057 /*============================================================================*/
2058 
2059 static int drxj_dap_write_reg16(struct i2c_device_addr *dev_addr,
2060 				       u32 addr,
2061 				       u16 data, u32 flags)
2062 {
2063 	int stat = -EIO;
2064 
2065 	/* Check param */
2066 	if (dev_addr == NULL)
2067 		return -EINVAL;
2068 
2069 	if (is_handled_by_aud_tr_if(addr))
2070 		stat = drxj_dap_write_aud_reg16(dev_addr, addr, data);
2071 	else
2072 		stat = drxdap_fasi_write_reg16(dev_addr,
2073 							    addr, data, flags);
2074 
2075 	return stat;
2076 }
2077 
2078 /*============================================================================*/
2079 
2080 /* Free data ram in SIO HI */
2081 #define SIO_HI_RA_RAM_USR_BEGIN__A 0x420040
2082 #define SIO_HI_RA_RAM_USR_END__A   0x420060
2083 
2084 #define DRXJ_HI_ATOMIC_BUF_START (SIO_HI_RA_RAM_USR_BEGIN__A)
2085 #define DRXJ_HI_ATOMIC_BUF_END   (SIO_HI_RA_RAM_USR_BEGIN__A + 7)
2086 #define DRXJ_HI_ATOMIC_READ      SIO_HI_RA_RAM_PAR_3_ACP_RW_READ
2087 #define DRXJ_HI_ATOMIC_WRITE     SIO_HI_RA_RAM_PAR_3_ACP_RW_WRITE
2088 
2089 /*
2090 * \fn int drxj_dap_atomic_read_write_block()
2091 * \brief Basic access routine for atomic read or write access
2092 * \param dev_addr  pointer to i2c dev address
2093 * \param addr     destination/source address
2094 * \param datasize size of data buffer in bytes
2095 * \param data     pointer to data buffer
2096 * \return int
2097 * \retval 0 Succes
2098 * \retval -EIO Timeout, I2C error, illegal bank
2099 *
2100 */
2101 static
2102 int drxj_dap_atomic_read_write_block(struct i2c_device_addr *dev_addr,
2103 					  u32 addr,
2104 					  u16 datasize,
2105 					  u8 *data, bool read_flag)
2106 {
2107 	struct drxj_hi_cmd hi_cmd;
2108 	int rc;
2109 	u16 word;
2110 	u16 dummy = 0;
2111 	u16 i = 0;
2112 
2113 	/* Parameter check */
2114 	if (!data || !dev_addr || ((datasize % 2)) || ((datasize / 2) > 8))
2115 		return -EINVAL;
2116 
2117 	/* Set up HI parameters to read or write n bytes */
2118 	hi_cmd.cmd = SIO_HI_RA_RAM_CMD_ATOMIC_COPY;
2119 	hi_cmd.param1 =
2120 	    (u16) ((DRXDAP_FASI_ADDR2BLOCK(DRXJ_HI_ATOMIC_BUF_START) << 6) +
2121 		     DRXDAP_FASI_ADDR2BANK(DRXJ_HI_ATOMIC_BUF_START));
2122 	hi_cmd.param2 =
2123 	    (u16) DRXDAP_FASI_ADDR2OFFSET(DRXJ_HI_ATOMIC_BUF_START);
2124 	hi_cmd.param3 = (u16) ((datasize / 2) - 1);
2125 	if (!read_flag)
2126 		hi_cmd.param3 |= DRXJ_HI_ATOMIC_WRITE;
2127 	else
2128 		hi_cmd.param3 |= DRXJ_HI_ATOMIC_READ;
2129 	hi_cmd.param4 = (u16) ((DRXDAP_FASI_ADDR2BLOCK(addr) << 6) +
2130 				DRXDAP_FASI_ADDR2BANK(addr));
2131 	hi_cmd.param5 = (u16) DRXDAP_FASI_ADDR2OFFSET(addr);
2132 
2133 	if (!read_flag) {
2134 		/* write data to buffer */
2135 		for (i = 0; i < (datasize / 2); i++) {
2136 
2137 			word = ((u16) data[2 * i]);
2138 			word += (((u16) data[(2 * i) + 1]) << 8);
2139 			drxj_dap_write_reg16(dev_addr,
2140 					     (DRXJ_HI_ATOMIC_BUF_START + i),
2141 					    word, 0);
2142 		}
2143 	}
2144 
2145 	rc = hi_command(dev_addr, &hi_cmd, &dummy);
2146 	if (rc != 0) {
2147 		pr_err("error %d\n", rc);
2148 		goto rw_error;
2149 	}
2150 
2151 	if (read_flag) {
2152 		/* read data from buffer */
2153 		for (i = 0; i < (datasize / 2); i++) {
2154 			rc = drxj_dap_read_reg16(dev_addr,
2155 						 (DRXJ_HI_ATOMIC_BUF_START + i),
2156 						 &word, 0);
2157 			if (rc) {
2158 				pr_err("error %d\n", rc);
2159 				goto rw_error;
2160 			}
2161 			data[2 * i] = (u8) (word & 0xFF);
2162 			data[(2 * i) + 1] = (u8) (word >> 8);
2163 		}
2164 	}
2165 
2166 	return 0;
2167 
2168 rw_error:
2169 	return rc;
2170 
2171 }
2172 
2173 /*============================================================================*/
2174 
2175 /*
2176 * \fn int drxj_dap_atomic_read_reg32()
2177 * \brief Atomic read of 32 bits words
2178 */
2179 static
2180 int drxj_dap_atomic_read_reg32(struct i2c_device_addr *dev_addr,
2181 				     u32 addr,
2182 				     u32 *data, u32 flags)
2183 {
2184 	u8 buf[sizeof(*data)] = { 0 };
2185 	int rc = -EIO;
2186 	u32 word = 0;
2187 
2188 	if (!data)
2189 		return -EINVAL;
2190 
2191 	rc = drxj_dap_atomic_read_write_block(dev_addr, addr,
2192 					      sizeof(*data), buf, true);
2193 
2194 	if (rc < 0)
2195 		return 0;
2196 
2197 	word = (u32) buf[3];
2198 	word <<= 8;
2199 	word |= (u32) buf[2];
2200 	word <<= 8;
2201 	word |= (u32) buf[1];
2202 	word <<= 8;
2203 	word |= (u32) buf[0];
2204 
2205 	*data = word;
2206 
2207 	return rc;
2208 }
2209 
2210 /*============================================================================*/
2211 
2212 /*============================================================================*/
2213 /*==                        END DRXJ DAP FUNCTIONS                          ==*/
2214 /*============================================================================*/
2215 
2216 /*============================================================================*/
2217 /*============================================================================*/
2218 /*==                      HOST INTERFACE FUNCTIONS                          ==*/
2219 /*============================================================================*/
2220 /*============================================================================*/
2221 
2222 /*
2223 * \fn int hi_cfg_command()
2224 * \brief Configure HI with settings stored in the demod structure.
2225 * \param demod Demodulator.
2226 * \return int.
2227 *
2228 * This routine was created because to much orthogonal settings have
2229 * been put into one HI API function (configure). Especially the I2C bridge
2230 * enable/disable should not need re-configuration of the HI.
2231 *
2232 */
2233 static int hi_cfg_command(const struct drx_demod_instance *demod)
2234 {
2235 	struct drxj_data *ext_attr = (struct drxj_data *) (NULL);
2236 	struct drxj_hi_cmd hi_cmd;
2237 	u16 result = 0;
2238 	int rc;
2239 
2240 	ext_attr = (struct drxj_data *) demod->my_ext_attr;
2241 
2242 	hi_cmd.cmd = SIO_HI_RA_RAM_CMD_CONFIG;
2243 	hi_cmd.param1 = SIO_HI_RA_RAM_PAR_1_PAR1_SEC_KEY;
2244 	hi_cmd.param2 = ext_attr->hi_cfg_timing_div;
2245 	hi_cmd.param3 = ext_attr->hi_cfg_bridge_delay;
2246 	hi_cmd.param4 = ext_attr->hi_cfg_wake_up_key;
2247 	hi_cmd.param5 = ext_attr->hi_cfg_ctrl;
2248 	hi_cmd.param6 = ext_attr->hi_cfg_transmit;
2249 
2250 	rc = hi_command(demod->my_i2c_dev_addr, &hi_cmd, &result);
2251 	if (rc != 0) {
2252 		pr_err("error %d\n", rc);
2253 		goto rw_error;
2254 	}
2255 
2256 	/* Reset power down flag (set one call only) */
2257 	ext_attr->hi_cfg_ctrl &= (~(SIO_HI_RA_RAM_PAR_5_CFG_SLEEP_ZZZ));
2258 
2259 	return 0;
2260 
2261 rw_error:
2262 	return rc;
2263 }
2264 
2265 /*
2266 * \fn int hi_command()
2267 * \brief Configure HI with settings stored in the demod structure.
2268 * \param dev_addr I2C address.
2269 * \param cmd HI command.
2270 * \param result HI command result.
2271 * \return int.
2272 *
2273 * Sends command to HI
2274 *
2275 */
2276 static int
2277 hi_command(struct i2c_device_addr *dev_addr, const struct drxj_hi_cmd *cmd, u16 *result)
2278 {
2279 	u16 wait_cmd = 0;
2280 	u16 nr_retries = 0;
2281 	bool powerdown_cmd = false;
2282 	int rc;
2283 
2284 	/* Write parameters */
2285 	switch (cmd->cmd) {
2286 
2287 	case SIO_HI_RA_RAM_CMD_CONFIG:
2288 	case SIO_HI_RA_RAM_CMD_ATOMIC_COPY:
2289 		rc = drxj_dap_write_reg16(dev_addr, SIO_HI_RA_RAM_PAR_6__A, cmd->param6, 0);
2290 		if (rc != 0) {
2291 			pr_err("error %d\n", rc);
2292 			goto rw_error;
2293 		}
2294 		rc = drxj_dap_write_reg16(dev_addr, SIO_HI_RA_RAM_PAR_5__A, cmd->param5, 0);
2295 		if (rc != 0) {
2296 			pr_err("error %d\n", rc);
2297 			goto rw_error;
2298 		}
2299 		rc = drxj_dap_write_reg16(dev_addr, SIO_HI_RA_RAM_PAR_4__A, cmd->param4, 0);
2300 		if (rc != 0) {
2301 			pr_err("error %d\n", rc);
2302 			goto rw_error;
2303 		}
2304 		rc = drxj_dap_write_reg16(dev_addr, SIO_HI_RA_RAM_PAR_3__A, cmd->param3, 0);
2305 		if (rc != 0) {
2306 			pr_err("error %d\n", rc);
2307 			goto rw_error;
2308 		}
2309 		/* fallthrough */
2310 	case SIO_HI_RA_RAM_CMD_BRDCTRL:
2311 		rc = drxj_dap_write_reg16(dev_addr, SIO_HI_RA_RAM_PAR_2__A, cmd->param2, 0);
2312 		if (rc != 0) {
2313 			pr_err("error %d\n", rc);
2314 			goto rw_error;
2315 		}
2316 		rc = drxj_dap_write_reg16(dev_addr, SIO_HI_RA_RAM_PAR_1__A, cmd->param1, 0);
2317 		if (rc != 0) {
2318 			pr_err("error %d\n", rc);
2319 			goto rw_error;
2320 		}
2321 		/* fallthrough */
2322 	case SIO_HI_RA_RAM_CMD_NULL:
2323 		/* No parameters */
2324 		break;
2325 
2326 	default:
2327 		return -EINVAL;
2328 		break;
2329 	}
2330 
2331 	/* Write command */
2332 	rc = drxj_dap_write_reg16(dev_addr, SIO_HI_RA_RAM_CMD__A, cmd->cmd, 0);
2333 	if (rc != 0) {
2334 		pr_err("error %d\n", rc);
2335 		goto rw_error;
2336 	}
2337 
2338 	if ((cmd->cmd) == SIO_HI_RA_RAM_CMD_RESET)
2339 		msleep(1);
2340 
2341 	/* Detect power down to ommit reading result */
2342 	powerdown_cmd = (bool) ((cmd->cmd == SIO_HI_RA_RAM_CMD_CONFIG) &&
2343 				  (((cmd->
2344 				     param5) & SIO_HI_RA_RAM_PAR_5_CFG_SLEEP__M)
2345 				   == SIO_HI_RA_RAM_PAR_5_CFG_SLEEP_ZZZ));
2346 	if (!powerdown_cmd) {
2347 		/* Wait until command rdy */
2348 		do {
2349 			nr_retries++;
2350 			if (nr_retries > DRXJ_MAX_RETRIES) {
2351 				pr_err("timeout\n");
2352 				goto rw_error;
2353 			}
2354 
2355 			rc = drxj_dap_read_reg16(dev_addr, SIO_HI_RA_RAM_CMD__A, &wait_cmd, 0);
2356 			if (rc != 0) {
2357 				pr_err("error %d\n", rc);
2358 				goto rw_error;
2359 			}
2360 		} while (wait_cmd != 0);
2361 
2362 		/* Read result */
2363 		rc = drxj_dap_read_reg16(dev_addr, SIO_HI_RA_RAM_RES__A, result, 0);
2364 		if (rc != 0) {
2365 			pr_err("error %d\n", rc);
2366 			goto rw_error;
2367 		}
2368 
2369 	}
2370 	/* if ( powerdown_cmd == true ) */
2371 	return 0;
2372 rw_error:
2373 	return rc;
2374 }
2375 
2376 /*
2377 * \fn int init_hi( const struct drx_demod_instance *demod )
2378 * \brief Initialise and configurate HI.
2379 * \param demod pointer to demod data.
2380 * \return int Return status.
2381 * \retval 0 Success.
2382 * \retval -EIO Failure.
2383 *
2384 * Needs to know Psys (System Clock period) and Posc (Osc Clock period)
2385 * Need to store configuration in driver because of the way I2C
2386 * bridging is controlled.
2387 *
2388 */
2389 static int init_hi(const struct drx_demod_instance *demod)
2390 {
2391 	struct drxj_data *ext_attr = (struct drxj_data *) (NULL);
2392 	struct drx_common_attr *common_attr = (struct drx_common_attr *) (NULL);
2393 	struct i2c_device_addr *dev_addr = (struct i2c_device_addr *)(NULL);
2394 	int rc;
2395 
2396 	ext_attr = (struct drxj_data *) demod->my_ext_attr;
2397 	common_attr = (struct drx_common_attr *) demod->my_common_attr;
2398 	dev_addr = demod->my_i2c_dev_addr;
2399 
2400 	/* PATCH for bug 5003, HI ucode v3.1.0 */
2401 	rc = drxj_dap_write_reg16(dev_addr, 0x4301D7, 0x801, 0);
2402 	if (rc != 0) {
2403 		pr_err("error %d\n", rc);
2404 		goto rw_error;
2405 	}
2406 
2407 	/* Timing div, 250ns/Psys */
2408 	/* Timing div, = ( delay (nano seconds) * sysclk (kHz) )/ 1000 */
2409 	ext_attr->hi_cfg_timing_div =
2410 	    (u16) ((common_attr->sys_clock_freq / 1000) * HI_I2C_DELAY) / 1000;
2411 	/* Clipping */
2412 	if ((ext_attr->hi_cfg_timing_div) > SIO_HI_RA_RAM_PAR_2_CFG_DIV__M)
2413 		ext_attr->hi_cfg_timing_div = SIO_HI_RA_RAM_PAR_2_CFG_DIV__M;
2414 	/* Bridge delay, uses oscilator clock */
2415 	/* Delay = ( delay (nano seconds) * oscclk (kHz) )/ 1000 */
2416 	/* SDA brdige delay */
2417 	ext_attr->hi_cfg_bridge_delay =
2418 	    (u16) ((common_attr->osc_clock_freq / 1000) * HI_I2C_BRIDGE_DELAY) /
2419 	    1000;
2420 	/* Clipping */
2421 	if ((ext_attr->hi_cfg_bridge_delay) > SIO_HI_RA_RAM_PAR_3_CFG_DBL_SDA__M)
2422 		ext_attr->hi_cfg_bridge_delay = SIO_HI_RA_RAM_PAR_3_CFG_DBL_SDA__M;
2423 	/* SCL bridge delay, same as SDA for now */
2424 	ext_attr->hi_cfg_bridge_delay += ((ext_attr->hi_cfg_bridge_delay) <<
2425 				      SIO_HI_RA_RAM_PAR_3_CFG_DBL_SCL__B);
2426 	/* Wakeup key, setting the read flag (as suggest in the documentation) does
2427 	   not always result into a working solution (barebones worked VI2C failed).
2428 	   Not setting the bit works in all cases . */
2429 	ext_attr->hi_cfg_wake_up_key = DRXJ_WAKE_UP_KEY;
2430 	/* port/bridge/power down ctrl */
2431 	ext_attr->hi_cfg_ctrl = (SIO_HI_RA_RAM_PAR_5_CFG_SLV0_SLAVE);
2432 	/* transit mode time out delay and watch dog divider */
2433 	ext_attr->hi_cfg_transmit = SIO_HI_RA_RAM_PAR_6__PRE;
2434 
2435 	rc = hi_cfg_command(demod);
2436 	if (rc != 0) {
2437 		pr_err("error %d\n", rc);
2438 		goto rw_error;
2439 	}
2440 
2441 	return 0;
2442 
2443 rw_error:
2444 	return rc;
2445 }
2446 
2447 /*============================================================================*/
2448 /*==                   END HOST INTERFACE FUNCTIONS                         ==*/
2449 /*============================================================================*/
2450 
2451 /*============================================================================*/
2452 /*============================================================================*/
2453 /*==                        AUXILIARY FUNCTIONS                             ==*/
2454 /*============================================================================*/
2455 /*============================================================================*/
2456 
2457 /*
2458 * \fn int get_device_capabilities()
2459 * \brief Get and store device capabilities.
2460 * \param demod  Pointer to demodulator instance.
2461 * \return int.
2462 * \return 0    Success
2463 * \retval -EIO Failure
2464 *
2465 * Depending on pulldowns on MDx pins the following internals are set:
2466 *  * common_attr->osc_clock_freq
2467 *  * ext_attr->has_lna
2468 *  * ext_attr->has_ntsc
2469 *  * ext_attr->has_btsc
2470 *  * ext_attr->has_oob
2471 *
2472 */
2473 static int get_device_capabilities(struct drx_demod_instance *demod)
2474 {
2475 	struct drx_common_attr *common_attr = (struct drx_common_attr *) (NULL);
2476 	struct drxj_data *ext_attr = (struct drxj_data *) NULL;
2477 	struct i2c_device_addr *dev_addr = (struct i2c_device_addr *)(NULL);
2478 	u16 sio_pdr_ohw_cfg = 0;
2479 	u32 sio_top_jtagid_lo = 0;
2480 	u16 bid = 0;
2481 	int rc;
2482 
2483 	common_attr = (struct drx_common_attr *) demod->my_common_attr;
2484 	ext_attr = (struct drxj_data *) demod->my_ext_attr;
2485 	dev_addr = demod->my_i2c_dev_addr;
2486 
2487 	rc = drxj_dap_write_reg16(dev_addr, SIO_TOP_COMM_KEY__A, SIO_TOP_COMM_KEY_KEY, 0);
2488 	if (rc != 0) {
2489 		pr_err("error %d\n", rc);
2490 		goto rw_error;
2491 	}
2492 	rc = drxj_dap_read_reg16(dev_addr, SIO_PDR_OHW_CFG__A, &sio_pdr_ohw_cfg, 0);
2493 	if (rc != 0) {
2494 		pr_err("error %d\n", rc);
2495 		goto rw_error;
2496 	}
2497 	rc = drxj_dap_write_reg16(dev_addr, SIO_TOP_COMM_KEY__A, SIO_TOP_COMM_KEY__PRE, 0);
2498 	if (rc != 0) {
2499 		pr_err("error %d\n", rc);
2500 		goto rw_error;
2501 	}
2502 
2503 	switch ((sio_pdr_ohw_cfg & SIO_PDR_OHW_CFG_FREF_SEL__M)) {
2504 	case 0:
2505 		/* ignore (bypass ?) */
2506 		break;
2507 	case 1:
2508 		/* 27 MHz */
2509 		common_attr->osc_clock_freq = 27000;
2510 		break;
2511 	case 2:
2512 		/* 20.25 MHz */
2513 		common_attr->osc_clock_freq = 20250;
2514 		break;
2515 	case 3:
2516 		/* 4 MHz */
2517 		common_attr->osc_clock_freq = 4000;
2518 		break;
2519 	default:
2520 		return -EIO;
2521 	}
2522 
2523 	/*
2524 	   Determine device capabilities
2525 	   Based on pinning v47
2526 	 */
2527 	rc = drxdap_fasi_read_reg32(dev_addr, SIO_TOP_JTAGID_LO__A, &sio_top_jtagid_lo, 0);
2528 	if (rc != 0) {
2529 		pr_err("error %d\n", rc);
2530 		goto rw_error;
2531 	}
2532 	ext_attr->mfx = (u8) ((sio_top_jtagid_lo >> 29) & 0xF);
2533 
2534 	switch ((sio_top_jtagid_lo >> 12) & 0xFF) {
2535 	case 0x31:
2536 		rc = drxj_dap_write_reg16(dev_addr, SIO_TOP_COMM_KEY__A, SIO_TOP_COMM_KEY_KEY, 0);
2537 		if (rc != 0) {
2538 			pr_err("error %d\n", rc);
2539 			goto rw_error;
2540 		}
2541 		rc = drxj_dap_read_reg16(dev_addr, SIO_PDR_UIO_IN_HI__A, &bid, 0);
2542 		if (rc != 0) {
2543 			pr_err("error %d\n", rc);
2544 			goto rw_error;
2545 		}
2546 		bid = (bid >> 10) & 0xf;
2547 		rc = drxj_dap_write_reg16(dev_addr, SIO_TOP_COMM_KEY__A, SIO_TOP_COMM_KEY__PRE, 0);
2548 		if (rc != 0) {
2549 			pr_err("error %d\n", rc);
2550 			goto rw_error;
2551 		}
2552 
2553 		ext_attr->has_lna = true;
2554 		ext_attr->has_ntsc = false;
2555 		ext_attr->has_btsc = false;
2556 		ext_attr->has_oob = false;
2557 		ext_attr->has_smatx = true;
2558 		ext_attr->has_smarx = false;
2559 		ext_attr->has_gpio = false;
2560 		ext_attr->has_irqn = false;
2561 		break;
2562 	case 0x33:
2563 		ext_attr->has_lna = false;
2564 		ext_attr->has_ntsc = false;
2565 		ext_attr->has_btsc = false;
2566 		ext_attr->has_oob = false;
2567 		ext_attr->has_smatx = true;
2568 		ext_attr->has_smarx = false;
2569 		ext_attr->has_gpio = false;
2570 		ext_attr->has_irqn = false;
2571 		break;
2572 	case 0x45:
2573 		ext_attr->has_lna = true;
2574 		ext_attr->has_ntsc = true;
2575 		ext_attr->has_btsc = false;
2576 		ext_attr->has_oob = false;
2577 		ext_attr->has_smatx = true;
2578 		ext_attr->has_smarx = true;
2579 		ext_attr->has_gpio = true;
2580 		ext_attr->has_irqn = false;
2581 		break;
2582 	case 0x46:
2583 		ext_attr->has_lna = false;
2584 		ext_attr->has_ntsc = true;
2585 		ext_attr->has_btsc = false;
2586 		ext_attr->has_oob = false;
2587 		ext_attr->has_smatx = true;
2588 		ext_attr->has_smarx = true;
2589 		ext_attr->has_gpio = true;
2590 		ext_attr->has_irqn = false;
2591 		break;
2592 	case 0x41:
2593 		ext_attr->has_lna = true;
2594 		ext_attr->has_ntsc = true;
2595 		ext_attr->has_btsc = true;
2596 		ext_attr->has_oob = false;
2597 		ext_attr->has_smatx = true;
2598 		ext_attr->has_smarx = true;
2599 		ext_attr->has_gpio = true;
2600 		ext_attr->has_irqn = false;
2601 		break;
2602 	case 0x43:
2603 		ext_attr->has_lna = false;
2604 		ext_attr->has_ntsc = true;
2605 		ext_attr->has_btsc = true;
2606 		ext_attr->has_oob = false;
2607 		ext_attr->has_smatx = true;
2608 		ext_attr->has_smarx = true;
2609 		ext_attr->has_gpio = true;
2610 		ext_attr->has_irqn = false;
2611 		break;
2612 	case 0x32:
2613 		ext_attr->has_lna = true;
2614 		ext_attr->has_ntsc = false;
2615 		ext_attr->has_btsc = false;
2616 		ext_attr->has_oob = true;
2617 		ext_attr->has_smatx = true;
2618 		ext_attr->has_smarx = true;
2619 		ext_attr->has_gpio = true;
2620 		ext_attr->has_irqn = true;
2621 		break;
2622 	case 0x34:
2623 		ext_attr->has_lna = false;
2624 		ext_attr->has_ntsc = true;
2625 		ext_attr->has_btsc = true;
2626 		ext_attr->has_oob = true;
2627 		ext_attr->has_smatx = true;
2628 		ext_attr->has_smarx = true;
2629 		ext_attr->has_gpio = true;
2630 		ext_attr->has_irqn = true;
2631 		break;
2632 	case 0x42:
2633 		ext_attr->has_lna = true;
2634 		ext_attr->has_ntsc = true;
2635 		ext_attr->has_btsc = true;
2636 		ext_attr->has_oob = true;
2637 		ext_attr->has_smatx = true;
2638 		ext_attr->has_smarx = true;
2639 		ext_attr->has_gpio = true;
2640 		ext_attr->has_irqn = true;
2641 		break;
2642 	case 0x44:
2643 		ext_attr->has_lna = false;
2644 		ext_attr->has_ntsc = true;
2645 		ext_attr->has_btsc = true;
2646 		ext_attr->has_oob = true;
2647 		ext_attr->has_smatx = true;
2648 		ext_attr->has_smarx = true;
2649 		ext_attr->has_gpio = true;
2650 		ext_attr->has_irqn = true;
2651 		break;
2652 	default:
2653 		/* Unknown device variant */
2654 		return -EIO;
2655 		break;
2656 	}
2657 
2658 	return 0;
2659 rw_error:
2660 	return rc;
2661 }
2662 
2663 /*
2664 * \fn int power_up_device()
2665 * \brief Power up device.
2666 * \param demod  Pointer to demodulator instance.
2667 * \return int.
2668 * \return 0    Success
2669 * \retval -EIO Failure, I2C or max retries reached
2670 *
2671 */
2672 
2673 #ifndef DRXJ_MAX_RETRIES_POWERUP
2674 #define DRXJ_MAX_RETRIES_POWERUP 10
2675 #endif
2676 
2677 static int power_up_device(struct drx_demod_instance *demod)
2678 {
2679 	struct i2c_device_addr *dev_addr = (struct i2c_device_addr *)(NULL);
2680 	u8 data = 0;
2681 	u16 retry_count = 0;
2682 	struct i2c_device_addr wake_up_addr;
2683 
2684 	dev_addr = demod->my_i2c_dev_addr;
2685 	wake_up_addr.i2c_addr = DRXJ_WAKE_UP_KEY;
2686 	wake_up_addr.i2c_dev_id = dev_addr->i2c_dev_id;
2687 	wake_up_addr.user_data = dev_addr->user_data;
2688 	/*
2689 	 * I2C access may fail in this case: no ack
2690 	 * dummy write must be used to wake uop device, dummy read must be used to
2691 	 * reset HI state machine (avoiding actual writes)
2692 	 */
2693 	do {
2694 		data = 0;
2695 		drxbsp_i2c_write_read(&wake_up_addr, 1, &data,
2696 				      (struct i2c_device_addr *)(NULL), 0,
2697 				     (u8 *)(NULL));
2698 		msleep(10);
2699 		retry_count++;
2700 	} while ((drxbsp_i2c_write_read
2701 		  ((struct i2c_device_addr *) (NULL), 0, (u8 *)(NULL), dev_addr, 1,
2702 		   &data)
2703 		  != 0) && (retry_count < DRXJ_MAX_RETRIES_POWERUP));
2704 
2705 	/* Need some recovery time .... */
2706 	msleep(10);
2707 
2708 	if (retry_count == DRXJ_MAX_RETRIES_POWERUP)
2709 		return -EIO;
2710 
2711 	return 0;
2712 }
2713 
2714 /*----------------------------------------------------------------------------*/
2715 /* MPEG Output Configuration Functions - begin                                */
2716 /*----------------------------------------------------------------------------*/
2717 /*
2718 * \fn int ctrl_set_cfg_mpeg_output()
2719 * \brief Set MPEG output configuration of the device.
2720 * \param devmod  Pointer to demodulator instance.
2721 * \param cfg_data Pointer to mpeg output configuaration.
2722 * \return int.
2723 *
2724 *  Configure MPEG output parameters.
2725 *
2726 */
2727 static int
2728 ctrl_set_cfg_mpeg_output(struct drx_demod_instance *demod, struct drx_cfg_mpeg_output *cfg_data)
2729 {
2730 	struct i2c_device_addr *dev_addr = (struct i2c_device_addr *)(NULL);
2731 	struct drxj_data *ext_attr = (struct drxj_data *) (NULL);
2732 	struct drx_common_attr *common_attr = (struct drx_common_attr *) (NULL);
2733 	int rc;
2734 	u16 fec_oc_reg_mode = 0;
2735 	u16 fec_oc_reg_ipr_mode = 0;
2736 	u16 fec_oc_reg_ipr_invert = 0;
2737 	u32 max_bit_rate = 0;
2738 	u32 rcn_rate = 0;
2739 	u32 nr_bits = 0;
2740 	u16 sio_pdr_md_cfg = 0;
2741 	/* data mask for the output data byte */
2742 	u16 invert_data_mask =
2743 	    FEC_OC_IPR_INVERT_MD7__M | FEC_OC_IPR_INVERT_MD6__M |
2744 	    FEC_OC_IPR_INVERT_MD5__M | FEC_OC_IPR_INVERT_MD4__M |
2745 	    FEC_OC_IPR_INVERT_MD3__M | FEC_OC_IPR_INVERT_MD2__M |
2746 	    FEC_OC_IPR_INVERT_MD1__M | FEC_OC_IPR_INVERT_MD0__M;
2747 
2748 	/* check arguments */
2749 	if ((demod == NULL) || (cfg_data == NULL))
2750 		return -EINVAL;
2751 
2752 	dev_addr = demod->my_i2c_dev_addr;
2753 	ext_attr = (struct drxj_data *) demod->my_ext_attr;
2754 	common_attr = (struct drx_common_attr *) demod->my_common_attr;
2755 
2756 	if (cfg_data->enable_mpeg_output == true) {
2757 		/* quick and dirty patch to set MPEG incase current std is not
2758 		   producing MPEG */
2759 		switch (ext_attr->standard) {
2760 		case DRX_STANDARD_8VSB:
2761 		case DRX_STANDARD_ITU_A:
2762 		case DRX_STANDARD_ITU_B:
2763 		case DRX_STANDARD_ITU_C:
2764 			break;
2765 		default:
2766 			return 0;
2767 		}
2768 
2769 		rc = drxj_dap_write_reg16(dev_addr, FEC_OC_OCR_INVERT__A, 0, 0);
2770 		if (rc != 0) {
2771 			pr_err("error %d\n", rc);
2772 			goto rw_error;
2773 		}
2774 		switch (ext_attr->standard) {
2775 		case DRX_STANDARD_8VSB:
2776 			rc = drxj_dap_write_reg16(dev_addr, FEC_OC_FCT_USAGE__A, 7, 0);
2777 			if (rc != 0) {
2778 				pr_err("error %d\n", rc);
2779 				goto rw_error;
2780 			}	/* 2048 bytes fifo ram */
2781 			rc = drxj_dap_write_reg16(dev_addr, FEC_OC_TMD_CTL_UPD_RATE__A, 10, 0);
2782 			if (rc != 0) {
2783 				pr_err("error %d\n", rc);
2784 				goto rw_error;
2785 			}
2786 			rc = drxj_dap_write_reg16(dev_addr, FEC_OC_TMD_INT_UPD_RATE__A, 10, 0);
2787 			if (rc != 0) {
2788 				pr_err("error %d\n", rc);
2789 				goto rw_error;
2790 			}
2791 			rc = drxj_dap_write_reg16(dev_addr, FEC_OC_AVR_PARM_A__A, 5, 0);
2792 			if (rc != 0) {
2793 				pr_err("error %d\n", rc);
2794 				goto rw_error;
2795 			}
2796 			rc = drxj_dap_write_reg16(dev_addr, FEC_OC_AVR_PARM_B__A, 7, 0);
2797 			if (rc != 0) {
2798 				pr_err("error %d\n", rc);
2799 				goto rw_error;
2800 			}
2801 			rc = drxj_dap_write_reg16(dev_addr, FEC_OC_RCN_GAIN__A, 10, 0);
2802 			if (rc != 0) {
2803 				pr_err("error %d\n", rc);
2804 				goto rw_error;
2805 			}
2806 			/* Low Water Mark for synchronization  */
2807 			rc = drxj_dap_write_reg16(dev_addr, FEC_OC_SNC_LWM__A, 3, 0);
2808 			if (rc != 0) {
2809 				pr_err("error %d\n", rc);
2810 				goto rw_error;
2811 			}
2812 			/* High Water Mark for synchronization */
2813 			rc = drxj_dap_write_reg16(dev_addr, FEC_OC_SNC_HWM__A, 5, 0);
2814 			if (rc != 0) {
2815 				pr_err("error %d\n", rc);
2816 				goto rw_error;
2817 			}
2818 			break;
2819 		case DRX_STANDARD_ITU_A:
2820 		case DRX_STANDARD_ITU_C:
2821 			switch (ext_attr->constellation) {
2822 			case DRX_CONSTELLATION_QAM256:
2823 				nr_bits = 8;
2824 				break;
2825 			case DRX_CONSTELLATION_QAM128:
2826 				nr_bits = 7;
2827 				break;
2828 			case DRX_CONSTELLATION_QAM64:
2829 				nr_bits = 6;
2830 				break;
2831 			case DRX_CONSTELLATION_QAM32:
2832 				nr_bits = 5;
2833 				break;
2834 			case DRX_CONSTELLATION_QAM16:
2835 				nr_bits = 4;
2836 				break;
2837 			default:
2838 				return -EIO;
2839 			}	/* ext_attr->constellation */
2840 			/* max_bit_rate = symbol_rate * nr_bits * coef */
2841 			/* coef = 188/204                          */
2842 			max_bit_rate =
2843 			    (ext_attr->curr_symbol_rate / 8) * nr_bits * 188;
2844 			/* pass through as b/c Annex A/c need following settings */
2845 			/* fall-through */
2846 		case DRX_STANDARD_ITU_B:
2847 			rc = drxj_dap_write_reg16(dev_addr, FEC_OC_FCT_USAGE__A, FEC_OC_FCT_USAGE__PRE, 0);
2848 			if (rc != 0) {
2849 				pr_err("error %d\n", rc);
2850 				goto rw_error;
2851 			}
2852 			rc = drxj_dap_write_reg16(dev_addr, FEC_OC_TMD_CTL_UPD_RATE__A, FEC_OC_TMD_CTL_UPD_RATE__PRE, 0);
2853 			if (rc != 0) {
2854 				pr_err("error %d\n", rc);
2855 				goto rw_error;
2856 			}
2857 			rc = drxj_dap_write_reg16(dev_addr, FEC_OC_TMD_INT_UPD_RATE__A, 5, 0);
2858 			if (rc != 0) {
2859 				pr_err("error %d\n", rc);
2860 				goto rw_error;
2861 			}
2862 			rc = drxj_dap_write_reg16(dev_addr, FEC_OC_AVR_PARM_A__A, FEC_OC_AVR_PARM_A__PRE, 0);
2863 			if (rc != 0) {
2864 				pr_err("error %d\n", rc);
2865 				goto rw_error;
2866 			}
2867 			rc = drxj_dap_write_reg16(dev_addr, FEC_OC_AVR_PARM_B__A, FEC_OC_AVR_PARM_B__PRE, 0);
2868 			if (rc != 0) {
2869 				pr_err("error %d\n", rc);
2870 				goto rw_error;
2871 			}
2872 			if (cfg_data->static_clk == true) {
2873 				rc = drxj_dap_write_reg16(dev_addr, FEC_OC_RCN_GAIN__A, 0xD, 0);
2874 				if (rc != 0) {
2875 					pr_err("error %d\n", rc);
2876 					goto rw_error;
2877 				}
2878 			} else {
2879 				rc = drxj_dap_write_reg16(dev_addr, FEC_OC_RCN_GAIN__A, FEC_OC_RCN_GAIN__PRE, 0);
2880 				if (rc != 0) {
2881 					pr_err("error %d\n", rc);
2882 					goto rw_error;
2883 				}
2884 			}
2885 			rc = drxj_dap_write_reg16(dev_addr, FEC_OC_SNC_LWM__A, 2, 0);
2886 			if (rc != 0) {
2887 				pr_err("error %d\n", rc);
2888 				goto rw_error;
2889 			}
2890 			rc = drxj_dap_write_reg16(dev_addr, FEC_OC_SNC_HWM__A, 12, 0);
2891 			if (rc != 0) {
2892 				pr_err("error %d\n", rc);
2893 				goto rw_error;
2894 			}
2895 			break;
2896 		default:
2897 			break;
2898 		}		/* swtich (standard) */
2899 
2900 		/* Check insertion of the Reed-Solomon parity bytes */
2901 		rc = drxj_dap_read_reg16(dev_addr, FEC_OC_MODE__A, &fec_oc_reg_mode, 0);
2902 		if (rc != 0) {
2903 			pr_err("error %d\n", rc);
2904 			goto rw_error;
2905 		}
2906 		rc = drxj_dap_read_reg16(dev_addr, FEC_OC_IPR_MODE__A, &fec_oc_reg_ipr_mode, 0);
2907 		if (rc != 0) {
2908 			pr_err("error %d\n", rc);
2909 			goto rw_error;
2910 		}
2911 		if (cfg_data->insert_rs_byte == true) {
2912 			/* enable parity symbol forward */
2913 			fec_oc_reg_mode |= FEC_OC_MODE_PARITY__M;
2914 			/* MVAL disable during parity bytes */
2915 			fec_oc_reg_ipr_mode |= FEC_OC_IPR_MODE_MVAL_DIS_PAR__M;
2916 			switch (ext_attr->standard) {
2917 			case DRX_STANDARD_8VSB:
2918 				rcn_rate = 0x004854D3;
2919 				break;
2920 			case DRX_STANDARD_ITU_B:
2921 				fec_oc_reg_mode |= FEC_OC_MODE_TRANSPARENT__M;
2922 				switch (ext_attr->constellation) {
2923 				case DRX_CONSTELLATION_QAM256:
2924 					rcn_rate = 0x008945E7;
2925 					break;
2926 				case DRX_CONSTELLATION_QAM64:
2927 					rcn_rate = 0x005F64D4;
2928 					break;
2929 				default:
2930 					return -EIO;
2931 				}
2932 				break;
2933 			case DRX_STANDARD_ITU_A:
2934 			case DRX_STANDARD_ITU_C:
2935 				/* insert_rs_byte = true -> coef = 188/188 -> 1, RS bits are in MPEG output */
2936 				rcn_rate =
2937 				    (frac28
2938 				     (max_bit_rate,
2939 				      (u32) (common_attr->sys_clock_freq / 8))) /
2940 				    188;
2941 				break;
2942 			default:
2943 				return -EIO;
2944 			}	/* ext_attr->standard */
2945 		} else {	/* insert_rs_byte == false */
2946 
2947 			/* disable parity symbol forward */
2948 			fec_oc_reg_mode &= (~FEC_OC_MODE_PARITY__M);
2949 			/* MVAL enable during parity bytes */
2950 			fec_oc_reg_ipr_mode &= (~FEC_OC_IPR_MODE_MVAL_DIS_PAR__M);
2951 			switch (ext_attr->standard) {
2952 			case DRX_STANDARD_8VSB:
2953 				rcn_rate = 0x0041605C;
2954 				break;
2955 			case DRX_STANDARD_ITU_B:
2956 				fec_oc_reg_mode &= (~FEC_OC_MODE_TRANSPARENT__M);
2957 				switch (ext_attr->constellation) {
2958 				case DRX_CONSTELLATION_QAM256:
2959 					rcn_rate = 0x0082D6A0;
2960 					break;
2961 				case DRX_CONSTELLATION_QAM64:
2962 					rcn_rate = 0x005AEC1A;
2963 					break;
2964 				default:
2965 					return -EIO;
2966 				}
2967 				break;
2968 			case DRX_STANDARD_ITU_A:
2969 			case DRX_STANDARD_ITU_C:
2970 				/* insert_rs_byte = false -> coef = 188/204, RS bits not in MPEG output */
2971 				rcn_rate =
2972 				    (frac28
2973 				     (max_bit_rate,
2974 				      (u32) (common_attr->sys_clock_freq / 8))) /
2975 				    204;
2976 				break;
2977 			default:
2978 				return -EIO;
2979 			}	/* ext_attr->standard */
2980 		}
2981 
2982 		if (cfg_data->enable_parallel == true) {	/* MPEG data output is parallel -> clear ipr_mode[0] */
2983 			fec_oc_reg_ipr_mode &= (~(FEC_OC_IPR_MODE_SERIAL__M));
2984 		} else {	/* MPEG data output is serial -> set ipr_mode[0] */
2985 			fec_oc_reg_ipr_mode |= FEC_OC_IPR_MODE_SERIAL__M;
2986 		}
2987 
2988 		/* Control slective inversion of output bits */
2989 		if (cfg_data->invert_data == true)
2990 			fec_oc_reg_ipr_invert |= invert_data_mask;
2991 		else
2992 			fec_oc_reg_ipr_invert &= (~(invert_data_mask));
2993 
2994 		if (cfg_data->invert_err == true)
2995 			fec_oc_reg_ipr_invert |= FEC_OC_IPR_INVERT_MERR__M;
2996 		else
2997 			fec_oc_reg_ipr_invert &= (~(FEC_OC_IPR_INVERT_MERR__M));
2998 
2999 		if (cfg_data->invert_str == true)
3000 			fec_oc_reg_ipr_invert |= FEC_OC_IPR_INVERT_MSTRT__M;
3001 		else
3002 			fec_oc_reg_ipr_invert &= (~(FEC_OC_IPR_INVERT_MSTRT__M));
3003 
3004 		if (cfg_data->invert_val == true)
3005 			fec_oc_reg_ipr_invert |= FEC_OC_IPR_INVERT_MVAL__M;
3006 		else
3007 			fec_oc_reg_ipr_invert &= (~(FEC_OC_IPR_INVERT_MVAL__M));
3008 
3009 		if (cfg_data->invert_clk == true)
3010 			fec_oc_reg_ipr_invert |= FEC_OC_IPR_INVERT_MCLK__M;
3011 		else
3012 			fec_oc_reg_ipr_invert &= (~(FEC_OC_IPR_INVERT_MCLK__M));
3013 
3014 
3015 		if (cfg_data->static_clk == true) {	/* Static mode */
3016 			u32 dto_rate = 0;
3017 			u32 bit_rate = 0;
3018 			u16 fec_oc_dto_burst_len = 0;
3019 			u16 fec_oc_dto_period = 0;
3020 
3021 			fec_oc_dto_burst_len = FEC_OC_DTO_BURST_LEN__PRE;
3022 
3023 			switch (ext_attr->standard) {
3024 			case DRX_STANDARD_8VSB:
3025 				fec_oc_dto_period = 4;
3026 				if (cfg_data->insert_rs_byte == true)
3027 					fec_oc_dto_burst_len = 208;
3028 				break;
3029 			case DRX_STANDARD_ITU_A:
3030 				{
3031 					u32 symbol_rate_th = 6400000;
3032 					if (cfg_data->insert_rs_byte == true) {
3033 						fec_oc_dto_burst_len = 204;
3034 						symbol_rate_th = 5900000;
3035 					}
3036 					if (ext_attr->curr_symbol_rate >=
3037 					    symbol_rate_th) {
3038 						fec_oc_dto_period = 0;
3039 					} else {
3040 						fec_oc_dto_period = 1;
3041 					}
3042 				}
3043 				break;
3044 			case DRX_STANDARD_ITU_B:
3045 				fec_oc_dto_period = 1;
3046 				if (cfg_data->insert_rs_byte == true)
3047 					fec_oc_dto_burst_len = 128;
3048 				break;
3049 			case DRX_STANDARD_ITU_C:
3050 				fec_oc_dto_period = 1;
3051 				if (cfg_data->insert_rs_byte == true)
3052 					fec_oc_dto_burst_len = 204;
3053 				break;
3054 			default:
3055 				return -EIO;
3056 			}
3057 			bit_rate =
3058 			    common_attr->sys_clock_freq * 1000 / (fec_oc_dto_period +
3059 							       2);
3060 			dto_rate =
3061 			    frac28(bit_rate, common_attr->sys_clock_freq * 1000);
3062 			dto_rate >>= 3;
3063 			rc = drxj_dap_write_reg16(dev_addr, FEC_OC_DTO_RATE_HI__A, (u16)((dto_rate >> 16) & FEC_OC_DTO_RATE_HI__M), 0);
3064 			if (rc != 0) {
3065 				pr_err("error %d\n", rc);
3066 				goto rw_error;
3067 			}
3068 			rc = drxj_dap_write_reg16(dev_addr, FEC_OC_DTO_RATE_LO__A, (u16)(dto_rate & FEC_OC_DTO_RATE_LO_RATE_LO__M), 0);
3069 			if (rc != 0) {
3070 				pr_err("error %d\n", rc);
3071 				goto rw_error;
3072 			}
3073 			rc = drxj_dap_write_reg16(dev_addr, FEC_OC_DTO_MODE__A, FEC_OC_DTO_MODE_DYNAMIC__M | FEC_OC_DTO_MODE_OFFSET_ENABLE__M, 0);
3074 			if (rc != 0) {
3075 				pr_err("error %d\n", rc);
3076 				goto rw_error;
3077 			}
3078 			rc = drxj_dap_write_reg16(dev_addr, FEC_OC_FCT_MODE__A, FEC_OC_FCT_MODE_RAT_ENA__M | FEC_OC_FCT_MODE_VIRT_ENA__M, 0);
3079 			if (rc != 0) {
3080 				pr_err("error %d\n", rc);
3081 				goto rw_error;
3082 			}
3083 			rc = drxj_dap_write_reg16(dev_addr, FEC_OC_DTO_BURST_LEN__A, fec_oc_dto_burst_len, 0);
3084 			if (rc != 0) {
3085 				pr_err("error %d\n", rc);
3086 				goto rw_error;
3087 			}
3088 			if (ext_attr->mpeg_output_clock_rate != DRXJ_MPEGOUTPUT_CLOCK_RATE_AUTO)
3089 				fec_oc_dto_period = ext_attr->mpeg_output_clock_rate - 1;
3090 			rc = drxj_dap_write_reg16(dev_addr, FEC_OC_DTO_PERIOD__A, fec_oc_dto_period, 0);
3091 			if (rc != 0) {
3092 				pr_err("error %d\n", rc);
3093 				goto rw_error;
3094 			}
3095 		} else {	/* Dynamic mode */
3096 
3097 			rc = drxj_dap_write_reg16(dev_addr, FEC_OC_DTO_MODE__A, FEC_OC_DTO_MODE_DYNAMIC__M, 0);
3098 			if (rc != 0) {
3099 				pr_err("error %d\n", rc);
3100 				goto rw_error;
3101 			}
3102 			rc = drxj_dap_write_reg16(dev_addr, FEC_OC_FCT_MODE__A, 0, 0);
3103 			if (rc != 0) {
3104 				pr_err("error %d\n", rc);
3105 				goto rw_error;
3106 			}
3107 		}
3108 
3109 		rc = drxdap_fasi_write_reg32(dev_addr, FEC_OC_RCN_CTL_RATE_LO__A, rcn_rate, 0);
3110 		if (rc != 0) {
3111 			pr_err("error %d\n", rc);
3112 			goto rw_error;
3113 		}
3114 
3115 		/* Write appropriate registers with requested configuration */
3116 		rc = drxj_dap_write_reg16(dev_addr, FEC_OC_MODE__A, fec_oc_reg_mode, 0);
3117 		if (rc != 0) {
3118 			pr_err("error %d\n", rc);
3119 			goto rw_error;
3120 		}
3121 		rc = drxj_dap_write_reg16(dev_addr, FEC_OC_IPR_MODE__A, fec_oc_reg_ipr_mode, 0);
3122 		if (rc != 0) {
3123 			pr_err("error %d\n", rc);
3124 			goto rw_error;
3125 		}
3126 		rc = drxj_dap_write_reg16(dev_addr, FEC_OC_IPR_INVERT__A, fec_oc_reg_ipr_invert, 0);
3127 		if (rc != 0) {
3128 			pr_err("error %d\n", rc);
3129 			goto rw_error;
3130 		}
3131 
3132 		/* enabling for both parallel and serial now */
3133 		/*  Write magic word to enable pdr reg write */
3134 		rc = drxj_dap_write_reg16(dev_addr, SIO_TOP_COMM_KEY__A, 0xFABA, 0);
3135 		if (rc != 0) {
3136 			pr_err("error %d\n", rc);
3137 			goto rw_error;
3138 		}
3139 		/*  Set MPEG TS pads to outputmode */
3140 		rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MSTRT_CFG__A, 0x0013, 0);
3141 		if (rc != 0) {
3142 			pr_err("error %d\n", rc);
3143 			goto rw_error;
3144 		}
3145 		rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MERR_CFG__A, 0x0013, 0);
3146 		if (rc != 0) {
3147 			pr_err("error %d\n", rc);
3148 			goto rw_error;
3149 		}
3150 		rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MCLK_CFG__A, MPEG_OUTPUT_CLK_DRIVE_STRENGTH << SIO_PDR_MCLK_CFG_DRIVE__B | 0x03 << SIO_PDR_MCLK_CFG_MODE__B, 0);
3151 		if (rc != 0) {
3152 			pr_err("error %d\n", rc);
3153 			goto rw_error;
3154 		}
3155 		rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MVAL_CFG__A, 0x0013, 0);
3156 		if (rc != 0) {
3157 			pr_err("error %d\n", rc);
3158 			goto rw_error;
3159 		}
3160 		sio_pdr_md_cfg =
3161 		    MPEG_SERIAL_OUTPUT_PIN_DRIVE_STRENGTH <<
3162 		    SIO_PDR_MD0_CFG_DRIVE__B | 0x03 << SIO_PDR_MD0_CFG_MODE__B;
3163 		rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MD0_CFG__A, sio_pdr_md_cfg, 0);
3164 		if (rc != 0) {
3165 			pr_err("error %d\n", rc);
3166 			goto rw_error;
3167 		}
3168 		if (cfg_data->enable_parallel == true) {	/* MPEG data output is parallel -> set MD1 to MD7 to output mode */
3169 			sio_pdr_md_cfg =
3170 			    MPEG_PARALLEL_OUTPUT_PIN_DRIVE_STRENGTH <<
3171 			    SIO_PDR_MD0_CFG_DRIVE__B | 0x03 <<
3172 			    SIO_PDR_MD0_CFG_MODE__B;
3173 			rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MD0_CFG__A, sio_pdr_md_cfg, 0);
3174 			if (rc != 0) {
3175 				pr_err("error %d\n", rc);
3176 				goto rw_error;
3177 			}
3178 			rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MD1_CFG__A, sio_pdr_md_cfg, 0);
3179 			if (rc != 0) {
3180 				pr_err("error %d\n", rc);
3181 				goto rw_error;
3182 			}
3183 			rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MD2_CFG__A, sio_pdr_md_cfg, 0);
3184 			if (rc != 0) {
3185 				pr_err("error %d\n", rc);
3186 				goto rw_error;
3187 			}
3188 			rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MD3_CFG__A, sio_pdr_md_cfg, 0);
3189 			if (rc != 0) {
3190 				pr_err("error %d\n", rc);
3191 				goto rw_error;
3192 			}
3193 			rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MD4_CFG__A, sio_pdr_md_cfg, 0);
3194 			if (rc != 0) {
3195 				pr_err("error %d\n", rc);
3196 				goto rw_error;
3197 			}
3198 			rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MD5_CFG__A, sio_pdr_md_cfg, 0);
3199 			if (rc != 0) {
3200 				pr_err("error %d\n", rc);
3201 				goto rw_error;
3202 			}
3203 			rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MD6_CFG__A, sio_pdr_md_cfg, 0);
3204 			if (rc != 0) {
3205 				pr_err("error %d\n", rc);
3206 				goto rw_error;
3207 			}
3208 			rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MD7_CFG__A, sio_pdr_md_cfg, 0);
3209 			if (rc != 0) {
3210 				pr_err("error %d\n", rc);
3211 				goto rw_error;
3212 			}
3213 		} else {	/* MPEG data output is serial -> set MD1 to MD7 to tri-state */
3214 			rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MD1_CFG__A, 0x0000, 0);
3215 			if (rc != 0) {
3216 				pr_err("error %d\n", rc);
3217 				goto rw_error;
3218 			}
3219 			rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MD2_CFG__A, 0x0000, 0);
3220 			if (rc != 0) {
3221 				pr_err("error %d\n", rc);
3222 				goto rw_error;
3223 			}
3224 			rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MD3_CFG__A, 0x0000, 0);
3225 			if (rc != 0) {
3226 				pr_err("error %d\n", rc);
3227 				goto rw_error;
3228 			}
3229 			rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MD4_CFG__A, 0x0000, 0);
3230 			if (rc != 0) {
3231 				pr_err("error %d\n", rc);
3232 				goto rw_error;
3233 			}
3234 			rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MD5_CFG__A, 0x0000, 0);
3235 			if (rc != 0) {
3236 				pr_err("error %d\n", rc);
3237 				goto rw_error;
3238 			}
3239 			rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MD6_CFG__A, 0x0000, 0);
3240 			if (rc != 0) {
3241 				pr_err("error %d\n", rc);
3242 				goto rw_error;
3243 			}
3244 			rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MD7_CFG__A, 0x0000, 0);
3245 			if (rc != 0) {
3246 				pr_err("error %d\n", rc);
3247 				goto rw_error;
3248 			}
3249 		}
3250 		/*  Enable Monitor Bus output over MPEG pads and ctl input */
3251 		rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MON_CFG__A, 0x0000, 0);
3252 		if (rc != 0) {
3253 			pr_err("error %d\n", rc);
3254 			goto rw_error;
3255 		}
3256 		/*  Write nomagic word to enable pdr reg write */
3257 		rc = drxj_dap_write_reg16(dev_addr, SIO_TOP_COMM_KEY__A, 0x0000, 0);
3258 		if (rc != 0) {
3259 			pr_err("error %d\n", rc);
3260 			goto rw_error;
3261 		}
3262 	} else {
3263 		/*  Write magic word to enable pdr reg write */
3264 		rc = drxj_dap_write_reg16(dev_addr, SIO_TOP_COMM_KEY__A, 0xFABA, 0);
3265 		if (rc != 0) {
3266 			pr_err("error %d\n", rc);
3267 			goto rw_error;
3268 		}
3269 		/*  Set MPEG TS pads to inputmode */
3270 		rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MSTRT_CFG__A, 0x0000, 0);
3271 		if (rc != 0) {
3272 			pr_err("error %d\n", rc);
3273 			goto rw_error;
3274 		}
3275 		rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MERR_CFG__A, 0x0000, 0);
3276 		if (rc != 0) {
3277 			pr_err("error %d\n", rc);
3278 			goto rw_error;
3279 		}
3280 		rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MCLK_CFG__A, 0x0000, 0);
3281 		if (rc != 0) {
3282 			pr_err("error %d\n", rc);
3283 			goto rw_error;
3284 		}
3285 		rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MVAL_CFG__A, 0x0000, 0);
3286 		if (rc != 0) {
3287 			pr_err("error %d\n", rc);
3288 			goto rw_error;
3289 		}
3290 		rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MD0_CFG__A, 0x0000, 0);
3291 		if (rc != 0) {
3292 			pr_err("error %d\n", rc);
3293 			goto rw_error;
3294 		}
3295 		rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MD1_CFG__A, 0x0000, 0);
3296 		if (rc != 0) {
3297 			pr_err("error %d\n", rc);
3298 			goto rw_error;
3299 		}
3300 		rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MD2_CFG__A, 0x0000, 0);
3301 		if (rc != 0) {
3302 			pr_err("error %d\n", rc);
3303 			goto rw_error;
3304 		}
3305 		rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MD3_CFG__A, 0x0000, 0);
3306 		if (rc != 0) {
3307 			pr_err("error %d\n", rc);
3308 			goto rw_error;
3309 		}
3310 		rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MD4_CFG__A, 0x0000, 0);
3311 		if (rc != 0) {
3312 			pr_err("error %d\n", rc);
3313 			goto rw_error;
3314 		}
3315 		rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MD5_CFG__A, 0x0000, 0);
3316 		if (rc != 0) {
3317 			pr_err("error %d\n", rc);
3318 			goto rw_error;
3319 		}
3320 		rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MD6_CFG__A, 0x0000, 0);
3321 		if (rc != 0) {
3322 			pr_err("error %d\n", rc);
3323 			goto rw_error;
3324 		}
3325 		rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MD7_CFG__A, 0x0000, 0);
3326 		if (rc != 0) {
3327 			pr_err("error %d\n", rc);
3328 			goto rw_error;
3329 		}
3330 		/* Enable Monitor Bus output over MPEG pads and ctl input */
3331 		rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MON_CFG__A, 0x0000, 0);
3332 		if (rc != 0) {
3333 			pr_err("error %d\n", rc);
3334 			goto rw_error;
3335 		}
3336 		/* Write nomagic word to enable pdr reg write */
3337 		rc = drxj_dap_write_reg16(dev_addr, SIO_TOP_COMM_KEY__A, 0x0000, 0);
3338 		if (rc != 0) {
3339 			pr_err("error %d\n", rc);
3340 			goto rw_error;
3341 		}
3342 	}
3343 
3344 	/* save values for restore after re-acquire */
3345 	common_attr->mpeg_cfg.enable_mpeg_output = cfg_data->enable_mpeg_output;
3346 
3347 	return 0;
3348 rw_error:
3349 	return rc;
3350 }
3351 
3352 /*----------------------------------------------------------------------------*/
3353 
3354 
3355 /*----------------------------------------------------------------------------*/
3356 /* MPEG Output Configuration Functions - end                                  */
3357 /*----------------------------------------------------------------------------*/
3358 
3359 /*----------------------------------------------------------------------------*/
3360 /* miscellaneous configurations - begin                           */
3361 /*----------------------------------------------------------------------------*/
3362 
3363 /*
3364 * \fn int set_mpegtei_handling()
3365 * \brief Activate MPEG TEI handling settings.
3366 * \param devmod  Pointer to demodulator instance.
3367 * \return int.
3368 *
3369 * This routine should be called during a set channel of QAM/VSB
3370 *
3371 */
3372 static int set_mpegtei_handling(struct drx_demod_instance *demod)
3373 {
3374 	struct drxj_data *ext_attr = (struct drxj_data *) (NULL);
3375 	struct i2c_device_addr *dev_addr = (struct i2c_device_addr *)(NULL);
3376 	int rc;
3377 	u16 fec_oc_dpr_mode = 0;
3378 	u16 fec_oc_snc_mode = 0;
3379 	u16 fec_oc_ems_mode = 0;
3380 
3381 	dev_addr = demod->my_i2c_dev_addr;
3382 	ext_attr = (struct drxj_data *) demod->my_ext_attr;
3383 
3384 	rc = drxj_dap_read_reg16(dev_addr, FEC_OC_DPR_MODE__A, &fec_oc_dpr_mode, 0);
3385 	if (rc != 0) {
3386 		pr_err("error %d\n", rc);
3387 		goto rw_error;
3388 	}
3389 	rc = drxj_dap_read_reg16(dev_addr, FEC_OC_SNC_MODE__A, &fec_oc_snc_mode, 0);
3390 	if (rc != 0) {
3391 		pr_err("error %d\n", rc);
3392 		goto rw_error;
3393 	}
3394 	rc = drxj_dap_read_reg16(dev_addr, FEC_OC_EMS_MODE__A, &fec_oc_ems_mode, 0);
3395 	if (rc != 0) {
3396 		pr_err("error %d\n", rc);
3397 		goto rw_error;
3398 	}
3399 
3400 	/* reset to default, allow TEI bit to be changed */
3401 	fec_oc_dpr_mode &= (~FEC_OC_DPR_MODE_ERR_DISABLE__M);
3402 	fec_oc_snc_mode &= (~(FEC_OC_SNC_MODE_ERROR_CTL__M |
3403 			   FEC_OC_SNC_MODE_CORR_DISABLE__M));
3404 	fec_oc_ems_mode &= (~FEC_OC_EMS_MODE_MODE__M);
3405 
3406 	if (ext_attr->disable_te_ihandling) {
3407 		/* do not change TEI bit */
3408 		fec_oc_dpr_mode |= FEC_OC_DPR_MODE_ERR_DISABLE__M;
3409 		fec_oc_snc_mode |= FEC_OC_SNC_MODE_CORR_DISABLE__M |
3410 		    ((0x2) << (FEC_OC_SNC_MODE_ERROR_CTL__B));
3411 		fec_oc_ems_mode |= ((0x01) << (FEC_OC_EMS_MODE_MODE__B));
3412 	}
3413 
3414 	rc = drxj_dap_write_reg16(dev_addr, FEC_OC_DPR_MODE__A, fec_oc_dpr_mode, 0);
3415 	if (rc != 0) {
3416 		pr_err("error %d\n", rc);
3417 		goto rw_error;
3418 	}
3419 	rc = drxj_dap_write_reg16(dev_addr, FEC_OC_SNC_MODE__A, fec_oc_snc_mode, 0);
3420 	if (rc != 0) {
3421 		pr_err("error %d\n", rc);
3422 		goto rw_error;
3423 	}
3424 	rc = drxj_dap_write_reg16(dev_addr, FEC_OC_EMS_MODE__A, fec_oc_ems_mode, 0);
3425 	if (rc != 0) {
3426 		pr_err("error %d\n", rc);
3427 		goto rw_error;
3428 	}
3429 
3430 	return 0;
3431 rw_error:
3432 	return rc;
3433 }
3434 
3435 /*----------------------------------------------------------------------------*/
3436 /*
3437 * \fn int bit_reverse_mpeg_output()
3438 * \brief Set MPEG output bit-endian settings.
3439 * \param devmod  Pointer to demodulator instance.
3440 * \return int.
3441 *
3442 * This routine should be called during a set channel of QAM/VSB
3443 *
3444 */
3445 static int bit_reverse_mpeg_output(struct drx_demod_instance *demod)
3446 {
3447 	struct drxj_data *ext_attr = (struct drxj_data *) (NULL);
3448 	struct i2c_device_addr *dev_addr = (struct i2c_device_addr *)(NULL);
3449 	int rc;
3450 	u16 fec_oc_ipr_mode = 0;
3451 
3452 	dev_addr = demod->my_i2c_dev_addr;
3453 	ext_attr = (struct drxj_data *) demod->my_ext_attr;
3454 
3455 	rc = drxj_dap_read_reg16(dev_addr, FEC_OC_IPR_MODE__A, &fec_oc_ipr_mode, 0);
3456 	if (rc != 0) {
3457 		pr_err("error %d\n", rc);
3458 		goto rw_error;
3459 	}
3460 
3461 	/* reset to default (normal bit order) */
3462 	fec_oc_ipr_mode &= (~FEC_OC_IPR_MODE_REVERSE_ORDER__M);
3463 
3464 	if (ext_attr->bit_reverse_mpeg_outout)
3465 		fec_oc_ipr_mode |= FEC_OC_IPR_MODE_REVERSE_ORDER__M;
3466 
3467 	rc = drxj_dap_write_reg16(dev_addr, FEC_OC_IPR_MODE__A, fec_oc_ipr_mode, 0);
3468 	if (rc != 0) {
3469 		pr_err("error %d\n", rc);
3470 		goto rw_error;
3471 	}
3472 
3473 	return 0;
3474 rw_error:
3475 	return rc;
3476 }
3477 
3478 /*----------------------------------------------------------------------------*/
3479 /*
3480 * \fn int set_mpeg_start_width()
3481 * \brief Set MPEG start width.
3482 * \param devmod  Pointer to demodulator instance.
3483 * \return int.
3484 *
3485 * This routine should be called during a set channel of QAM/VSB
3486 *
3487 */
3488 static int set_mpeg_start_width(struct drx_demod_instance *demod)
3489 {
3490 	struct drxj_data *ext_attr = (struct drxj_data *) (NULL);
3491 	struct i2c_device_addr *dev_addr = (struct i2c_device_addr *)(NULL);
3492 	struct drx_common_attr *common_attr = (struct drx_common_attr *) NULL;
3493 	int rc;
3494 	u16 fec_oc_comm_mb = 0;
3495 
3496 	dev_addr = demod->my_i2c_dev_addr;
3497 	ext_attr = (struct drxj_data *) demod->my_ext_attr;
3498 	common_attr = demod->my_common_attr;
3499 
3500 	if ((common_attr->mpeg_cfg.static_clk == true)
3501 	    && (common_attr->mpeg_cfg.enable_parallel == false)) {
3502 		rc = drxj_dap_read_reg16(dev_addr, FEC_OC_COMM_MB__A, &fec_oc_comm_mb, 0);
3503 		if (rc != 0) {
3504 			pr_err("error %d\n", rc);
3505 			goto rw_error;
3506 		}
3507 		fec_oc_comm_mb &= ~FEC_OC_COMM_MB_CTL_ON;
3508 		if (ext_attr->mpeg_start_width == DRXJ_MPEG_START_WIDTH_8CLKCYC)
3509 			fec_oc_comm_mb |= FEC_OC_COMM_MB_CTL_ON;
3510 		rc = drxj_dap_write_reg16(dev_addr, FEC_OC_COMM_MB__A, fec_oc_comm_mb, 0);
3511 		if (rc != 0) {
3512 			pr_err("error %d\n", rc);
3513 			goto rw_error;
3514 		}
3515 	}
3516 
3517 	return 0;
3518 rw_error:
3519 	return rc;
3520 }
3521 
3522 /*----------------------------------------------------------------------------*/
3523 /* miscellaneous configurations - end                             */
3524 /*----------------------------------------------------------------------------*/
3525 
3526 /*----------------------------------------------------------------------------*/
3527 /* UIO Configuration Functions - begin                                        */
3528 /*----------------------------------------------------------------------------*/
3529 /*
3530 * \fn int ctrl_set_uio_cfg()
3531 * \brief Configure modus oprandi UIO.
3532 * \param demod Pointer to demodulator instance.
3533 * \param uio_cfg Pointer to a configuration setting for a certain UIO.
3534 * \return int.
3535 */
3536 static int ctrl_set_uio_cfg(struct drx_demod_instance *demod, struct drxuio_cfg *uio_cfg)
3537 {
3538 	struct drxj_data *ext_attr = (struct drxj_data *) (NULL);
3539 	int rc;
3540 
3541 	if ((uio_cfg == NULL) || (demod == NULL))
3542 		return -EINVAL;
3543 
3544 	ext_attr = (struct drxj_data *) demod->my_ext_attr;
3545 
3546 	/*  Write magic word to enable pdr reg write               */
3547 	rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, SIO_TOP_COMM_KEY__A, SIO_TOP_COMM_KEY_KEY, 0);
3548 	if (rc != 0) {
3549 		pr_err("error %d\n", rc);
3550 		goto rw_error;
3551 	}
3552 	switch (uio_cfg->uio) {
3553       /*====================================================================*/
3554 	case DRX_UIO1:
3555 		/* DRX_UIO1: SMA_TX UIO-1 */
3556 		if (!ext_attr->has_smatx)
3557 			return -EIO;
3558 		switch (uio_cfg->mode) {
3559 		case DRX_UIO_MODE_FIRMWARE_SMA:	/* falltrough */
3560 		case DRX_UIO_MODE_FIRMWARE_SAW:	/* falltrough */
3561 		case DRX_UIO_MODE_READWRITE:
3562 			ext_attr->uio_sma_tx_mode = uio_cfg->mode;
3563 			break;
3564 		case DRX_UIO_MODE_DISABLE:
3565 			ext_attr->uio_sma_tx_mode = uio_cfg->mode;
3566 			/* pad configuration register is set 0 - input mode */
3567 			rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, SIO_PDR_SMA_TX_CFG__A, 0, 0);
3568 			if (rc != 0) {
3569 				pr_err("error %d\n", rc);
3570 				goto rw_error;
3571 			}
3572 			break;
3573 		default:
3574 			return -EINVAL;
3575 		}		/* switch ( uio_cfg->mode ) */
3576 		break;
3577       /*====================================================================*/
3578 	case DRX_UIO2:
3579 		/* DRX_UIO2: SMA_RX UIO-2 */
3580 		if (!ext_attr->has_smarx)
3581 			return -EIO;
3582 		switch (uio_cfg->mode) {
3583 		case DRX_UIO_MODE_FIRMWARE0:	/* falltrough */
3584 		case DRX_UIO_MODE_READWRITE:
3585 			ext_attr->uio_sma_rx_mode = uio_cfg->mode;
3586 			break;
3587 		case DRX_UIO_MODE_DISABLE:
3588 			ext_attr->uio_sma_rx_mode = uio_cfg->mode;
3589 			/* pad configuration register is set 0 - input mode */
3590 			rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, SIO_PDR_SMA_RX_CFG__A, 0, 0);
3591 			if (rc != 0) {
3592 				pr_err("error %d\n", rc);
3593 				goto rw_error;
3594 			}
3595 			break;
3596 		default:
3597 			return -EINVAL;
3598 			break;
3599 		}		/* switch ( uio_cfg->mode ) */
3600 		break;
3601       /*====================================================================*/
3602 	case DRX_UIO3:
3603 		/* DRX_UIO3: GPIO UIO-3 */
3604 		if (!ext_attr->has_gpio)
3605 			return -EIO;
3606 		switch (uio_cfg->mode) {
3607 		case DRX_UIO_MODE_FIRMWARE0:	/* falltrough */
3608 		case DRX_UIO_MODE_READWRITE:
3609 			ext_attr->uio_gpio_mode = uio_cfg->mode;
3610 			break;
3611 		case DRX_UIO_MODE_DISABLE:
3612 			ext_attr->uio_gpio_mode = uio_cfg->mode;
3613 			/* pad configuration register is set 0 - input mode */
3614 			rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, SIO_PDR_GPIO_CFG__A, 0, 0);
3615 			if (rc != 0) {
3616 				pr_err("error %d\n", rc);
3617 				goto rw_error;
3618 			}
3619 			break;
3620 		default:
3621 			return -EINVAL;
3622 			break;
3623 		}		/* switch ( uio_cfg->mode ) */
3624 		break;
3625       /*====================================================================*/
3626 	case DRX_UIO4:
3627 		/* DRX_UIO4: IRQN UIO-4 */
3628 		if (!ext_attr->has_irqn)
3629 			return -EIO;
3630 		switch (uio_cfg->mode) {
3631 		case DRX_UIO_MODE_READWRITE:
3632 			ext_attr->uio_irqn_mode = uio_cfg->mode;
3633 			break;
3634 		case DRX_UIO_MODE_DISABLE:
3635 			/* pad configuration register is set 0 - input mode */
3636 			rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, SIO_PDR_IRQN_CFG__A, 0, 0);
3637 			if (rc != 0) {
3638 				pr_err("error %d\n", rc);
3639 				goto rw_error;
3640 			}
3641 			ext_attr->uio_irqn_mode = uio_cfg->mode;
3642 			break;
3643 		case DRX_UIO_MODE_FIRMWARE0:	/* falltrough */
3644 		default:
3645 			return -EINVAL;
3646 			break;
3647 		}		/* switch ( uio_cfg->mode ) */
3648 		break;
3649       /*====================================================================*/
3650 	default:
3651 		return -EINVAL;
3652 	}			/* switch ( uio_cfg->uio ) */
3653 
3654 	/*  Write magic word to disable pdr reg write               */
3655 	rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, SIO_TOP_COMM_KEY__A, 0x0000, 0);
3656 	if (rc != 0) {
3657 		pr_err("error %d\n", rc);
3658 		goto rw_error;
3659 	}
3660 
3661 	return 0;
3662 rw_error:
3663 	return rc;
3664 }
3665 
3666 /*
3667 * \fn int ctrl_uio_write()
3668 * \brief Write to a UIO.
3669 * \param demod Pointer to demodulator instance.
3670 * \param uio_data Pointer to data container for a certain UIO.
3671 * \return int.
3672 */
3673 static int
3674 ctrl_uio_write(struct drx_demod_instance *demod, struct drxuio_data *uio_data)
3675 {
3676 	struct drxj_data *ext_attr = (struct drxj_data *) (NULL);
3677 	int rc;
3678 	u16 pin_cfg_value = 0;
3679 	u16 value = 0;
3680 
3681 	if ((uio_data == NULL) || (demod == NULL))
3682 		return -EINVAL;
3683 
3684 	ext_attr = (struct drxj_data *) demod->my_ext_attr;
3685 
3686 	/*  Write magic word to enable pdr reg write               */
3687 	rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, SIO_TOP_COMM_KEY__A, SIO_TOP_COMM_KEY_KEY, 0);
3688 	if (rc != 0) {
3689 		pr_err("error %d\n", rc);
3690 		goto rw_error;
3691 	}
3692 	switch (uio_data->uio) {
3693       /*====================================================================*/
3694 	case DRX_UIO1:
3695 		/* DRX_UIO1: SMA_TX UIO-1 */
3696 		if (!ext_attr->has_smatx)
3697 			return -EIO;
3698 		if ((ext_attr->uio_sma_tx_mode != DRX_UIO_MODE_READWRITE)
3699 		    && (ext_attr->uio_sma_tx_mode != DRX_UIO_MODE_FIRMWARE_SAW)) {
3700 			return -EIO;
3701 		}
3702 		pin_cfg_value = 0;
3703 		/* io_pad_cfg register (8 bit reg.) MSB bit is 1 (default value) */
3704 		pin_cfg_value |= 0x0113;
3705 		/* io_pad_cfg_mode output mode is drive always */
3706 		/* io_pad_cfg_drive is set to power 2 (23 mA) */
3707 
3708 		/* write to io pad configuration register - output mode */
3709 		rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, SIO_PDR_SMA_TX_CFG__A, pin_cfg_value, 0);
3710 		if (rc != 0) {
3711 			pr_err("error %d\n", rc);
3712 			goto rw_error;
3713 		}
3714 
3715 		/* use corresponding bit in io data output registar */
3716 		rc = drxj_dap_read_reg16(demod->my_i2c_dev_addr, SIO_PDR_UIO_OUT_LO__A, &value, 0);
3717 		if (rc != 0) {
3718 			pr_err("error %d\n", rc);
3719 			goto rw_error;
3720 		}
3721 		if (!uio_data->value)
3722 			value &= 0x7FFF;	/* write zero to 15th bit - 1st UIO */
3723 		else
3724 			value |= 0x8000;	/* write one to 15th bit - 1st UIO */
3725 
3726 		/* write back to io data output register */
3727 		rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, SIO_PDR_UIO_OUT_LO__A, value, 0);
3728 		if (rc != 0) {
3729 			pr_err("error %d\n", rc);
3730 			goto rw_error;
3731 		}
3732 		break;
3733    /*======================================================================*/
3734 	case DRX_UIO2:
3735 		/* DRX_UIO2: SMA_RX UIO-2 */
3736 		if (!ext_attr->has_smarx)
3737 			return -EIO;
3738 		if (ext_attr->uio_sma_rx_mode != DRX_UIO_MODE_READWRITE)
3739 			return -EIO;
3740 
3741 		pin_cfg_value = 0;
3742 		/* io_pad_cfg register (8 bit reg.) MSB bit is 1 (default value) */
3743 		pin_cfg_value |= 0x0113;
3744 		/* io_pad_cfg_mode output mode is drive always */
3745 		/* io_pad_cfg_drive is set to power 2 (23 mA) */
3746 
3747 		/* write to io pad configuration register - output mode */
3748 		rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, SIO_PDR_SMA_RX_CFG__A, pin_cfg_value, 0);
3749 		if (rc != 0) {
3750 			pr_err("error %d\n", rc);
3751 			goto rw_error;
3752 		}
3753 
3754 		/* use corresponding bit in io data output registar */
3755 		rc = drxj_dap_read_reg16(demod->my_i2c_dev_addr, SIO_PDR_UIO_OUT_LO__A, &value, 0);
3756 		if (rc != 0) {
3757 			pr_err("error %d\n", rc);
3758 			goto rw_error;
3759 		}
3760 		if (!uio_data->value)
3761 			value &= 0xBFFF;	/* write zero to 14th bit - 2nd UIO */
3762 		else
3763 			value |= 0x4000;	/* write one to 14th bit - 2nd UIO */
3764 
3765 		/* write back to io data output register */
3766 		rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, SIO_PDR_UIO_OUT_LO__A, value, 0);
3767 		if (rc != 0) {
3768 			pr_err("error %d\n", rc);
3769 			goto rw_error;
3770 		}
3771 		break;
3772    /*====================================================================*/
3773 	case DRX_UIO3:
3774 		/* DRX_UIO3: ASEL UIO-3 */
3775 		if (!ext_attr->has_gpio)
3776 			return -EIO;
3777 		if (ext_attr->uio_gpio_mode != DRX_UIO_MODE_READWRITE)
3778 			return -EIO;
3779 
3780 		pin_cfg_value = 0;
3781 		/* io_pad_cfg register (8 bit reg.) MSB bit is 1 (default value) */
3782 		pin_cfg_value |= 0x0113;
3783 		/* io_pad_cfg_mode output mode is drive always */
3784 		/* io_pad_cfg_drive is set to power 2 (23 mA) */
3785 
3786 		/* write to io pad configuration register - output mode */
3787 		rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, SIO_PDR_GPIO_CFG__A, pin_cfg_value, 0);
3788 		if (rc != 0) {
3789 			pr_err("error %d\n", rc);
3790 			goto rw_error;
3791 		}
3792 
3793 		/* use corresponding bit in io data output registar */
3794 		rc = drxj_dap_read_reg16(demod->my_i2c_dev_addr, SIO_PDR_UIO_OUT_HI__A, &value, 0);
3795 		if (rc != 0) {
3796 			pr_err("error %d\n", rc);
3797 			goto rw_error;
3798 		}
3799 		if (!uio_data->value)
3800 			value &= 0xFFFB;	/* write zero to 2nd bit - 3rd UIO */
3801 		else
3802 			value |= 0x0004;	/* write one to 2nd bit - 3rd UIO */
3803 
3804 		/* write back to io data output register */
3805 		rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, SIO_PDR_UIO_OUT_HI__A, value, 0);
3806 		if (rc != 0) {
3807 			pr_err("error %d\n", rc);
3808 			goto rw_error;
3809 		}
3810 		break;
3811    /*=====================================================================*/
3812 	case DRX_UIO4:
3813 		/* DRX_UIO4: IRQN UIO-4 */
3814 		if (!ext_attr->has_irqn)
3815 			return -EIO;
3816 
3817 		if (ext_attr->uio_irqn_mode != DRX_UIO_MODE_READWRITE)
3818 			return -EIO;
3819 
3820 		pin_cfg_value = 0;
3821 		/* io_pad_cfg register (8 bit reg.) MSB bit is 1 (default value) */
3822 		pin_cfg_value |= 0x0113;
3823 		/* io_pad_cfg_mode output mode is drive always */
3824 		/* io_pad_cfg_drive is set to power 2 (23 mA) */
3825 
3826 		/* write to io pad configuration register - output mode */
3827 		rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, SIO_PDR_IRQN_CFG__A, pin_cfg_value, 0);
3828 		if (rc != 0) {
3829 			pr_err("error %d\n", rc);
3830 			goto rw_error;
3831 		}
3832 
3833 		/* use corresponding bit in io data output registar */
3834 		rc = drxj_dap_read_reg16(demod->my_i2c_dev_addr, SIO_PDR_UIO_OUT_LO__A, &value, 0);
3835 		if (rc != 0) {
3836 			pr_err("error %d\n", rc);
3837 			goto rw_error;
3838 		}
3839 		if (uio_data->value == false)
3840 			value &= 0xEFFF;	/* write zero to 12th bit - 4th UIO */
3841 		else
3842 			value |= 0x1000;	/* write one to 12th bit - 4th UIO */
3843 
3844 		/* write back to io data output register */
3845 		rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, SIO_PDR_UIO_OUT_LO__A, value, 0);
3846 		if (rc != 0) {
3847 			pr_err("error %d\n", rc);
3848 			goto rw_error;
3849 		}
3850 		break;
3851       /*=====================================================================*/
3852 	default:
3853 		return -EINVAL;
3854 	}			/* switch ( uio_data->uio ) */
3855 
3856 	/*  Write magic word to disable pdr reg write               */
3857 	rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, SIO_TOP_COMM_KEY__A, 0x0000, 0);
3858 	if (rc != 0) {
3859 		pr_err("error %d\n", rc);
3860 		goto rw_error;
3861 	}
3862 
3863 	return 0;
3864 rw_error:
3865 	return rc;
3866 }
3867 
3868 /*---------------------------------------------------------------------------*/
3869 /* UIO Configuration Functions - end                                         */
3870 /*---------------------------------------------------------------------------*/
3871 
3872 /*----------------------------------------------------------------------------*/
3873 /* I2C Bridge Functions - begin                                               */
3874 /*----------------------------------------------------------------------------*/
3875 /*
3876 * \fn int ctrl_i2c_bridge()
3877 * \brief Open or close the I2C switch to tuner.
3878 * \param demod Pointer to demodulator instance.
3879 * \param bridge_closed Pointer to bool indication if bridge is closed not.
3880 * \return int.
3881 
3882 */
3883 static int
3884 ctrl_i2c_bridge(struct drx_demod_instance *demod, bool *bridge_closed)
3885 {
3886 	struct drxj_hi_cmd hi_cmd;
3887 	u16 result = 0;
3888 
3889 	/* check arguments */
3890 	if (bridge_closed == NULL)
3891 		return -EINVAL;
3892 
3893 	hi_cmd.cmd = SIO_HI_RA_RAM_CMD_BRDCTRL;
3894 	hi_cmd.param1 = SIO_HI_RA_RAM_PAR_1_PAR1_SEC_KEY;
3895 	if (*bridge_closed)
3896 		hi_cmd.param2 = SIO_HI_RA_RAM_PAR_2_BRD_CFG_CLOSED;
3897 	else
3898 		hi_cmd.param2 = SIO_HI_RA_RAM_PAR_2_BRD_CFG_OPEN;
3899 
3900 	return hi_command(demod->my_i2c_dev_addr, &hi_cmd, &result);
3901 }
3902 
3903 /*----------------------------------------------------------------------------*/
3904 /* I2C Bridge Functions - end                                                 */
3905 /*----------------------------------------------------------------------------*/
3906 
3907 /*----------------------------------------------------------------------------*/
3908 /* Smart antenna Functions - begin                                            */
3909 /*----------------------------------------------------------------------------*/
3910 /*
3911 * \fn int smart_ant_init()
3912 * \brief Initialize Smart Antenna.
3913 * \param pointer to struct drx_demod_instance.
3914 * \return int.
3915 *
3916 */
3917 static int smart_ant_init(struct drx_demod_instance *demod)
3918 {
3919 	struct drxj_data *ext_attr = NULL;
3920 	struct i2c_device_addr *dev_addr = NULL;
3921 	struct drxuio_cfg uio_cfg = { DRX_UIO1, DRX_UIO_MODE_FIRMWARE_SMA };
3922 	int rc;
3923 	u16 data = 0;
3924 
3925 	dev_addr = demod->my_i2c_dev_addr;
3926 	ext_attr = (struct drxj_data *) demod->my_ext_attr;
3927 
3928 	/*  Write magic word to enable pdr reg write               */
3929 	rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, SIO_TOP_COMM_KEY__A, SIO_TOP_COMM_KEY_KEY, 0);
3930 	if (rc != 0) {
3931 		pr_err("error %d\n", rc);
3932 		goto rw_error;
3933 	}
3934 	/* init smart antenna */
3935 	rc = drxj_dap_read_reg16(dev_addr, SIO_SA_TX_COMMAND__A, &data, 0);
3936 	if (rc != 0) {
3937 		pr_err("error %d\n", rc);
3938 		goto rw_error;
3939 	}
3940 	if (ext_attr->smart_ant_inverted) {
3941 		rc = drxj_dap_write_reg16(dev_addr, SIO_SA_TX_COMMAND__A, (data | SIO_SA_TX_COMMAND_TX_INVERT__M) | SIO_SA_TX_COMMAND_TX_ENABLE__M, 0);
3942 		if (rc != 0) {
3943 			pr_err("error %d\n", rc);
3944 			goto rw_error;
3945 		}
3946 	} else {
3947 		rc = drxj_dap_write_reg16(dev_addr, SIO_SA_TX_COMMAND__A, (data & (~SIO_SA_TX_COMMAND_TX_INVERT__M)) | SIO_SA_TX_COMMAND_TX_ENABLE__M, 0);
3948 		if (rc != 0) {
3949 			pr_err("error %d\n", rc);
3950 			goto rw_error;
3951 		}
3952 	}
3953 
3954 	/* config SMA_TX pin to smart antenna mode */
3955 	rc = ctrl_set_uio_cfg(demod, &uio_cfg);
3956 	if (rc != 0) {
3957 		pr_err("error %d\n", rc);
3958 		goto rw_error;
3959 	}
3960 	rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, SIO_PDR_SMA_TX_CFG__A, 0x13, 0);
3961 	if (rc != 0) {
3962 		pr_err("error %d\n", rc);
3963 		goto rw_error;
3964 	}
3965 	rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, SIO_PDR_SMA_TX_GPIO_FNC__A, 0x03, 0);
3966 	if (rc != 0) {
3967 		pr_err("error %d\n", rc);
3968 		goto rw_error;
3969 	}
3970 
3971 	/*  Write magic word to disable pdr reg write               */
3972 	rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, SIO_TOP_COMM_KEY__A, 0x0000, 0);
3973 	if (rc != 0) {
3974 		pr_err("error %d\n", rc);
3975 		goto rw_error;
3976 	}
3977 
3978 	return 0;
3979 rw_error:
3980 	return rc;
3981 }
3982 
3983 static int scu_command(struct i2c_device_addr *dev_addr, struct drxjscu_cmd *cmd)
3984 {
3985 	int rc;
3986 	u16 cur_cmd = 0;
3987 	unsigned long timeout;
3988 
3989 	/* Check param */
3990 	if (cmd == NULL)
3991 		return -EINVAL;
3992 
3993 	/* Wait until SCU command interface is ready to receive command */
3994 	rc = drxj_dap_read_reg16(dev_addr, SCU_RAM_COMMAND__A, &cur_cmd, 0);
3995 	if (rc != 0) {
3996 		pr_err("error %d\n", rc);
3997 		goto rw_error;
3998 	}
3999 	if (cur_cmd != DRX_SCU_READY)
4000 		return -EIO;
4001 
4002 	switch (cmd->parameter_len) {
4003 	case 5:
4004 		rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_PARAM_4__A, *(cmd->parameter + 4), 0);
4005 		if (rc != 0) {
4006 			pr_err("error %d\n", rc);
4007 			goto rw_error;
4008 		}	/* fallthrough */
4009 	case 4:
4010 		rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_PARAM_3__A, *(cmd->parameter + 3), 0);
4011 		if (rc != 0) {
4012 			pr_err("error %d\n", rc);
4013 			goto rw_error;
4014 		}	/* fallthrough */
4015 	case 3:
4016 		rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_PARAM_2__A, *(cmd->parameter + 2), 0);
4017 		if (rc != 0) {
4018 			pr_err("error %d\n", rc);
4019 			goto rw_error;
4020 		}	/* fallthrough */
4021 	case 2:
4022 		rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_PARAM_1__A, *(cmd->parameter + 1), 0);
4023 		if (rc != 0) {
4024 			pr_err("error %d\n", rc);
4025 			goto rw_error;
4026 		}	/* fallthrough */
4027 	case 1:
4028 		rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_PARAM_0__A, *(cmd->parameter + 0), 0);
4029 		if (rc != 0) {
4030 			pr_err("error %d\n", rc);
4031 			goto rw_error;
4032 		}	/* fallthrough */
4033 	case 0:
4034 		/* do nothing */
4035 		break;
4036 	default:
4037 		/* this number of parameters is not supported */
4038 		return -EIO;
4039 	}
4040 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_COMMAND__A, cmd->command, 0);
4041 	if (rc != 0) {
4042 		pr_err("error %d\n", rc);
4043 		goto rw_error;
4044 	}
4045 
4046 	/* Wait until SCU has processed command */
4047 	timeout = jiffies + msecs_to_jiffies(DRXJ_MAX_WAITTIME);
4048 	while (time_is_after_jiffies(timeout)) {
4049 		rc = drxj_dap_read_reg16(dev_addr, SCU_RAM_COMMAND__A, &cur_cmd, 0);
4050 		if (rc != 0) {
4051 			pr_err("error %d\n", rc);
4052 			goto rw_error;
4053 		}
4054 		if (cur_cmd == DRX_SCU_READY)
4055 			break;
4056 		usleep_range(1000, 2000);
4057 	}
4058 
4059 	if (cur_cmd != DRX_SCU_READY)
4060 		return -EIO;
4061 
4062 	/* read results */
4063 	if ((cmd->result_len > 0) && (cmd->result != NULL)) {
4064 		s16 err;
4065 
4066 		switch (cmd->result_len) {
4067 		case 4:
4068 			rc = drxj_dap_read_reg16(dev_addr, SCU_RAM_PARAM_3__A, cmd->result + 3, 0);
4069 			if (rc != 0) {
4070 				pr_err("error %d\n", rc);
4071 				goto rw_error;
4072 			}	/* fallthrough */
4073 		case 3:
4074 			rc = drxj_dap_read_reg16(dev_addr, SCU_RAM_PARAM_2__A, cmd->result + 2, 0);
4075 			if (rc != 0) {
4076 				pr_err("error %d\n", rc);
4077 				goto rw_error;
4078 			}	/* fallthrough */
4079 		case 2:
4080 			rc = drxj_dap_read_reg16(dev_addr, SCU_RAM_PARAM_1__A, cmd->result + 1, 0);
4081 			if (rc != 0) {
4082 				pr_err("error %d\n", rc);
4083 				goto rw_error;
4084 			}	/* fallthrough */
4085 		case 1:
4086 			rc = drxj_dap_read_reg16(dev_addr, SCU_RAM_PARAM_0__A, cmd->result + 0, 0);
4087 			if (rc != 0) {
4088 				pr_err("error %d\n", rc);
4089 				goto rw_error;
4090 			}	/* fallthrough */
4091 		case 0:
4092 			/* do nothing */
4093 			break;
4094 		default:
4095 			/* this number of parameters is not supported */
4096 			return -EIO;
4097 		}
4098 
4099 		/* Check if an error was reported by SCU */
4100 		err = cmd->result[0];
4101 
4102 		/* check a few fixed error codes */
4103 		if ((err == (s16) SCU_RAM_PARAM_0_RESULT_UNKSTD)
4104 		    || (err == (s16) SCU_RAM_PARAM_0_RESULT_UNKCMD)
4105 		    || (err == (s16) SCU_RAM_PARAM_0_RESULT_INVPAR)
4106 		    || (err == (s16) SCU_RAM_PARAM_0_RESULT_SIZE)
4107 		    ) {
4108 			return -EINVAL;
4109 		}
4110 		/* here it is assumed that negative means error, and positive no error */
4111 		else if (err < 0)
4112 			return -EIO;
4113 		else
4114 			return 0;
4115 	}
4116 
4117 	return 0;
4118 
4119 rw_error:
4120 	return rc;
4121 }
4122 
4123 /*
4124 * \fn int DRXJ_DAP_SCUAtomicReadWriteBlock()
4125 * \brief Basic access routine for SCU atomic read or write access
4126 * \param dev_addr  pointer to i2c dev address
4127 * \param addr     destination/source address
4128 * \param datasize size of data buffer in bytes
4129 * \param data     pointer to data buffer
4130 * \return int
4131 * \retval 0 Succes
4132 * \retval -EIO Timeout, I2C error, illegal bank
4133 *
4134 */
4135 #define ADDR_AT_SCU_SPACE(x) ((x - 0x82E000) * 2)
4136 static
4137 int drxj_dap_scu_atomic_read_write_block(struct i2c_device_addr *dev_addr, u32 addr, u16 datasize,	/* max 30 bytes because the limit of SCU parameter */
4138 					      u8 *data, bool read_flag)
4139 {
4140 	struct drxjscu_cmd scu_cmd;
4141 	int rc;
4142 	u16 set_param_parameters[18];
4143 	u16 cmd_result[15];
4144 
4145 	/* Parameter check */
4146 	if (!data || !dev_addr || (datasize % 2) || ((datasize / 2) > 16))
4147 		return -EINVAL;
4148 
4149 	set_param_parameters[1] = (u16) ADDR_AT_SCU_SPACE(addr);
4150 	if (read_flag) {		/* read */
4151 		set_param_parameters[0] = ((~(0x0080)) & datasize);
4152 		scu_cmd.parameter_len = 2;
4153 		scu_cmd.result_len = datasize / 2 + 2;
4154 	} else {
4155 		int i = 0;
4156 
4157 		set_param_parameters[0] = 0x0080 | datasize;
4158 		for (i = 0; i < (datasize / 2); i++) {
4159 			set_param_parameters[i + 2] =
4160 			    (data[2 * i] | (data[(2 * i) + 1] << 8));
4161 		}
4162 		scu_cmd.parameter_len = datasize / 2 + 2;
4163 		scu_cmd.result_len = 1;
4164 	}
4165 
4166 	scu_cmd.command =
4167 	    SCU_RAM_COMMAND_STANDARD_TOP |
4168 	    SCU_RAM_COMMAND_CMD_AUX_SCU_ATOMIC_ACCESS;
4169 	scu_cmd.result = cmd_result;
4170 	scu_cmd.parameter = set_param_parameters;
4171 	rc = scu_command(dev_addr, &scu_cmd);
4172 	if (rc != 0) {
4173 		pr_err("error %d\n", rc);
4174 		goto rw_error;
4175 	}
4176 
4177 	if (read_flag) {
4178 		int i = 0;
4179 		/* read data from buffer */
4180 		for (i = 0; i < (datasize / 2); i++) {
4181 			data[2 * i] = (u8) (scu_cmd.result[i + 2] & 0xFF);
4182 			data[(2 * i) + 1] = (u8) (scu_cmd.result[i + 2] >> 8);
4183 		}
4184 	}
4185 
4186 	return 0;
4187 
4188 rw_error:
4189 	return rc;
4190 
4191 }
4192 
4193 /*============================================================================*/
4194 
4195 /*
4196 * \fn int DRXJ_DAP_AtomicReadReg16()
4197 * \brief Atomic read of 16 bits words
4198 */
4199 static
4200 int drxj_dap_scu_atomic_read_reg16(struct i2c_device_addr *dev_addr,
4201 					 u32 addr,
4202 					 u16 *data, u32 flags)
4203 {
4204 	u8 buf[2] = { 0 };
4205 	int rc = -EIO;
4206 	u16 word = 0;
4207 
4208 	if (!data)
4209 		return -EINVAL;
4210 
4211 	rc = drxj_dap_scu_atomic_read_write_block(dev_addr, addr, 2, buf, true);
4212 	if (rc < 0)
4213 		return rc;
4214 
4215 	word = (u16) (buf[0] + (buf[1] << 8));
4216 
4217 	*data = word;
4218 
4219 	return rc;
4220 }
4221 
4222 /*============================================================================*/
4223 /*
4224 * \fn int drxj_dap_scu_atomic_write_reg16()
4225 * \brief Atomic read of 16 bits words
4226 */
4227 static
4228 int drxj_dap_scu_atomic_write_reg16(struct i2c_device_addr *dev_addr,
4229 					  u32 addr,
4230 					  u16 data, u32 flags)
4231 {
4232 	u8 buf[2];
4233 	int rc = -EIO;
4234 
4235 	buf[0] = (u8) (data & 0xff);
4236 	buf[1] = (u8) ((data >> 8) & 0xff);
4237 
4238 	rc = drxj_dap_scu_atomic_read_write_block(dev_addr, addr, 2, buf, false);
4239 
4240 	return rc;
4241 }
4242 
4243 /* -------------------------------------------------------------------------- */
4244 /*
4245 * \brief Measure result of ADC synchronisation
4246 * \param demod demod instance
4247 * \param count (returned) count
4248 * \return int.
4249 * \retval 0    Success
4250 * \retval -EIO Failure: I2C error
4251 *
4252 */
4253 static int adc_sync_measurement(struct drx_demod_instance *demod, u16 *count)
4254 {
4255 	struct i2c_device_addr *dev_addr = NULL;
4256 	int rc;
4257 	u16 data = 0;
4258 
4259 	dev_addr = demod->my_i2c_dev_addr;
4260 
4261 	/* Start measurement */
4262 	rc = drxj_dap_write_reg16(dev_addr, IQM_AF_COMM_EXEC__A, IQM_AF_COMM_EXEC_ACTIVE, 0);
4263 	if (rc != 0) {
4264 		pr_err("error %d\n", rc);
4265 		goto rw_error;
4266 	}
4267 	rc = drxj_dap_write_reg16(dev_addr, IQM_AF_START_LOCK__A, 1, 0);
4268 	if (rc != 0) {
4269 		pr_err("error %d\n", rc);
4270 		goto rw_error;
4271 	}
4272 
4273 	/* Wait at least 3*128*(1/sysclk) <<< 1 millisec */
4274 	msleep(1);
4275 
4276 	*count = 0;
4277 	rc = drxj_dap_read_reg16(dev_addr, IQM_AF_PHASE0__A, &data, 0);
4278 	if (rc != 0) {
4279 		pr_err("error %d\n", rc);
4280 		goto rw_error;
4281 	}
4282 	if (data == 127)
4283 		*count = *count + 1;
4284 	rc = drxj_dap_read_reg16(dev_addr, IQM_AF_PHASE1__A, &data, 0);
4285 	if (rc != 0) {
4286 		pr_err("error %d\n", rc);
4287 		goto rw_error;
4288 	}
4289 	if (data == 127)
4290 		*count = *count + 1;
4291 	rc = drxj_dap_read_reg16(dev_addr, IQM_AF_PHASE2__A, &data, 0);
4292 	if (rc != 0) {
4293 		pr_err("error %d\n", rc);
4294 		goto rw_error;
4295 	}
4296 	if (data == 127)
4297 		*count = *count + 1;
4298 
4299 	return 0;
4300 rw_error:
4301 	return rc;
4302 }
4303 
4304 /*
4305 * \brief Synchronize analog and digital clock domains
4306 * \param demod demod instance
4307 * \return int.
4308 * \retval 0    Success
4309 * \retval -EIO Failure: I2C error or failure to synchronize
4310 *
4311 * An IQM reset will also reset the results of this synchronization.
4312 * After an IQM reset this routine needs to be called again.
4313 *
4314 */
4315 
4316 static int adc_synchronization(struct drx_demod_instance *demod)
4317 {
4318 	struct i2c_device_addr *dev_addr = NULL;
4319 	int rc;
4320 	u16 count = 0;
4321 
4322 	dev_addr = demod->my_i2c_dev_addr;
4323 
4324 	rc = adc_sync_measurement(demod, &count);
4325 	if (rc != 0) {
4326 		pr_err("error %d\n", rc);
4327 		goto rw_error;
4328 	}
4329 
4330 	if (count == 1) {
4331 		/* Try sampling on a different edge */
4332 		u16 clk_neg = 0;
4333 
4334 		rc = drxj_dap_read_reg16(dev_addr, IQM_AF_CLKNEG__A, &clk_neg, 0);
4335 		if (rc != 0) {
4336 			pr_err("error %d\n", rc);
4337 			goto rw_error;
4338 		}
4339 
4340 		clk_neg ^= IQM_AF_CLKNEG_CLKNEGDATA__M;
4341 		rc = drxj_dap_write_reg16(dev_addr, IQM_AF_CLKNEG__A, clk_neg, 0);
4342 		if (rc != 0) {
4343 			pr_err("error %d\n", rc);
4344 			goto rw_error;
4345 		}
4346 
4347 		rc = adc_sync_measurement(demod, &count);
4348 		if (rc != 0) {
4349 			pr_err("error %d\n", rc);
4350 			goto rw_error;
4351 		}
4352 	}
4353 
4354 	/* TODO: implement fallback scenarios */
4355 	if (count < 2)
4356 		return -EIO;
4357 
4358 	return 0;
4359 rw_error:
4360 	return rc;
4361 }
4362 
4363 /*============================================================================*/
4364 /*==                      END AUXILIARY FUNCTIONS                           ==*/
4365 /*============================================================================*/
4366 
4367 /*============================================================================*/
4368 /*============================================================================*/
4369 /*==                8VSB & QAM COMMON DATAPATH FUNCTIONS                    ==*/
4370 /*============================================================================*/
4371 /*============================================================================*/
4372 /*
4373 * \fn int init_agc ()
4374 * \brief Initialize AGC for all standards.
4375 * \param demod instance of demodulator.
4376 * \param channel pointer to channel data.
4377 * \return int.
4378 */
4379 static int init_agc(struct drx_demod_instance *demod)
4380 {
4381 	struct i2c_device_addr *dev_addr = NULL;
4382 	struct drx_common_attr *common_attr = NULL;
4383 	struct drxj_data *ext_attr = NULL;
4384 	struct drxj_cfg_agc *p_agc_rf_settings = NULL;
4385 	struct drxj_cfg_agc *p_agc_if_settings = NULL;
4386 	int rc;
4387 	u16 ingain_tgt_max = 0;
4388 	u16 clp_dir_to = 0;
4389 	u16 sns_sum_max = 0;
4390 	u16 clp_sum_max = 0;
4391 	u16 sns_dir_to = 0;
4392 	u16 ki_innergain_min = 0;
4393 	u16 agc_ki = 0;
4394 	u16 ki_max = 0;
4395 	u16 if_iaccu_hi_tgt_min = 0;
4396 	u16 data = 0;
4397 	u16 agc_ki_dgain = 0;
4398 	u16 ki_min = 0;
4399 	u16 clp_ctrl_mode = 0;
4400 	u16 agc_rf = 0;
4401 	u16 agc_if = 0;
4402 
4403 	dev_addr = demod->my_i2c_dev_addr;
4404 	common_attr = (struct drx_common_attr *) demod->my_common_attr;
4405 	ext_attr = (struct drxj_data *) demod->my_ext_attr;
4406 
4407 	switch (ext_attr->standard) {
4408 	case DRX_STANDARD_8VSB:
4409 		clp_sum_max = 1023;
4410 		clp_dir_to = (u16) (-9);
4411 		sns_sum_max = 1023;
4412 		sns_dir_to = (u16) (-9);
4413 		ki_innergain_min = (u16) (-32768);
4414 		ki_max = 0x032C;
4415 		agc_ki_dgain = 0xC;
4416 		if_iaccu_hi_tgt_min = 2047;
4417 		ki_min = 0x0117;
4418 		ingain_tgt_max = 16383;
4419 		clp_ctrl_mode = 0;
4420 		rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_KI_MINGAIN__A, 0x7fff, 0);
4421 		if (rc != 0) {
4422 			pr_err("error %d\n", rc);
4423 			goto rw_error;
4424 		}
4425 		rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_KI_MAXGAIN__A, 0x0, 0);
4426 		if (rc != 0) {
4427 			pr_err("error %d\n", rc);
4428 			goto rw_error;
4429 		}
4430 		rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_CLP_SUM__A, 0, 0);
4431 		if (rc != 0) {
4432 			pr_err("error %d\n", rc);
4433 			goto rw_error;
4434 		}
4435 		rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_CLP_CYCCNT__A, 0, 0);
4436 		if (rc != 0) {
4437 			pr_err("error %d\n", rc);
4438 			goto rw_error;
4439 		}
4440 		rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_CLP_DIR_WD__A, 0, 0);
4441 		if (rc != 0) {
4442 			pr_err("error %d\n", rc);
4443 			goto rw_error;
4444 		}
4445 		rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_CLP_DIR_STP__A, 1, 0);
4446 		if (rc != 0) {
4447 			pr_err("error %d\n", rc);
4448 			goto rw_error;
4449 		}
4450 		rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_SNS_SUM__A, 0, 0);
4451 		if (rc != 0) {
4452 			pr_err("error %d\n", rc);
4453 			goto rw_error;
4454 		}
4455 		rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_SNS_CYCCNT__A, 0, 0);
4456 		if (rc != 0) {
4457 			pr_err("error %d\n", rc);
4458 			goto rw_error;
4459 		}
4460 		rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_SNS_DIR_WD__A, 0, 0);
4461 		if (rc != 0) {
4462 			pr_err("error %d\n", rc);
4463 			goto rw_error;
4464 		}
4465 		rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_SNS_DIR_STP__A, 1, 0);
4466 		if (rc != 0) {
4467 			pr_err("error %d\n", rc);
4468 			goto rw_error;
4469 		}
4470 		rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_INGAIN__A, 1024, 0);
4471 		if (rc != 0) {
4472 			pr_err("error %d\n", rc);
4473 			goto rw_error;
4474 		}
4475 		rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_VSB_AGC_POW_TGT__A, 22600, 0);
4476 		if (rc != 0) {
4477 			pr_err("error %d\n", rc);
4478 			goto rw_error;
4479 		}
4480 		rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_INGAIN_TGT__A, 13200, 0);
4481 		if (rc != 0) {
4482 			pr_err("error %d\n", rc);
4483 			goto rw_error;
4484 		}
4485 		p_agc_if_settings = &(ext_attr->vsb_if_agc_cfg);
4486 		p_agc_rf_settings = &(ext_attr->vsb_rf_agc_cfg);
4487 		break;
4488 #ifndef DRXJ_VSB_ONLY
4489 	case DRX_STANDARD_ITU_A:
4490 	case DRX_STANDARD_ITU_C:
4491 	case DRX_STANDARD_ITU_B:
4492 		ingain_tgt_max = 5119;
4493 		clp_sum_max = 1023;
4494 		clp_dir_to = (u16) (-5);
4495 		sns_sum_max = 127;
4496 		sns_dir_to = (u16) (-3);
4497 		ki_innergain_min = 0;
4498 		ki_max = 0x0657;
4499 		if_iaccu_hi_tgt_min = 2047;
4500 		agc_ki_dgain = 0x7;
4501 		ki_min = 0x0117;
4502 		clp_ctrl_mode = 0;
4503 		rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_KI_MINGAIN__A, 0x7fff, 0);
4504 		if (rc != 0) {
4505 			pr_err("error %d\n", rc);
4506 			goto rw_error;
4507 		}
4508 		rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_KI_MAXGAIN__A, 0x0, 0);
4509 		if (rc != 0) {
4510 			pr_err("error %d\n", rc);
4511 			goto rw_error;
4512 		}
4513 		rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_CLP_SUM__A, 0, 0);
4514 		if (rc != 0) {
4515 			pr_err("error %d\n", rc);
4516 			goto rw_error;
4517 		}
4518 		rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_CLP_CYCCNT__A, 0, 0);
4519 		if (rc != 0) {
4520 			pr_err("error %d\n", rc);
4521 			goto rw_error;
4522 		}
4523 		rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_CLP_DIR_WD__A, 0, 0);
4524 		if (rc != 0) {
4525 			pr_err("error %d\n", rc);
4526 			goto rw_error;
4527 		}
4528 		rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_CLP_DIR_STP__A, 1, 0);
4529 		if (rc != 0) {
4530 			pr_err("error %d\n", rc);
4531 			goto rw_error;
4532 		}
4533 		rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_SNS_SUM__A, 0, 0);
4534 		if (rc != 0) {
4535 			pr_err("error %d\n", rc);
4536 			goto rw_error;
4537 		}
4538 		rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_SNS_CYCCNT__A, 0, 0);
4539 		if (rc != 0) {
4540 			pr_err("error %d\n", rc);
4541 			goto rw_error;
4542 		}
4543 		rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_SNS_DIR_WD__A, 0, 0);
4544 		if (rc != 0) {
4545 			pr_err("error %d\n", rc);
4546 			goto rw_error;
4547 		}
4548 		rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_SNS_DIR_STP__A, 1, 0);
4549 		if (rc != 0) {
4550 			pr_err("error %d\n", rc);
4551 			goto rw_error;
4552 		}
4553 		p_agc_if_settings = &(ext_attr->qam_if_agc_cfg);
4554 		p_agc_rf_settings = &(ext_attr->qam_rf_agc_cfg);
4555 		rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_INGAIN_TGT__A, p_agc_if_settings->top, 0);
4556 		if (rc != 0) {
4557 			pr_err("error %d\n", rc);
4558 			goto rw_error;
4559 		}
4560 
4561 		rc = drxj_dap_read_reg16(dev_addr, SCU_RAM_AGC_KI__A, &agc_ki, 0);
4562 		if (rc != 0) {
4563 			pr_err("error %d\n", rc);
4564 			goto rw_error;
4565 		}
4566 		agc_ki &= 0xf000;
4567 		rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_KI__A, agc_ki, 0);
4568 		if (rc != 0) {
4569 			pr_err("error %d\n", rc);
4570 			goto rw_error;
4571 		}
4572 		break;
4573 #endif
4574 	default:
4575 		return -EINVAL;
4576 	}
4577 
4578 	/* for new AGC interface */
4579 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_INGAIN_TGT_MIN__A, p_agc_if_settings->top, 0);
4580 	if (rc != 0) {
4581 		pr_err("error %d\n", rc);
4582 		goto rw_error;
4583 	}
4584 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_INGAIN__A, p_agc_if_settings->top, 0);
4585 	if (rc != 0) {
4586 		pr_err("error %d\n", rc);
4587 		goto rw_error;
4588 	}	/* Gain fed from inner to outer AGC */
4589 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_INGAIN_TGT_MAX__A, ingain_tgt_max, 0);
4590 	if (rc != 0) {
4591 		pr_err("error %d\n", rc);
4592 		goto rw_error;
4593 	}
4594 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_IF_IACCU_HI_TGT_MIN__A, if_iaccu_hi_tgt_min, 0);
4595 	if (rc != 0) {
4596 		pr_err("error %d\n", rc);
4597 		goto rw_error;
4598 	}
4599 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_IF_IACCU_HI__A, 0, 0);
4600 	if (rc != 0) {
4601 		pr_err("error %d\n", rc);
4602 		goto rw_error;
4603 	}	/* set to p_agc_settings->top before */
4604 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_IF_IACCU_LO__A, 0, 0);
4605 	if (rc != 0) {
4606 		pr_err("error %d\n", rc);
4607 		goto rw_error;
4608 	}
4609 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_RF_IACCU_HI__A, 0, 0);
4610 	if (rc != 0) {
4611 		pr_err("error %d\n", rc);
4612 		goto rw_error;
4613 	}
4614 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_RF_IACCU_LO__A, 0, 0);
4615 	if (rc != 0) {
4616 		pr_err("error %d\n", rc);
4617 		goto rw_error;
4618 	}
4619 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_RF_MAX__A, 32767, 0);
4620 	if (rc != 0) {
4621 		pr_err("error %d\n", rc);
4622 		goto rw_error;
4623 	}
4624 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_CLP_SUM_MAX__A, clp_sum_max, 0);
4625 	if (rc != 0) {
4626 		pr_err("error %d\n", rc);
4627 		goto rw_error;
4628 	}
4629 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_SNS_SUM_MAX__A, sns_sum_max, 0);
4630 	if (rc != 0) {
4631 		pr_err("error %d\n", rc);
4632 		goto rw_error;
4633 	}
4634 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_KI_INNERGAIN_MIN__A, ki_innergain_min, 0);
4635 	if (rc != 0) {
4636 		pr_err("error %d\n", rc);
4637 		goto rw_error;
4638 	}
4639 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_FAST_SNS_CTRL_DELAY__A, 50, 0);
4640 	if (rc != 0) {
4641 		pr_err("error %d\n", rc);
4642 		goto rw_error;
4643 	}
4644 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_KI_CYCLEN__A, 500, 0);
4645 	if (rc != 0) {
4646 		pr_err("error %d\n", rc);
4647 		goto rw_error;
4648 	}
4649 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_SNS_CYCLEN__A, 500, 0);
4650 	if (rc != 0) {
4651 		pr_err("error %d\n", rc);
4652 		goto rw_error;
4653 	}
4654 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_KI_MAXMINGAIN_TH__A, 20, 0);
4655 	if (rc != 0) {
4656 		pr_err("error %d\n", rc);
4657 		goto rw_error;
4658 	}
4659 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_KI_MIN__A, ki_min, 0);
4660 	if (rc != 0) {
4661 		pr_err("error %d\n", rc);
4662 		goto rw_error;
4663 	}
4664 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_KI_MAX__A, ki_max, 0);
4665 	if (rc != 0) {
4666 		pr_err("error %d\n", rc);
4667 		goto rw_error;
4668 	}
4669 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_KI_RED__A, 0, 0);
4670 	if (rc != 0) {
4671 		pr_err("error %d\n", rc);
4672 		goto rw_error;
4673 	}
4674 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_CLP_SUM_MIN__A, 8, 0);
4675 	if (rc != 0) {
4676 		pr_err("error %d\n", rc);
4677 		goto rw_error;
4678 	}
4679 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_CLP_CYCLEN__A, 500, 0);
4680 	if (rc != 0) {
4681 		pr_err("error %d\n", rc);
4682 		goto rw_error;
4683 	}
4684 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_CLP_DIR_TO__A, clp_dir_to, 0);
4685 	if (rc != 0) {
4686 		pr_err("error %d\n", rc);
4687 		goto rw_error;
4688 	}
4689 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_SNS_SUM_MIN__A, 8, 0);
4690 	if (rc != 0) {
4691 		pr_err("error %d\n", rc);
4692 		goto rw_error;
4693 	}
4694 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_SNS_DIR_TO__A, sns_dir_to, 0);
4695 	if (rc != 0) {
4696 		pr_err("error %d\n", rc);
4697 		goto rw_error;
4698 	}
4699 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_FAST_CLP_CTRL_DELAY__A, 50, 0);
4700 	if (rc != 0) {
4701 		pr_err("error %d\n", rc);
4702 		goto rw_error;
4703 	}
4704 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_CLP_CTRL_MODE__A, clp_ctrl_mode, 0);
4705 	if (rc != 0) {
4706 		pr_err("error %d\n", rc);
4707 		goto rw_error;
4708 	}
4709 
4710 	agc_rf = 0x800 + p_agc_rf_settings->cut_off_current;
4711 	if (common_attr->tuner_rf_agc_pol == true)
4712 		agc_rf = 0x87ff - agc_rf;
4713 
4714 	agc_if = 0x800;
4715 	if (common_attr->tuner_if_agc_pol == true)
4716 		agc_rf = 0x87ff - agc_rf;
4717 
4718 	rc = drxj_dap_write_reg16(dev_addr, IQM_AF_AGC_RF__A, agc_rf, 0);
4719 	if (rc != 0) {
4720 		pr_err("error %d\n", rc);
4721 		goto rw_error;
4722 	}
4723 	rc = drxj_dap_write_reg16(dev_addr, IQM_AF_AGC_IF__A, agc_if, 0);
4724 	if (rc != 0) {
4725 		pr_err("error %d\n", rc);
4726 		goto rw_error;
4727 	}
4728 
4729 	/* Set/restore Ki DGAIN factor */
4730 	rc = drxj_dap_read_reg16(dev_addr, SCU_RAM_AGC_KI__A, &data, 0);
4731 	if (rc != 0) {
4732 		pr_err("error %d\n", rc);
4733 		goto rw_error;
4734 	}
4735 	data &= ~SCU_RAM_AGC_KI_DGAIN__M;
4736 	data |= (agc_ki_dgain << SCU_RAM_AGC_KI_DGAIN__B);
4737 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_KI__A, data, 0);
4738 	if (rc != 0) {
4739 		pr_err("error %d\n", rc);
4740 		goto rw_error;
4741 	}
4742 
4743 	return 0;
4744 rw_error:
4745 	return rc;
4746 }
4747 
4748 /*
4749 * \fn int set_frequency ()
4750 * \brief Set frequency shift.
4751 * \param demod instance of demodulator.
4752 * \param channel pointer to channel data.
4753 * \param tuner_freq_offset residual frequency from tuner.
4754 * \return int.
4755 */
4756 static int
4757 set_frequency(struct drx_demod_instance *demod,
4758 	      struct drx_channel *channel, s32 tuner_freq_offset)
4759 {
4760 	struct i2c_device_addr *dev_addr = demod->my_i2c_dev_addr;
4761 	struct drxj_data *ext_attr = demod->my_ext_attr;
4762 	int rc;
4763 	s32 sampling_frequency = 0;
4764 	s32 frequency_shift = 0;
4765 	s32 if_freq_actual = 0;
4766 	s32 rf_freq_residual = -1 * tuner_freq_offset;
4767 	s32 adc_freq = 0;
4768 	s32 intermediate_freq = 0;
4769 	u32 iqm_fs_rate_ofs = 0;
4770 	bool adc_flip = true;
4771 	bool select_pos_image = false;
4772 	bool rf_mirror;
4773 	bool tuner_mirror;
4774 	bool image_to_select = true;
4775 	s32 fm_frequency_shift = 0;
4776 
4777 	rf_mirror = (ext_attr->mirror == DRX_MIRROR_YES) ? true : false;
4778 	tuner_mirror = demod->my_common_attr->mirror_freq_spect ? false : true;
4779 	/*
4780 	   Program frequency shifter
4781 	   No need to account for mirroring on RF
4782 	 */
4783 	switch (ext_attr->standard) {
4784 	case DRX_STANDARD_ITU_A:
4785 	case DRX_STANDARD_ITU_C:
4786 	case DRX_STANDARD_PAL_SECAM_LP:
4787 	case DRX_STANDARD_8VSB:
4788 		select_pos_image = true;
4789 		break;
4790 	case DRX_STANDARD_FM:
4791 		/* After IQM FS sound carrier must appear at 4 Mhz in spect.
4792 		   Sound carrier is already 3Mhz above centre frequency due
4793 		   to tuner setting so now add an extra shift of 1MHz... */
4794 		fm_frequency_shift = 1000;
4795 		/*fall through */
4796 	case DRX_STANDARD_ITU_B:
4797 	case DRX_STANDARD_NTSC:
4798 	case DRX_STANDARD_PAL_SECAM_BG:
4799 	case DRX_STANDARD_PAL_SECAM_DK:
4800 	case DRX_STANDARD_PAL_SECAM_I:
4801 	case DRX_STANDARD_PAL_SECAM_L:
4802 		select_pos_image = false;
4803 		break;
4804 	default:
4805 		return -EINVAL;
4806 	}
4807 	intermediate_freq = demod->my_common_attr->intermediate_freq;
4808 	sampling_frequency = demod->my_common_attr->sys_clock_freq / 3;
4809 	if (tuner_mirror)
4810 		if_freq_actual = intermediate_freq + rf_freq_residual + fm_frequency_shift;
4811 	else
4812 		if_freq_actual = intermediate_freq - rf_freq_residual - fm_frequency_shift;
4813 	if (if_freq_actual > sampling_frequency / 2) {
4814 		/* adc mirrors */
4815 		adc_freq = sampling_frequency - if_freq_actual;
4816 		adc_flip = true;
4817 	} else {
4818 		/* adc doesn't mirror */
4819 		adc_freq = if_freq_actual;
4820 		adc_flip = false;
4821 	}
4822 
4823 	frequency_shift = adc_freq;
4824 	image_to_select =
4825 	    (bool) (rf_mirror ^ tuner_mirror ^ adc_flip ^ select_pos_image);
4826 	iqm_fs_rate_ofs = frac28(frequency_shift, sampling_frequency);
4827 
4828 	if (image_to_select)
4829 		iqm_fs_rate_ofs = ~iqm_fs_rate_ofs + 1;
4830 
4831 	/* Program frequency shifter with tuner offset compensation */
4832 	/* frequency_shift += tuner_freq_offset; TODO */
4833 	rc = drxdap_fasi_write_reg32(dev_addr, IQM_FS_RATE_OFS_LO__A, iqm_fs_rate_ofs, 0);
4834 	if (rc != 0) {
4835 		pr_err("error %d\n", rc);
4836 		goto rw_error;
4837 	}
4838 	ext_attr->iqm_fs_rate_ofs = iqm_fs_rate_ofs;
4839 	ext_attr->pos_image = (bool) (rf_mirror ^ tuner_mirror ^ select_pos_image);
4840 
4841 	return 0;
4842 rw_error:
4843 	return rc;
4844 }
4845 
4846 /*
4847 * \fn int get_acc_pkt_err()
4848 * \brief Retrieve signal strength for VSB and QAM.
4849 * \param demod Pointer to demod instance
4850 * \param packet_err Pointer to packet error
4851 * \return int.
4852 * \retval 0 sig_strength contains valid data.
4853 * \retval -EINVAL sig_strength is NULL.
4854 * \retval -EIO Erroneous data, sig_strength contains invalid data.
4855 */
4856 #ifdef DRXJ_SIGNAL_ACCUM_ERR
4857 static int get_acc_pkt_err(struct drx_demod_instance *demod, u16 *packet_err)
4858 {
4859 	int rc;
4860 	static u16 pkt_err;
4861 	static u16 last_pkt_err;
4862 	u16 data = 0;
4863 	struct drxj_data *ext_attr = NULL;
4864 	struct i2c_device_addr *dev_addr = NULL;
4865 
4866 	ext_attr = (struct drxj_data *) demod->my_ext_attr;
4867 	dev_addr = demod->my_i2c_dev_addr;
4868 
4869 	rc = drxj_dap_read_reg16(dev_addr, SCU_RAM_FEC_ACCUM_PKT_FAILURES__A, &data, 0);
4870 	if (rc != 0) {
4871 		pr_err("error %d\n", rc);
4872 		goto rw_error;
4873 	}
4874 	if (ext_attr->reset_pkt_err_acc) {
4875 		last_pkt_err = data;
4876 		pkt_err = 0;
4877 		ext_attr->reset_pkt_err_acc = false;
4878 	}
4879 
4880 	if (data < last_pkt_err) {
4881 		pkt_err += 0xffff - last_pkt_err;
4882 		pkt_err += data;
4883 	} else {
4884 		pkt_err += (data - last_pkt_err);
4885 	}
4886 	*packet_err = pkt_err;
4887 	last_pkt_err = data;
4888 
4889 	return 0;
4890 rw_error:
4891 	return rc;
4892 }
4893 #endif
4894 
4895 
4896 /*============================================================================*/
4897 
4898 /*
4899 * \fn int set_agc_rf ()
4900 * \brief Configure RF AGC
4901 * \param demod instance of demodulator.
4902 * \param agc_settings AGC configuration structure
4903 * \return int.
4904 */
4905 static int
4906 set_agc_rf(struct drx_demod_instance *demod, struct drxj_cfg_agc *agc_settings, bool atomic)
4907 {
4908 	struct i2c_device_addr *dev_addr = NULL;
4909 	struct drxj_data *ext_attr = NULL;
4910 	struct drxj_cfg_agc *p_agc_settings = NULL;
4911 	struct drx_common_attr *common_attr = NULL;
4912 	int rc;
4913 	drx_write_reg16func_t scu_wr16 = NULL;
4914 	drx_read_reg16func_t scu_rr16 = NULL;
4915 
4916 	common_attr = (struct drx_common_attr *) demod->my_common_attr;
4917 	dev_addr = demod->my_i2c_dev_addr;
4918 	ext_attr = (struct drxj_data *) demod->my_ext_attr;
4919 
4920 	if (atomic) {
4921 		scu_rr16 = drxj_dap_scu_atomic_read_reg16;
4922 		scu_wr16 = drxj_dap_scu_atomic_write_reg16;
4923 	} else {
4924 		scu_rr16 = drxj_dap_read_reg16;
4925 		scu_wr16 = drxj_dap_write_reg16;
4926 	}
4927 
4928 	/* Configure AGC only if standard is currently active */
4929 	if ((ext_attr->standard == agc_settings->standard) ||
4930 	    (DRXJ_ISQAMSTD(ext_attr->standard) &&
4931 	     DRXJ_ISQAMSTD(agc_settings->standard)) ||
4932 	    (DRXJ_ISATVSTD(ext_attr->standard) &&
4933 	     DRXJ_ISATVSTD(agc_settings->standard))) {
4934 		u16 data = 0;
4935 
4936 		switch (agc_settings->ctrl_mode) {
4937 		case DRX_AGC_CTRL_AUTO:
4938 
4939 			/* Enable RF AGC DAC */
4940 			rc = drxj_dap_read_reg16(dev_addr, IQM_AF_STDBY__A, &data, 0);
4941 			if (rc != 0) {
4942 				pr_err("error %d\n", rc);
4943 				goto rw_error;
4944 			}
4945 			data |= IQM_AF_STDBY_STDBY_TAGC_RF_A2_ACTIVE;
4946 			rc = drxj_dap_write_reg16(dev_addr, IQM_AF_STDBY__A, data, 0);
4947 			if (rc != 0) {
4948 				pr_err("error %d\n", rc);
4949 				goto rw_error;
4950 			}
4951 
4952 			/* Enable SCU RF AGC loop */
4953 			rc = (*scu_rr16)(dev_addr, SCU_RAM_AGC_KI__A, &data, 0);
4954 			if (rc != 0) {
4955 				pr_err("error %d\n", rc);
4956 				goto rw_error;
4957 			}
4958 			data &= ~SCU_RAM_AGC_KI_RF__M;
4959 			if (ext_attr->standard == DRX_STANDARD_8VSB)
4960 				data |= (2 << SCU_RAM_AGC_KI_RF__B);
4961 			else if (DRXJ_ISQAMSTD(ext_attr->standard))
4962 				data |= (5 << SCU_RAM_AGC_KI_RF__B);
4963 			else
4964 				data |= (4 << SCU_RAM_AGC_KI_RF__B);
4965 
4966 			if (common_attr->tuner_rf_agc_pol)
4967 				data |= SCU_RAM_AGC_KI_INV_RF_POL__M;
4968 			else
4969 				data &= ~SCU_RAM_AGC_KI_INV_RF_POL__M;
4970 			rc = (*scu_wr16)(dev_addr, SCU_RAM_AGC_KI__A, data, 0);
4971 			if (rc != 0) {
4972 				pr_err("error %d\n", rc);
4973 				goto rw_error;
4974 			}
4975 
4976 			/* Set speed ( using complementary reduction value ) */
4977 			rc = (*scu_rr16)(dev_addr, SCU_RAM_AGC_KI_RED__A, &data, 0);
4978 			if (rc != 0) {
4979 				pr_err("error %d\n", rc);
4980 				goto rw_error;
4981 			}
4982 			data &= ~SCU_RAM_AGC_KI_RED_RAGC_RED__M;
4983 			rc = (*scu_wr16)(dev_addr, SCU_RAM_AGC_KI_RED__A, (~(agc_settings->speed << SCU_RAM_AGC_KI_RED_RAGC_RED__B) & SCU_RAM_AGC_KI_RED_RAGC_RED__M) | data, 0);
4984 			if (rc != 0) {
4985 				pr_err("error %d\n", rc);
4986 				goto rw_error;
4987 			}
4988 
4989 			if (agc_settings->standard == DRX_STANDARD_8VSB)
4990 				p_agc_settings = &(ext_attr->vsb_if_agc_cfg);
4991 			else if (DRXJ_ISQAMSTD(agc_settings->standard))
4992 				p_agc_settings = &(ext_attr->qam_if_agc_cfg);
4993 			else if (DRXJ_ISATVSTD(agc_settings->standard))
4994 				p_agc_settings = &(ext_attr->atv_if_agc_cfg);
4995 			else
4996 				return -EINVAL;
4997 
4998 			/* Set TOP, only if IF-AGC is in AUTO mode */
4999 			if (p_agc_settings->ctrl_mode == DRX_AGC_CTRL_AUTO) {
5000 				rc = (*scu_wr16)(dev_addr, SCU_RAM_AGC_IF_IACCU_HI_TGT_MAX__A, agc_settings->top, 0);
5001 				if (rc != 0) {
5002 					pr_err("error %d\n", rc);
5003 					goto rw_error;
5004 				}
5005 				rc = (*scu_wr16)(dev_addr, SCU_RAM_AGC_IF_IACCU_HI_TGT__A, agc_settings->top, 0);
5006 				if (rc != 0) {
5007 					pr_err("error %d\n", rc);
5008 					goto rw_error;
5009 				}
5010 			}
5011 
5012 			/* Cut-Off current */
5013 			rc = (*scu_wr16)(dev_addr, SCU_RAM_AGC_RF_IACCU_HI_CO__A, agc_settings->cut_off_current, 0);
5014 			if (rc != 0) {
5015 				pr_err("error %d\n", rc);
5016 				goto rw_error;
5017 			}
5018 			break;
5019 		case DRX_AGC_CTRL_USER:
5020 
5021 			/* Enable RF AGC DAC */
5022 			rc = drxj_dap_read_reg16(dev_addr, IQM_AF_STDBY__A, &data, 0);
5023 			if (rc != 0) {
5024 				pr_err("error %d\n", rc);
5025 				goto rw_error;
5026 			}
5027 			data |= IQM_AF_STDBY_STDBY_TAGC_RF_A2_ACTIVE;
5028 			rc = drxj_dap_write_reg16(dev_addr, IQM_AF_STDBY__A, data, 0);
5029 			if (rc != 0) {
5030 				pr_err("error %d\n", rc);
5031 				goto rw_error;
5032 			}
5033 
5034 			/* Disable SCU RF AGC loop */
5035 			rc = (*scu_rr16)(dev_addr, SCU_RAM_AGC_KI__A, &data, 0);
5036 			if (rc != 0) {
5037 				pr_err("error %d\n", rc);
5038 				goto rw_error;
5039 			}
5040 			data &= ~SCU_RAM_AGC_KI_RF__M;
5041 			if (common_attr->tuner_rf_agc_pol)
5042 				data |= SCU_RAM_AGC_KI_INV_RF_POL__M;
5043 			else
5044 				data &= ~SCU_RAM_AGC_KI_INV_RF_POL__M;
5045 			rc = (*scu_wr16)(dev_addr, SCU_RAM_AGC_KI__A, data, 0);
5046 			if (rc != 0) {
5047 				pr_err("error %d\n", rc);
5048 				goto rw_error;
5049 			}
5050 
5051 			/* Write value to output pin */
5052 			rc = (*scu_wr16)(dev_addr, SCU_RAM_AGC_RF_IACCU_HI__A, agc_settings->output_level, 0);
5053 			if (rc != 0) {
5054 				pr_err("error %d\n", rc);
5055 				goto rw_error;
5056 			}
5057 			break;
5058 		case DRX_AGC_CTRL_OFF:
5059 
5060 			/* Disable RF AGC DAC */
5061 			rc = drxj_dap_read_reg16(dev_addr, IQM_AF_STDBY__A, &data, 0);
5062 			if (rc != 0) {
5063 				pr_err("error %d\n", rc);
5064 				goto rw_error;
5065 			}
5066 			data &= (~IQM_AF_STDBY_STDBY_TAGC_RF_A2_ACTIVE);
5067 			rc = drxj_dap_write_reg16(dev_addr, IQM_AF_STDBY__A, data, 0);
5068 			if (rc != 0) {
5069 				pr_err("error %d\n", rc);
5070 				goto rw_error;
5071 			}
5072 
5073 			/* Disable SCU RF AGC loop */
5074 			rc = (*scu_rr16)(dev_addr, SCU_RAM_AGC_KI__A, &data, 0);
5075 			if (rc != 0) {
5076 				pr_err("error %d\n", rc);
5077 				goto rw_error;
5078 			}
5079 			data &= ~SCU_RAM_AGC_KI_RF__M;
5080 			rc = (*scu_wr16)(dev_addr, SCU_RAM_AGC_KI__A, data, 0);
5081 			if (rc != 0) {
5082 				pr_err("error %d\n", rc);
5083 				goto rw_error;
5084 			}
5085 			break;
5086 		default:
5087 			return -EINVAL;
5088 		}		/* switch ( agcsettings->ctrl_mode ) */
5089 	}
5090 
5091 	/* Store rf agc settings */
5092 	switch (agc_settings->standard) {
5093 	case DRX_STANDARD_8VSB:
5094 		ext_attr->vsb_rf_agc_cfg = *agc_settings;
5095 		break;
5096 #ifndef DRXJ_VSB_ONLY
5097 	case DRX_STANDARD_ITU_A:
5098 	case DRX_STANDARD_ITU_B:
5099 	case DRX_STANDARD_ITU_C:
5100 		ext_attr->qam_rf_agc_cfg = *agc_settings;
5101 		break;
5102 #endif
5103 	default:
5104 		return -EIO;
5105 	}
5106 
5107 	return 0;
5108 rw_error:
5109 	return rc;
5110 }
5111 
5112 /*
5113 * \fn int set_agc_if ()
5114 * \brief Configure If AGC
5115 * \param demod instance of demodulator.
5116 * \param agc_settings AGC configuration structure
5117 * \return int.
5118 */
5119 static int
5120 set_agc_if(struct drx_demod_instance *demod, struct drxj_cfg_agc *agc_settings, bool atomic)
5121 {
5122 	struct i2c_device_addr *dev_addr = NULL;
5123 	struct drxj_data *ext_attr = NULL;
5124 	struct drxj_cfg_agc *p_agc_settings = NULL;
5125 	struct drx_common_attr *common_attr = NULL;
5126 	drx_write_reg16func_t scu_wr16 = NULL;
5127 	drx_read_reg16func_t scu_rr16 = NULL;
5128 	int rc;
5129 
5130 	common_attr = (struct drx_common_attr *) demod->my_common_attr;
5131 	dev_addr = demod->my_i2c_dev_addr;
5132 	ext_attr = (struct drxj_data *) demod->my_ext_attr;
5133 
5134 	if (atomic) {
5135 		scu_rr16 = drxj_dap_scu_atomic_read_reg16;
5136 		scu_wr16 = drxj_dap_scu_atomic_write_reg16;
5137 	} else {
5138 		scu_rr16 = drxj_dap_read_reg16;
5139 		scu_wr16 = drxj_dap_write_reg16;
5140 	}
5141 
5142 	/* Configure AGC only if standard is currently active */
5143 	if ((ext_attr->standard == agc_settings->standard) ||
5144 	    (DRXJ_ISQAMSTD(ext_attr->standard) &&
5145 	     DRXJ_ISQAMSTD(agc_settings->standard)) ||
5146 	    (DRXJ_ISATVSTD(ext_attr->standard) &&
5147 	     DRXJ_ISATVSTD(agc_settings->standard))) {
5148 		u16 data = 0;
5149 
5150 		switch (agc_settings->ctrl_mode) {
5151 		case DRX_AGC_CTRL_AUTO:
5152 			/* Enable IF AGC DAC */
5153 			rc = drxj_dap_read_reg16(dev_addr, IQM_AF_STDBY__A, &data, 0);
5154 			if (rc != 0) {
5155 				pr_err("error %d\n", rc);
5156 				goto rw_error;
5157 			}
5158 			data |= IQM_AF_STDBY_STDBY_TAGC_IF_A2_ACTIVE;
5159 			rc = drxj_dap_write_reg16(dev_addr, IQM_AF_STDBY__A, data, 0);
5160 			if (rc != 0) {
5161 				pr_err("error %d\n", rc);
5162 				goto rw_error;
5163 			}
5164 
5165 			/* Enable SCU IF AGC loop */
5166 			rc = (*scu_rr16)(dev_addr, SCU_RAM_AGC_KI__A, &data, 0);
5167 			if (rc != 0) {
5168 				pr_err("error %d\n", rc);
5169 				goto rw_error;
5170 			}
5171 			data &= ~SCU_RAM_AGC_KI_IF_AGC_DISABLE__M;
5172 			data &= ~SCU_RAM_AGC_KI_IF__M;
5173 			if (ext_attr->standard == DRX_STANDARD_8VSB)
5174 				data |= (3 << SCU_RAM_AGC_KI_IF__B);
5175 			else if (DRXJ_ISQAMSTD(ext_attr->standard))
5176 				data |= (6 << SCU_RAM_AGC_KI_IF__B);
5177 			else
5178 				data |= (5 << SCU_RAM_AGC_KI_IF__B);
5179 
5180 			if (common_attr->tuner_if_agc_pol)
5181 				data |= SCU_RAM_AGC_KI_INV_IF_POL__M;
5182 			else
5183 				data &= ~SCU_RAM_AGC_KI_INV_IF_POL__M;
5184 			rc = (*scu_wr16)(dev_addr, SCU_RAM_AGC_KI__A, data, 0);
5185 			if (rc != 0) {
5186 				pr_err("error %d\n", rc);
5187 				goto rw_error;
5188 			}
5189 
5190 			/* Set speed (using complementary reduction value) */
5191 			rc = (*scu_rr16)(dev_addr, SCU_RAM_AGC_KI_RED__A, &data, 0);
5192 			if (rc != 0) {
5193 				pr_err("error %d\n", rc);
5194 				goto rw_error;
5195 			}
5196 			data &= ~SCU_RAM_AGC_KI_RED_IAGC_RED__M;
5197 			rc = (*scu_wr16) (dev_addr, SCU_RAM_AGC_KI_RED__A, (~(agc_settings->speed << SCU_RAM_AGC_KI_RED_IAGC_RED__B) & SCU_RAM_AGC_KI_RED_IAGC_RED__M) | data, 0);
5198 			if (rc != 0) {
5199 				pr_err("error %d\n", rc);
5200 				goto rw_error;
5201 			}
5202 
5203 			if (agc_settings->standard == DRX_STANDARD_8VSB)
5204 				p_agc_settings = &(ext_attr->vsb_rf_agc_cfg);
5205 			else if (DRXJ_ISQAMSTD(agc_settings->standard))
5206 				p_agc_settings = &(ext_attr->qam_rf_agc_cfg);
5207 			else if (DRXJ_ISATVSTD(agc_settings->standard))
5208 				p_agc_settings = &(ext_attr->atv_rf_agc_cfg);
5209 			else
5210 				return -EINVAL;
5211 
5212 			/* Restore TOP */
5213 			if (p_agc_settings->ctrl_mode == DRX_AGC_CTRL_AUTO) {
5214 				rc = (*scu_wr16)(dev_addr, SCU_RAM_AGC_IF_IACCU_HI_TGT_MAX__A, p_agc_settings->top, 0);
5215 				if (rc != 0) {
5216 					pr_err("error %d\n", rc);
5217 					goto rw_error;
5218 				}
5219 				rc = (*scu_wr16)(dev_addr, SCU_RAM_AGC_IF_IACCU_HI_TGT__A, p_agc_settings->top, 0);
5220 				if (rc != 0) {
5221 					pr_err("error %d\n", rc);
5222 					goto rw_error;
5223 				}
5224 			} else {
5225 				rc = (*scu_wr16)(dev_addr, SCU_RAM_AGC_IF_IACCU_HI_TGT_MAX__A, 0, 0);
5226 				if (rc != 0) {
5227 					pr_err("error %d\n", rc);
5228 					goto rw_error;
5229 				}
5230 				rc = (*scu_wr16)(dev_addr, SCU_RAM_AGC_IF_IACCU_HI_TGT__A, 0, 0);
5231 				if (rc != 0) {
5232 					pr_err("error %d\n", rc);
5233 					goto rw_error;
5234 				}
5235 			}
5236 			break;
5237 
5238 		case DRX_AGC_CTRL_USER:
5239 
5240 			/* Enable IF AGC DAC */
5241 			rc = drxj_dap_read_reg16(dev_addr, IQM_AF_STDBY__A, &data, 0);
5242 			if (rc != 0) {
5243 				pr_err("error %d\n", rc);
5244 				goto rw_error;
5245 			}
5246 			data |= IQM_AF_STDBY_STDBY_TAGC_IF_A2_ACTIVE;
5247 			rc = drxj_dap_write_reg16(dev_addr, IQM_AF_STDBY__A, data, 0);
5248 			if (rc != 0) {
5249 				pr_err("error %d\n", rc);
5250 				goto rw_error;
5251 			}
5252 
5253 			/* Disable SCU IF AGC loop */
5254 			rc = (*scu_rr16)(dev_addr, SCU_RAM_AGC_KI__A, &data, 0);
5255 			if (rc != 0) {
5256 				pr_err("error %d\n", rc);
5257 				goto rw_error;
5258 			}
5259 			data &= ~SCU_RAM_AGC_KI_IF_AGC_DISABLE__M;
5260 			data |= SCU_RAM_AGC_KI_IF_AGC_DISABLE__M;
5261 			if (common_attr->tuner_if_agc_pol)
5262 				data |= SCU_RAM_AGC_KI_INV_IF_POL__M;
5263 			else
5264 				data &= ~SCU_RAM_AGC_KI_INV_IF_POL__M;
5265 			rc = (*scu_wr16)(dev_addr, SCU_RAM_AGC_KI__A, data, 0);
5266 			if (rc != 0) {
5267 				pr_err("error %d\n", rc);
5268 				goto rw_error;
5269 			}
5270 
5271 			/* Write value to output pin */
5272 			rc = (*scu_wr16)(dev_addr, SCU_RAM_AGC_IF_IACCU_HI_TGT_MAX__A, agc_settings->output_level, 0);
5273 			if (rc != 0) {
5274 				pr_err("error %d\n", rc);
5275 				goto rw_error;
5276 			}
5277 			break;
5278 
5279 		case DRX_AGC_CTRL_OFF:
5280 
5281 			/* Disable If AGC DAC */
5282 			rc = drxj_dap_read_reg16(dev_addr, IQM_AF_STDBY__A, &data, 0);
5283 			if (rc != 0) {
5284 				pr_err("error %d\n", rc);
5285 				goto rw_error;
5286 			}
5287 			data &= (~IQM_AF_STDBY_STDBY_TAGC_IF_A2_ACTIVE);
5288 			rc = drxj_dap_write_reg16(dev_addr, IQM_AF_STDBY__A, data, 0);
5289 			if (rc != 0) {
5290 				pr_err("error %d\n", rc);
5291 				goto rw_error;
5292 			}
5293 
5294 			/* Disable SCU IF AGC loop */
5295 			rc = (*scu_rr16)(dev_addr, SCU_RAM_AGC_KI__A, &data, 0);
5296 			if (rc != 0) {
5297 				pr_err("error %d\n", rc);
5298 				goto rw_error;
5299 			}
5300 			data &= ~SCU_RAM_AGC_KI_IF_AGC_DISABLE__M;
5301 			data |= SCU_RAM_AGC_KI_IF_AGC_DISABLE__M;
5302 			rc = (*scu_wr16)(dev_addr, SCU_RAM_AGC_KI__A, data, 0);
5303 			if (rc != 0) {
5304 				pr_err("error %d\n", rc);
5305 				goto rw_error;
5306 			}
5307 			break;
5308 		default:
5309 			return -EINVAL;
5310 		}		/* switch ( agcsettings->ctrl_mode ) */
5311 
5312 		/* always set the top to support configurations without if-loop */
5313 		rc = (*scu_wr16) (dev_addr, SCU_RAM_AGC_INGAIN_TGT_MIN__A, agc_settings->top, 0);
5314 		if (rc != 0) {
5315 			pr_err("error %d\n", rc);
5316 			goto rw_error;
5317 		}
5318 	}
5319 
5320 	/* Store if agc settings */
5321 	switch (agc_settings->standard) {
5322 	case DRX_STANDARD_8VSB:
5323 		ext_attr->vsb_if_agc_cfg = *agc_settings;
5324 		break;
5325 #ifndef DRXJ_VSB_ONLY
5326 	case DRX_STANDARD_ITU_A:
5327 	case DRX_STANDARD_ITU_B:
5328 	case DRX_STANDARD_ITU_C:
5329 		ext_attr->qam_if_agc_cfg = *agc_settings;
5330 		break;
5331 #endif
5332 	default:
5333 		return -EIO;
5334 	}
5335 
5336 	return 0;
5337 rw_error:
5338 	return rc;
5339 }
5340 
5341 /*
5342 * \fn int set_iqm_af ()
5343 * \brief Configure IQM AF registers
5344 * \param demod instance of demodulator.
5345 * \param active
5346 * \return int.
5347 */
5348 static int set_iqm_af(struct drx_demod_instance *demod, bool active)
5349 {
5350 	u16 data = 0;
5351 	struct i2c_device_addr *dev_addr = NULL;
5352 	int rc;
5353 
5354 	dev_addr = demod->my_i2c_dev_addr;
5355 
5356 	/* Configure IQM */
5357 	rc = drxj_dap_read_reg16(dev_addr, IQM_AF_STDBY__A, &data, 0);
5358 	if (rc != 0) {
5359 		pr_err("error %d\n", rc);
5360 		goto rw_error;
5361 	}
5362 	if (!active)
5363 		data &= ((~IQM_AF_STDBY_STDBY_ADC_A2_ACTIVE) & (~IQM_AF_STDBY_STDBY_AMP_A2_ACTIVE) & (~IQM_AF_STDBY_STDBY_PD_A2_ACTIVE) & (~IQM_AF_STDBY_STDBY_TAGC_IF_A2_ACTIVE) & (~IQM_AF_STDBY_STDBY_TAGC_RF_A2_ACTIVE));
5364 	else
5365 		data |= (IQM_AF_STDBY_STDBY_ADC_A2_ACTIVE | IQM_AF_STDBY_STDBY_AMP_A2_ACTIVE | IQM_AF_STDBY_STDBY_PD_A2_ACTIVE | IQM_AF_STDBY_STDBY_TAGC_IF_A2_ACTIVE | IQM_AF_STDBY_STDBY_TAGC_RF_A2_ACTIVE);
5366 	rc = drxj_dap_write_reg16(dev_addr, IQM_AF_STDBY__A, data, 0);
5367 	if (rc != 0) {
5368 		pr_err("error %d\n", rc);
5369 		goto rw_error;
5370 	}
5371 
5372 	return 0;
5373 rw_error:
5374 	return rc;
5375 }
5376 
5377 /*============================================================================*/
5378 /*==              END 8VSB & QAM COMMON DATAPATH FUNCTIONS                  ==*/
5379 /*============================================================================*/
5380 
5381 /*============================================================================*/
5382 /*============================================================================*/
5383 /*==                       8VSB DATAPATH FUNCTIONS                          ==*/
5384 /*============================================================================*/
5385 /*============================================================================*/
5386 
5387 /*
5388 * \fn int power_down_vsb ()
5389 * \brief Powr down QAM related blocks.
5390 * \param demod instance of demodulator.
5391 * \param channel pointer to channel data.
5392 * \return int.
5393 */
5394 static int power_down_vsb(struct drx_demod_instance *demod, bool primary)
5395 {
5396 	struct i2c_device_addr *dev_addr = demod->my_i2c_dev_addr;
5397 	struct drxjscu_cmd cmd_scu = { /* command     */ 0,
5398 		/* parameter_len */ 0,
5399 		/* result_len    */ 0,
5400 		/* *parameter   */ NULL,
5401 		/* *result      */ NULL
5402 	};
5403 	struct drx_cfg_mpeg_output cfg_mpeg_output;
5404 	int rc;
5405 	u16 cmd_result = 0;
5406 
5407 	/*
5408 	   STOP demodulator
5409 	   reset of FEC and VSB HW
5410 	 */
5411 	cmd_scu.command = SCU_RAM_COMMAND_STANDARD_VSB |
5412 	    SCU_RAM_COMMAND_CMD_DEMOD_STOP;
5413 	cmd_scu.parameter_len = 0;
5414 	cmd_scu.result_len = 1;
5415 	cmd_scu.parameter = NULL;
5416 	cmd_scu.result = &cmd_result;
5417 	rc = scu_command(dev_addr, &cmd_scu);
5418 	if (rc != 0) {
5419 		pr_err("error %d\n", rc);
5420 		goto rw_error;
5421 	}
5422 
5423 	/* stop all comm_exec */
5424 	rc = drxj_dap_write_reg16(dev_addr, FEC_COMM_EXEC__A, FEC_COMM_EXEC_STOP, 0);
5425 	if (rc != 0) {
5426 		pr_err("error %d\n", rc);
5427 		goto rw_error;
5428 	}
5429 	rc = drxj_dap_write_reg16(dev_addr, VSB_COMM_EXEC__A, VSB_COMM_EXEC_STOP, 0);
5430 	if (rc != 0) {
5431 		pr_err("error %d\n", rc);
5432 		goto rw_error;
5433 	}
5434 	if (primary) {
5435 		rc = drxj_dap_write_reg16(dev_addr, IQM_COMM_EXEC__A, IQM_COMM_EXEC_STOP, 0);
5436 		if (rc != 0) {
5437 			pr_err("error %d\n", rc);
5438 			goto rw_error;
5439 		}
5440 		rc = set_iqm_af(demod, false);
5441 		if (rc != 0) {
5442 			pr_err("error %d\n", rc);
5443 			goto rw_error;
5444 		}
5445 	} else {
5446 		rc = drxj_dap_write_reg16(dev_addr, IQM_FS_COMM_EXEC__A, IQM_FS_COMM_EXEC_STOP, 0);
5447 		if (rc != 0) {
5448 			pr_err("error %d\n", rc);
5449 			goto rw_error;
5450 		}
5451 		rc = drxj_dap_write_reg16(dev_addr, IQM_FD_COMM_EXEC__A, IQM_FD_COMM_EXEC_STOP, 0);
5452 		if (rc != 0) {
5453 			pr_err("error %d\n", rc);
5454 			goto rw_error;
5455 		}
5456 		rc = drxj_dap_write_reg16(dev_addr, IQM_RC_COMM_EXEC__A, IQM_RC_COMM_EXEC_STOP, 0);
5457 		if (rc != 0) {
5458 			pr_err("error %d\n", rc);
5459 			goto rw_error;
5460 		}
5461 		rc = drxj_dap_write_reg16(dev_addr, IQM_RT_COMM_EXEC__A, IQM_RT_COMM_EXEC_STOP, 0);
5462 		if (rc != 0) {
5463 			pr_err("error %d\n", rc);
5464 			goto rw_error;
5465 		}
5466 		rc = drxj_dap_write_reg16(dev_addr, IQM_CF_COMM_EXEC__A, IQM_CF_COMM_EXEC_STOP, 0);
5467 		if (rc != 0) {
5468 			pr_err("error %d\n", rc);
5469 			goto rw_error;
5470 		}
5471 	}
5472 
5473 	cfg_mpeg_output.enable_mpeg_output = false;
5474 	rc = ctrl_set_cfg_mpeg_output(demod, &cfg_mpeg_output);
5475 	if (rc != 0) {
5476 		pr_err("error %d\n", rc);
5477 		goto rw_error;
5478 	}
5479 
5480 	return 0;
5481 rw_error:
5482 	return rc;
5483 }
5484 
5485 /*
5486 * \fn int set_vsb_leak_n_gain ()
5487 * \brief Set ATSC demod.
5488 * \param demod instance of demodulator.
5489 * \return int.
5490 */
5491 static int set_vsb_leak_n_gain(struct drx_demod_instance *demod)
5492 {
5493 	struct i2c_device_addr *dev_addr = NULL;
5494 	int rc;
5495 
5496 	static const u8 vsb_ffe_leak_gain_ram0[] = {
5497 		DRXJ_16TO8(0x8),	/* FFETRAINLKRATIO1  */
5498 		DRXJ_16TO8(0x8),	/* FFETRAINLKRATIO2  */
5499 		DRXJ_16TO8(0x8),	/* FFETRAINLKRATIO3  */
5500 		DRXJ_16TO8(0xf),	/* FFETRAINLKRATIO4  */
5501 		DRXJ_16TO8(0xf),	/* FFETRAINLKRATIO5  */
5502 		DRXJ_16TO8(0xf),	/* FFETRAINLKRATIO6  */
5503 		DRXJ_16TO8(0xf),	/* FFETRAINLKRATIO7  */
5504 		DRXJ_16TO8(0xf),	/* FFETRAINLKRATIO8  */
5505 		DRXJ_16TO8(0xf),	/* FFETRAINLKRATIO9  */
5506 		DRXJ_16TO8(0x8),	/* FFETRAINLKRATIO10  */
5507 		DRXJ_16TO8(0x8),	/* FFETRAINLKRATIO11 */
5508 		DRXJ_16TO8(0x8),	/* FFETRAINLKRATIO12 */
5509 		DRXJ_16TO8(0x10),	/* FFERCA1TRAINLKRATIO1 */
5510 		DRXJ_16TO8(0x10),	/* FFERCA1TRAINLKRATIO2 */
5511 		DRXJ_16TO8(0x10),	/* FFERCA1TRAINLKRATIO3 */
5512 		DRXJ_16TO8(0x20),	/* FFERCA1TRAINLKRATIO4 */
5513 		DRXJ_16TO8(0x20),	/* FFERCA1TRAINLKRATIO5 */
5514 		DRXJ_16TO8(0x20),	/* FFERCA1TRAINLKRATIO6 */
5515 		DRXJ_16TO8(0x20),	/* FFERCA1TRAINLKRATIO7 */
5516 		DRXJ_16TO8(0x20),	/* FFERCA1TRAINLKRATIO8 */
5517 		DRXJ_16TO8(0x20),	/* FFERCA1TRAINLKRATIO9 */
5518 		DRXJ_16TO8(0x10),	/* FFERCA1TRAINLKRATIO10 */
5519 		DRXJ_16TO8(0x10),	/* FFERCA1TRAINLKRATIO11 */
5520 		DRXJ_16TO8(0x10),	/* FFERCA1TRAINLKRATIO12 */
5521 		DRXJ_16TO8(0x10),	/* FFERCA1DATALKRATIO1 */
5522 		DRXJ_16TO8(0x10),	/* FFERCA1DATALKRATIO2 */
5523 		DRXJ_16TO8(0x10),	/* FFERCA1DATALKRATIO3 */
5524 		DRXJ_16TO8(0x20),	/* FFERCA1DATALKRATIO4 */
5525 		DRXJ_16TO8(0x20),	/* FFERCA1DATALKRATIO5 */
5526 		DRXJ_16TO8(0x20),	/* FFERCA1DATALKRATIO6 */
5527 		DRXJ_16TO8(0x20),	/* FFERCA1DATALKRATIO7 */
5528 		DRXJ_16TO8(0x20),	/* FFERCA1DATALKRATIO8 */
5529 		DRXJ_16TO8(0x20),	/* FFERCA1DATALKRATIO9 */
5530 		DRXJ_16TO8(0x10),	/* FFERCA1DATALKRATIO10 */
5531 		DRXJ_16TO8(0x10),	/* FFERCA1DATALKRATIO11 */
5532 		DRXJ_16TO8(0x10),	/* FFERCA1DATALKRATIO12 */
5533 		DRXJ_16TO8(0x10),	/* FFERCA2TRAINLKRATIO1 */
5534 		DRXJ_16TO8(0x10),	/* FFERCA2TRAINLKRATIO2 */
5535 		DRXJ_16TO8(0x10),	/* FFERCA2TRAINLKRATIO3 */
5536 		DRXJ_16TO8(0x20),	/* FFERCA2TRAINLKRATIO4 */
5537 		DRXJ_16TO8(0x20),	/* FFERCA2TRAINLKRATIO5 */
5538 		DRXJ_16TO8(0x20),	/* FFERCA2TRAINLKRATIO6 */
5539 		DRXJ_16TO8(0x20),	/* FFERCA2TRAINLKRATIO7 */
5540 		DRXJ_16TO8(0x20),	/* FFERCA2TRAINLKRATIO8 */
5541 		DRXJ_16TO8(0x20),	/* FFERCA2TRAINLKRATIO9 */
5542 		DRXJ_16TO8(0x10),	/* FFERCA2TRAINLKRATIO10 */
5543 		DRXJ_16TO8(0x10),	/* FFERCA2TRAINLKRATIO11 */
5544 		DRXJ_16TO8(0x10),	/* FFERCA2TRAINLKRATIO12 */
5545 		DRXJ_16TO8(0x10),	/* FFERCA2DATALKRATIO1 */
5546 		DRXJ_16TO8(0x10),	/* FFERCA2DATALKRATIO2 */
5547 		DRXJ_16TO8(0x10),	/* FFERCA2DATALKRATIO3 */
5548 		DRXJ_16TO8(0x20),	/* FFERCA2DATALKRATIO4 */
5549 		DRXJ_16TO8(0x20),	/* FFERCA2DATALKRATIO5 */
5550 		DRXJ_16TO8(0x20),	/* FFERCA2DATALKRATIO6 */
5551 		DRXJ_16TO8(0x20),	/* FFERCA2DATALKRATIO7 */
5552 		DRXJ_16TO8(0x20),	/* FFERCA2DATALKRATIO8 */
5553 		DRXJ_16TO8(0x20),	/* FFERCA2DATALKRATIO9 */
5554 		DRXJ_16TO8(0x10),	/* FFERCA2DATALKRATIO10 */
5555 		DRXJ_16TO8(0x10),	/* FFERCA2DATALKRATIO11 */
5556 		DRXJ_16TO8(0x10),	/* FFERCA2DATALKRATIO12 */
5557 		DRXJ_16TO8(0x07),	/* FFEDDM1TRAINLKRATIO1 */
5558 		DRXJ_16TO8(0x07),	/* FFEDDM1TRAINLKRATIO2 */
5559 		DRXJ_16TO8(0x07),	/* FFEDDM1TRAINLKRATIO3 */
5560 		DRXJ_16TO8(0x0e),	/* FFEDDM1TRAINLKRATIO4 */
5561 		DRXJ_16TO8(0x0e),	/* FFEDDM1TRAINLKRATIO5 */
5562 		DRXJ_16TO8(0x0e),	/* FFEDDM1TRAINLKRATIO6 */
5563 		DRXJ_16TO8(0x0e),	/* FFEDDM1TRAINLKRATIO7 */
5564 		DRXJ_16TO8(0x0e),	/* FFEDDM1TRAINLKRATIO8 */
5565 		DRXJ_16TO8(0x0e),	/* FFEDDM1TRAINLKRATIO9 */
5566 		DRXJ_16TO8(0x07),	/* FFEDDM1TRAINLKRATIO10 */
5567 		DRXJ_16TO8(0x07),	/* FFEDDM1TRAINLKRATIO11 */
5568 		DRXJ_16TO8(0x07),	/* FFEDDM1TRAINLKRATIO12 */
5569 		DRXJ_16TO8(0x07),	/* FFEDDM1DATALKRATIO1 */
5570 		DRXJ_16TO8(0x07),	/* FFEDDM1DATALKRATIO2 */
5571 		DRXJ_16TO8(0x07),	/* FFEDDM1DATALKRATIO3 */
5572 		DRXJ_16TO8(0x0e),	/* FFEDDM1DATALKRATIO4 */
5573 		DRXJ_16TO8(0x0e),	/* FFEDDM1DATALKRATIO5 */
5574 		DRXJ_16TO8(0x0e),	/* FFEDDM1DATALKRATIO6 */
5575 		DRXJ_16TO8(0x0e),	/* FFEDDM1DATALKRATIO7 */
5576 		DRXJ_16TO8(0x0e),	/* FFEDDM1DATALKRATIO8 */
5577 		DRXJ_16TO8(0x0e),	/* FFEDDM1DATALKRATIO9 */
5578 		DRXJ_16TO8(0x07),	/* FFEDDM1DATALKRATIO10 */
5579 		DRXJ_16TO8(0x07),	/* FFEDDM1DATALKRATIO11 */
5580 		DRXJ_16TO8(0x07),	/* FFEDDM1DATALKRATIO12 */
5581 		DRXJ_16TO8(0x06),	/* FFEDDM2TRAINLKRATIO1 */
5582 		DRXJ_16TO8(0x06),	/* FFEDDM2TRAINLKRATIO2 */
5583 		DRXJ_16TO8(0x06),	/* FFEDDM2TRAINLKRATIO3 */
5584 		DRXJ_16TO8(0x0c),	/* FFEDDM2TRAINLKRATIO4 */
5585 		DRXJ_16TO8(0x0c),	/* FFEDDM2TRAINLKRATIO5 */
5586 		DRXJ_16TO8(0x0c),	/* FFEDDM2TRAINLKRATIO6 */
5587 		DRXJ_16TO8(0x0c),	/* FFEDDM2TRAINLKRATIO7 */
5588 		DRXJ_16TO8(0x0c),	/* FFEDDM2TRAINLKRATIO8 */
5589 		DRXJ_16TO8(0x0c),	/* FFEDDM2TRAINLKRATIO9 */
5590 		DRXJ_16TO8(0x06),	/* FFEDDM2TRAINLKRATIO10 */
5591 		DRXJ_16TO8(0x06),	/* FFEDDM2TRAINLKRATIO11 */
5592 		DRXJ_16TO8(0x06),	/* FFEDDM2TRAINLKRATIO12 */
5593 		DRXJ_16TO8(0x06),	/* FFEDDM2DATALKRATIO1 */
5594 		DRXJ_16TO8(0x06),	/* FFEDDM2DATALKRATIO2 */
5595 		DRXJ_16TO8(0x06),	/* FFEDDM2DATALKRATIO3 */
5596 		DRXJ_16TO8(0x0c),	/* FFEDDM2DATALKRATIO4 */
5597 		DRXJ_16TO8(0x0c),	/* FFEDDM2DATALKRATIO5 */
5598 		DRXJ_16TO8(0x0c),	/* FFEDDM2DATALKRATIO6 */
5599 		DRXJ_16TO8(0x0c),	/* FFEDDM2DATALKRATIO7 */
5600 		DRXJ_16TO8(0x0c),	/* FFEDDM2DATALKRATIO8 */
5601 		DRXJ_16TO8(0x0c),	/* FFEDDM2DATALKRATIO9 */
5602 		DRXJ_16TO8(0x06),	/* FFEDDM2DATALKRATIO10 */
5603 		DRXJ_16TO8(0x06),	/* FFEDDM2DATALKRATIO11 */
5604 		DRXJ_16TO8(0x06),	/* FFEDDM2DATALKRATIO12 */
5605 		DRXJ_16TO8(0x2020),	/* FIRTRAINGAIN1 */
5606 		DRXJ_16TO8(0x2020),	/* FIRTRAINGAIN2 */
5607 		DRXJ_16TO8(0x2020),	/* FIRTRAINGAIN3 */
5608 		DRXJ_16TO8(0x4040),	/* FIRTRAINGAIN4 */
5609 		DRXJ_16TO8(0x4040),	/* FIRTRAINGAIN5 */
5610 		DRXJ_16TO8(0x4040),	/* FIRTRAINGAIN6 */
5611 		DRXJ_16TO8(0x4040),	/* FIRTRAINGAIN7 */
5612 		DRXJ_16TO8(0x4040),	/* FIRTRAINGAIN8 */
5613 		DRXJ_16TO8(0x4040),	/* FIRTRAINGAIN9 */
5614 		DRXJ_16TO8(0x2020),	/* FIRTRAINGAIN10 */
5615 		DRXJ_16TO8(0x2020),	/* FIRTRAINGAIN11 */
5616 		DRXJ_16TO8(0x2020),	/* FIRTRAINGAIN12 */
5617 		DRXJ_16TO8(0x0808),	/* FIRRCA1GAIN1 */
5618 		DRXJ_16TO8(0x0808),	/* FIRRCA1GAIN2 */
5619 		DRXJ_16TO8(0x0808),	/* FIRRCA1GAIN3 */
5620 		DRXJ_16TO8(0x1010),	/* FIRRCA1GAIN4 */
5621 		DRXJ_16TO8(0x1010),	/* FIRRCA1GAIN5 */
5622 		DRXJ_16TO8(0x1010),	/* FIRRCA1GAIN6 */
5623 		DRXJ_16TO8(0x1010),	/* FIRRCA1GAIN7 */
5624 		DRXJ_16TO8(0x1010)	/* FIRRCA1GAIN8 */
5625 	};
5626 
5627 	static const u8 vsb_ffe_leak_gain_ram1[] = {
5628 		DRXJ_16TO8(0x1010),	/* FIRRCA1GAIN9 */
5629 		DRXJ_16TO8(0x0808),	/* FIRRCA1GAIN10 */
5630 		DRXJ_16TO8(0x0808),	/* FIRRCA1GAIN11 */
5631 		DRXJ_16TO8(0x0808),	/* FIRRCA1GAIN12 */
5632 		DRXJ_16TO8(0x0808),	/* FIRRCA2GAIN1 */
5633 		DRXJ_16TO8(0x0808),	/* FIRRCA2GAIN2 */
5634 		DRXJ_16TO8(0x0808),	/* FIRRCA2GAIN3 */
5635 		DRXJ_16TO8(0x1010),	/* FIRRCA2GAIN4 */
5636 		DRXJ_16TO8(0x1010),	/* FIRRCA2GAIN5 */
5637 		DRXJ_16TO8(0x1010),	/* FIRRCA2GAIN6 */
5638 		DRXJ_16TO8(0x1010),	/* FIRRCA2GAIN7 */
5639 		DRXJ_16TO8(0x1010),	/* FIRRCA2GAIN8 */
5640 		DRXJ_16TO8(0x1010),	/* FIRRCA2GAIN9 */
5641 		DRXJ_16TO8(0x0808),	/* FIRRCA2GAIN10 */
5642 		DRXJ_16TO8(0x0808),	/* FIRRCA2GAIN11 */
5643 		DRXJ_16TO8(0x0808),	/* FIRRCA2GAIN12 */
5644 		DRXJ_16TO8(0x0303),	/* FIRDDM1GAIN1 */
5645 		DRXJ_16TO8(0x0303),	/* FIRDDM1GAIN2 */
5646 		DRXJ_16TO8(0x0303),	/* FIRDDM1GAIN3 */
5647 		DRXJ_16TO8(0x0606),	/* FIRDDM1GAIN4 */
5648 		DRXJ_16TO8(0x0606),	/* FIRDDM1GAIN5 */
5649 		DRXJ_16TO8(0x0606),	/* FIRDDM1GAIN6 */
5650 		DRXJ_16TO8(0x0606),	/* FIRDDM1GAIN7 */
5651 		DRXJ_16TO8(0x0606),	/* FIRDDM1GAIN8 */
5652 		DRXJ_16TO8(0x0606),	/* FIRDDM1GAIN9 */
5653 		DRXJ_16TO8(0x0303),	/* FIRDDM1GAIN10 */
5654 		DRXJ_16TO8(0x0303),	/* FIRDDM1GAIN11 */
5655 		DRXJ_16TO8(0x0303),	/* FIRDDM1GAIN12 */
5656 		DRXJ_16TO8(0x0303),	/* FIRDDM2GAIN1 */
5657 		DRXJ_16TO8(0x0303),	/* FIRDDM2GAIN2 */
5658 		DRXJ_16TO8(0x0303),	/* FIRDDM2GAIN3 */
5659 		DRXJ_16TO8(0x0505),	/* FIRDDM2GAIN4 */
5660 		DRXJ_16TO8(0x0505),	/* FIRDDM2GAIN5 */
5661 		DRXJ_16TO8(0x0505),	/* FIRDDM2GAIN6 */
5662 		DRXJ_16TO8(0x0505),	/* FIRDDM2GAIN7 */
5663 		DRXJ_16TO8(0x0505),	/* FIRDDM2GAIN8 */
5664 		DRXJ_16TO8(0x0505),	/* FIRDDM2GAIN9 */
5665 		DRXJ_16TO8(0x0303),	/* FIRDDM2GAIN10 */
5666 		DRXJ_16TO8(0x0303),	/* FIRDDM2GAIN11 */
5667 		DRXJ_16TO8(0x0303),	/* FIRDDM2GAIN12 */
5668 		DRXJ_16TO8(0x001f),	/* DFETRAINLKRATIO */
5669 		DRXJ_16TO8(0x01ff),	/* DFERCA1TRAINLKRATIO */
5670 		DRXJ_16TO8(0x01ff),	/* DFERCA1DATALKRATIO */
5671 		DRXJ_16TO8(0x004f),	/* DFERCA2TRAINLKRATIO */
5672 		DRXJ_16TO8(0x004f),	/* DFERCA2DATALKRATIO */
5673 		DRXJ_16TO8(0x01ff),	/* DFEDDM1TRAINLKRATIO */
5674 		DRXJ_16TO8(0x01ff),	/* DFEDDM1DATALKRATIO */
5675 		DRXJ_16TO8(0x0352),	/* DFEDDM2TRAINLKRATIO */
5676 		DRXJ_16TO8(0x0352),	/* DFEDDM2DATALKRATIO */
5677 		DRXJ_16TO8(0x0000),	/* DFETRAINGAIN */
5678 		DRXJ_16TO8(0x2020),	/* DFERCA1GAIN */
5679 		DRXJ_16TO8(0x1010),	/* DFERCA2GAIN */
5680 		DRXJ_16TO8(0x1818),	/* DFEDDM1GAIN */
5681 		DRXJ_16TO8(0x1212)	/* DFEDDM2GAIN */
5682 	};
5683 
5684 	dev_addr = demod->my_i2c_dev_addr;
5685 	rc = drxdap_fasi_write_block(dev_addr, VSB_SYSCTRL_RAM0_FFETRAINLKRATIO1__A, sizeof(vsb_ffe_leak_gain_ram0), ((u8 *)vsb_ffe_leak_gain_ram0), 0);
5686 	if (rc != 0) {
5687 		pr_err("error %d\n", rc);
5688 		goto rw_error;
5689 	}
5690 	rc = drxdap_fasi_write_block(dev_addr, VSB_SYSCTRL_RAM1_FIRRCA1GAIN9__A, sizeof(vsb_ffe_leak_gain_ram1), ((u8 *)vsb_ffe_leak_gain_ram1), 0);
5691 	if (rc != 0) {
5692 		pr_err("error %d\n", rc);
5693 		goto rw_error;
5694 	}
5695 
5696 	return 0;
5697 rw_error:
5698 	return rc;
5699 }
5700 
5701 /*
5702 * \fn int set_vsb()
5703 * \brief Set 8VSB demod.
5704 * \param demod instance of demodulator.
5705 * \return int.
5706 *
5707 */
5708 static int set_vsb(struct drx_demod_instance *demod)
5709 {
5710 	struct i2c_device_addr *dev_addr = NULL;
5711 	int rc;
5712 	struct drx_common_attr *common_attr = NULL;
5713 	struct drxjscu_cmd cmd_scu;
5714 	struct drxj_data *ext_attr = NULL;
5715 	u16 cmd_result = 0;
5716 	u16 cmd_param = 0;
5717 	static const u8 vsb_taps_re[] = {
5718 		DRXJ_16TO8(-2),	/* re0  */
5719 		DRXJ_16TO8(4),	/* re1  */
5720 		DRXJ_16TO8(1),	/* re2  */
5721 		DRXJ_16TO8(-4),	/* re3  */
5722 		DRXJ_16TO8(1),	/* re4  */
5723 		DRXJ_16TO8(4),	/* re5  */
5724 		DRXJ_16TO8(-3),	/* re6  */
5725 		DRXJ_16TO8(-3),	/* re7  */
5726 		DRXJ_16TO8(6),	/* re8  */
5727 		DRXJ_16TO8(1),	/* re9  */
5728 		DRXJ_16TO8(-9),	/* re10 */
5729 		DRXJ_16TO8(3),	/* re11 */
5730 		DRXJ_16TO8(12),	/* re12 */
5731 		DRXJ_16TO8(-9),	/* re13 */
5732 		DRXJ_16TO8(-15),	/* re14 */
5733 		DRXJ_16TO8(17),	/* re15 */
5734 		DRXJ_16TO8(19),	/* re16 */
5735 		DRXJ_16TO8(-29),	/* re17 */
5736 		DRXJ_16TO8(-22),	/* re18 */
5737 		DRXJ_16TO8(45),	/* re19 */
5738 		DRXJ_16TO8(25),	/* re20 */
5739 		DRXJ_16TO8(-70),	/* re21 */
5740 		DRXJ_16TO8(-28),	/* re22 */
5741 		DRXJ_16TO8(111),	/* re23 */
5742 		DRXJ_16TO8(30),	/* re24 */
5743 		DRXJ_16TO8(-201),	/* re25 */
5744 		DRXJ_16TO8(-31),	/* re26 */
5745 		DRXJ_16TO8(629)	/* re27 */
5746 	};
5747 
5748 	dev_addr = demod->my_i2c_dev_addr;
5749 	common_attr = (struct drx_common_attr *) demod->my_common_attr;
5750 	ext_attr = (struct drxj_data *) demod->my_ext_attr;
5751 
5752 	/* stop all comm_exec */
5753 	rc = drxj_dap_write_reg16(dev_addr, FEC_COMM_EXEC__A, FEC_COMM_EXEC_STOP, 0);
5754 	if (rc != 0) {
5755 		pr_err("error %d\n", rc);
5756 		goto rw_error;
5757 	}
5758 	rc = drxj_dap_write_reg16(dev_addr, VSB_COMM_EXEC__A, VSB_COMM_EXEC_STOP, 0);
5759 	if (rc != 0) {
5760 		pr_err("error %d\n", rc);
5761 		goto rw_error;
5762 	}
5763 	rc = drxj_dap_write_reg16(dev_addr, IQM_FS_COMM_EXEC__A, IQM_FS_COMM_EXEC_STOP, 0);
5764 	if (rc != 0) {
5765 		pr_err("error %d\n", rc);
5766 		goto rw_error;
5767 	}
5768 	rc = drxj_dap_write_reg16(dev_addr, IQM_FD_COMM_EXEC__A, IQM_FD_COMM_EXEC_STOP, 0);
5769 	if (rc != 0) {
5770 		pr_err("error %d\n", rc);
5771 		goto rw_error;
5772 	}
5773 	rc = drxj_dap_write_reg16(dev_addr, IQM_RC_COMM_EXEC__A, IQM_RC_COMM_EXEC_STOP, 0);
5774 	if (rc != 0) {
5775 		pr_err("error %d\n", rc);
5776 		goto rw_error;
5777 	}
5778 	rc = drxj_dap_write_reg16(dev_addr, IQM_RT_COMM_EXEC__A, IQM_RT_COMM_EXEC_STOP, 0);
5779 	if (rc != 0) {
5780 		pr_err("error %d\n", rc);
5781 		goto rw_error;
5782 	}
5783 	rc = drxj_dap_write_reg16(dev_addr, IQM_CF_COMM_EXEC__A, IQM_CF_COMM_EXEC_STOP, 0);
5784 	if (rc != 0) {
5785 		pr_err("error %d\n", rc);
5786 		goto rw_error;
5787 	}
5788 
5789 	/* reset demodulator */
5790 	cmd_scu.command = SCU_RAM_COMMAND_STANDARD_VSB
5791 	    | SCU_RAM_COMMAND_CMD_DEMOD_RESET;
5792 	cmd_scu.parameter_len = 0;
5793 	cmd_scu.result_len = 1;
5794 	cmd_scu.parameter = NULL;
5795 	cmd_scu.result = &cmd_result;
5796 	rc = scu_command(dev_addr, &cmd_scu);
5797 	if (rc != 0) {
5798 		pr_err("error %d\n", rc);
5799 		goto rw_error;
5800 	}
5801 
5802 	rc = drxj_dap_write_reg16(dev_addr, IQM_AF_DCF_BYPASS__A, 1, 0);
5803 	if (rc != 0) {
5804 		pr_err("error %d\n", rc);
5805 		goto rw_error;
5806 	}
5807 	rc = drxj_dap_write_reg16(dev_addr, IQM_FS_ADJ_SEL__A, IQM_FS_ADJ_SEL_B_VSB, 0);
5808 	if (rc != 0) {
5809 		pr_err("error %d\n", rc);
5810 		goto rw_error;
5811 	}
5812 	rc = drxj_dap_write_reg16(dev_addr, IQM_RC_ADJ_SEL__A, IQM_RC_ADJ_SEL_B_VSB, 0);
5813 	if (rc != 0) {
5814 		pr_err("error %d\n", rc);
5815 		goto rw_error;
5816 	}
5817 	ext_attr->iqm_rc_rate_ofs = 0x00AD0D79;
5818 	rc = drxdap_fasi_write_reg32(dev_addr, IQM_RC_RATE_OFS_LO__A, ext_attr->iqm_rc_rate_ofs, 0);
5819 	if (rc != 0) {
5820 		pr_err("error %d\n", rc);
5821 		goto rw_error;
5822 	}
5823 	rc = drxj_dap_write_reg16(dev_addr, VSB_TOP_CFAGC_GAINSHIFT__A, 4, 0);
5824 	if (rc != 0) {
5825 		pr_err("error %d\n", rc);
5826 		goto rw_error;
5827 	}
5828 	rc = drxj_dap_write_reg16(dev_addr, VSB_TOP_CYGN1TRK__A, 1, 0);
5829 	if (rc != 0) {
5830 		pr_err("error %d\n", rc);
5831 		goto rw_error;
5832 	}
5833 
5834 	rc = drxj_dap_write_reg16(dev_addr, IQM_RC_CROUT_ENA__A, 1, 0);
5835 	if (rc != 0) {
5836 		pr_err("error %d\n", rc);
5837 		goto rw_error;
5838 	}
5839 	rc = drxj_dap_write_reg16(dev_addr, IQM_RC_STRETCH__A, 28, 0);
5840 	if (rc != 0) {
5841 		pr_err("error %d\n", rc);
5842 		goto rw_error;
5843 	}
5844 	rc = drxj_dap_write_reg16(dev_addr, IQM_RT_ACTIVE__A, 0, 0);
5845 	if (rc != 0) {
5846 		pr_err("error %d\n", rc);
5847 		goto rw_error;
5848 	}
5849 	rc = drxj_dap_write_reg16(dev_addr, IQM_CF_SYMMETRIC__A, 0, 0);
5850 	if (rc != 0) {
5851 		pr_err("error %d\n", rc);
5852 		goto rw_error;
5853 	}
5854 	rc = drxj_dap_write_reg16(dev_addr, IQM_CF_MIDTAP__A, 3, 0);
5855 	if (rc != 0) {
5856 		pr_err("error %d\n", rc);
5857 		goto rw_error;
5858 	}
5859 	rc = drxj_dap_write_reg16(dev_addr, IQM_CF_OUT_ENA__A, IQM_CF_OUT_ENA_VSB__M, 0);
5860 	if (rc != 0) {
5861 		pr_err("error %d\n", rc);
5862 		goto rw_error;
5863 	}
5864 	rc = drxj_dap_write_reg16(dev_addr, IQM_CF_SCALE__A, 1393, 0);
5865 	if (rc != 0) {
5866 		pr_err("error %d\n", rc);
5867 		goto rw_error;
5868 	}
5869 	rc = drxj_dap_write_reg16(dev_addr, IQM_CF_SCALE_SH__A, 0, 0);
5870 	if (rc != 0) {
5871 		pr_err("error %d\n", rc);
5872 		goto rw_error;
5873 	}
5874 	rc = drxj_dap_write_reg16(dev_addr, IQM_CF_POW_MEAS_LEN__A, 1, 0);
5875 	if (rc != 0) {
5876 		pr_err("error %d\n", rc);
5877 		goto rw_error;
5878 	}
5879 
5880 	rc = drxdap_fasi_write_block(dev_addr, IQM_CF_TAP_RE0__A, sizeof(vsb_taps_re), ((u8 *)vsb_taps_re), 0);
5881 	if (rc != 0) {
5882 		pr_err("error %d\n", rc);
5883 		goto rw_error;
5884 	}
5885 	rc = drxdap_fasi_write_block(dev_addr, IQM_CF_TAP_IM0__A, sizeof(vsb_taps_re), ((u8 *)vsb_taps_re), 0);
5886 	if (rc != 0) {
5887 		pr_err("error %d\n", rc);
5888 		goto rw_error;
5889 	}
5890 
5891 	rc = drxj_dap_write_reg16(dev_addr, VSB_TOP_BNTHRESH__A, 330, 0);
5892 	if (rc != 0) {
5893 		pr_err("error %d\n", rc);
5894 		goto rw_error;
5895 	}	/* set higher threshold */
5896 	rc = drxj_dap_write_reg16(dev_addr, VSB_TOP_CLPLASTNUM__A, 90, 0);
5897 	if (rc != 0) {
5898 		pr_err("error %d\n", rc);
5899 		goto rw_error;
5900 	}	/* burst detection on   */
5901 	rc = drxj_dap_write_reg16(dev_addr, VSB_TOP_SNRTH_RCA1__A, 0x0042, 0);
5902 	if (rc != 0) {
5903 		pr_err("error %d\n", rc);
5904 		goto rw_error;
5905 	}	/* drop thresholds by 1 dB */
5906 	rc = drxj_dap_write_reg16(dev_addr, VSB_TOP_SNRTH_RCA2__A, 0x0053, 0);
5907 	if (rc != 0) {
5908 		pr_err("error %d\n", rc);
5909 		goto rw_error;
5910 	}	/* drop thresholds by 2 dB */
5911 	rc = drxj_dap_write_reg16(dev_addr, VSB_TOP_EQCTRL__A, 0x1, 0);
5912 	if (rc != 0) {
5913 		pr_err("error %d\n", rc);
5914 		goto rw_error;
5915 	}	/* cma on               */
5916 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_GPIO__A, 0, 0);
5917 	if (rc != 0) {
5918 		pr_err("error %d\n", rc);
5919 		goto rw_error;
5920 	}	/* GPIO               */
5921 
5922 	/* Initialize the FEC Subsystem */
5923 	rc = drxj_dap_write_reg16(dev_addr, FEC_TOP_ANNEX__A, FEC_TOP_ANNEX_D, 0);
5924 	if (rc != 0) {
5925 		pr_err("error %d\n", rc);
5926 		goto rw_error;
5927 	}
5928 	{
5929 		u16 fec_oc_snc_mode = 0;
5930 		rc = drxj_dap_read_reg16(dev_addr, FEC_OC_SNC_MODE__A, &fec_oc_snc_mode, 0);
5931 		if (rc != 0) {
5932 			pr_err("error %d\n", rc);
5933 			goto rw_error;
5934 		}
5935 		/* output data even when not locked */
5936 		rc = drxj_dap_write_reg16(dev_addr, FEC_OC_SNC_MODE__A, fec_oc_snc_mode | FEC_OC_SNC_MODE_UNLOCK_ENABLE__M, 0);
5937 		if (rc != 0) {
5938 			pr_err("error %d\n", rc);
5939 			goto rw_error;
5940 		}
5941 	}
5942 
5943 	/* set clip */
5944 	rc = drxj_dap_write_reg16(dev_addr, IQM_AF_CLP_LEN__A, 0, 0);
5945 	if (rc != 0) {
5946 		pr_err("error %d\n", rc);
5947 		goto rw_error;
5948 	}
5949 	rc = drxj_dap_write_reg16(dev_addr, IQM_AF_CLP_TH__A, 470, 0);
5950 	if (rc != 0) {
5951 		pr_err("error %d\n", rc);
5952 		goto rw_error;
5953 	}
5954 	rc = drxj_dap_write_reg16(dev_addr, IQM_AF_SNS_LEN__A, 0, 0);
5955 	if (rc != 0) {
5956 		pr_err("error %d\n", rc);
5957 		goto rw_error;
5958 	}
5959 	rc = drxj_dap_write_reg16(dev_addr, VSB_TOP_SNRTH_PT__A, 0xD4, 0);
5960 	if (rc != 0) {
5961 		pr_err("error %d\n", rc);
5962 		goto rw_error;
5963 	}
5964 	/* no transparent, no A&C framing; parity is set in mpegoutput */
5965 	{
5966 		u16 fec_oc_reg_mode = 0;
5967 		rc = drxj_dap_read_reg16(dev_addr, FEC_OC_MODE__A, &fec_oc_reg_mode, 0);
5968 		if (rc != 0) {
5969 			pr_err("error %d\n", rc);
5970 			goto rw_error;
5971 		}
5972 		rc = drxj_dap_write_reg16(dev_addr, FEC_OC_MODE__A, fec_oc_reg_mode & (~(FEC_OC_MODE_TRANSPARENT__M | FEC_OC_MODE_CLEAR__M | FEC_OC_MODE_RETAIN_FRAMING__M)), 0);
5973 		if (rc != 0) {
5974 			pr_err("error %d\n", rc);
5975 			goto rw_error;
5976 		}
5977 	}
5978 
5979 	rc = drxj_dap_write_reg16(dev_addr, FEC_DI_TIMEOUT_LO__A, 0, 0);
5980 	if (rc != 0) {
5981 		pr_err("error %d\n", rc);
5982 		goto rw_error;
5983 	}	/* timeout counter for restarting */
5984 	rc = drxj_dap_write_reg16(dev_addr, FEC_DI_TIMEOUT_HI__A, 3, 0);
5985 	if (rc != 0) {
5986 		pr_err("error %d\n", rc);
5987 		goto rw_error;
5988 	}
5989 	rc = drxj_dap_write_reg16(dev_addr, FEC_RS_MODE__A, 0, 0);
5990 	if (rc != 0) {
5991 		pr_err("error %d\n", rc);
5992 		goto rw_error;
5993 	}	/* bypass disabled */
5994 	/* initialize RS packet error measurement parameters */
5995 	rc = drxj_dap_write_reg16(dev_addr, FEC_RS_MEASUREMENT_PERIOD__A, FEC_RS_MEASUREMENT_PERIOD, 0);
5996 	if (rc != 0) {
5997 		pr_err("error %d\n", rc);
5998 		goto rw_error;
5999 	}
6000 	rc = drxj_dap_write_reg16(dev_addr, FEC_RS_MEASUREMENT_PRESCALE__A, FEC_RS_MEASUREMENT_PRESCALE, 0);
6001 	if (rc != 0) {
6002 		pr_err("error %d\n", rc);
6003 		goto rw_error;
6004 	}
6005 
6006 	/* init measurement period of MER/SER */
6007 	rc = drxj_dap_write_reg16(dev_addr, VSB_TOP_MEASUREMENT_PERIOD__A, VSB_TOP_MEASUREMENT_PERIOD, 0);
6008 	if (rc != 0) {
6009 		pr_err("error %d\n", rc);
6010 		goto rw_error;
6011 	}
6012 	rc = drxdap_fasi_write_reg32(dev_addr, SCU_RAM_FEC_ACCUM_CW_CORRECTED_LO__A, 0, 0);
6013 	if (rc != 0) {
6014 		pr_err("error %d\n", rc);
6015 		goto rw_error;
6016 	}
6017 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_FEC_MEAS_COUNT__A, 0, 0);
6018 	if (rc != 0) {
6019 		pr_err("error %d\n", rc);
6020 		goto rw_error;
6021 	}
6022 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_FEC_ACCUM_PKT_FAILURES__A, 0, 0);
6023 	if (rc != 0) {
6024 		pr_err("error %d\n", rc);
6025 		goto rw_error;
6026 	}
6027 
6028 	rc = drxj_dap_write_reg16(dev_addr, VSB_TOP_CKGN1TRK__A, 128, 0);
6029 	if (rc != 0) {
6030 		pr_err("error %d\n", rc);
6031 		goto rw_error;
6032 	}
6033 	/* B-Input to ADC, PGA+filter in standby */
6034 	if (!ext_attr->has_lna) {
6035 		rc = drxj_dap_write_reg16(dev_addr, IQM_AF_AMUX__A, 0x02, 0);
6036 		if (rc != 0) {
6037 			pr_err("error %d\n", rc);
6038 			goto rw_error;
6039 		}
6040 	}
6041 
6042 	/* turn on IQMAF. It has to be in front of setAgc**() */
6043 	rc = set_iqm_af(demod, true);
6044 	if (rc != 0) {
6045 		pr_err("error %d\n", rc);
6046 		goto rw_error;
6047 	}
6048 	rc = adc_synchronization(demod);
6049 	if (rc != 0) {
6050 		pr_err("error %d\n", rc);
6051 		goto rw_error;
6052 	}
6053 
6054 	rc = init_agc(demod);
6055 	if (rc != 0) {
6056 		pr_err("error %d\n", rc);
6057 		goto rw_error;
6058 	}
6059 	rc = set_agc_if(demod, &(ext_attr->vsb_if_agc_cfg), false);
6060 	if (rc != 0) {
6061 		pr_err("error %d\n", rc);
6062 		goto rw_error;
6063 	}
6064 	rc = set_agc_rf(demod, &(ext_attr->vsb_rf_agc_cfg), false);
6065 	if (rc != 0) {
6066 		pr_err("error %d\n", rc);
6067 		goto rw_error;
6068 	}
6069 	{
6070 		/* TODO fix this, store a struct drxj_cfg_afe_gain structure in struct drxj_data instead
6071 		   of only the gain */
6072 		struct drxj_cfg_afe_gain vsb_pga_cfg = { DRX_STANDARD_8VSB, 0 };
6073 
6074 		vsb_pga_cfg.gain = ext_attr->vsb_pga_cfg;
6075 		rc = ctrl_set_cfg_afe_gain(demod, &vsb_pga_cfg);
6076 		if (rc != 0) {
6077 			pr_err("error %d\n", rc);
6078 			goto rw_error;
6079 		}
6080 	}
6081 	rc = ctrl_set_cfg_pre_saw(demod, &(ext_attr->vsb_pre_saw_cfg));
6082 	if (rc != 0) {
6083 		pr_err("error %d\n", rc);
6084 		goto rw_error;
6085 	}
6086 
6087 	/* Mpeg output has to be in front of FEC active */
6088 	rc = set_mpegtei_handling(demod);
6089 	if (rc != 0) {
6090 		pr_err("error %d\n", rc);
6091 		goto rw_error;
6092 	}
6093 	rc = bit_reverse_mpeg_output(demod);
6094 	if (rc != 0) {
6095 		pr_err("error %d\n", rc);
6096 		goto rw_error;
6097 	}
6098 	rc = set_mpeg_start_width(demod);
6099 	if (rc != 0) {
6100 		pr_err("error %d\n", rc);
6101 		goto rw_error;
6102 	}
6103 	{
6104 		/* TODO: move to set_standard after hardware reset value problem is solved */
6105 		/* Configure initial MPEG output */
6106 		struct drx_cfg_mpeg_output cfg_mpeg_output;
6107 
6108 		memcpy(&cfg_mpeg_output, &common_attr->mpeg_cfg, sizeof(cfg_mpeg_output));
6109 		cfg_mpeg_output.enable_mpeg_output = true;
6110 
6111 		rc = ctrl_set_cfg_mpeg_output(demod, &cfg_mpeg_output);
6112 		if (rc != 0) {
6113 			pr_err("error %d\n", rc);
6114 			goto rw_error;
6115 		}
6116 	}
6117 
6118 	/* TBD: what parameters should be set */
6119 	cmd_param = 0x00;	/* Default mode AGC on, etc */
6120 	cmd_scu.command = SCU_RAM_COMMAND_STANDARD_VSB
6121 	    | SCU_RAM_COMMAND_CMD_DEMOD_SET_PARAM;
6122 	cmd_scu.parameter_len = 1;
6123 	cmd_scu.result_len = 1;
6124 	cmd_scu.parameter = &cmd_param;
6125 	cmd_scu.result = &cmd_result;
6126 	rc = scu_command(dev_addr, &cmd_scu);
6127 	if (rc != 0) {
6128 		pr_err("error %d\n", rc);
6129 		goto rw_error;
6130 	}
6131 
6132 	rc = drxj_dap_write_reg16(dev_addr, VSB_TOP_BEAGC_GAINSHIFT__A, 0x0004, 0);
6133 	if (rc != 0) {
6134 		pr_err("error %d\n", rc);
6135 		goto rw_error;
6136 	}
6137 	rc = drxj_dap_write_reg16(dev_addr, VSB_TOP_SNRTH_PT__A, 0x00D2, 0);
6138 	if (rc != 0) {
6139 		pr_err("error %d\n", rc);
6140 		goto rw_error;
6141 	}
6142 	rc = drxj_dap_write_reg16(dev_addr, VSB_TOP_SYSSMTRNCTRL__A, VSB_TOP_SYSSMTRNCTRL__PRE | VSB_TOP_SYSSMTRNCTRL_NCOTIMEOUTCNTEN__M, 0);
6143 	if (rc != 0) {
6144 		pr_err("error %d\n", rc);
6145 		goto rw_error;
6146 	}
6147 	rc = drxj_dap_write_reg16(dev_addr, VSB_TOP_BEDETCTRL__A, 0x142, 0);
6148 	if (rc != 0) {
6149 		pr_err("error %d\n", rc);
6150 		goto rw_error;
6151 	}
6152 	rc = drxj_dap_write_reg16(dev_addr, VSB_TOP_LBAGCREFLVL__A, 640, 0);
6153 	if (rc != 0) {
6154 		pr_err("error %d\n", rc);
6155 		goto rw_error;
6156 	}
6157 	rc = drxj_dap_write_reg16(dev_addr, VSB_TOP_CYGN1ACQ__A, 4, 0);
6158 	if (rc != 0) {
6159 		pr_err("error %d\n", rc);
6160 		goto rw_error;
6161 	}
6162 	rc = drxj_dap_write_reg16(dev_addr, VSB_TOP_CYGN1TRK__A, 2, 0);
6163 	if (rc != 0) {
6164 		pr_err("error %d\n", rc);
6165 		goto rw_error;
6166 	}
6167 	rc = drxj_dap_write_reg16(dev_addr, VSB_TOP_CYGN2TRK__A, 3, 0);
6168 	if (rc != 0) {
6169 		pr_err("error %d\n", rc);
6170 		goto rw_error;
6171 	}
6172 
6173 	/* start demodulator */
6174 	cmd_scu.command = SCU_RAM_COMMAND_STANDARD_VSB
6175 	    | SCU_RAM_COMMAND_CMD_DEMOD_START;
6176 	cmd_scu.parameter_len = 0;
6177 	cmd_scu.result_len = 1;
6178 	cmd_scu.parameter = NULL;
6179 	cmd_scu.result = &cmd_result;
6180 	rc = scu_command(dev_addr, &cmd_scu);
6181 	if (rc != 0) {
6182 		pr_err("error %d\n", rc);
6183 		goto rw_error;
6184 	}
6185 
6186 	rc = drxj_dap_write_reg16(dev_addr, IQM_COMM_EXEC__A, IQM_COMM_EXEC_ACTIVE, 0);
6187 	if (rc != 0) {
6188 		pr_err("error %d\n", rc);
6189 		goto rw_error;
6190 	}
6191 	rc = drxj_dap_write_reg16(dev_addr, VSB_COMM_EXEC__A, VSB_COMM_EXEC_ACTIVE, 0);
6192 	if (rc != 0) {
6193 		pr_err("error %d\n", rc);
6194 		goto rw_error;
6195 	}
6196 	rc = drxj_dap_write_reg16(dev_addr, FEC_COMM_EXEC__A, FEC_COMM_EXEC_ACTIVE, 0);
6197 	if (rc != 0) {
6198 		pr_err("error %d\n", rc);
6199 		goto rw_error;
6200 	}
6201 
6202 	return 0;
6203 rw_error:
6204 	return rc;
6205 }
6206 
6207 /*
6208 * \fn static short get_vsb_post_rs_pck_err(struct i2c_device_addr *dev_addr, u16 *PckErrs)
6209 * \brief Get the values of packet error in 8VSB mode
6210 * \return Error code
6211 */
6212 static int get_vsb_post_rs_pck_err(struct i2c_device_addr *dev_addr,
6213 				   u32 *pck_errs, u32 *pck_count)
6214 {
6215 	int rc;
6216 	u16 data = 0;
6217 	u16 period = 0;
6218 	u16 prescale = 0;
6219 	u16 packet_errors_mant = 0;
6220 	u16 packet_errors_exp = 0;
6221 
6222 	rc = drxj_dap_read_reg16(dev_addr, FEC_RS_NR_FAILURES__A, &data, 0);
6223 	if (rc != 0) {
6224 		pr_err("error %d\n", rc);
6225 		goto rw_error;
6226 	}
6227 	packet_errors_mant = data & FEC_RS_NR_FAILURES_FIXED_MANT__M;
6228 	packet_errors_exp = (data & FEC_RS_NR_FAILURES_EXP__M)
6229 	    >> FEC_RS_NR_FAILURES_EXP__B;
6230 	period = FEC_RS_MEASUREMENT_PERIOD;
6231 	prescale = FEC_RS_MEASUREMENT_PRESCALE;
6232 	/* packet error rate = (error packet number) per second */
6233 	/* 77.3 us is time for per packet */
6234 	if (period * prescale == 0) {
6235 		pr_err("error: period and/or prescale is zero!\n");
6236 		return -EIO;
6237 	}
6238 	*pck_errs = packet_errors_mant * (1 << packet_errors_exp);
6239 	*pck_count = period * prescale * 77;
6240 
6241 	return 0;
6242 rw_error:
6243 	return rc;
6244 }
6245 
6246 /*
6247 * \fn static short GetVSBBer(struct i2c_device_addr *dev_addr, u32 *ber)
6248 * \brief Get the values of ber in VSB mode
6249 * \return Error code
6250 */
6251 static int get_vs_bpost_viterbi_ber(struct i2c_device_addr *dev_addr,
6252 				    u32 *ber, u32 *cnt)
6253 {
6254 	int rc;
6255 	u16 data = 0;
6256 	u16 period = 0;
6257 	u16 prescale = 0;
6258 	u16 bit_errors_mant = 0;
6259 	u16 bit_errors_exp = 0;
6260 
6261 	rc = drxj_dap_read_reg16(dev_addr, FEC_RS_NR_BIT_ERRORS__A, &data, 0);
6262 	if (rc != 0) {
6263 		pr_err("error %d\n", rc);
6264 		goto rw_error;
6265 	}
6266 	period = FEC_RS_MEASUREMENT_PERIOD;
6267 	prescale = FEC_RS_MEASUREMENT_PRESCALE;
6268 
6269 	bit_errors_mant = data & FEC_RS_NR_BIT_ERRORS_FIXED_MANT__M;
6270 	bit_errors_exp = (data & FEC_RS_NR_BIT_ERRORS_EXP__M)
6271 	    >> FEC_RS_NR_BIT_ERRORS_EXP__B;
6272 
6273 	*cnt = period * prescale * 207 * ((bit_errors_exp > 2) ? 1 : 8);
6274 
6275 	if (((bit_errors_mant << bit_errors_exp) >> 3) > 68700)
6276 		*ber = (*cnt) * 26570;
6277 	else {
6278 		if (period * prescale == 0) {
6279 			pr_err("error: period and/or prescale is zero!\n");
6280 			return -EIO;
6281 		}
6282 		*ber = bit_errors_mant << ((bit_errors_exp > 2) ?
6283 			(bit_errors_exp - 3) : bit_errors_exp);
6284 	}
6285 
6286 	return 0;
6287 rw_error:
6288 	return rc;
6289 }
6290 
6291 /*
6292 * \fn static short get_vs_bpre_viterbi_ber(struct i2c_device_addr *dev_addr, u32 *ber)
6293 * \brief Get the values of ber in VSB mode
6294 * \return Error code
6295 */
6296 static int get_vs_bpre_viterbi_ber(struct i2c_device_addr *dev_addr,
6297 				   u32 *ber, u32 *cnt)
6298 {
6299 	u16 data = 0;
6300 	int rc;
6301 
6302 	rc = drxj_dap_read_reg16(dev_addr, VSB_TOP_NR_SYM_ERRS__A, &data, 0);
6303 	if (rc != 0) {
6304 		pr_err("error %d\n", rc);
6305 		return -EIO;
6306 	}
6307 	*ber = data;
6308 	*cnt = VSB_TOP_MEASUREMENT_PERIOD * SYMBOLS_PER_SEGMENT;
6309 
6310 	return 0;
6311 }
6312 
6313 /*
6314 * \fn static int get_vsbmer(struct i2c_device_addr *dev_addr, u16 *mer)
6315 * \brief Get the values of MER
6316 * \return Error code
6317 */
6318 static int get_vsbmer(struct i2c_device_addr *dev_addr, u16 *mer)
6319 {
6320 	int rc;
6321 	u16 data_hi = 0;
6322 
6323 	rc = drxj_dap_read_reg16(dev_addr, VSB_TOP_ERR_ENERGY_H__A, &data_hi, 0);
6324 	if (rc != 0) {
6325 		pr_err("error %d\n", rc);
6326 		goto rw_error;
6327 	}
6328 	*mer =
6329 	    (u16) (log1_times100(21504) - log1_times100((data_hi << 6) / 52));
6330 
6331 	return 0;
6332 rw_error:
6333 	return rc;
6334 }
6335 
6336 
6337 /*============================================================================*/
6338 /*==                     END 8VSB DATAPATH FUNCTIONS                        ==*/
6339 /*============================================================================*/
6340 
6341 /*============================================================================*/
6342 /*============================================================================*/
6343 /*==                       QAM DATAPATH FUNCTIONS                           ==*/
6344 /*============================================================================*/
6345 /*============================================================================*/
6346 
6347 /*
6348 * \fn int power_down_qam ()
6349 * \brief Powr down QAM related blocks.
6350 * \param demod instance of demodulator.
6351 * \param channel pointer to channel data.
6352 * \return int.
6353 */
6354 static int power_down_qam(struct drx_demod_instance *demod, bool primary)
6355 {
6356 	struct drxjscu_cmd cmd_scu = { /* command      */ 0,
6357 		/* parameter_len */ 0,
6358 		/* result_len    */ 0,
6359 		/* *parameter   */ NULL,
6360 		/* *result      */ NULL
6361 	};
6362 	int rc;
6363 	struct i2c_device_addr *dev_addr = demod->my_i2c_dev_addr;
6364 	struct drx_cfg_mpeg_output cfg_mpeg_output;
6365 	struct drx_common_attr *common_attr = demod->my_common_attr;
6366 	u16 cmd_result = 0;
6367 
6368 	/*
6369 	   STOP demodulator
6370 	   resets IQM, QAM and FEC HW blocks
6371 	 */
6372 	/* stop all comm_exec */
6373 	rc = drxj_dap_write_reg16(dev_addr, FEC_COMM_EXEC__A, FEC_COMM_EXEC_STOP, 0);
6374 	if (rc != 0) {
6375 		pr_err("error %d\n", rc);
6376 		goto rw_error;
6377 	}
6378 	rc = drxj_dap_write_reg16(dev_addr, QAM_COMM_EXEC__A, QAM_COMM_EXEC_STOP, 0);
6379 	if (rc != 0) {
6380 		pr_err("error %d\n", rc);
6381 		goto rw_error;
6382 	}
6383 
6384 	cmd_scu.command = SCU_RAM_COMMAND_STANDARD_QAM |
6385 	    SCU_RAM_COMMAND_CMD_DEMOD_STOP;
6386 	cmd_scu.parameter_len = 0;
6387 	cmd_scu.result_len = 1;
6388 	cmd_scu.parameter = NULL;
6389 	cmd_scu.result = &cmd_result;
6390 	rc = scu_command(dev_addr, &cmd_scu);
6391 	if (rc != 0) {
6392 		pr_err("error %d\n", rc);
6393 		goto rw_error;
6394 	}
6395 
6396 	if (primary) {
6397 		rc = drxj_dap_write_reg16(dev_addr, IQM_COMM_EXEC__A, IQM_COMM_EXEC_STOP, 0);
6398 		if (rc != 0) {
6399 			pr_err("error %d\n", rc);
6400 			goto rw_error;
6401 		}
6402 		rc = set_iqm_af(demod, false);
6403 		if (rc != 0) {
6404 			pr_err("error %d\n", rc);
6405 			goto rw_error;
6406 		}
6407 	} else {
6408 		rc = drxj_dap_write_reg16(dev_addr, IQM_FS_COMM_EXEC__A, IQM_FS_COMM_EXEC_STOP, 0);
6409 		if (rc != 0) {
6410 			pr_err("error %d\n", rc);
6411 			goto rw_error;
6412 		}
6413 		rc = drxj_dap_write_reg16(dev_addr, IQM_FD_COMM_EXEC__A, IQM_FD_COMM_EXEC_STOP, 0);
6414 		if (rc != 0) {
6415 			pr_err("error %d\n", rc);
6416 			goto rw_error;
6417 		}
6418 		rc = drxj_dap_write_reg16(dev_addr, IQM_RC_COMM_EXEC__A, IQM_RC_COMM_EXEC_STOP, 0);
6419 		if (rc != 0) {
6420 			pr_err("error %d\n", rc);
6421 			goto rw_error;
6422 		}
6423 		rc = drxj_dap_write_reg16(dev_addr, IQM_RT_COMM_EXEC__A, IQM_RT_COMM_EXEC_STOP, 0);
6424 		if (rc != 0) {
6425 			pr_err("error %d\n", rc);
6426 			goto rw_error;
6427 		}
6428 		rc = drxj_dap_write_reg16(dev_addr, IQM_CF_COMM_EXEC__A, IQM_CF_COMM_EXEC_STOP, 0);
6429 		if (rc != 0) {
6430 			pr_err("error %d\n", rc);
6431 			goto rw_error;
6432 		}
6433 	}
6434 
6435 	memcpy(&cfg_mpeg_output, &common_attr->mpeg_cfg, sizeof(cfg_mpeg_output));
6436 	cfg_mpeg_output.enable_mpeg_output = false;
6437 
6438 	rc = ctrl_set_cfg_mpeg_output(demod, &cfg_mpeg_output);
6439 	if (rc != 0) {
6440 		pr_err("error %d\n", rc);
6441 		goto rw_error;
6442 	}
6443 
6444 	return 0;
6445 rw_error:
6446 	return rc;
6447 }
6448 
6449 /*============================================================================*/
6450 
6451 /*
6452 * \fn int set_qam_measurement ()
6453 * \brief Setup of the QAM Measuremnt intervals for signal quality
6454 * \param demod instance of demod.
6455 * \param constellation current constellation.
6456 * \return int.
6457 *
6458 *  NOTE:
6459 *  Take into account that for certain settings the errorcounters can overflow.
6460 *  The implementation does not check this.
6461 *
6462 *  TODO: overriding the ext_attr->fec_bits_desired by constellation dependent
6463 *  constants to get a measurement period of approx. 1 sec. Remove fec_bits_desired
6464 *  field ?
6465 *
6466 */
6467 #ifndef DRXJ_VSB_ONLY
6468 static int
6469 set_qam_measurement(struct drx_demod_instance *demod,
6470 		    enum drx_modulation constellation, u32 symbol_rate)
6471 {
6472 	struct i2c_device_addr *dev_addr = NULL;	/* device address for I2C writes */
6473 	struct drxj_data *ext_attr = NULL;	/* Global data container for DRXJ specific data */
6474 	int rc;
6475 	u32 fec_bits_desired = 0;	/* BER accounting period */
6476 	u16 fec_rs_plen = 0;	/* defines RS BER measurement period */
6477 	u16 fec_rs_prescale = 0;	/* ReedSolomon Measurement Prescale */
6478 	u32 fec_rs_period = 0;	/* Value for corresponding I2C register */
6479 	u32 fec_rs_bit_cnt = 0;	/* Actual precise amount of bits */
6480 	u32 fec_oc_snc_fail_period = 0;	/* Value for corresponding I2C register */
6481 	u32 qam_vd_period = 0;	/* Value for corresponding I2C register */
6482 	u32 qam_vd_bit_cnt = 0;	/* Actual precise amount of bits */
6483 	u16 fec_vd_plen = 0;	/* no of trellis symbols: VD SER measur period */
6484 	u16 qam_vd_prescale = 0;	/* Viterbi Measurement Prescale */
6485 
6486 	dev_addr = demod->my_i2c_dev_addr;
6487 	ext_attr = (struct drxj_data *) demod->my_ext_attr;
6488 
6489 	fec_bits_desired = ext_attr->fec_bits_desired;
6490 	fec_rs_prescale = ext_attr->fec_rs_prescale;
6491 
6492 	switch (constellation) {
6493 	case DRX_CONSTELLATION_QAM16:
6494 		fec_bits_desired = 4 * symbol_rate;
6495 		break;
6496 	case DRX_CONSTELLATION_QAM32:
6497 		fec_bits_desired = 5 * symbol_rate;
6498 		break;
6499 	case DRX_CONSTELLATION_QAM64:
6500 		fec_bits_desired = 6 * symbol_rate;
6501 		break;
6502 	case DRX_CONSTELLATION_QAM128:
6503 		fec_bits_desired = 7 * symbol_rate;
6504 		break;
6505 	case DRX_CONSTELLATION_QAM256:
6506 		fec_bits_desired = 8 * symbol_rate;
6507 		break;
6508 	default:
6509 		return -EINVAL;
6510 	}
6511 
6512 	/* Parameters for Reed-Solomon Decoder */
6513 	/* fecrs_period = (int)ceil(FEC_BITS_DESIRED/(fecrs_prescale*plen)) */
6514 	/* rs_bit_cnt   = fecrs_period*fecrs_prescale*plen                  */
6515 	/*     result is within 32 bit arithmetic ->                        */
6516 	/*     no need for mult or frac functions                           */
6517 
6518 	/* TODO: use constant instead of calculation and remove the fec_rs_plen in ext_attr */
6519 	switch (ext_attr->standard) {
6520 	case DRX_STANDARD_ITU_A:
6521 	case DRX_STANDARD_ITU_C:
6522 		fec_rs_plen = 204 * 8;
6523 		break;
6524 	case DRX_STANDARD_ITU_B:
6525 		fec_rs_plen = 128 * 7;
6526 		break;
6527 	default:
6528 		return -EINVAL;
6529 	}
6530 
6531 	ext_attr->fec_rs_plen = fec_rs_plen;	/* for getSigQual */
6532 	fec_rs_bit_cnt = fec_rs_prescale * fec_rs_plen;	/* temp storage   */
6533 	if (fec_rs_bit_cnt == 0) {
6534 		pr_err("error: fec_rs_bit_cnt is zero!\n");
6535 		return -EIO;
6536 	}
6537 	fec_rs_period = fec_bits_desired / fec_rs_bit_cnt + 1;	/* ceil */
6538 	if (ext_attr->standard != DRX_STANDARD_ITU_B)
6539 		fec_oc_snc_fail_period = fec_rs_period;
6540 
6541 	/* limit to max 16 bit value (I2C register width) if needed */
6542 	if (fec_rs_period > 0xFFFF)
6543 		fec_rs_period = 0xFFFF;
6544 
6545 	/* write corresponding registers */
6546 	switch (ext_attr->standard) {
6547 	case DRX_STANDARD_ITU_A:
6548 	case DRX_STANDARD_ITU_C:
6549 		break;
6550 	case DRX_STANDARD_ITU_B:
6551 		switch (constellation) {
6552 		case DRX_CONSTELLATION_QAM64:
6553 			fec_rs_period = 31581;
6554 			fec_oc_snc_fail_period = 17932;
6555 			break;
6556 		case DRX_CONSTELLATION_QAM256:
6557 			fec_rs_period = 45446;
6558 			fec_oc_snc_fail_period = 25805;
6559 			break;
6560 		default:
6561 			return -EINVAL;
6562 		}
6563 		break;
6564 	default:
6565 		return -EINVAL;
6566 	}
6567 
6568 	rc = drxj_dap_write_reg16(dev_addr, FEC_OC_SNC_FAIL_PERIOD__A, (u16)fec_oc_snc_fail_period, 0);
6569 	if (rc != 0) {
6570 		pr_err("error %d\n", rc);
6571 		goto rw_error;
6572 	}
6573 	rc = drxj_dap_write_reg16(dev_addr, FEC_RS_MEASUREMENT_PERIOD__A, (u16)fec_rs_period, 0);
6574 	if (rc != 0) {
6575 		pr_err("error %d\n", rc);
6576 		goto rw_error;
6577 	}
6578 	rc = drxj_dap_write_reg16(dev_addr, FEC_RS_MEASUREMENT_PRESCALE__A, fec_rs_prescale, 0);
6579 	if (rc != 0) {
6580 		pr_err("error %d\n", rc);
6581 		goto rw_error;
6582 	}
6583 	ext_attr->fec_rs_period = (u16) fec_rs_period;
6584 	ext_attr->fec_rs_prescale = fec_rs_prescale;
6585 	rc = drxdap_fasi_write_reg32(dev_addr, SCU_RAM_FEC_ACCUM_CW_CORRECTED_LO__A, 0, 0);
6586 	if (rc != 0) {
6587 		pr_err("error %d\n", rc);
6588 		goto rw_error;
6589 	}
6590 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_FEC_MEAS_COUNT__A, 0, 0);
6591 	if (rc != 0) {
6592 		pr_err("error %d\n", rc);
6593 		goto rw_error;
6594 	}
6595 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_FEC_ACCUM_PKT_FAILURES__A, 0, 0);
6596 	if (rc != 0) {
6597 		pr_err("error %d\n", rc);
6598 		goto rw_error;
6599 	}
6600 
6601 	if (ext_attr->standard == DRX_STANDARD_ITU_B) {
6602 		/* Parameters for Viterbi Decoder */
6603 		/* qamvd_period = (int)ceil(FEC_BITS_DESIRED/                      */
6604 		/*                    (qamvd_prescale*plen*(qam_constellation+1))) */
6605 		/* vd_bit_cnt   = qamvd_period*qamvd_prescale*plen                 */
6606 		/*     result is within 32 bit arithmetic ->                       */
6607 		/*     no need for mult or frac functions                          */
6608 
6609 		/* a(8 bit) * b(8 bit) = 16 bit result => mult32 not needed */
6610 		fec_vd_plen = ext_attr->fec_vd_plen;
6611 		qam_vd_prescale = ext_attr->qam_vd_prescale;
6612 		qam_vd_bit_cnt = qam_vd_prescale * fec_vd_plen;	/* temp storage */
6613 
6614 		switch (constellation) {
6615 		case DRX_CONSTELLATION_QAM64:
6616 			/* a(16 bit) * b(4 bit) = 20 bit result => mult32 not needed */
6617 			qam_vd_period =
6618 			    qam_vd_bit_cnt * (QAM_TOP_CONSTELLATION_QAM64 + 1)
6619 			    * (QAM_TOP_CONSTELLATION_QAM64 + 1);
6620 			break;
6621 		case DRX_CONSTELLATION_QAM256:
6622 			/* a(16 bit) * b(5 bit) = 21 bit result => mult32 not needed */
6623 			qam_vd_period =
6624 			    qam_vd_bit_cnt * (QAM_TOP_CONSTELLATION_QAM256 + 1)
6625 			    * (QAM_TOP_CONSTELLATION_QAM256 + 1);
6626 			break;
6627 		default:
6628 			return -EINVAL;
6629 		}
6630 		if (qam_vd_period == 0) {
6631 			pr_err("error: qam_vd_period is zero!\n");
6632 			return -EIO;
6633 		}
6634 		qam_vd_period = fec_bits_desired / qam_vd_period;
6635 		/* limit to max 16 bit value (I2C register width) if needed */
6636 		if (qam_vd_period > 0xFFFF)
6637 			qam_vd_period = 0xFFFF;
6638 
6639 		/* a(16 bit) * b(16 bit) = 32 bit result => mult32 not needed */
6640 		qam_vd_bit_cnt *= qam_vd_period;
6641 
6642 		rc = drxj_dap_write_reg16(dev_addr, QAM_VD_MEASUREMENT_PERIOD__A, (u16)qam_vd_period, 0);
6643 		if (rc != 0) {
6644 			pr_err("error %d\n", rc);
6645 			goto rw_error;
6646 		}
6647 		rc = drxj_dap_write_reg16(dev_addr, QAM_VD_MEASUREMENT_PRESCALE__A, qam_vd_prescale, 0);
6648 		if (rc != 0) {
6649 			pr_err("error %d\n", rc);
6650 			goto rw_error;
6651 		}
6652 		ext_attr->qam_vd_period = (u16) qam_vd_period;
6653 		ext_attr->qam_vd_prescale = qam_vd_prescale;
6654 	}
6655 
6656 	return 0;
6657 rw_error:
6658 	return rc;
6659 }
6660 
6661 /*============================================================================*/
6662 
6663 /*
6664 * \fn int set_qam16 ()
6665 * \brief QAM16 specific setup
6666 * \param demod instance of demod.
6667 * \return int.
6668 */
6669 static int set_qam16(struct drx_demod_instance *demod)
6670 {
6671 	struct i2c_device_addr *dev_addr = demod->my_i2c_dev_addr;
6672 	int rc;
6673 	static const u8 qam_dq_qual_fun[] = {
6674 		DRXJ_16TO8(2),	/* fun0  */
6675 		DRXJ_16TO8(2),	/* fun1  */
6676 		DRXJ_16TO8(2),	/* fun2  */
6677 		DRXJ_16TO8(2),	/* fun3  */
6678 		DRXJ_16TO8(3),	/* fun4  */
6679 		DRXJ_16TO8(3),	/* fun5  */
6680 	};
6681 	static const u8 qam_eq_cma_rad[] = {
6682 		DRXJ_16TO8(13517),	/* RAD0  */
6683 		DRXJ_16TO8(13517),	/* RAD1  */
6684 		DRXJ_16TO8(13517),	/* RAD2  */
6685 		DRXJ_16TO8(13517),	/* RAD3  */
6686 		DRXJ_16TO8(13517),	/* RAD4  */
6687 		DRXJ_16TO8(13517),	/* RAD5  */
6688 	};
6689 
6690 	rc = drxdap_fasi_write_block(dev_addr, QAM_DQ_QUAL_FUN0__A, sizeof(qam_dq_qual_fun), ((u8 *)qam_dq_qual_fun), 0);
6691 	if (rc != 0) {
6692 		pr_err("error %d\n", rc);
6693 		goto rw_error;
6694 	}
6695 	rc = drxdap_fasi_write_block(dev_addr, SCU_RAM_QAM_EQ_CMA_RAD0__A, sizeof(qam_eq_cma_rad), ((u8 *)qam_eq_cma_rad), 0);
6696 	if (rc != 0) {
6697 		pr_err("error %d\n", rc);
6698 		goto rw_error;
6699 	}
6700 
6701 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_RTH__A, 140, 0);
6702 	if (rc != 0) {
6703 		pr_err("error %d\n", rc);
6704 		goto rw_error;
6705 	}
6706 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_FTH__A, 50, 0);
6707 	if (rc != 0) {
6708 		pr_err("error %d\n", rc);
6709 		goto rw_error;
6710 	}
6711 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_PTH__A, 120, 0);
6712 	if (rc != 0) {
6713 		pr_err("error %d\n", rc);
6714 		goto rw_error;
6715 	}
6716 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_QTH__A, 230, 0);
6717 	if (rc != 0) {
6718 		pr_err("error %d\n", rc);
6719 		goto rw_error;
6720 	}
6721 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_CTH__A, 95, 0);
6722 	if (rc != 0) {
6723 		pr_err("error %d\n", rc);
6724 		goto rw_error;
6725 	}
6726 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_MTH__A, 105, 0);
6727 	if (rc != 0) {
6728 		pr_err("error %d\n", rc);
6729 		goto rw_error;
6730 	}
6731 
6732 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_RATE_LIM__A, 40, 0);
6733 	if (rc != 0) {
6734 		pr_err("error %d\n", rc);
6735 		goto rw_error;
6736 	}
6737 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_FREQ_LIM__A, 56, 0);
6738 	if (rc != 0) {
6739 		pr_err("error %d\n", rc);
6740 		goto rw_error;
6741 	}
6742 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_COUNT_LIM__A, 3, 0);
6743 	if (rc != 0) {
6744 		pr_err("error %d\n", rc);
6745 		goto rw_error;
6746 	}
6747 
6748 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__A, 16, 0);
6749 	if (rc != 0) {
6750 		pr_err("error %d\n", rc);
6751 		goto rw_error;
6752 	}
6753 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__A, 220, 0);
6754 	if (rc != 0) {
6755 		pr_err("error %d\n", rc);
6756 		goto rw_error;
6757 	}
6758 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET1__A, 25, 0);
6759 	if (rc != 0) {
6760 		pr_err("error %d\n", rc);
6761 		goto rw_error;
6762 	}
6763 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET2__A, 6, 0);
6764 	if (rc != 0) {
6765 		pr_err("error %d\n", rc);
6766 		goto rw_error;
6767 	}
6768 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET3__A, (u16)(-24), 0);
6769 	if (rc != 0) {
6770 		pr_err("error %d\n", rc);
6771 		goto rw_error;
6772 	}
6773 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET4__A, (u16)(-65), 0);
6774 	if (rc != 0) {
6775 		pr_err("error %d\n", rc);
6776 		goto rw_error;
6777 	}
6778 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A, (u16)(-127), 0);
6779 	if (rc != 0) {
6780 		pr_err("error %d\n", rc);
6781 		goto rw_error;
6782 	}
6783 
6784 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CA_FINE__A, 15, 0);
6785 	if (rc != 0) {
6786 		pr_err("error %d\n", rc);
6787 		goto rw_error;
6788 	}
6789 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CA_COARSE__A, 40, 0);
6790 	if (rc != 0) {
6791 		pr_err("error %d\n", rc);
6792 		goto rw_error;
6793 	}
6794 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CP_FINE__A, 2, 0);
6795 	if (rc != 0) {
6796 		pr_err("error %d\n", rc);
6797 		goto rw_error;
6798 	}
6799 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CP_MEDIUM__A, 20, 0);
6800 	if (rc != 0) {
6801 		pr_err("error %d\n", rc);
6802 		goto rw_error;
6803 	}
6804 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CP_COARSE__A, 255, 0);
6805 	if (rc != 0) {
6806 		pr_err("error %d\n", rc);
6807 		goto rw_error;
6808 	}
6809 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CI_FINE__A, 2, 0);
6810 	if (rc != 0) {
6811 		pr_err("error %d\n", rc);
6812 		goto rw_error;
6813 	}
6814 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CI_MEDIUM__A, 10, 0);
6815 	if (rc != 0) {
6816 		pr_err("error %d\n", rc);
6817 		goto rw_error;
6818 	}
6819 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CI_COARSE__A, 50, 0);
6820 	if (rc != 0) {
6821 		pr_err("error %d\n", rc);
6822 		goto rw_error;
6823 	}
6824 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EP_FINE__A, 12, 0);
6825 	if (rc != 0) {
6826 		pr_err("error %d\n", rc);
6827 		goto rw_error;
6828 	}
6829 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EP_MEDIUM__A, 24, 0);
6830 	if (rc != 0) {
6831 		pr_err("error %d\n", rc);
6832 		goto rw_error;
6833 	}
6834 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EP_COARSE__A, 24, 0);
6835 	if (rc != 0) {
6836 		pr_err("error %d\n", rc);
6837 		goto rw_error;
6838 	}
6839 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EI_FINE__A, 12, 0);
6840 	if (rc != 0) {
6841 		pr_err("error %d\n", rc);
6842 		goto rw_error;
6843 	}
6844 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EI_MEDIUM__A, 16, 0);
6845 	if (rc != 0) {
6846 		pr_err("error %d\n", rc);
6847 		goto rw_error;
6848 	}
6849 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EI_COARSE__A, 16, 0);
6850 	if (rc != 0) {
6851 		pr_err("error %d\n", rc);
6852 		goto rw_error;
6853 	}
6854 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF_FINE__A, 16, 0);
6855 	if (rc != 0) {
6856 		pr_err("error %d\n", rc);
6857 		goto rw_error;
6858 	}
6859 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF_MEDIUM__A, 32, 0);
6860 	if (rc != 0) {
6861 		pr_err("error %d\n", rc);
6862 		goto rw_error;
6863 	}
6864 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF_COARSE__A, 240, 0);
6865 	if (rc != 0) {
6866 		pr_err("error %d\n", rc);
6867 		goto rw_error;
6868 	}
6869 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF1_FINE__A, 5, 0);
6870 	if (rc != 0) {
6871 		pr_err("error %d\n", rc);
6872 		goto rw_error;
6873 	}
6874 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF1_MEDIUM__A, 15, 0);
6875 	if (rc != 0) {
6876 		pr_err("error %d\n", rc);
6877 		goto rw_error;
6878 	}
6879 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF1_COARSE__A, 32, 0);
6880 	if (rc != 0) {
6881 		pr_err("error %d\n", rc);
6882 		goto rw_error;
6883 	}
6884 
6885 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_SL_SIG_POWER__A, 40960, 0);
6886 	if (rc != 0) {
6887 		pr_err("error %d\n", rc);
6888 		goto rw_error;
6889 	}
6890 
6891 	return 0;
6892 rw_error:
6893 	return rc;
6894 }
6895 
6896 /*============================================================================*/
6897 
6898 /*
6899 * \fn int set_qam32 ()
6900 * \brief QAM32 specific setup
6901 * \param demod instance of demod.
6902 * \return int.
6903 */
6904 static int set_qam32(struct drx_demod_instance *demod)
6905 {
6906 	struct i2c_device_addr *dev_addr = demod->my_i2c_dev_addr;
6907 	int rc;
6908 	static const u8 qam_dq_qual_fun[] = {
6909 		DRXJ_16TO8(3),	/* fun0  */
6910 		DRXJ_16TO8(3),	/* fun1  */
6911 		DRXJ_16TO8(3),	/* fun2  */
6912 		DRXJ_16TO8(3),	/* fun3  */
6913 		DRXJ_16TO8(4),	/* fun4  */
6914 		DRXJ_16TO8(4),	/* fun5  */
6915 	};
6916 	static const u8 qam_eq_cma_rad[] = {
6917 		DRXJ_16TO8(6707),	/* RAD0  */
6918 		DRXJ_16TO8(6707),	/* RAD1  */
6919 		DRXJ_16TO8(6707),	/* RAD2  */
6920 		DRXJ_16TO8(6707),	/* RAD3  */
6921 		DRXJ_16TO8(6707),	/* RAD4  */
6922 		DRXJ_16TO8(6707),	/* RAD5  */
6923 	};
6924 
6925 	rc = drxdap_fasi_write_block(dev_addr, QAM_DQ_QUAL_FUN0__A, sizeof(qam_dq_qual_fun), ((u8 *)qam_dq_qual_fun), 0);
6926 	if (rc != 0) {
6927 		pr_err("error %d\n", rc);
6928 		goto rw_error;
6929 	}
6930 	rc = drxdap_fasi_write_block(dev_addr, SCU_RAM_QAM_EQ_CMA_RAD0__A, sizeof(qam_eq_cma_rad), ((u8 *)qam_eq_cma_rad), 0);
6931 	if (rc != 0) {
6932 		pr_err("error %d\n", rc);
6933 		goto rw_error;
6934 	}
6935 
6936 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_RTH__A, 90, 0);
6937 	if (rc != 0) {
6938 		pr_err("error %d\n", rc);
6939 		goto rw_error;
6940 	}
6941 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_FTH__A, 50, 0);
6942 	if (rc != 0) {
6943 		pr_err("error %d\n", rc);
6944 		goto rw_error;
6945 	}
6946 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_PTH__A, 100, 0);
6947 	if (rc != 0) {
6948 		pr_err("error %d\n", rc);
6949 		goto rw_error;
6950 	}
6951 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_QTH__A, 170, 0);
6952 	if (rc != 0) {
6953 		pr_err("error %d\n", rc);
6954 		goto rw_error;
6955 	}
6956 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_CTH__A, 80, 0);
6957 	if (rc != 0) {
6958 		pr_err("error %d\n", rc);
6959 		goto rw_error;
6960 	}
6961 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_MTH__A, 100, 0);
6962 	if (rc != 0) {
6963 		pr_err("error %d\n", rc);
6964 		goto rw_error;
6965 	}
6966 
6967 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_RATE_LIM__A, 40, 0);
6968 	if (rc != 0) {
6969 		pr_err("error %d\n", rc);
6970 		goto rw_error;
6971 	}
6972 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_FREQ_LIM__A, 56, 0);
6973 	if (rc != 0) {
6974 		pr_err("error %d\n", rc);
6975 		goto rw_error;
6976 	}
6977 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_COUNT_LIM__A, 3, 0);
6978 	if (rc != 0) {
6979 		pr_err("error %d\n", rc);
6980 		goto rw_error;
6981 	}
6982 
6983 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__A, 12, 0);
6984 	if (rc != 0) {
6985 		pr_err("error %d\n", rc);
6986 		goto rw_error;
6987 	}
6988 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__A, 140, 0);
6989 	if (rc != 0) {
6990 		pr_err("error %d\n", rc);
6991 		goto rw_error;
6992 	}
6993 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET1__A, (u16)(-8), 0);
6994 	if (rc != 0) {
6995 		pr_err("error %d\n", rc);
6996 		goto rw_error;
6997 	}
6998 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET2__A, (u16)(-16), 0);
6999 	if (rc != 0) {
7000 		pr_err("error %d\n", rc);
7001 		goto rw_error;
7002 	}
7003 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET3__A, (u16)(-26), 0);
7004 	if (rc != 0) {
7005 		pr_err("error %d\n", rc);
7006 		goto rw_error;
7007 	}
7008 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET4__A, (u16)(-56), 0);
7009 	if (rc != 0) {
7010 		pr_err("error %d\n", rc);
7011 		goto rw_error;
7012 	}
7013 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A, (u16)(-86), 0);
7014 	if (rc != 0) {
7015 		pr_err("error %d\n", rc);
7016 		goto rw_error;
7017 	}
7018 
7019 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CA_FINE__A, 15, 0);
7020 	if (rc != 0) {
7021 		pr_err("error %d\n", rc);
7022 		goto rw_error;
7023 	}
7024 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CA_COARSE__A, 40, 0);
7025 	if (rc != 0) {
7026 		pr_err("error %d\n", rc);
7027 		goto rw_error;
7028 	}
7029 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CP_FINE__A, 2, 0);
7030 	if (rc != 0) {
7031 		pr_err("error %d\n", rc);
7032 		goto rw_error;
7033 	}
7034 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CP_MEDIUM__A, 20, 0);
7035 	if (rc != 0) {
7036 		pr_err("error %d\n", rc);
7037 		goto rw_error;
7038 	}
7039 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CP_COARSE__A, 255, 0);
7040 	if (rc != 0) {
7041 		pr_err("error %d\n", rc);
7042 		goto rw_error;
7043 	}
7044 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CI_FINE__A, 2, 0);
7045 	if (rc != 0) {
7046 		pr_err("error %d\n", rc);
7047 		goto rw_error;
7048 	}
7049 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CI_MEDIUM__A, 10, 0);
7050 	if (rc != 0) {
7051 		pr_err("error %d\n", rc);
7052 		goto rw_error;
7053 	}
7054 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CI_COARSE__A, 50, 0);
7055 	if (rc != 0) {
7056 		pr_err("error %d\n", rc);
7057 		goto rw_error;
7058 	}
7059 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EP_FINE__A, 12, 0);
7060 	if (rc != 0) {
7061 		pr_err("error %d\n", rc);
7062 		goto rw_error;
7063 	}
7064 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EP_MEDIUM__A, 24, 0);
7065 	if (rc != 0) {
7066 		pr_err("error %d\n", rc);
7067 		goto rw_error;
7068 	}
7069 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EP_COARSE__A, 24, 0);
7070 	if (rc != 0) {
7071 		pr_err("error %d\n", rc);
7072 		goto rw_error;
7073 	}
7074 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EI_FINE__A, 12, 0);
7075 	if (rc != 0) {
7076 		pr_err("error %d\n", rc);
7077 		goto rw_error;
7078 	}
7079 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EI_MEDIUM__A, 16, 0);
7080 	if (rc != 0) {
7081 		pr_err("error %d\n", rc);
7082 		goto rw_error;
7083 	}
7084 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EI_COARSE__A, 16, 0);
7085 	if (rc != 0) {
7086 		pr_err("error %d\n", rc);
7087 		goto rw_error;
7088 	}
7089 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF_FINE__A, 16, 0);
7090 	if (rc != 0) {
7091 		pr_err("error %d\n", rc);
7092 		goto rw_error;
7093 	}
7094 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF_MEDIUM__A, 32, 0);
7095 	if (rc != 0) {
7096 		pr_err("error %d\n", rc);
7097 		goto rw_error;
7098 	}
7099 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF_COARSE__A, 176, 0);
7100 	if (rc != 0) {
7101 		pr_err("error %d\n", rc);
7102 		goto rw_error;
7103 	}
7104 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF1_FINE__A, 5, 0);
7105 	if (rc != 0) {
7106 		pr_err("error %d\n", rc);
7107 		goto rw_error;
7108 	}
7109 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF1_MEDIUM__A, 15, 0);
7110 	if (rc != 0) {
7111 		pr_err("error %d\n", rc);
7112 		goto rw_error;
7113 	}
7114 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF1_COARSE__A, 8, 0);
7115 	if (rc != 0) {
7116 		pr_err("error %d\n", rc);
7117 		goto rw_error;
7118 	}
7119 
7120 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_SL_SIG_POWER__A, 20480, 0);
7121 	if (rc != 0) {
7122 		pr_err("error %d\n", rc);
7123 		goto rw_error;
7124 	}
7125 
7126 	return 0;
7127 rw_error:
7128 	return rc;
7129 }
7130 
7131 /*============================================================================*/
7132 
7133 /*
7134 * \fn int set_qam64 ()
7135 * \brief QAM64 specific setup
7136 * \param demod instance of demod.
7137 * \return int.
7138 */
7139 static int set_qam64(struct drx_demod_instance *demod)
7140 {
7141 	struct i2c_device_addr *dev_addr = demod->my_i2c_dev_addr;
7142 	int rc;
7143 	static const u8 qam_dq_qual_fun[] = {
7144 		/* this is hw reset value. no necessary to re-write */
7145 		DRXJ_16TO8(4),	/* fun0  */
7146 		DRXJ_16TO8(4),	/* fun1  */
7147 		DRXJ_16TO8(4),	/* fun2  */
7148 		DRXJ_16TO8(4),	/* fun3  */
7149 		DRXJ_16TO8(6),	/* fun4  */
7150 		DRXJ_16TO8(6),	/* fun5  */
7151 	};
7152 	static const u8 qam_eq_cma_rad[] = {
7153 		DRXJ_16TO8(13336),	/* RAD0  */
7154 		DRXJ_16TO8(12618),	/* RAD1  */
7155 		DRXJ_16TO8(11988),	/* RAD2  */
7156 		DRXJ_16TO8(13809),	/* RAD3  */
7157 		DRXJ_16TO8(13809),	/* RAD4  */
7158 		DRXJ_16TO8(15609),	/* RAD5  */
7159 	};
7160 
7161 	rc = drxdap_fasi_write_block(dev_addr, QAM_DQ_QUAL_FUN0__A, sizeof(qam_dq_qual_fun), ((u8 *)qam_dq_qual_fun), 0);
7162 	if (rc != 0) {
7163 		pr_err("error %d\n", rc);
7164 		goto rw_error;
7165 	}
7166 	rc = drxdap_fasi_write_block(dev_addr, SCU_RAM_QAM_EQ_CMA_RAD0__A, sizeof(qam_eq_cma_rad), ((u8 *)qam_eq_cma_rad), 0);
7167 	if (rc != 0) {
7168 		pr_err("error %d\n", rc);
7169 		goto rw_error;
7170 	}
7171 
7172 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_RTH__A, 105, 0);
7173 	if (rc != 0) {
7174 		pr_err("error %d\n", rc);
7175 		goto rw_error;
7176 	}
7177 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_FTH__A, 60, 0);
7178 	if (rc != 0) {
7179 		pr_err("error %d\n", rc);
7180 		goto rw_error;
7181 	}
7182 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_PTH__A, 100, 0);
7183 	if (rc != 0) {
7184 		pr_err("error %d\n", rc);
7185 		goto rw_error;
7186 	}
7187 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_QTH__A, 195, 0);
7188 	if (rc != 0) {
7189 		pr_err("error %d\n", rc);
7190 		goto rw_error;
7191 	}
7192 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_CTH__A, 80, 0);
7193 	if (rc != 0) {
7194 		pr_err("error %d\n", rc);
7195 		goto rw_error;
7196 	}
7197 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_MTH__A, 84, 0);
7198 	if (rc != 0) {
7199 		pr_err("error %d\n", rc);
7200 		goto rw_error;
7201 	}
7202 
7203 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_RATE_LIM__A, 40, 0);
7204 	if (rc != 0) {
7205 		pr_err("error %d\n", rc);
7206 		goto rw_error;
7207 	}
7208 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_FREQ_LIM__A, 32, 0);
7209 	if (rc != 0) {
7210 		pr_err("error %d\n", rc);
7211 		goto rw_error;
7212 	}
7213 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_COUNT_LIM__A, 3, 0);
7214 	if (rc != 0) {
7215 		pr_err("error %d\n", rc);
7216 		goto rw_error;
7217 	}
7218 
7219 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__A, 12, 0);
7220 	if (rc != 0) {
7221 		pr_err("error %d\n", rc);
7222 		goto rw_error;
7223 	}
7224 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__A, 141, 0);
7225 	if (rc != 0) {
7226 		pr_err("error %d\n", rc);
7227 		goto rw_error;
7228 	}
7229 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET1__A, 7, 0);
7230 	if (rc != 0) {
7231 		pr_err("error %d\n", rc);
7232 		goto rw_error;
7233 	}
7234 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET2__A, 0, 0);
7235 	if (rc != 0) {
7236 		pr_err("error %d\n", rc);
7237 		goto rw_error;
7238 	}
7239 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET3__A, (u16)(-15), 0);
7240 	if (rc != 0) {
7241 		pr_err("error %d\n", rc);
7242 		goto rw_error;
7243 	}
7244 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET4__A, (u16)(-45), 0);
7245 	if (rc != 0) {
7246 		pr_err("error %d\n", rc);
7247 		goto rw_error;
7248 	}
7249 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A, (u16)(-80), 0);
7250 	if (rc != 0) {
7251 		pr_err("error %d\n", rc);
7252 		goto rw_error;
7253 	}
7254 
7255 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CA_FINE__A, 15, 0);
7256 	if (rc != 0) {
7257 		pr_err("error %d\n", rc);
7258 		goto rw_error;
7259 	}
7260 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CA_COARSE__A, 40, 0);
7261 	if (rc != 0) {
7262 		pr_err("error %d\n", rc);
7263 		goto rw_error;
7264 	}
7265 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CP_FINE__A, 2, 0);
7266 	if (rc != 0) {
7267 		pr_err("error %d\n", rc);
7268 		goto rw_error;
7269 	}
7270 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CP_MEDIUM__A, 30, 0);
7271 	if (rc != 0) {
7272 		pr_err("error %d\n", rc);
7273 		goto rw_error;
7274 	}
7275 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CP_COARSE__A, 255, 0);
7276 	if (rc != 0) {
7277 		pr_err("error %d\n", rc);
7278 		goto rw_error;
7279 	}
7280 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CI_FINE__A, 2, 0);
7281 	if (rc != 0) {
7282 		pr_err("error %d\n", rc);
7283 		goto rw_error;
7284 	}
7285 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CI_MEDIUM__A, 15, 0);
7286 	if (rc != 0) {
7287 		pr_err("error %d\n", rc);
7288 		goto rw_error;
7289 	}
7290 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CI_COARSE__A, 80, 0);
7291 	if (rc != 0) {
7292 		pr_err("error %d\n", rc);
7293 		goto rw_error;
7294 	}
7295 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EP_FINE__A, 12, 0);
7296 	if (rc != 0) {
7297 		pr_err("error %d\n", rc);
7298 		goto rw_error;
7299 	}
7300 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EP_MEDIUM__A, 24, 0);
7301 	if (rc != 0) {
7302 		pr_err("error %d\n", rc);
7303 		goto rw_error;
7304 	}
7305 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EP_COARSE__A, 24, 0);
7306 	if (rc != 0) {
7307 		pr_err("error %d\n", rc);
7308 		goto rw_error;
7309 	}
7310 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EI_FINE__A, 12, 0);
7311 	if (rc != 0) {
7312 		pr_err("error %d\n", rc);
7313 		goto rw_error;
7314 	}
7315 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EI_MEDIUM__A, 16, 0);
7316 	if (rc != 0) {
7317 		pr_err("error %d\n", rc);
7318 		goto rw_error;
7319 	}
7320 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EI_COARSE__A, 16, 0);
7321 	if (rc != 0) {
7322 		pr_err("error %d\n", rc);
7323 		goto rw_error;
7324 	}
7325 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF_FINE__A, 16, 0);
7326 	if (rc != 0) {
7327 		pr_err("error %d\n", rc);
7328 		goto rw_error;
7329 	}
7330 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF_MEDIUM__A, 48, 0);
7331 	if (rc != 0) {
7332 		pr_err("error %d\n", rc);
7333 		goto rw_error;
7334 	}
7335 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF_COARSE__A, 160, 0);
7336 	if (rc != 0) {
7337 		pr_err("error %d\n", rc);
7338 		goto rw_error;
7339 	}
7340 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF1_FINE__A, 5, 0);
7341 	if (rc != 0) {
7342 		pr_err("error %d\n", rc);
7343 		goto rw_error;
7344 	}
7345 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF1_MEDIUM__A, 15, 0);
7346 	if (rc != 0) {
7347 		pr_err("error %d\n", rc);
7348 		goto rw_error;
7349 	}
7350 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF1_COARSE__A, 32, 0);
7351 	if (rc != 0) {
7352 		pr_err("error %d\n", rc);
7353 		goto rw_error;
7354 	}
7355 
7356 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_SL_SIG_POWER__A, 43008, 0);
7357 	if (rc != 0) {
7358 		pr_err("error %d\n", rc);
7359 		goto rw_error;
7360 	}
7361 
7362 	return 0;
7363 rw_error:
7364 	return rc;
7365 }
7366 
7367 /*============================================================================*/
7368 
7369 /*
7370 * \fn int set_qam128 ()
7371 * \brief QAM128 specific setup
7372 * \param demod: instance of demod.
7373 * \return int.
7374 */
7375 static int set_qam128(struct drx_demod_instance *demod)
7376 {
7377 	struct i2c_device_addr *dev_addr = demod->my_i2c_dev_addr;
7378 	int rc;
7379 	static const u8 qam_dq_qual_fun[] = {
7380 		DRXJ_16TO8(6),	/* fun0  */
7381 		DRXJ_16TO8(6),	/* fun1  */
7382 		DRXJ_16TO8(6),	/* fun2  */
7383 		DRXJ_16TO8(6),	/* fun3  */
7384 		DRXJ_16TO8(9),	/* fun4  */
7385 		DRXJ_16TO8(9),	/* fun5  */
7386 	};
7387 	static const u8 qam_eq_cma_rad[] = {
7388 		DRXJ_16TO8(6164),	/* RAD0  */
7389 		DRXJ_16TO8(6598),	/* RAD1  */
7390 		DRXJ_16TO8(6394),	/* RAD2  */
7391 		DRXJ_16TO8(6409),	/* RAD3  */
7392 		DRXJ_16TO8(6656),	/* RAD4  */
7393 		DRXJ_16TO8(7238),	/* RAD5  */
7394 	};
7395 
7396 	rc = drxdap_fasi_write_block(dev_addr, QAM_DQ_QUAL_FUN0__A, sizeof(qam_dq_qual_fun), ((u8 *)qam_dq_qual_fun), 0);
7397 	if (rc != 0) {
7398 		pr_err("error %d\n", rc);
7399 		goto rw_error;
7400 	}
7401 	rc = drxdap_fasi_write_block(dev_addr, SCU_RAM_QAM_EQ_CMA_RAD0__A, sizeof(qam_eq_cma_rad), ((u8 *)qam_eq_cma_rad), 0);
7402 	if (rc != 0) {
7403 		pr_err("error %d\n", rc);
7404 		goto rw_error;
7405 	}
7406 
7407 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_RTH__A, 50, 0);
7408 	if (rc != 0) {
7409 		pr_err("error %d\n", rc);
7410 		goto rw_error;
7411 	}
7412 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_FTH__A, 60, 0);
7413 	if (rc != 0) {
7414 		pr_err("error %d\n", rc);
7415 		goto rw_error;
7416 	}
7417 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_PTH__A, 100, 0);
7418 	if (rc != 0) {
7419 		pr_err("error %d\n", rc);
7420 		goto rw_error;
7421 	}
7422 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_QTH__A, 140, 0);
7423 	if (rc != 0) {
7424 		pr_err("error %d\n", rc);
7425 		goto rw_error;
7426 	}
7427 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_CTH__A, 80, 0);
7428 	if (rc != 0) {
7429 		pr_err("error %d\n", rc);
7430 		goto rw_error;
7431 	}
7432 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_MTH__A, 100, 0);
7433 	if (rc != 0) {
7434 		pr_err("error %d\n", rc);
7435 		goto rw_error;
7436 	}
7437 
7438 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_RATE_LIM__A, 40, 0);
7439 	if (rc != 0) {
7440 		pr_err("error %d\n", rc);
7441 		goto rw_error;
7442 	}
7443 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_FREQ_LIM__A, 32, 0);
7444 	if (rc != 0) {
7445 		pr_err("error %d\n", rc);
7446 		goto rw_error;
7447 	}
7448 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_COUNT_LIM__A, 3, 0);
7449 	if (rc != 0) {
7450 		pr_err("error %d\n", rc);
7451 		goto rw_error;
7452 	}
7453 
7454 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__A, 8, 0);
7455 	if (rc != 0) {
7456 		pr_err("error %d\n", rc);
7457 		goto rw_error;
7458 	}
7459 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__A, 65, 0);
7460 	if (rc != 0) {
7461 		pr_err("error %d\n", rc);
7462 		goto rw_error;
7463 	}
7464 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET1__A, 5, 0);
7465 	if (rc != 0) {
7466 		pr_err("error %d\n", rc);
7467 		goto rw_error;
7468 	}
7469 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET2__A, 3, 0);
7470 	if (rc != 0) {
7471 		pr_err("error %d\n", rc);
7472 		goto rw_error;
7473 	}
7474 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET3__A, (u16)(-1), 0);
7475 	if (rc != 0) {
7476 		pr_err("error %d\n", rc);
7477 		goto rw_error;
7478 	}
7479 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET4__A, 12, 0);
7480 	if (rc != 0) {
7481 		pr_err("error %d\n", rc);
7482 		goto rw_error;
7483 	}
7484 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A, (u16)(-23), 0);
7485 	if (rc != 0) {
7486 		pr_err("error %d\n", rc);
7487 		goto rw_error;
7488 	}
7489 
7490 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CA_FINE__A, 15, 0);
7491 	if (rc != 0) {
7492 		pr_err("error %d\n", rc);
7493 		goto rw_error;
7494 	}
7495 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CA_COARSE__A, 40, 0);
7496 	if (rc != 0) {
7497 		pr_err("error %d\n", rc);
7498 		goto rw_error;
7499 	}
7500 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CP_FINE__A, 2, 0);
7501 	if (rc != 0) {
7502 		pr_err("error %d\n", rc);
7503 		goto rw_error;
7504 	}
7505 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CP_MEDIUM__A, 40, 0);
7506 	if (rc != 0) {
7507 		pr_err("error %d\n", rc);
7508 		goto rw_error;
7509 	}
7510 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CP_COARSE__A, 255, 0);
7511 	if (rc != 0) {
7512 		pr_err("error %d\n", rc);
7513 		goto rw_error;
7514 	}
7515 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CI_FINE__A, 2, 0);
7516 	if (rc != 0) {
7517 		pr_err("error %d\n", rc);
7518 		goto rw_error;
7519 	}
7520 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CI_MEDIUM__A, 20, 0);
7521 	if (rc != 0) {
7522 		pr_err("error %d\n", rc);
7523 		goto rw_error;
7524 	}
7525 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CI_COARSE__A, 80, 0);
7526 	if (rc != 0) {
7527 		pr_err("error %d\n", rc);
7528 		goto rw_error;
7529 	}
7530 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EP_FINE__A, 12, 0);
7531 	if (rc != 0) {
7532 		pr_err("error %d\n", rc);
7533 		goto rw_error;
7534 	}
7535 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EP_MEDIUM__A, 24, 0);
7536 	if (rc != 0) {
7537 		pr_err("error %d\n", rc);
7538 		goto rw_error;
7539 	}
7540 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EP_COARSE__A, 24, 0);
7541 	if (rc != 0) {
7542 		pr_err("error %d\n", rc);
7543 		goto rw_error;
7544 	}
7545 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EI_FINE__A, 12, 0);
7546 	if (rc != 0) {
7547 		pr_err("error %d\n", rc);
7548 		goto rw_error;
7549 	}
7550 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EI_MEDIUM__A, 16, 0);
7551 	if (rc != 0) {
7552 		pr_err("error %d\n", rc);
7553 		goto rw_error;
7554 	}
7555 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EI_COARSE__A, 16, 0);
7556 	if (rc != 0) {
7557 		pr_err("error %d\n", rc);
7558 		goto rw_error;
7559 	}
7560 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF_FINE__A, 16, 0);
7561 	if (rc != 0) {
7562 		pr_err("error %d\n", rc);
7563 		goto rw_error;
7564 	}
7565 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF_MEDIUM__A, 32, 0);
7566 	if (rc != 0) {
7567 		pr_err("error %d\n", rc);
7568 		goto rw_error;
7569 	}
7570 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF_COARSE__A, 144, 0);
7571 	if (rc != 0) {
7572 		pr_err("error %d\n", rc);
7573 		goto rw_error;
7574 	}
7575 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF1_FINE__A, 5, 0);
7576 	if (rc != 0) {
7577 		pr_err("error %d\n", rc);
7578 		goto rw_error;
7579 	}
7580 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF1_MEDIUM__A, 15, 0);
7581 	if (rc != 0) {
7582 		pr_err("error %d\n", rc);
7583 		goto rw_error;
7584 	}
7585 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF1_COARSE__A, 16, 0);
7586 	if (rc != 0) {
7587 		pr_err("error %d\n", rc);
7588 		goto rw_error;
7589 	}
7590 
7591 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_SL_SIG_POWER__A, 20992, 0);
7592 	if (rc != 0) {
7593 		pr_err("error %d\n", rc);
7594 		goto rw_error;
7595 	}
7596 
7597 	return 0;
7598 rw_error:
7599 	return rc;
7600 }
7601 
7602 /*============================================================================*/
7603 
7604 /*
7605 * \fn int set_qam256 ()
7606 * \brief QAM256 specific setup
7607 * \param demod: instance of demod.
7608 * \return int.
7609 */
7610 static int set_qam256(struct drx_demod_instance *demod)
7611 {
7612 	struct i2c_device_addr *dev_addr = demod->my_i2c_dev_addr;
7613 	int rc;
7614 	static const u8 qam_dq_qual_fun[] = {
7615 		DRXJ_16TO8(8),	/* fun0  */
7616 		DRXJ_16TO8(8),	/* fun1  */
7617 		DRXJ_16TO8(8),	/* fun2  */
7618 		DRXJ_16TO8(8),	/* fun3  */
7619 		DRXJ_16TO8(12),	/* fun4  */
7620 		DRXJ_16TO8(12),	/* fun5  */
7621 	};
7622 	static const u8 qam_eq_cma_rad[] = {
7623 		DRXJ_16TO8(12345),	/* RAD0  */
7624 		DRXJ_16TO8(12345),	/* RAD1  */
7625 		DRXJ_16TO8(13626),	/* RAD2  */
7626 		DRXJ_16TO8(12931),	/* RAD3  */
7627 		DRXJ_16TO8(14719),	/* RAD4  */
7628 		DRXJ_16TO8(15356),	/* RAD5  */
7629 	};
7630 
7631 	rc = drxdap_fasi_write_block(dev_addr, QAM_DQ_QUAL_FUN0__A, sizeof(qam_dq_qual_fun), ((u8 *)qam_dq_qual_fun), 0);
7632 	if (rc != 0) {
7633 		pr_err("error %d\n", rc);
7634 		goto rw_error;
7635 	}
7636 	rc = drxdap_fasi_write_block(dev_addr, SCU_RAM_QAM_EQ_CMA_RAD0__A, sizeof(qam_eq_cma_rad), ((u8 *)qam_eq_cma_rad), 0);
7637 	if (rc != 0) {
7638 		pr_err("error %d\n", rc);
7639 		goto rw_error;
7640 	}
7641 
7642 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_RTH__A, 50, 0);
7643 	if (rc != 0) {
7644 		pr_err("error %d\n", rc);
7645 		goto rw_error;
7646 	}
7647 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_FTH__A, 60, 0);
7648 	if (rc != 0) {
7649 		pr_err("error %d\n", rc);
7650 		goto rw_error;
7651 	}
7652 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_PTH__A, 100, 0);
7653 	if (rc != 0) {
7654 		pr_err("error %d\n", rc);
7655 		goto rw_error;
7656 	}
7657 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_QTH__A, 150, 0);
7658 	if (rc != 0) {
7659 		pr_err("error %d\n", rc);
7660 		goto rw_error;
7661 	}
7662 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_CTH__A, 80, 0);
7663 	if (rc != 0) {
7664 		pr_err("error %d\n", rc);
7665 		goto rw_error;
7666 	}
7667 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_MTH__A, 110, 0);
7668 	if (rc != 0) {
7669 		pr_err("error %d\n", rc);
7670 		goto rw_error;
7671 	}
7672 
7673 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_RATE_LIM__A, 40, 0);
7674 	if (rc != 0) {
7675 		pr_err("error %d\n", rc);
7676 		goto rw_error;
7677 	}
7678 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_FREQ_LIM__A, 16, 0);
7679 	if (rc != 0) {
7680 		pr_err("error %d\n", rc);
7681 		goto rw_error;
7682 	}
7683 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_COUNT_LIM__A, 3, 0);
7684 	if (rc != 0) {
7685 		pr_err("error %d\n", rc);
7686 		goto rw_error;
7687 	}
7688 
7689 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__A, 8, 0);
7690 	if (rc != 0) {
7691 		pr_err("error %d\n", rc);
7692 		goto rw_error;
7693 	}
7694 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__A, 74, 0);
7695 	if (rc != 0) {
7696 		pr_err("error %d\n", rc);
7697 		goto rw_error;
7698 	}
7699 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET1__A, 18, 0);
7700 	if (rc != 0) {
7701 		pr_err("error %d\n", rc);
7702 		goto rw_error;
7703 	}
7704 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET2__A, 13, 0);
7705 	if (rc != 0) {
7706 		pr_err("error %d\n", rc);
7707 		goto rw_error;
7708 	}
7709 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET3__A, 7, 0);
7710 	if (rc != 0) {
7711 		pr_err("error %d\n", rc);
7712 		goto rw_error;
7713 	}
7714 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET4__A, 0, 0);
7715 	if (rc != 0) {
7716 		pr_err("error %d\n", rc);
7717 		goto rw_error;
7718 	}
7719 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A, (u16)(-8), 0);
7720 	if (rc != 0) {
7721 		pr_err("error %d\n", rc);
7722 		goto rw_error;
7723 	}
7724 
7725 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CA_FINE__A, 15, 0);
7726 	if (rc != 0) {
7727 		pr_err("error %d\n", rc);
7728 		goto rw_error;
7729 	}
7730 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CA_COARSE__A, 40, 0);
7731 	if (rc != 0) {
7732 		pr_err("error %d\n", rc);
7733 		goto rw_error;
7734 	}
7735 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CP_FINE__A, 2, 0);
7736 	if (rc != 0) {
7737 		pr_err("error %d\n", rc);
7738 		goto rw_error;
7739 	}
7740 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CP_MEDIUM__A, 50, 0);
7741 	if (rc != 0) {
7742 		pr_err("error %d\n", rc);
7743 		goto rw_error;
7744 	}
7745 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CP_COARSE__A, 255, 0);
7746 	if (rc != 0) {
7747 		pr_err("error %d\n", rc);
7748 		goto rw_error;
7749 	}
7750 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CI_FINE__A, 2, 0);
7751 	if (rc != 0) {
7752 		pr_err("error %d\n", rc);
7753 		goto rw_error;
7754 	}
7755 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CI_MEDIUM__A, 25, 0);
7756 	if (rc != 0) {
7757 		pr_err("error %d\n", rc);
7758 		goto rw_error;
7759 	}
7760 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CI_COARSE__A, 80, 0);
7761 	if (rc != 0) {
7762 		pr_err("error %d\n", rc);
7763 		goto rw_error;
7764 	}
7765 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EP_FINE__A, 12, 0);
7766 	if (rc != 0) {
7767 		pr_err("error %d\n", rc);
7768 		goto rw_error;
7769 	}
7770 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EP_MEDIUM__A, 24, 0);
7771 	if (rc != 0) {
7772 		pr_err("error %d\n", rc);
7773 		goto rw_error;
7774 	}
7775 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EP_COARSE__A, 24, 0);
7776 	if (rc != 0) {
7777 		pr_err("error %d\n", rc);
7778 		goto rw_error;
7779 	}
7780 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EI_FINE__A, 12, 0);
7781 	if (rc != 0) {
7782 		pr_err("error %d\n", rc);
7783 		goto rw_error;
7784 	}
7785 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EI_MEDIUM__A, 16, 0);
7786 	if (rc != 0) {
7787 		pr_err("error %d\n", rc);
7788 		goto rw_error;
7789 	}
7790 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EI_COARSE__A, 16, 0);
7791 	if (rc != 0) {
7792 		pr_err("error %d\n", rc);
7793 		goto rw_error;
7794 	}
7795 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF_FINE__A, 16, 0);
7796 	if (rc != 0) {
7797 		pr_err("error %d\n", rc);
7798 		goto rw_error;
7799 	}
7800 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF_MEDIUM__A, 48, 0);
7801 	if (rc != 0) {
7802 		pr_err("error %d\n", rc);
7803 		goto rw_error;
7804 	}
7805 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF_COARSE__A, 80, 0);
7806 	if (rc != 0) {
7807 		pr_err("error %d\n", rc);
7808 		goto rw_error;
7809 	}
7810 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF1_FINE__A, 5, 0);
7811 	if (rc != 0) {
7812 		pr_err("error %d\n", rc);
7813 		goto rw_error;
7814 	}
7815 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF1_MEDIUM__A, 15, 0);
7816 	if (rc != 0) {
7817 		pr_err("error %d\n", rc);
7818 		goto rw_error;
7819 	}
7820 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF1_COARSE__A, 16, 0);
7821 	if (rc != 0) {
7822 		pr_err("error %d\n", rc);
7823 		goto rw_error;
7824 	}
7825 
7826 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_SL_SIG_POWER__A, 43520, 0);
7827 	if (rc != 0) {
7828 		pr_err("error %d\n", rc);
7829 		goto rw_error;
7830 	}
7831 
7832 	return 0;
7833 rw_error:
7834 	return rc;
7835 }
7836 
7837 /*============================================================================*/
7838 #define QAM_SET_OP_ALL 0x1
7839 #define QAM_SET_OP_CONSTELLATION 0x2
7840 #define QAM_SET_OP_SPECTRUM 0X4
7841 
7842 /*
7843 * \fn int set_qam ()
7844 * \brief Set QAM demod.
7845 * \param demod:   instance of demod.
7846 * \param channel: pointer to channel data.
7847 * \return int.
7848 */
7849 static int
7850 set_qam(struct drx_demod_instance *demod,
7851 	struct drx_channel *channel, s32 tuner_freq_offset, u32 op)
7852 {
7853 	struct i2c_device_addr *dev_addr = NULL;
7854 	struct drxj_data *ext_attr = NULL;
7855 	struct drx_common_attr *common_attr = NULL;
7856 	int rc;
7857 	u32 adc_frequency = 0;
7858 	u32 iqm_rc_rate = 0;
7859 	u16 cmd_result = 0;
7860 	u16 lc_symbol_freq = 0;
7861 	u16 iqm_rc_stretch = 0;
7862 	u16 set_env_parameters = 0;
7863 	u16 set_param_parameters[2] = { 0 };
7864 	struct drxjscu_cmd cmd_scu = { /* command      */ 0,
7865 		/* parameter_len */ 0,
7866 		/* result_len    */ 0,
7867 		/* parameter    */ NULL,
7868 		/* result       */ NULL
7869 	};
7870 	static const u8 qam_a_taps[] = {
7871 		DRXJ_16TO8(-1),	/* re0  */
7872 		DRXJ_16TO8(1),	/* re1  */
7873 		DRXJ_16TO8(1),	/* re2  */
7874 		DRXJ_16TO8(-1),	/* re3  */
7875 		DRXJ_16TO8(-1),	/* re4  */
7876 		DRXJ_16TO8(2),	/* re5  */
7877 		DRXJ_16TO8(1),	/* re6  */
7878 		DRXJ_16TO8(-2),	/* re7  */
7879 		DRXJ_16TO8(0),	/* re8  */
7880 		DRXJ_16TO8(3),	/* re9  */
7881 		DRXJ_16TO8(-1),	/* re10 */
7882 		DRXJ_16TO8(-3),	/* re11 */
7883 		DRXJ_16TO8(4),	/* re12 */
7884 		DRXJ_16TO8(1),	/* re13 */
7885 		DRXJ_16TO8(-8),	/* re14 */
7886 		DRXJ_16TO8(4),	/* re15 */
7887 		DRXJ_16TO8(13),	/* re16 */
7888 		DRXJ_16TO8(-13),	/* re17 */
7889 		DRXJ_16TO8(-19),	/* re18 */
7890 		DRXJ_16TO8(28),	/* re19 */
7891 		DRXJ_16TO8(25),	/* re20 */
7892 		DRXJ_16TO8(-53),	/* re21 */
7893 		DRXJ_16TO8(-31),	/* re22 */
7894 		DRXJ_16TO8(96),	/* re23 */
7895 		DRXJ_16TO8(37),	/* re24 */
7896 		DRXJ_16TO8(-190),	/* re25 */
7897 		DRXJ_16TO8(-40),	/* re26 */
7898 		DRXJ_16TO8(619)	/* re27 */
7899 	};
7900 	static const u8 qam_b64_taps[] = {
7901 		DRXJ_16TO8(0),	/* re0  */
7902 		DRXJ_16TO8(-2),	/* re1  */
7903 		DRXJ_16TO8(1),	/* re2  */
7904 		DRXJ_16TO8(2),	/* re3  */
7905 		DRXJ_16TO8(-2),	/* re4  */
7906 		DRXJ_16TO8(0),	/* re5  */
7907 		DRXJ_16TO8(4),	/* re6  */
7908 		DRXJ_16TO8(-2),	/* re7  */
7909 		DRXJ_16TO8(-4),	/* re8  */
7910 		DRXJ_16TO8(4),	/* re9  */
7911 		DRXJ_16TO8(3),	/* re10 */
7912 		DRXJ_16TO8(-6),	/* re11 */
7913 		DRXJ_16TO8(0),	/* re12 */
7914 		DRXJ_16TO8(6),	/* re13 */
7915 		DRXJ_16TO8(-5),	/* re14 */
7916 		DRXJ_16TO8(-3),	/* re15 */
7917 		DRXJ_16TO8(11),	/* re16 */
7918 		DRXJ_16TO8(-4),	/* re17 */
7919 		DRXJ_16TO8(-19),	/* re18 */
7920 		DRXJ_16TO8(19),	/* re19 */
7921 		DRXJ_16TO8(28),	/* re20 */
7922 		DRXJ_16TO8(-45),	/* re21 */
7923 		DRXJ_16TO8(-36),	/* re22 */
7924 		DRXJ_16TO8(90),	/* re23 */
7925 		DRXJ_16TO8(42),	/* re24 */
7926 		DRXJ_16TO8(-185),	/* re25 */
7927 		DRXJ_16TO8(-46),	/* re26 */
7928 		DRXJ_16TO8(614)	/* re27 */
7929 	};
7930 	static const u8 qam_b256_taps[] = {
7931 		DRXJ_16TO8(-2),	/* re0  */
7932 		DRXJ_16TO8(4),	/* re1  */
7933 		DRXJ_16TO8(1),	/* re2  */
7934 		DRXJ_16TO8(-4),	/* re3  */
7935 		DRXJ_16TO8(0),	/* re4  */
7936 		DRXJ_16TO8(4),	/* re5  */
7937 		DRXJ_16TO8(-2),	/* re6  */
7938 		DRXJ_16TO8(-4),	/* re7  */
7939 		DRXJ_16TO8(5),	/* re8  */
7940 		DRXJ_16TO8(2),	/* re9  */
7941 		DRXJ_16TO8(-8),	/* re10 */
7942 		DRXJ_16TO8(2),	/* re11 */
7943 		DRXJ_16TO8(11),	/* re12 */
7944 		DRXJ_16TO8(-8),	/* re13 */
7945 		DRXJ_16TO8(-15),	/* re14 */
7946 		DRXJ_16TO8(16),	/* re15 */
7947 		DRXJ_16TO8(19),	/* re16 */
7948 		DRXJ_16TO8(-27),	/* re17 */
7949 		DRXJ_16TO8(-22),	/* re18 */
7950 		DRXJ_16TO8(44),	/* re19 */
7951 		DRXJ_16TO8(26),	/* re20 */
7952 		DRXJ_16TO8(-69),	/* re21 */
7953 		DRXJ_16TO8(-28),	/* re22 */
7954 		DRXJ_16TO8(110),	/* re23 */
7955 		DRXJ_16TO8(31),	/* re24 */
7956 		DRXJ_16TO8(-201),	/* re25 */
7957 		DRXJ_16TO8(-32),	/* re26 */
7958 		DRXJ_16TO8(628)	/* re27 */
7959 	};
7960 	static const u8 qam_c_taps[] = {
7961 		DRXJ_16TO8(-3),	/* re0  */
7962 		DRXJ_16TO8(3),	/* re1  */
7963 		DRXJ_16TO8(2),	/* re2  */
7964 		DRXJ_16TO8(-4),	/* re3  */
7965 		DRXJ_16TO8(0),	/* re4  */
7966 		DRXJ_16TO8(4),	/* re5  */
7967 		DRXJ_16TO8(-1),	/* re6  */
7968 		DRXJ_16TO8(-4),	/* re7  */
7969 		DRXJ_16TO8(3),	/* re8  */
7970 		DRXJ_16TO8(3),	/* re9  */
7971 		DRXJ_16TO8(-5),	/* re10 */
7972 		DRXJ_16TO8(0),	/* re11 */
7973 		DRXJ_16TO8(9),	/* re12 */
7974 		DRXJ_16TO8(-4),	/* re13 */
7975 		DRXJ_16TO8(-12),	/* re14 */
7976 		DRXJ_16TO8(10),	/* re15 */
7977 		DRXJ_16TO8(16),	/* re16 */
7978 		DRXJ_16TO8(-21),	/* re17 */
7979 		DRXJ_16TO8(-20),	/* re18 */
7980 		DRXJ_16TO8(37),	/* re19 */
7981 		DRXJ_16TO8(25),	/* re20 */
7982 		DRXJ_16TO8(-62),	/* re21 */
7983 		DRXJ_16TO8(-28),	/* re22 */
7984 		DRXJ_16TO8(105),	/* re23 */
7985 		DRXJ_16TO8(31),	/* re24 */
7986 		DRXJ_16TO8(-197),	/* re25 */
7987 		DRXJ_16TO8(-33),	/* re26 */
7988 		DRXJ_16TO8(626)	/* re27 */
7989 	};
7990 
7991 	dev_addr = demod->my_i2c_dev_addr;
7992 	ext_attr = (struct drxj_data *) demod->my_ext_attr;
7993 	common_attr = (struct drx_common_attr *) demod->my_common_attr;
7994 
7995 	if ((op & QAM_SET_OP_ALL) || (op & QAM_SET_OP_CONSTELLATION)) {
7996 		if (ext_attr->standard == DRX_STANDARD_ITU_B) {
7997 			switch (channel->constellation) {
7998 			case DRX_CONSTELLATION_QAM256:
7999 				iqm_rc_rate = 0x00AE3562;
8000 				lc_symbol_freq =
8001 				    QAM_LC_SYMBOL_FREQ_FREQ_QAM_B_256;
8002 				channel->symbolrate = 5360537;
8003 				iqm_rc_stretch = IQM_RC_STRETCH_QAM_B_256;
8004 				break;
8005 			case DRX_CONSTELLATION_QAM64:
8006 				iqm_rc_rate = 0x00C05A0E;
8007 				lc_symbol_freq = 409;
8008 				channel->symbolrate = 5056941;
8009 				iqm_rc_stretch = IQM_RC_STRETCH_QAM_B_64;
8010 				break;
8011 			default:
8012 				return -EINVAL;
8013 			}
8014 		} else {
8015 			adc_frequency = (common_attr->sys_clock_freq * 1000) / 3;
8016 			if (channel->symbolrate == 0) {
8017 				pr_err("error: channel symbolrate is zero!\n");
8018 				return -EIO;
8019 			}
8020 			iqm_rc_rate =
8021 			    (adc_frequency / channel->symbolrate) * (1 << 21) +
8022 			    (frac28
8023 			     ((adc_frequency % channel->symbolrate),
8024 			      channel->symbolrate) >> 7) - (1 << 23);
8025 			lc_symbol_freq =
8026 			    (u16) (frac28
8027 				     (channel->symbolrate +
8028 				      (adc_frequency >> 13),
8029 				      adc_frequency) >> 16);
8030 			if (lc_symbol_freq > 511)
8031 				lc_symbol_freq = 511;
8032 
8033 			iqm_rc_stretch = 21;
8034 		}
8035 
8036 		if (ext_attr->standard == DRX_STANDARD_ITU_A) {
8037 			set_env_parameters = QAM_TOP_ANNEX_A;	/* annex             */
8038 			set_param_parameters[0] = channel->constellation;	/* constellation     */
8039 			set_param_parameters[1] = DRX_INTERLEAVEMODE_I12_J17;	/* interleave mode   */
8040 		} else if (ext_attr->standard == DRX_STANDARD_ITU_B) {
8041 			set_env_parameters = QAM_TOP_ANNEX_B;	/* annex             */
8042 			set_param_parameters[0] = channel->constellation;	/* constellation     */
8043 			set_param_parameters[1] = channel->interleavemode;	/* interleave mode   */
8044 		} else if (ext_attr->standard == DRX_STANDARD_ITU_C) {
8045 			set_env_parameters = QAM_TOP_ANNEX_C;	/* annex             */
8046 			set_param_parameters[0] = channel->constellation;	/* constellation     */
8047 			set_param_parameters[1] = DRX_INTERLEAVEMODE_I12_J17;	/* interleave mode   */
8048 		} else {
8049 			return -EINVAL;
8050 		}
8051 	}
8052 
8053 	if (op & QAM_SET_OP_ALL) {
8054 		/*
8055 		   STEP 1: reset demodulator
8056 		   resets IQM, QAM and FEC HW blocks
8057 		   resets SCU variables
8058 		 */
8059 		/* stop all comm_exec */
8060 		rc = drxj_dap_write_reg16(dev_addr, FEC_COMM_EXEC__A, FEC_COMM_EXEC_STOP, 0);
8061 		if (rc != 0) {
8062 			pr_err("error %d\n", rc);
8063 			goto rw_error;
8064 		}
8065 		rc = drxj_dap_write_reg16(dev_addr, QAM_COMM_EXEC__A, QAM_COMM_EXEC_STOP, 0);
8066 		if (rc != 0) {
8067 			pr_err("error %d\n", rc);
8068 			goto rw_error;
8069 		}
8070 		rc = drxj_dap_write_reg16(dev_addr, IQM_FS_COMM_EXEC__A, IQM_FS_COMM_EXEC_STOP, 0);
8071 		if (rc != 0) {
8072 			pr_err("error %d\n", rc);
8073 			goto rw_error;
8074 		}
8075 		rc = drxj_dap_write_reg16(dev_addr, IQM_FD_COMM_EXEC__A, IQM_FD_COMM_EXEC_STOP, 0);
8076 		if (rc != 0) {
8077 			pr_err("error %d\n", rc);
8078 			goto rw_error;
8079 		}
8080 		rc = drxj_dap_write_reg16(dev_addr, IQM_RC_COMM_EXEC__A, IQM_RC_COMM_EXEC_STOP, 0);
8081 		if (rc != 0) {
8082 			pr_err("error %d\n", rc);
8083 			goto rw_error;
8084 		}
8085 		rc = drxj_dap_write_reg16(dev_addr, IQM_RT_COMM_EXEC__A, IQM_RT_COMM_EXEC_STOP, 0);
8086 		if (rc != 0) {
8087 			pr_err("error %d\n", rc);
8088 			goto rw_error;
8089 		}
8090 		rc = drxj_dap_write_reg16(dev_addr, IQM_CF_COMM_EXEC__A, IQM_CF_COMM_EXEC_STOP, 0);
8091 		if (rc != 0) {
8092 			pr_err("error %d\n", rc);
8093 			goto rw_error;
8094 		}
8095 
8096 		cmd_scu.command = SCU_RAM_COMMAND_STANDARD_QAM |
8097 		    SCU_RAM_COMMAND_CMD_DEMOD_RESET;
8098 		cmd_scu.parameter_len = 0;
8099 		cmd_scu.result_len = 1;
8100 		cmd_scu.parameter = NULL;
8101 		cmd_scu.result = &cmd_result;
8102 		rc = scu_command(dev_addr, &cmd_scu);
8103 		if (rc != 0) {
8104 			pr_err("error %d\n", rc);
8105 			goto rw_error;
8106 		}
8107 	}
8108 
8109 	if ((op & QAM_SET_OP_ALL) || (op & QAM_SET_OP_CONSTELLATION)) {
8110 		/*
8111 		   STEP 2: configure demodulator
8112 		   -set env
8113 		   -set params (resets IQM,QAM,FEC HW; initializes some SCU variables )
8114 		 */
8115 		cmd_scu.command = SCU_RAM_COMMAND_STANDARD_QAM |
8116 		    SCU_RAM_COMMAND_CMD_DEMOD_SET_ENV;
8117 		cmd_scu.parameter_len = 1;
8118 		cmd_scu.result_len = 1;
8119 		cmd_scu.parameter = &set_env_parameters;
8120 		cmd_scu.result = &cmd_result;
8121 		rc = scu_command(dev_addr, &cmd_scu);
8122 		if (rc != 0) {
8123 			pr_err("error %d\n", rc);
8124 			goto rw_error;
8125 		}
8126 
8127 		cmd_scu.command = SCU_RAM_COMMAND_STANDARD_QAM |
8128 		    SCU_RAM_COMMAND_CMD_DEMOD_SET_PARAM;
8129 		cmd_scu.parameter_len = 2;
8130 		cmd_scu.result_len = 1;
8131 		cmd_scu.parameter = set_param_parameters;
8132 		cmd_scu.result = &cmd_result;
8133 		rc = scu_command(dev_addr, &cmd_scu);
8134 		if (rc != 0) {
8135 			pr_err("error %d\n", rc);
8136 			goto rw_error;
8137 		}
8138 		/* set symbol rate */
8139 		rc = drxdap_fasi_write_reg32(dev_addr, IQM_RC_RATE_OFS_LO__A, iqm_rc_rate, 0);
8140 		if (rc != 0) {
8141 			pr_err("error %d\n", rc);
8142 			goto rw_error;
8143 		}
8144 		ext_attr->iqm_rc_rate_ofs = iqm_rc_rate;
8145 		rc = set_qam_measurement(demod, channel->constellation, channel->symbolrate);
8146 		if (rc != 0) {
8147 			pr_err("error %d\n", rc);
8148 			goto rw_error;
8149 		}
8150 	}
8151 	/* STEP 3: enable the system in a mode where the ADC provides valid signal
8152 	   setup constellation independent registers */
8153 	/* from qam_cmd.py script (qam_driver_b) */
8154 	/* TODO: remove re-writes of HW reset values */
8155 	if ((op & QAM_SET_OP_ALL) || (op & QAM_SET_OP_SPECTRUM)) {
8156 		rc = set_frequency(demod, channel, tuner_freq_offset);
8157 		if (rc != 0) {
8158 			pr_err("error %d\n", rc);
8159 			goto rw_error;
8160 		}
8161 	}
8162 
8163 	if ((op & QAM_SET_OP_ALL) || (op & QAM_SET_OP_CONSTELLATION)) {
8164 
8165 		rc = drxj_dap_write_reg16(dev_addr, QAM_LC_SYMBOL_FREQ__A, lc_symbol_freq, 0);
8166 		if (rc != 0) {
8167 			pr_err("error %d\n", rc);
8168 			goto rw_error;
8169 		}
8170 		rc = drxj_dap_write_reg16(dev_addr, IQM_RC_STRETCH__A, iqm_rc_stretch, 0);
8171 		if (rc != 0) {
8172 			pr_err("error %d\n", rc);
8173 			goto rw_error;
8174 		}
8175 	}
8176 
8177 	if (op & QAM_SET_OP_ALL) {
8178 		if (!ext_attr->has_lna) {
8179 			rc = drxj_dap_write_reg16(dev_addr, IQM_AF_AMUX__A, 0x02, 0);
8180 			if (rc != 0) {
8181 				pr_err("error %d\n", rc);
8182 				goto rw_error;
8183 			}
8184 		}
8185 		rc = drxj_dap_write_reg16(dev_addr, IQM_CF_SYMMETRIC__A, 0, 0);
8186 		if (rc != 0) {
8187 			pr_err("error %d\n", rc);
8188 			goto rw_error;
8189 		}
8190 		rc = drxj_dap_write_reg16(dev_addr, IQM_CF_MIDTAP__A, 3, 0);
8191 		if (rc != 0) {
8192 			pr_err("error %d\n", rc);
8193 			goto rw_error;
8194 		}
8195 		rc = drxj_dap_write_reg16(dev_addr, IQM_CF_OUT_ENA__A, IQM_CF_OUT_ENA_QAM__M, 0);
8196 		if (rc != 0) {
8197 			pr_err("error %d\n", rc);
8198 			goto rw_error;
8199 		}
8200 
8201 		rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_WR_RSV_0__A, 0x5f, 0);
8202 		if (rc != 0) {
8203 			pr_err("error %d\n", rc);
8204 			goto rw_error;
8205 		}	/* scu temporary shut down agc */
8206 
8207 		rc = drxj_dap_write_reg16(dev_addr, IQM_AF_SYNC_SEL__A, 3, 0);
8208 		if (rc != 0) {
8209 			pr_err("error %d\n", rc);
8210 			goto rw_error;
8211 		}
8212 		rc = drxj_dap_write_reg16(dev_addr, IQM_AF_CLP_LEN__A, 0, 0);
8213 		if (rc != 0) {
8214 			pr_err("error %d\n", rc);
8215 			goto rw_error;
8216 		}
8217 		rc = drxj_dap_write_reg16(dev_addr, IQM_AF_CLP_TH__A, 448, 0);
8218 		if (rc != 0) {
8219 			pr_err("error %d\n", rc);
8220 			goto rw_error;
8221 		}
8222 		rc = drxj_dap_write_reg16(dev_addr, IQM_AF_SNS_LEN__A, 0, 0);
8223 		if (rc != 0) {
8224 			pr_err("error %d\n", rc);
8225 			goto rw_error;
8226 		}
8227 		rc = drxj_dap_write_reg16(dev_addr, IQM_AF_PDREF__A, 4, 0);
8228 		if (rc != 0) {
8229 			pr_err("error %d\n", rc);
8230 			goto rw_error;
8231 		}
8232 		rc = drxj_dap_write_reg16(dev_addr, IQM_AF_STDBY__A, 0x10, 0);
8233 		if (rc != 0) {
8234 			pr_err("error %d\n", rc);
8235 			goto rw_error;
8236 		}
8237 		rc = drxj_dap_write_reg16(dev_addr, IQM_AF_PGA_GAIN__A, 11, 0);
8238 		if (rc != 0) {
8239 			pr_err("error %d\n", rc);
8240 			goto rw_error;
8241 		}
8242 
8243 		rc = drxj_dap_write_reg16(dev_addr, IQM_CF_POW_MEAS_LEN__A, 1, 0);
8244 		if (rc != 0) {
8245 			pr_err("error %d\n", rc);
8246 			goto rw_error;
8247 		}
8248 		rc = drxj_dap_write_reg16(dev_addr, IQM_CF_SCALE_SH__A, IQM_CF_SCALE_SH__PRE, 0);
8249 		if (rc != 0) {
8250 			pr_err("error %d\n", rc);
8251 			goto rw_error;
8252 		}	/*! reset default val ! */
8253 
8254 		rc = drxj_dap_write_reg16(dev_addr, QAM_SY_TIMEOUT__A, QAM_SY_TIMEOUT__PRE, 0);
8255 		if (rc != 0) {
8256 			pr_err("error %d\n", rc);
8257 			goto rw_error;
8258 		}	/*! reset default val ! */
8259 		if (ext_attr->standard == DRX_STANDARD_ITU_B) {
8260 			rc = drxj_dap_write_reg16(dev_addr, QAM_SY_SYNC_LWM__A, QAM_SY_SYNC_LWM__PRE, 0);
8261 			if (rc != 0) {
8262 				pr_err("error %d\n", rc);
8263 				goto rw_error;
8264 			}	/*! reset default val ! */
8265 			rc = drxj_dap_write_reg16(dev_addr, QAM_SY_SYNC_AWM__A, QAM_SY_SYNC_AWM__PRE, 0);
8266 			if (rc != 0) {
8267 				pr_err("error %d\n", rc);
8268 				goto rw_error;
8269 			}	/*! reset default val ! */
8270 			rc = drxj_dap_write_reg16(dev_addr, QAM_SY_SYNC_HWM__A, QAM_SY_SYNC_HWM__PRE, 0);
8271 			if (rc != 0) {
8272 				pr_err("error %d\n", rc);
8273 				goto rw_error;
8274 			}	/*! reset default val ! */
8275 		} else {
8276 			switch (channel->constellation) {
8277 			case DRX_CONSTELLATION_QAM16:
8278 			case DRX_CONSTELLATION_QAM64:
8279 			case DRX_CONSTELLATION_QAM256:
8280 				rc = drxj_dap_write_reg16(dev_addr, QAM_SY_SYNC_LWM__A, 0x03, 0);
8281 				if (rc != 0) {
8282 					pr_err("error %d\n", rc);
8283 					goto rw_error;
8284 				}
8285 				rc = drxj_dap_write_reg16(dev_addr, QAM_SY_SYNC_AWM__A, 0x04, 0);
8286 				if (rc != 0) {
8287 					pr_err("error %d\n", rc);
8288 					goto rw_error;
8289 				}
8290 				rc = drxj_dap_write_reg16(dev_addr, QAM_SY_SYNC_HWM__A, QAM_SY_SYNC_HWM__PRE, 0);
8291 				if (rc != 0) {
8292 					pr_err("error %d\n", rc);
8293 					goto rw_error;
8294 				}	/*! reset default val ! */
8295 				break;
8296 			case DRX_CONSTELLATION_QAM32:
8297 			case DRX_CONSTELLATION_QAM128:
8298 				rc = drxj_dap_write_reg16(dev_addr, QAM_SY_SYNC_LWM__A, 0x03, 0);
8299 				if (rc != 0) {
8300 					pr_err("error %d\n", rc);
8301 					goto rw_error;
8302 				}
8303 				rc = drxj_dap_write_reg16(dev_addr, QAM_SY_SYNC_AWM__A, 0x05, 0);
8304 				if (rc != 0) {
8305 					pr_err("error %d\n", rc);
8306 					goto rw_error;
8307 				}
8308 				rc = drxj_dap_write_reg16(dev_addr, QAM_SY_SYNC_HWM__A, 0x06, 0);
8309 				if (rc != 0) {
8310 					pr_err("error %d\n", rc);
8311 					goto rw_error;
8312 				}
8313 				break;
8314 			default:
8315 				return -EIO;
8316 			}	/* switch */
8317 		}
8318 
8319 		rc = drxj_dap_write_reg16(dev_addr, QAM_LC_MODE__A, QAM_LC_MODE__PRE, 0);
8320 		if (rc != 0) {
8321 			pr_err("error %d\n", rc);
8322 			goto rw_error;
8323 		}	/*! reset default val ! */
8324 		rc = drxj_dap_write_reg16(dev_addr, QAM_LC_RATE_LIMIT__A, 3, 0);
8325 		if (rc != 0) {
8326 			pr_err("error %d\n", rc);
8327 			goto rw_error;
8328 		}
8329 		rc = drxj_dap_write_reg16(dev_addr, QAM_LC_LPF_FACTORP__A, 4, 0);
8330 		if (rc != 0) {
8331 			pr_err("error %d\n", rc);
8332 			goto rw_error;
8333 		}
8334 		rc = drxj_dap_write_reg16(dev_addr, QAM_LC_LPF_FACTORI__A, 4, 0);
8335 		if (rc != 0) {
8336 			pr_err("error %d\n", rc);
8337 			goto rw_error;
8338 		}
8339 		rc = drxj_dap_write_reg16(dev_addr, QAM_LC_MODE__A, 7, 0);
8340 		if (rc != 0) {
8341 			pr_err("error %d\n", rc);
8342 			goto rw_error;
8343 		}
8344 		rc = drxj_dap_write_reg16(dev_addr, QAM_LC_QUAL_TAB0__A, 1, 0);
8345 		if (rc != 0) {
8346 			pr_err("error %d\n", rc);
8347 			goto rw_error;
8348 		}
8349 		rc = drxj_dap_write_reg16(dev_addr, QAM_LC_QUAL_TAB1__A, 1, 0);
8350 		if (rc != 0) {
8351 			pr_err("error %d\n", rc);
8352 			goto rw_error;
8353 		}
8354 		rc = drxj_dap_write_reg16(dev_addr, QAM_LC_QUAL_TAB2__A, 1, 0);
8355 		if (rc != 0) {
8356 			pr_err("error %d\n", rc);
8357 			goto rw_error;
8358 		}
8359 		rc = drxj_dap_write_reg16(dev_addr, QAM_LC_QUAL_TAB3__A, 1, 0);
8360 		if (rc != 0) {
8361 			pr_err("error %d\n", rc);
8362 			goto rw_error;
8363 		}
8364 		rc = drxj_dap_write_reg16(dev_addr, QAM_LC_QUAL_TAB4__A, 2, 0);
8365 		if (rc != 0) {
8366 			pr_err("error %d\n", rc);
8367 			goto rw_error;
8368 		}
8369 		rc = drxj_dap_write_reg16(dev_addr, QAM_LC_QUAL_TAB5__A, 2, 0);
8370 		if (rc != 0) {
8371 			pr_err("error %d\n", rc);
8372 			goto rw_error;
8373 		}
8374 		rc = drxj_dap_write_reg16(dev_addr, QAM_LC_QUAL_TAB6__A, 2, 0);
8375 		if (rc != 0) {
8376 			pr_err("error %d\n", rc);
8377 			goto rw_error;
8378 		}
8379 		rc = drxj_dap_write_reg16(dev_addr, QAM_LC_QUAL_TAB8__A, 2, 0);
8380 		if (rc != 0) {
8381 			pr_err("error %d\n", rc);
8382 			goto rw_error;
8383 		}
8384 		rc = drxj_dap_write_reg16(dev_addr, QAM_LC_QUAL_TAB9__A, 2, 0);
8385 		if (rc != 0) {
8386 			pr_err("error %d\n", rc);
8387 			goto rw_error;
8388 		}
8389 		rc = drxj_dap_write_reg16(dev_addr, QAM_LC_QUAL_TAB10__A, 2, 0);
8390 		if (rc != 0) {
8391 			pr_err("error %d\n", rc);
8392 			goto rw_error;
8393 		}
8394 		rc = drxj_dap_write_reg16(dev_addr, QAM_LC_QUAL_TAB12__A, 2, 0);
8395 		if (rc != 0) {
8396 			pr_err("error %d\n", rc);
8397 			goto rw_error;
8398 		}
8399 		rc = drxj_dap_write_reg16(dev_addr, QAM_LC_QUAL_TAB15__A, 3, 0);
8400 		if (rc != 0) {
8401 			pr_err("error %d\n", rc);
8402 			goto rw_error;
8403 		}
8404 		rc = drxj_dap_write_reg16(dev_addr, QAM_LC_QUAL_TAB16__A, 3, 0);
8405 		if (rc != 0) {
8406 			pr_err("error %d\n", rc);
8407 			goto rw_error;
8408 		}
8409 		rc = drxj_dap_write_reg16(dev_addr, QAM_LC_QUAL_TAB20__A, 4, 0);
8410 		if (rc != 0) {
8411 			pr_err("error %d\n", rc);
8412 			goto rw_error;
8413 		}
8414 		rc = drxj_dap_write_reg16(dev_addr, QAM_LC_QUAL_TAB25__A, 4, 0);
8415 		if (rc != 0) {
8416 			pr_err("error %d\n", rc);
8417 			goto rw_error;
8418 		}
8419 
8420 		rc = drxj_dap_write_reg16(dev_addr, IQM_FS_ADJ_SEL__A, 1, 0);
8421 		if (rc != 0) {
8422 			pr_err("error %d\n", rc);
8423 			goto rw_error;
8424 		}
8425 		rc = drxj_dap_write_reg16(dev_addr, IQM_RC_ADJ_SEL__A, 1, 0);
8426 		if (rc != 0) {
8427 			pr_err("error %d\n", rc);
8428 			goto rw_error;
8429 		}
8430 		rc = drxj_dap_write_reg16(dev_addr, IQM_CF_ADJ_SEL__A, 1, 0);
8431 		if (rc != 0) {
8432 			pr_err("error %d\n", rc);
8433 			goto rw_error;
8434 		}
8435 		rc = drxj_dap_write_reg16(dev_addr, IQM_CF_POW_MEAS_LEN__A, 0, 0);
8436 		if (rc != 0) {
8437 			pr_err("error %d\n", rc);
8438 			goto rw_error;
8439 		}
8440 		rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_GPIO__A, 0, 0);
8441 		if (rc != 0) {
8442 			pr_err("error %d\n", rc);
8443 			goto rw_error;
8444 		}
8445 
8446 		/* No more resets of the IQM, current standard correctly set =>
8447 		   now AGCs can be configured. */
8448 		/* turn on IQMAF. It has to be in front of setAgc**() */
8449 		rc = set_iqm_af(demod, true);
8450 		if (rc != 0) {
8451 			pr_err("error %d\n", rc);
8452 			goto rw_error;
8453 		}
8454 		rc = adc_synchronization(demod);
8455 		if (rc != 0) {
8456 			pr_err("error %d\n", rc);
8457 			goto rw_error;
8458 		}
8459 
8460 		rc = init_agc(demod);
8461 		if (rc != 0) {
8462 			pr_err("error %d\n", rc);
8463 			goto rw_error;
8464 		}
8465 		rc = set_agc_if(demod, &(ext_attr->qam_if_agc_cfg), false);
8466 		if (rc != 0) {
8467 			pr_err("error %d\n", rc);
8468 			goto rw_error;
8469 		}
8470 		rc = set_agc_rf(demod, &(ext_attr->qam_rf_agc_cfg), false);
8471 		if (rc != 0) {
8472 			pr_err("error %d\n", rc);
8473 			goto rw_error;
8474 		}
8475 		{
8476 			/* TODO fix this, store a struct drxj_cfg_afe_gain structure in struct drxj_data instead
8477 			   of only the gain */
8478 			struct drxj_cfg_afe_gain qam_pga_cfg = { DRX_STANDARD_ITU_B, 0 };
8479 
8480 			qam_pga_cfg.gain = ext_attr->qam_pga_cfg;
8481 			rc = ctrl_set_cfg_afe_gain(demod, &qam_pga_cfg);
8482 			if (rc != 0) {
8483 				pr_err("error %d\n", rc);
8484 				goto rw_error;
8485 			}
8486 		}
8487 		rc = ctrl_set_cfg_pre_saw(demod, &(ext_attr->qam_pre_saw_cfg));
8488 		if (rc != 0) {
8489 			pr_err("error %d\n", rc);
8490 			goto rw_error;
8491 		}
8492 	}
8493 
8494 	if ((op & QAM_SET_OP_ALL) || (op & QAM_SET_OP_CONSTELLATION)) {
8495 		if (ext_attr->standard == DRX_STANDARD_ITU_A) {
8496 			rc = drxdap_fasi_write_block(dev_addr, IQM_CF_TAP_RE0__A, sizeof(qam_a_taps), ((u8 *)qam_a_taps), 0);
8497 			if (rc != 0) {
8498 				pr_err("error %d\n", rc);
8499 				goto rw_error;
8500 			}
8501 			rc = drxdap_fasi_write_block(dev_addr, IQM_CF_TAP_IM0__A, sizeof(qam_a_taps), ((u8 *)qam_a_taps), 0);
8502 			if (rc != 0) {
8503 				pr_err("error %d\n", rc);
8504 				goto rw_error;
8505 			}
8506 		} else if (ext_attr->standard == DRX_STANDARD_ITU_B) {
8507 			switch (channel->constellation) {
8508 			case DRX_CONSTELLATION_QAM64:
8509 				rc = drxdap_fasi_write_block(dev_addr, IQM_CF_TAP_RE0__A, sizeof(qam_b64_taps), ((u8 *)qam_b64_taps), 0);
8510 				if (rc != 0) {
8511 					pr_err("error %d\n", rc);
8512 					goto rw_error;
8513 				}
8514 				rc = drxdap_fasi_write_block(dev_addr, IQM_CF_TAP_IM0__A, sizeof(qam_b64_taps), ((u8 *)qam_b64_taps), 0);
8515 				if (rc != 0) {
8516 					pr_err("error %d\n", rc);
8517 					goto rw_error;
8518 				}
8519 				break;
8520 			case DRX_CONSTELLATION_QAM256:
8521 				rc = drxdap_fasi_write_block(dev_addr, IQM_CF_TAP_RE0__A, sizeof(qam_b256_taps), ((u8 *)qam_b256_taps), 0);
8522 				if (rc != 0) {
8523 					pr_err("error %d\n", rc);
8524 					goto rw_error;
8525 				}
8526 				rc = drxdap_fasi_write_block(dev_addr, IQM_CF_TAP_IM0__A, sizeof(qam_b256_taps), ((u8 *)qam_b256_taps), 0);
8527 				if (rc != 0) {
8528 					pr_err("error %d\n", rc);
8529 					goto rw_error;
8530 				}
8531 				break;
8532 			default:
8533 				return -EIO;
8534 			}
8535 		} else if (ext_attr->standard == DRX_STANDARD_ITU_C) {
8536 			rc = drxdap_fasi_write_block(dev_addr, IQM_CF_TAP_RE0__A, sizeof(qam_c_taps), ((u8 *)qam_c_taps), 0);
8537 			if (rc != 0) {
8538 				pr_err("error %d\n", rc);
8539 				goto rw_error;
8540 			}
8541 			rc = drxdap_fasi_write_block(dev_addr, IQM_CF_TAP_IM0__A, sizeof(qam_c_taps), ((u8 *)qam_c_taps), 0);
8542 			if (rc != 0) {
8543 				pr_err("error %d\n", rc);
8544 				goto rw_error;
8545 			}
8546 		}
8547 
8548 		/* SETP 4: constellation specific setup */
8549 		switch (channel->constellation) {
8550 		case DRX_CONSTELLATION_QAM16:
8551 			rc = set_qam16(demod);
8552 			if (rc != 0) {
8553 				pr_err("error %d\n", rc);
8554 				goto rw_error;
8555 			}
8556 			break;
8557 		case DRX_CONSTELLATION_QAM32:
8558 			rc = set_qam32(demod);
8559 			if (rc != 0) {
8560 				pr_err("error %d\n", rc);
8561 				goto rw_error;
8562 			}
8563 			break;
8564 		case DRX_CONSTELLATION_QAM64:
8565 			rc = set_qam64(demod);
8566 			if (rc != 0) {
8567 				pr_err("error %d\n", rc);
8568 				goto rw_error;
8569 			}
8570 			break;
8571 		case DRX_CONSTELLATION_QAM128:
8572 			rc = set_qam128(demod);
8573 			if (rc != 0) {
8574 				pr_err("error %d\n", rc);
8575 				goto rw_error;
8576 			}
8577 			break;
8578 		case DRX_CONSTELLATION_QAM256:
8579 			rc = set_qam256(demod);
8580 			if (rc != 0) {
8581 				pr_err("error %d\n", rc);
8582 				goto rw_error;
8583 			}
8584 			break;
8585 		default:
8586 			return -EIO;
8587 		}		/* switch */
8588 	}
8589 
8590 	if ((op & QAM_SET_OP_ALL)) {
8591 		rc = drxj_dap_write_reg16(dev_addr, IQM_CF_SCALE_SH__A, 0, 0);
8592 		if (rc != 0) {
8593 			pr_err("error %d\n", rc);
8594 			goto rw_error;
8595 		}
8596 
8597 		/* Mpeg output has to be in front of FEC active */
8598 		rc = set_mpegtei_handling(demod);
8599 		if (rc != 0) {
8600 			pr_err("error %d\n", rc);
8601 			goto rw_error;
8602 		}
8603 		rc = bit_reverse_mpeg_output(demod);
8604 		if (rc != 0) {
8605 			pr_err("error %d\n", rc);
8606 			goto rw_error;
8607 		}
8608 		rc = set_mpeg_start_width(demod);
8609 		if (rc != 0) {
8610 			pr_err("error %d\n", rc);
8611 			goto rw_error;
8612 		}
8613 		{
8614 			/* TODO: move to set_standard after hardware reset value problem is solved */
8615 			/* Configure initial MPEG output */
8616 			struct drx_cfg_mpeg_output cfg_mpeg_output;
8617 
8618 			memcpy(&cfg_mpeg_output, &common_attr->mpeg_cfg, sizeof(cfg_mpeg_output));
8619 			cfg_mpeg_output.enable_mpeg_output = true;
8620 
8621 			rc = ctrl_set_cfg_mpeg_output(demod, &cfg_mpeg_output);
8622 			if (rc != 0) {
8623 				pr_err("error %d\n", rc);
8624 				goto rw_error;
8625 			}
8626 		}
8627 	}
8628 
8629 	if ((op & QAM_SET_OP_ALL) || (op & QAM_SET_OP_CONSTELLATION)) {
8630 
8631 		/* STEP 5: start QAM demodulator (starts FEC, QAM and IQM HW) */
8632 		cmd_scu.command = SCU_RAM_COMMAND_STANDARD_QAM |
8633 		    SCU_RAM_COMMAND_CMD_DEMOD_START;
8634 		cmd_scu.parameter_len = 0;
8635 		cmd_scu.result_len = 1;
8636 		cmd_scu.parameter = NULL;
8637 		cmd_scu.result = &cmd_result;
8638 		rc = scu_command(dev_addr, &cmd_scu);
8639 		if (rc != 0) {
8640 			pr_err("error %d\n", rc);
8641 			goto rw_error;
8642 		}
8643 	}
8644 
8645 	rc = drxj_dap_write_reg16(dev_addr, IQM_COMM_EXEC__A, IQM_COMM_EXEC_ACTIVE, 0);
8646 	if (rc != 0) {
8647 		pr_err("error %d\n", rc);
8648 		goto rw_error;
8649 	}
8650 	rc = drxj_dap_write_reg16(dev_addr, QAM_COMM_EXEC__A, QAM_COMM_EXEC_ACTIVE, 0);
8651 	if (rc != 0) {
8652 		pr_err("error %d\n", rc);
8653 		goto rw_error;
8654 	}
8655 	rc = drxj_dap_write_reg16(dev_addr, FEC_COMM_EXEC__A, FEC_COMM_EXEC_ACTIVE, 0);
8656 	if (rc != 0) {
8657 		pr_err("error %d\n", rc);
8658 		goto rw_error;
8659 	}
8660 
8661 	return 0;
8662 rw_error:
8663 	return rc;
8664 }
8665 
8666 /*============================================================================*/
8667 static int ctrl_get_qam_sig_quality(struct drx_demod_instance *demod);
8668 
8669 static int qam_flip_spec(struct drx_demod_instance *demod, struct drx_channel *channel)
8670 {
8671 	struct i2c_device_addr *dev_addr = demod->my_i2c_dev_addr;
8672 	struct drxj_data *ext_attr = demod->my_ext_attr;
8673 	int rc;
8674 	u32 iqm_fs_rate_ofs = 0;
8675 	u32 iqm_fs_rate_lo = 0;
8676 	u16 qam_ctl_ena = 0;
8677 	u16 data = 0;
8678 	u16 equ_mode = 0;
8679 	u16 fsm_state = 0;
8680 	int i = 0;
8681 	int ofsofs = 0;
8682 
8683 	/* Silence the controlling of lc, equ, and the acquisition state machine */
8684 	rc = drxj_dap_read_reg16(dev_addr, SCU_RAM_QAM_CTL_ENA__A, &qam_ctl_ena, 0);
8685 	if (rc != 0) {
8686 		pr_err("error %d\n", rc);
8687 		goto rw_error;
8688 	}
8689 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_CTL_ENA__A, qam_ctl_ena & ~(SCU_RAM_QAM_CTL_ENA_ACQ__M | SCU_RAM_QAM_CTL_ENA_EQU__M | SCU_RAM_QAM_CTL_ENA_LC__M), 0);
8690 	if (rc != 0) {
8691 		pr_err("error %d\n", rc);
8692 		goto rw_error;
8693 	}
8694 
8695 	/* freeze the frequency control loop */
8696 	rc = drxj_dap_write_reg16(dev_addr, QAM_LC_CF__A, 0, 0);
8697 	if (rc != 0) {
8698 		pr_err("error %d\n", rc);
8699 		goto rw_error;
8700 	}
8701 	rc = drxj_dap_write_reg16(dev_addr, QAM_LC_CF1__A, 0, 0);
8702 	if (rc != 0) {
8703 		pr_err("error %d\n", rc);
8704 		goto rw_error;
8705 	}
8706 
8707 	rc = drxj_dap_atomic_read_reg32(dev_addr, IQM_FS_RATE_OFS_LO__A, &iqm_fs_rate_ofs, 0);
8708 	if (rc != 0) {
8709 		pr_err("error %d\n", rc);
8710 		goto rw_error;
8711 	}
8712 	rc = drxj_dap_atomic_read_reg32(dev_addr, IQM_FS_RATE_LO__A, &iqm_fs_rate_lo, 0);
8713 	if (rc != 0) {
8714 		pr_err("error %d\n", rc);
8715 		goto rw_error;
8716 	}
8717 	ofsofs = iqm_fs_rate_lo - iqm_fs_rate_ofs;
8718 	iqm_fs_rate_ofs = ~iqm_fs_rate_ofs + 1;
8719 	iqm_fs_rate_ofs -= 2 * ofsofs;
8720 
8721 	/* freeze dq/fq updating */
8722 	rc = drxj_dap_read_reg16(dev_addr, QAM_DQ_MODE__A, &data, 0);
8723 	if (rc != 0) {
8724 		pr_err("error %d\n", rc);
8725 		goto rw_error;
8726 	}
8727 	data = (data & 0xfff9);
8728 	rc = drxj_dap_write_reg16(dev_addr, QAM_DQ_MODE__A, data, 0);
8729 	if (rc != 0) {
8730 		pr_err("error %d\n", rc);
8731 		goto rw_error;
8732 	}
8733 	rc = drxj_dap_write_reg16(dev_addr, QAM_FQ_MODE__A, data, 0);
8734 	if (rc != 0) {
8735 		pr_err("error %d\n", rc);
8736 		goto rw_error;
8737 	}
8738 
8739 	/* lc_cp / _ci / _ca */
8740 	rc = drxj_dap_write_reg16(dev_addr, QAM_LC_CI__A, 0, 0);
8741 	if (rc != 0) {
8742 		pr_err("error %d\n", rc);
8743 		goto rw_error;
8744 	}
8745 	rc = drxj_dap_write_reg16(dev_addr, QAM_LC_EP__A, 0, 0);
8746 	if (rc != 0) {
8747 		pr_err("error %d\n", rc);
8748 		goto rw_error;
8749 	}
8750 	rc = drxj_dap_write_reg16(dev_addr, QAM_FQ_LA_FACTOR__A, 0, 0);
8751 	if (rc != 0) {
8752 		pr_err("error %d\n", rc);
8753 		goto rw_error;
8754 	}
8755 
8756 	/* flip the spec */
8757 	rc = drxdap_fasi_write_reg32(dev_addr, IQM_FS_RATE_OFS_LO__A, iqm_fs_rate_ofs, 0);
8758 	if (rc != 0) {
8759 		pr_err("error %d\n", rc);
8760 		goto rw_error;
8761 	}
8762 	ext_attr->iqm_fs_rate_ofs = iqm_fs_rate_ofs;
8763 	ext_attr->pos_image = (ext_attr->pos_image) ? false : true;
8764 
8765 	/* freeze dq/fq updating */
8766 	rc = drxj_dap_read_reg16(dev_addr, QAM_DQ_MODE__A, &data, 0);
8767 	if (rc != 0) {
8768 		pr_err("error %d\n", rc);
8769 		goto rw_error;
8770 	}
8771 	equ_mode = data;
8772 	data = (data & 0xfff9);
8773 	rc = drxj_dap_write_reg16(dev_addr, QAM_DQ_MODE__A, data, 0);
8774 	if (rc != 0) {
8775 		pr_err("error %d\n", rc);
8776 		goto rw_error;
8777 	}
8778 	rc = drxj_dap_write_reg16(dev_addr, QAM_FQ_MODE__A, data, 0);
8779 	if (rc != 0) {
8780 		pr_err("error %d\n", rc);
8781 		goto rw_error;
8782 	}
8783 
8784 	for (i = 0; i < 28; i++) {
8785 		rc = drxj_dap_read_reg16(dev_addr, QAM_DQ_TAP_IM_EL0__A + (2 * i), &data, 0);
8786 		if (rc != 0) {
8787 			pr_err("error %d\n", rc);
8788 			goto rw_error;
8789 		}
8790 		rc = drxj_dap_write_reg16(dev_addr, QAM_DQ_TAP_IM_EL0__A + (2 * i), -data, 0);
8791 		if (rc != 0) {
8792 			pr_err("error %d\n", rc);
8793 			goto rw_error;
8794 		}
8795 	}
8796 
8797 	for (i = 0; i < 24; i++) {
8798 		rc = drxj_dap_read_reg16(dev_addr, QAM_FQ_TAP_IM_EL0__A + (2 * i), &data, 0);
8799 		if (rc != 0) {
8800 			pr_err("error %d\n", rc);
8801 			goto rw_error;
8802 		}
8803 		rc = drxj_dap_write_reg16(dev_addr, QAM_FQ_TAP_IM_EL0__A + (2 * i), -data, 0);
8804 		if (rc != 0) {
8805 			pr_err("error %d\n", rc);
8806 			goto rw_error;
8807 		}
8808 	}
8809 
8810 	data = equ_mode;
8811 	rc = drxj_dap_write_reg16(dev_addr, QAM_DQ_MODE__A, data, 0);
8812 	if (rc != 0) {
8813 		pr_err("error %d\n", rc);
8814 		goto rw_error;
8815 	}
8816 	rc = drxj_dap_write_reg16(dev_addr, QAM_FQ_MODE__A, data, 0);
8817 	if (rc != 0) {
8818 		pr_err("error %d\n", rc);
8819 		goto rw_error;
8820 	}
8821 
8822 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_STATE_TGT__A, 4, 0);
8823 	if (rc != 0) {
8824 		pr_err("error %d\n", rc);
8825 		goto rw_error;
8826 	}
8827 
8828 	i = 0;
8829 	while ((fsm_state != 4) && (i++ < 100)) {
8830 		rc = drxj_dap_read_reg16(dev_addr, SCU_RAM_QAM_FSM_STATE__A, &fsm_state, 0);
8831 		if (rc != 0) {
8832 			pr_err("error %d\n", rc);
8833 			goto rw_error;
8834 		}
8835 	}
8836 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_CTL_ENA__A, (qam_ctl_ena | 0x0016), 0);
8837 	if (rc != 0) {
8838 		pr_err("error %d\n", rc);
8839 		goto rw_error;
8840 	}
8841 
8842 	return 0;
8843 rw_error:
8844 	return rc;
8845 
8846 }
8847 
8848 #define  NO_LOCK        0x0
8849 #define  DEMOD_LOCKED   0x1
8850 #define  SYNC_FLIPPED   0x2
8851 #define  SPEC_MIRRORED  0x4
8852 /*
8853 * \fn int qam64auto ()
8854 * \brief auto do sync pattern switching and mirroring.
8855 * \param demod:   instance of demod.
8856 * \param channel: pointer to channel data.
8857 * \param tuner_freq_offset: tuner frequency offset.
8858 * \param lock_status: pointer to lock status.
8859 * \return int.
8860 */
8861 static int
8862 qam64auto(struct drx_demod_instance *demod,
8863 	  struct drx_channel *channel,
8864 	  s32 tuner_freq_offset, enum drx_lock_status *lock_status)
8865 {
8866 	struct drxj_data *ext_attr = demod->my_ext_attr;
8867 	struct i2c_device_addr *dev_addr = demod->my_i2c_dev_addr;
8868 	struct drx39xxj_state *state = dev_addr->user_data;
8869 	struct dtv_frontend_properties *p = &state->frontend.dtv_property_cache;
8870 	int rc;
8871 	u32 lck_state = NO_LOCK;
8872 	u32 start_time = 0;
8873 	u32 d_locked_time = 0;
8874 	u32 timeout_ofs = 0;
8875 	u16 data = 0;
8876 
8877 	/* external attributes for storing acquired channel constellation */
8878 	*lock_status = DRX_NOT_LOCKED;
8879 	start_time = jiffies_to_msecs(jiffies);
8880 	lck_state = NO_LOCK;
8881 	do {
8882 		rc = ctrl_lock_status(demod, lock_status);
8883 		if (rc != 0) {
8884 			pr_err("error %d\n", rc);
8885 			goto rw_error;
8886 		}
8887 
8888 		switch (lck_state) {
8889 		case NO_LOCK:
8890 			if (*lock_status == DRXJ_DEMOD_LOCK) {
8891 				rc = ctrl_get_qam_sig_quality(demod);
8892 				if (rc != 0) {
8893 					pr_err("error %d\n", rc);
8894 					goto rw_error;
8895 				}
8896 				if (p->cnr.stat[0].svalue > 20800) {
8897 					lck_state = DEMOD_LOCKED;
8898 					/* some delay to see if fec_lock possible TODO find the right value */
8899 					timeout_ofs += DRXJ_QAM_DEMOD_LOCK_EXT_WAITTIME;	/* see something, waiting longer */
8900 					d_locked_time = jiffies_to_msecs(jiffies);
8901 				}
8902 			}
8903 			break;
8904 		case DEMOD_LOCKED:
8905 			if ((*lock_status == DRXJ_DEMOD_LOCK) &&	/* still demod_lock in 150ms */
8906 			    ((jiffies_to_msecs(jiffies) - d_locked_time) >
8907 			     DRXJ_QAM_FEC_LOCK_WAITTIME)) {
8908 				rc = drxj_dap_read_reg16(demod->my_i2c_dev_addr, QAM_SY_TIMEOUT__A, &data, 0);
8909 				if (rc != 0) {
8910 					pr_err("error %d\n", rc);
8911 					goto rw_error;
8912 				}
8913 				rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, QAM_SY_TIMEOUT__A, data | 0x1, 0);
8914 				if (rc != 0) {
8915 					pr_err("error %d\n", rc);
8916 					goto rw_error;
8917 				}
8918 				lck_state = SYNC_FLIPPED;
8919 				msleep(10);
8920 			}
8921 			break;
8922 		case SYNC_FLIPPED:
8923 			if (*lock_status == DRXJ_DEMOD_LOCK) {
8924 				if (channel->mirror == DRX_MIRROR_AUTO) {
8925 					/* flip sync pattern back */
8926 					rc = drxj_dap_read_reg16(demod->my_i2c_dev_addr, QAM_SY_TIMEOUT__A, &data, 0);
8927 					if (rc != 0) {
8928 						pr_err("error %d\n", rc);
8929 						goto rw_error;
8930 					}
8931 					rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, QAM_SY_TIMEOUT__A, data & 0xFFFE, 0);
8932 					if (rc != 0) {
8933 						pr_err("error %d\n", rc);
8934 						goto rw_error;
8935 					}
8936 					/* flip spectrum */
8937 					ext_attr->mirror = DRX_MIRROR_YES;
8938 					rc = qam_flip_spec(demod, channel);
8939 					if (rc != 0) {
8940 						pr_err("error %d\n", rc);
8941 						goto rw_error;
8942 					}
8943 					lck_state = SPEC_MIRRORED;
8944 					/* reset timer TODO: still need 500ms? */
8945 					start_time = d_locked_time =
8946 					    jiffies_to_msecs(jiffies);
8947 					timeout_ofs = 0;
8948 				} else {	/* no need to wait lock */
8949 
8950 					start_time =
8951 					    jiffies_to_msecs(jiffies) -
8952 					    DRXJ_QAM_MAX_WAITTIME - timeout_ofs;
8953 				}
8954 			}
8955 			break;
8956 		case SPEC_MIRRORED:
8957 			if ((*lock_status == DRXJ_DEMOD_LOCK) &&	/* still demod_lock in 150ms */
8958 			    ((jiffies_to_msecs(jiffies) - d_locked_time) >
8959 			     DRXJ_QAM_FEC_LOCK_WAITTIME)) {
8960 				rc = ctrl_get_qam_sig_quality(demod);
8961 				if (rc != 0) {
8962 					pr_err("error %d\n", rc);
8963 					goto rw_error;
8964 				}
8965 				if (p->cnr.stat[0].svalue > 20800) {
8966 					rc = drxj_dap_read_reg16(demod->my_i2c_dev_addr, QAM_SY_TIMEOUT__A, &data, 0);
8967 					if (rc != 0) {
8968 						pr_err("error %d\n", rc);
8969 						goto rw_error;
8970 					}
8971 					rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, QAM_SY_TIMEOUT__A, data | 0x1, 0);
8972 					if (rc != 0) {
8973 						pr_err("error %d\n", rc);
8974 						goto rw_error;
8975 					}
8976 					/* no need to wait lock */
8977 					start_time =
8978 					    jiffies_to_msecs(jiffies) -
8979 					    DRXJ_QAM_MAX_WAITTIME - timeout_ofs;
8980 				}
8981 			}
8982 			break;
8983 		default:
8984 			break;
8985 		}
8986 		msleep(10);
8987 	} while
8988 	    ((*lock_status != DRX_LOCKED) &&
8989 	     (*lock_status != DRX_NEVER_LOCK) &&
8990 	     ((jiffies_to_msecs(jiffies) - start_time) <
8991 	      (DRXJ_QAM_MAX_WAITTIME + timeout_ofs))
8992 	    );
8993 	/* Returning control to apllication ... */
8994 
8995 	return 0;
8996 rw_error:
8997 	return rc;
8998 }
8999 
9000 /*
9001 * \fn int qam256auto ()
9002 * \brief auto do sync pattern switching and mirroring.
9003 * \param demod:   instance of demod.
9004 * \param channel: pointer to channel data.
9005 * \param tuner_freq_offset: tuner frequency offset.
9006 * \param lock_status: pointer to lock status.
9007 * \return int.
9008 */
9009 static int
9010 qam256auto(struct drx_demod_instance *demod,
9011 	   struct drx_channel *channel,
9012 	   s32 tuner_freq_offset, enum drx_lock_status *lock_status)
9013 {
9014 	struct drxj_data *ext_attr = demod->my_ext_attr;
9015 	struct i2c_device_addr *dev_addr = demod->my_i2c_dev_addr;
9016 	struct drx39xxj_state *state = dev_addr->user_data;
9017 	struct dtv_frontend_properties *p = &state->frontend.dtv_property_cache;
9018 	int rc;
9019 	u32 lck_state = NO_LOCK;
9020 	u32 start_time = 0;
9021 	u32 d_locked_time = 0;
9022 	u32 timeout_ofs = DRXJ_QAM_DEMOD_LOCK_EXT_WAITTIME;
9023 
9024 	/* external attributes for storing acquired channel constellation */
9025 	*lock_status = DRX_NOT_LOCKED;
9026 	start_time = jiffies_to_msecs(jiffies);
9027 	lck_state = NO_LOCK;
9028 	do {
9029 		rc = ctrl_lock_status(demod, lock_status);
9030 		if (rc != 0) {
9031 			pr_err("error %d\n", rc);
9032 			goto rw_error;
9033 		}
9034 		switch (lck_state) {
9035 		case NO_LOCK:
9036 			if (*lock_status == DRXJ_DEMOD_LOCK) {
9037 				rc = ctrl_get_qam_sig_quality(demod);
9038 				if (rc != 0) {
9039 					pr_err("error %d\n", rc);
9040 					goto rw_error;
9041 				}
9042 				if (p->cnr.stat[0].svalue > 26800) {
9043 					lck_state = DEMOD_LOCKED;
9044 					timeout_ofs += DRXJ_QAM_DEMOD_LOCK_EXT_WAITTIME;	/* see something, wait longer */
9045 					d_locked_time = jiffies_to_msecs(jiffies);
9046 				}
9047 			}
9048 			break;
9049 		case DEMOD_LOCKED:
9050 			if (*lock_status == DRXJ_DEMOD_LOCK) {
9051 				if ((channel->mirror == DRX_MIRROR_AUTO) &&
9052 				    ((jiffies_to_msecs(jiffies) - d_locked_time) >
9053 				     DRXJ_QAM_FEC_LOCK_WAITTIME)) {
9054 					ext_attr->mirror = DRX_MIRROR_YES;
9055 					rc = qam_flip_spec(demod, channel);
9056 					if (rc != 0) {
9057 						pr_err("error %d\n", rc);
9058 						goto rw_error;
9059 					}
9060 					lck_state = SPEC_MIRRORED;
9061 					/* reset timer TODO: still need 300ms? */
9062 					start_time = jiffies_to_msecs(jiffies);
9063 					timeout_ofs = -DRXJ_QAM_MAX_WAITTIME / 2;
9064 				}
9065 			}
9066 			break;
9067 		case SPEC_MIRRORED:
9068 			break;
9069 		default:
9070 			break;
9071 		}
9072 		msleep(10);
9073 	} while
9074 	    ((*lock_status < DRX_LOCKED) &&
9075 	     (*lock_status != DRX_NEVER_LOCK) &&
9076 	     ((jiffies_to_msecs(jiffies) - start_time) <
9077 	      (DRXJ_QAM_MAX_WAITTIME + timeout_ofs)));
9078 
9079 	return 0;
9080 rw_error:
9081 	return rc;
9082 }
9083 
9084 /*
9085 * \fn int set_qam_channel ()
9086 * \brief Set QAM channel according to the requested constellation.
9087 * \param demod:   instance of demod.
9088 * \param channel: pointer to channel data.
9089 * \return int.
9090 */
9091 static int
9092 set_qam_channel(struct drx_demod_instance *demod,
9093 	       struct drx_channel *channel, s32 tuner_freq_offset)
9094 {
9095 	struct drxj_data *ext_attr = NULL;
9096 	int rc;
9097 	enum drx_lock_status lock_status = DRX_NOT_LOCKED;
9098 	bool auto_flag = false;
9099 
9100 	/* external attributes for storing acquired channel constellation */
9101 	ext_attr = (struct drxj_data *) demod->my_ext_attr;
9102 
9103 	/* set QAM channel constellation */
9104 	switch (channel->constellation) {
9105 	case DRX_CONSTELLATION_QAM16:
9106 	case DRX_CONSTELLATION_QAM32:
9107 	case DRX_CONSTELLATION_QAM128:
9108 		return -EINVAL;
9109 	case DRX_CONSTELLATION_QAM64:
9110 	case DRX_CONSTELLATION_QAM256:
9111 		if (ext_attr->standard != DRX_STANDARD_ITU_B)
9112 			return -EINVAL;
9113 
9114 		ext_attr->constellation = channel->constellation;
9115 		if (channel->mirror == DRX_MIRROR_AUTO)
9116 			ext_attr->mirror = DRX_MIRROR_NO;
9117 		else
9118 			ext_attr->mirror = channel->mirror;
9119 
9120 		rc = set_qam(demod, channel, tuner_freq_offset, QAM_SET_OP_ALL);
9121 		if (rc != 0) {
9122 			pr_err("error %d\n", rc);
9123 			goto rw_error;
9124 		}
9125 
9126 		if (channel->constellation == DRX_CONSTELLATION_QAM64)
9127 			rc = qam64auto(demod, channel, tuner_freq_offset,
9128 				       &lock_status);
9129 		else
9130 			rc = qam256auto(demod, channel, tuner_freq_offset,
9131 					&lock_status);
9132 		if (rc != 0) {
9133 			pr_err("error %d\n", rc);
9134 			goto rw_error;
9135 		}
9136 		break;
9137 	case DRX_CONSTELLATION_AUTO:	/* for channel scan */
9138 		if (ext_attr->standard == DRX_STANDARD_ITU_B) {
9139 			u16 qam_ctl_ena = 0;
9140 
9141 			auto_flag = true;
9142 
9143 			/* try to lock default QAM constellation: QAM256 */
9144 			channel->constellation = DRX_CONSTELLATION_QAM256;
9145 			ext_attr->constellation = DRX_CONSTELLATION_QAM256;
9146 			if (channel->mirror == DRX_MIRROR_AUTO)
9147 				ext_attr->mirror = DRX_MIRROR_NO;
9148 			else
9149 				ext_attr->mirror = channel->mirror;
9150 			rc = set_qam(demod, channel, tuner_freq_offset,
9151 				     QAM_SET_OP_ALL);
9152 			if (rc != 0) {
9153 				pr_err("error %d\n", rc);
9154 				goto rw_error;
9155 			}
9156 			rc = qam256auto(demod, channel, tuner_freq_offset,
9157 					&lock_status);
9158 			if (rc != 0) {
9159 				pr_err("error %d\n", rc);
9160 				goto rw_error;
9161 			}
9162 
9163 			if (lock_status >= DRX_LOCKED) {
9164 				channel->constellation = DRX_CONSTELLATION_AUTO;
9165 				break;
9166 			}
9167 
9168 			/* QAM254 not locked. Try QAM64 constellation */
9169 			channel->constellation = DRX_CONSTELLATION_QAM64;
9170 			ext_attr->constellation = DRX_CONSTELLATION_QAM64;
9171 			if (channel->mirror == DRX_MIRROR_AUTO)
9172 				ext_attr->mirror = DRX_MIRROR_NO;
9173 			else
9174 				ext_attr->mirror = channel->mirror;
9175 
9176 			rc = drxj_dap_read_reg16(demod->my_i2c_dev_addr,
9177 						     SCU_RAM_QAM_CTL_ENA__A,
9178 						     &qam_ctl_ena, 0);
9179 			if (rc != 0) {
9180 				pr_err("error %d\n", rc);
9181 				goto rw_error;
9182 			}
9183 			rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr,
9184 						      SCU_RAM_QAM_CTL_ENA__A,
9185 						      qam_ctl_ena & ~SCU_RAM_QAM_CTL_ENA_ACQ__M, 0);
9186 			if (rc != 0) {
9187 				pr_err("error %d\n", rc);
9188 				goto rw_error;
9189 			}
9190 			rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr,
9191 						      SCU_RAM_QAM_FSM_STATE_TGT__A,
9192 						      0x2, 0);
9193 			if (rc != 0) {
9194 				pr_err("error %d\n", rc);
9195 				goto rw_error;
9196 			}	/* force to rate hunting */
9197 
9198 			rc = set_qam(demod, channel, tuner_freq_offset,
9199 				     QAM_SET_OP_CONSTELLATION);
9200 			if (rc != 0) {
9201 				pr_err("error %d\n", rc);
9202 				goto rw_error;
9203 			}
9204 			rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr,
9205 						      SCU_RAM_QAM_CTL_ENA__A,
9206 						      qam_ctl_ena, 0);
9207 			if (rc != 0) {
9208 				pr_err("error %d\n", rc);
9209 				goto rw_error;
9210 			}
9211 
9212 			rc = qam64auto(demod, channel, tuner_freq_offset,
9213 				       &lock_status);
9214 			if (rc != 0) {
9215 				pr_err("error %d\n", rc);
9216 				goto rw_error;
9217 			}
9218 
9219 			channel->constellation = DRX_CONSTELLATION_AUTO;
9220 		} else if (ext_attr->standard == DRX_STANDARD_ITU_C) {
9221 			u16 qam_ctl_ena = 0;
9222 
9223 			channel->constellation = DRX_CONSTELLATION_QAM64;
9224 			ext_attr->constellation = DRX_CONSTELLATION_QAM64;
9225 			auto_flag = true;
9226 
9227 			if (channel->mirror == DRX_MIRROR_AUTO)
9228 				ext_attr->mirror = DRX_MIRROR_NO;
9229 			else
9230 				ext_attr->mirror = channel->mirror;
9231 			rc = drxj_dap_read_reg16(demod->my_i2c_dev_addr,
9232 						     SCU_RAM_QAM_CTL_ENA__A,
9233 						     &qam_ctl_ena, 0);
9234 			if (rc != 0) {
9235 				pr_err("error %d\n", rc);
9236 				goto rw_error;
9237 			}
9238 			rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr,
9239 						      SCU_RAM_QAM_CTL_ENA__A,
9240 						      qam_ctl_ena & ~SCU_RAM_QAM_CTL_ENA_ACQ__M, 0);
9241 			if (rc != 0) {
9242 				pr_err("error %d\n", rc);
9243 				goto rw_error;
9244 			}
9245 			rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr,
9246 						      SCU_RAM_QAM_FSM_STATE_TGT__A,
9247 						      0x2, 0);
9248 			if (rc != 0) {
9249 				pr_err("error %d\n", rc);
9250 				goto rw_error;
9251 			}	/* force to rate hunting */
9252 
9253 			rc = set_qam(demod, channel, tuner_freq_offset,
9254 				     QAM_SET_OP_CONSTELLATION);
9255 			if (rc != 0) {
9256 				pr_err("error %d\n", rc);
9257 				goto rw_error;
9258 			}
9259 			rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr,
9260 						      SCU_RAM_QAM_CTL_ENA__A,
9261 						      qam_ctl_ena, 0);
9262 			if (rc != 0) {
9263 				pr_err("error %d\n", rc);
9264 				goto rw_error;
9265 			}
9266 			rc = qam64auto(demod, channel, tuner_freq_offset,
9267 				       &lock_status);
9268 			if (rc != 0) {
9269 				pr_err("error %d\n", rc);
9270 				goto rw_error;
9271 			}
9272 			channel->constellation = DRX_CONSTELLATION_AUTO;
9273 		} else {
9274 			return -EINVAL;
9275 		}
9276 		break;
9277 	default:
9278 		return -EINVAL;
9279 	}
9280 
9281 	return 0;
9282 rw_error:
9283 	/* restore starting value */
9284 	if (auto_flag)
9285 		channel->constellation = DRX_CONSTELLATION_AUTO;
9286 	return rc;
9287 }
9288 
9289 /*============================================================================*/
9290 
9291 /*
9292 * \fn static short get_qamrs_err_count(struct i2c_device_addr *dev_addr)
9293 * \brief Get RS error count in QAM mode (used for post RS BER calculation)
9294 * \return Error code
9295 *
9296 * precondition: measurement period & measurement prescale must be set
9297 *
9298 */
9299 static int
9300 get_qamrs_err_count(struct i2c_device_addr *dev_addr,
9301 		    struct drxjrs_errors *rs_errors)
9302 {
9303 	int rc;
9304 	u16 nr_bit_errors = 0,
9305 	    nr_symbol_errors = 0,
9306 	    nr_packet_errors = 0, nr_failures = 0, nr_snc_par_fail_count = 0;
9307 
9308 	/* check arguments */
9309 	if (dev_addr == NULL)
9310 		return -EINVAL;
9311 
9312 	/* all reported errors are received in the  */
9313 	/* most recently finished measurment period */
9314 	/*   no of pre RS bit errors */
9315 	rc = drxj_dap_read_reg16(dev_addr, FEC_RS_NR_BIT_ERRORS__A, &nr_bit_errors, 0);
9316 	if (rc != 0) {
9317 		pr_err("error %d\n", rc);
9318 		goto rw_error;
9319 	}
9320 	/*   no of symbol errors      */
9321 	rc = drxj_dap_read_reg16(dev_addr, FEC_RS_NR_SYMBOL_ERRORS__A, &nr_symbol_errors, 0);
9322 	if (rc != 0) {
9323 		pr_err("error %d\n", rc);
9324 		goto rw_error;
9325 	}
9326 	/*   no of packet errors      */
9327 	rc = drxj_dap_read_reg16(dev_addr, FEC_RS_NR_PACKET_ERRORS__A, &nr_packet_errors, 0);
9328 	if (rc != 0) {
9329 		pr_err("error %d\n", rc);
9330 		goto rw_error;
9331 	}
9332 	/*   no of failures to decode */
9333 	rc = drxj_dap_read_reg16(dev_addr, FEC_RS_NR_FAILURES__A, &nr_failures, 0);
9334 	if (rc != 0) {
9335 		pr_err("error %d\n", rc);
9336 		goto rw_error;
9337 	}
9338 	/*   no of post RS bit erros  */
9339 	rc = drxj_dap_read_reg16(dev_addr, FEC_OC_SNC_FAIL_COUNT__A, &nr_snc_par_fail_count, 0);
9340 	if (rc != 0) {
9341 		pr_err("error %d\n", rc);
9342 		goto rw_error;
9343 	}
9344 	/* TODO: NOTE */
9345 	/* These register values are fetched in non-atomic fashion           */
9346 	/* It is possible that the read values contain unrelated information */
9347 
9348 	rs_errors->nr_bit_errors = nr_bit_errors & FEC_RS_NR_BIT_ERRORS__M;
9349 	rs_errors->nr_symbol_errors = nr_symbol_errors & FEC_RS_NR_SYMBOL_ERRORS__M;
9350 	rs_errors->nr_packet_errors = nr_packet_errors & FEC_RS_NR_PACKET_ERRORS__M;
9351 	rs_errors->nr_failures = nr_failures & FEC_RS_NR_FAILURES__M;
9352 	rs_errors->nr_snc_par_fail_count =
9353 	    nr_snc_par_fail_count & FEC_OC_SNC_FAIL_COUNT__M;
9354 
9355 	return 0;
9356 rw_error:
9357 	return rc;
9358 }
9359 
9360 /*============================================================================*/
9361 
9362 /*
9363  * \fn int get_sig_strength()
9364  * \brief Retrieve signal strength for VSB and QAM.
9365  * \param demod Pointer to demod instance
9366  * \param u16-t Pointer to signal strength data; range 0, .. , 100.
9367  * \return int.
9368  * \retval 0 sig_strength contains valid data.
9369  * \retval -EINVAL sig_strength is NULL.
9370  * \retval -EIO Erroneous data, sig_strength contains invalid data.
9371  */
9372 #define DRXJ_AGC_TOP    0x2800
9373 #define DRXJ_AGC_SNS    0x1600
9374 #define DRXJ_RFAGC_MAX  0x3fff
9375 #define DRXJ_RFAGC_MIN  0x800
9376 
9377 static int get_sig_strength(struct drx_demod_instance *demod, u16 *sig_strength)
9378 {
9379 	struct i2c_device_addr *dev_addr = demod->my_i2c_dev_addr;
9380 	int rc;
9381 	u16 rf_gain = 0;
9382 	u16 if_gain = 0;
9383 	u16 if_agc_sns = 0;
9384 	u16 if_agc_top = 0;
9385 	u16 rf_agc_max = 0;
9386 	u16 rf_agc_min = 0;
9387 
9388 	rc = drxj_dap_read_reg16(dev_addr, IQM_AF_AGC_IF__A, &if_gain, 0);
9389 	if (rc != 0) {
9390 		pr_err("error %d\n", rc);
9391 		goto rw_error;
9392 	}
9393 	if_gain &= IQM_AF_AGC_IF__M;
9394 	rc = drxj_dap_read_reg16(dev_addr, IQM_AF_AGC_RF__A, &rf_gain, 0);
9395 	if (rc != 0) {
9396 		pr_err("error %d\n", rc);
9397 		goto rw_error;
9398 	}
9399 	rf_gain &= IQM_AF_AGC_RF__M;
9400 
9401 	if_agc_sns = DRXJ_AGC_SNS;
9402 	if_agc_top = DRXJ_AGC_TOP;
9403 	rf_agc_max = DRXJ_RFAGC_MAX;
9404 	rf_agc_min = DRXJ_RFAGC_MIN;
9405 
9406 	if (if_gain > if_agc_top) {
9407 		if (rf_gain > rf_agc_max)
9408 			*sig_strength = 100;
9409 		else if (rf_gain > rf_agc_min) {
9410 			if (rf_agc_max == rf_agc_min) {
9411 				pr_err("error: rf_agc_max == rf_agc_min\n");
9412 				return -EIO;
9413 			}
9414 			*sig_strength =
9415 			75 + 25 * (rf_gain - rf_agc_min) / (rf_agc_max -
9416 								rf_agc_min);
9417 		} else
9418 			*sig_strength = 75;
9419 	} else if (if_gain > if_agc_sns) {
9420 		if (if_agc_top == if_agc_sns) {
9421 			pr_err("error: if_agc_top == if_agc_sns\n");
9422 			return -EIO;
9423 		}
9424 		*sig_strength =
9425 		20 + 55 * (if_gain - if_agc_sns) / (if_agc_top - if_agc_sns);
9426 	} else {
9427 		if (!if_agc_sns) {
9428 			pr_err("error: if_agc_sns is zero!\n");
9429 			return -EIO;
9430 		}
9431 		*sig_strength = (20 * if_gain / if_agc_sns);
9432 	}
9433 
9434 	if (*sig_strength <= 7)
9435 		*sig_strength = 0;
9436 
9437 	return 0;
9438 rw_error:
9439 	return rc;
9440 }
9441 
9442 /*
9443 * \fn int ctrl_get_qam_sig_quality()
9444 * \brief Retrieve QAM signal quality from device.
9445 * \param devmod Pointer to demodulator instance.
9446 * \param sig_quality Pointer to signal quality data.
9447 * \return int.
9448 * \retval 0 sig_quality contains valid data.
9449 * \retval -EINVAL sig_quality is NULL.
9450 * \retval -EIO Erroneous data, sig_quality contains invalid data.
9451 
9452 *  Pre-condition: Device must be started and in lock.
9453 */
9454 static int
9455 ctrl_get_qam_sig_quality(struct drx_demod_instance *demod)
9456 {
9457 	struct i2c_device_addr *dev_addr = demod->my_i2c_dev_addr;
9458 	struct drxj_data *ext_attr = demod->my_ext_attr;
9459 	struct drx39xxj_state *state = dev_addr->user_data;
9460 	struct dtv_frontend_properties *p = &state->frontend.dtv_property_cache;
9461 	struct drxjrs_errors measuredrs_errors = { 0, 0, 0, 0, 0 };
9462 	enum drx_modulation constellation = ext_attr->constellation;
9463 	int rc;
9464 
9465 	u32 pre_bit_err_rs = 0;	/* pre RedSolomon Bit Error Rate */
9466 	u32 post_bit_err_rs = 0;	/* post RedSolomon Bit Error Rate */
9467 	u32 pkt_errs = 0;	/* no of packet errors in RS */
9468 	u16 qam_sl_err_power = 0;	/* accumulated error between raw and sliced symbols */
9469 	u16 qsym_err_vd = 0;	/* quadrature symbol errors in QAM_VD */
9470 	u16 fec_oc_period = 0;	/* SNC sync failure measurement period */
9471 	u16 fec_rs_prescale = 0;	/* ReedSolomon Measurement Prescale */
9472 	u16 fec_rs_period = 0;	/* Value for corresponding I2C register */
9473 	/* calculation constants */
9474 	u32 rs_bit_cnt = 0;	/* RedSolomon Bit Count */
9475 	u32 qam_sl_sig_power = 0;	/* used for MER, depends of QAM constellation */
9476 	/* intermediate results */
9477 	u32 e = 0;		/* exponent value used for QAM BER/SER */
9478 	u32 m = 0;		/* mantisa value used for QAM BER/SER */
9479 	u32 ber_cnt = 0;	/* BER count */
9480 	/* signal quality info */
9481 	u32 qam_sl_mer = 0;	/* QAM MER */
9482 	u32 qam_pre_rs_ber = 0;	/* Pre RedSolomon BER */
9483 	u32 qam_post_rs_ber = 0;	/* Post RedSolomon BER */
9484 	u32 qam_vd_ser = 0;	/* ViterbiDecoder SER */
9485 	u16 qam_vd_prescale = 0;	/* Viterbi Measurement Prescale */
9486 	u16 qam_vd_period = 0;	/* Viterbi Measurement period */
9487 	u32 vd_bit_cnt = 0;	/* ViterbiDecoder Bit Count */
9488 
9489 	p->block_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
9490 
9491 	/* read the physical registers */
9492 	/*   Get the RS error data */
9493 	rc = get_qamrs_err_count(dev_addr, &measuredrs_errors);
9494 	if (rc != 0) {
9495 		pr_err("error %d\n", rc);
9496 		goto rw_error;
9497 	}
9498 	/* get the register value needed for MER */
9499 	rc = drxj_dap_read_reg16(dev_addr, QAM_SL_ERR_POWER__A, &qam_sl_err_power, 0);
9500 	if (rc != 0) {
9501 		pr_err("error %d\n", rc);
9502 		goto rw_error;
9503 	}
9504 	/* get the register value needed for post RS BER */
9505 	rc = drxj_dap_read_reg16(dev_addr, FEC_OC_SNC_FAIL_PERIOD__A, &fec_oc_period, 0);
9506 	if (rc != 0) {
9507 		pr_err("error %d\n", rc);
9508 		goto rw_error;
9509 	}
9510 
9511 	/* get constants needed for signal quality calculation */
9512 	fec_rs_period = ext_attr->fec_rs_period;
9513 	fec_rs_prescale = ext_attr->fec_rs_prescale;
9514 	rs_bit_cnt = fec_rs_period * fec_rs_prescale * ext_attr->fec_rs_plen;
9515 	qam_vd_period = ext_attr->qam_vd_period;
9516 	qam_vd_prescale = ext_attr->qam_vd_prescale;
9517 	vd_bit_cnt = qam_vd_period * qam_vd_prescale * ext_attr->fec_vd_plen;
9518 
9519 	/* DRXJ_QAM_SL_SIG_POWER_QAMxxx  * 4     */
9520 	switch (constellation) {
9521 	case DRX_CONSTELLATION_QAM16:
9522 		qam_sl_sig_power = DRXJ_QAM_SL_SIG_POWER_QAM16 << 2;
9523 		break;
9524 	case DRX_CONSTELLATION_QAM32:
9525 		qam_sl_sig_power = DRXJ_QAM_SL_SIG_POWER_QAM32 << 2;
9526 		break;
9527 	case DRX_CONSTELLATION_QAM64:
9528 		qam_sl_sig_power = DRXJ_QAM_SL_SIG_POWER_QAM64 << 2;
9529 		break;
9530 	case DRX_CONSTELLATION_QAM128:
9531 		qam_sl_sig_power = DRXJ_QAM_SL_SIG_POWER_QAM128 << 2;
9532 		break;
9533 	case DRX_CONSTELLATION_QAM256:
9534 		qam_sl_sig_power = DRXJ_QAM_SL_SIG_POWER_QAM256 << 2;
9535 		break;
9536 	default:
9537 		return -EIO;
9538 	}
9539 
9540 	/* ------------------------------ */
9541 	/* MER Calculation                */
9542 	/* ------------------------------ */
9543 	/* MER is good if it is above 27.5 for QAM256 or 21.5 for QAM64 */
9544 
9545 	/* 10.0*log10(qam_sl_sig_power * 4.0 / qam_sl_err_power); */
9546 	if (qam_sl_err_power == 0)
9547 		qam_sl_mer = 0;
9548 	else
9549 		qam_sl_mer = log1_times100(qam_sl_sig_power) - log1_times100((u32)qam_sl_err_power);
9550 
9551 	/* ----------------------------------------- */
9552 	/* Pre Viterbi Symbol Error Rate Calculation */
9553 	/* ----------------------------------------- */
9554 	/* pre viterbi SER is good if it is below 0.025 */
9555 
9556 	/* get the register value */
9557 	/*   no of quadrature symbol errors */
9558 	rc = drxj_dap_read_reg16(dev_addr, QAM_VD_NR_QSYM_ERRORS__A, &qsym_err_vd, 0);
9559 	if (rc != 0) {
9560 		pr_err("error %d\n", rc);
9561 		goto rw_error;
9562 	}
9563 	/* Extract the Exponent and the Mantisa  */
9564 	/* of number of quadrature symbol errors */
9565 	e = (qsym_err_vd & QAM_VD_NR_QSYM_ERRORS_EXP__M) >>
9566 	    QAM_VD_NR_QSYM_ERRORS_EXP__B;
9567 	m = (qsym_err_vd & QAM_VD_NR_SYMBOL_ERRORS_FIXED_MANT__M) >>
9568 	    QAM_VD_NR_SYMBOL_ERRORS_FIXED_MANT__B;
9569 
9570 	if ((m << e) >> 3 > 549752)
9571 		qam_vd_ser = 500000 * vd_bit_cnt * ((e > 2) ? 1 : 8) / 8;
9572 	else
9573 		qam_vd_ser = m << ((e > 2) ? (e - 3) : e);
9574 
9575 	/* --------------------------------------- */
9576 	/* pre and post RedSolomon BER Calculation */
9577 	/* --------------------------------------- */
9578 	/* pre RS BER is good if it is below 3.5e-4 */
9579 
9580 	/* get the register values */
9581 	pre_bit_err_rs = (u32) measuredrs_errors.nr_bit_errors;
9582 	pkt_errs = post_bit_err_rs = (u32) measuredrs_errors.nr_snc_par_fail_count;
9583 
9584 	/* Extract the Exponent and the Mantisa of the */
9585 	/* pre Reed-Solomon bit error count            */
9586 	e = (pre_bit_err_rs & FEC_RS_NR_BIT_ERRORS_EXP__M) >>
9587 	    FEC_RS_NR_BIT_ERRORS_EXP__B;
9588 	m = (pre_bit_err_rs & FEC_RS_NR_BIT_ERRORS_FIXED_MANT__M) >>
9589 	    FEC_RS_NR_BIT_ERRORS_FIXED_MANT__B;
9590 
9591 	ber_cnt = m << e;
9592 
9593 	/*qam_pre_rs_ber = frac_times1e6( ber_cnt, rs_bit_cnt ); */
9594 	if (m > (rs_bit_cnt >> (e + 1)) || (rs_bit_cnt >> e) == 0)
9595 		qam_pre_rs_ber = 500000 * rs_bit_cnt >> e;
9596 	else
9597 		qam_pre_rs_ber = ber_cnt;
9598 
9599 	/* post RS BER = 1000000* (11.17 * FEC_OC_SNC_FAIL_COUNT__A) /  */
9600 	/*               (1504.0 * FEC_OC_SNC_FAIL_PERIOD__A)  */
9601 	/*
9602 	   => c = (1000000*100*11.17)/1504 =
9603 	   post RS BER = (( c* FEC_OC_SNC_FAIL_COUNT__A) /
9604 	   (100 * FEC_OC_SNC_FAIL_PERIOD__A)
9605 	   *100 and /100 is for more precision.
9606 	   => (20 bits * 12 bits) /(16 bits * 7 bits)  => safe in 32 bits computation
9607 
9608 	   Precision errors still possible.
9609 	 */
9610 	if (!fec_oc_period) {
9611 		qam_post_rs_ber = 0xFFFFFFFF;
9612 	} else {
9613 		e = post_bit_err_rs * 742686;
9614 		m = fec_oc_period * 100;
9615 		qam_post_rs_ber = e / m;
9616 	}
9617 
9618 	/* fill signal quality data structure */
9619 	p->pre_bit_count.stat[0].scale = FE_SCALE_COUNTER;
9620 	p->post_bit_count.stat[0].scale = FE_SCALE_COUNTER;
9621 	p->pre_bit_error.stat[0].scale = FE_SCALE_COUNTER;
9622 	p->post_bit_error.stat[0].scale = FE_SCALE_COUNTER;
9623 	p->block_error.stat[0].scale = FE_SCALE_COUNTER;
9624 	p->cnr.stat[0].scale = FE_SCALE_DECIBEL;
9625 
9626 	p->cnr.stat[0].svalue = ((u16) qam_sl_mer) * 100;
9627 	if (ext_attr->standard == DRX_STANDARD_ITU_B) {
9628 		p->pre_bit_error.stat[0].uvalue += qam_vd_ser;
9629 		p->pre_bit_count.stat[0].uvalue += vd_bit_cnt * ((e > 2) ? 1 : 8) / 8;
9630 	} else {
9631 		p->pre_bit_error.stat[0].uvalue += qam_pre_rs_ber;
9632 		p->pre_bit_count.stat[0].uvalue += rs_bit_cnt >> e;
9633 	}
9634 
9635 	p->post_bit_error.stat[0].uvalue += qam_post_rs_ber;
9636 	p->post_bit_count.stat[0].uvalue += rs_bit_cnt >> e;
9637 
9638 	p->block_error.stat[0].uvalue += pkt_errs;
9639 
9640 #ifdef DRXJ_SIGNAL_ACCUM_ERR
9641 	rc = get_acc_pkt_err(demod, &sig_quality->packet_error);
9642 	if (rc != 0) {
9643 		pr_err("error %d\n", rc);
9644 		goto rw_error;
9645 	}
9646 #endif
9647 
9648 	return 0;
9649 rw_error:
9650 	p->pre_bit_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
9651 	p->post_bit_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
9652 	p->pre_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
9653 	p->post_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
9654 	p->block_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
9655 	p->cnr.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
9656 
9657 	return rc;
9658 }
9659 
9660 #endif /* #ifndef DRXJ_VSB_ONLY */
9661 
9662 /*============================================================================*/
9663 /*==                     END QAM DATAPATH FUNCTIONS                         ==*/
9664 /*============================================================================*/
9665 
9666 /*============================================================================*/
9667 /*============================================================================*/
9668 /*==                       ATV DATAPATH FUNCTIONS                           ==*/
9669 /*============================================================================*/
9670 /*============================================================================*/
9671 
9672 /*
9673    Implementation notes.
9674 
9675    NTSC/FM AGCs
9676 
9677       Four AGCs are used for NTSC:
9678       (1) RF (used to attenuate the input signal in case of to much power)
9679       (2) IF (used to attenuate the input signal in case of to much power)
9680       (3) Video AGC (used to amplify the output signal in case input to low)
9681       (4) SIF AGC (used to amplify the output signal in case input to low)
9682 
9683       Video AGC is coupled to RF and IF. SIF AGC is not coupled. It is assumed
9684       that the coupling between Video AGC and the RF and IF AGCs also works in
9685       favor of the SIF AGC.
9686 
9687       Three AGCs are used for FM:
9688       (1) RF (used to attenuate the input signal in case of to much power)
9689       (2) IF (used to attenuate the input signal in case of to much power)
9690       (3) SIF AGC (used to amplify the output signal in case input to low)
9691 
9692       The SIF AGC is now coupled to the RF/IF AGCs.
9693       The SIF AGC is needed for both SIF ouput and the internal SIF signal to
9694       the AUD block.
9695 
9696       RF and IF AGCs DACs are part of AFE, Video and SIF AGC DACs are part of
9697       the ATV block. The AGC control algorithms are all implemented in
9698       microcode.
9699 
9700    ATV SETTINGS
9701 
9702       (Shadow settings will not be used for now, they will be implemented
9703        later on because of the schedule)
9704 
9705       Several HW/SCU "settings" can be used for ATV. The standard selection
9706       will reset most of these settings. To avoid that the end user apllication
9707       has to perform these settings each time the ATV or FM standards is
9708       selected the driver will shadow these settings. This enables the end user
9709       to perform the settings only once after a drx_open(). The driver must
9710       write the shadow settings to HW/SCU incase:
9711 	 ( setstandard FM/ATV) ||
9712 	 ( settings have changed && FM/ATV standard is active)
9713       The shadow settings will be stored in the device specific data container.
9714       A set of flags will be defined to flag changes in shadow settings.
9715       A routine will be implemented to write all changed shadow settings to
9716       HW/SCU.
9717 
9718       The "settings" will consist of: AGC settings, filter settings etc.
9719 
9720       Disadvantage of use of shadow settings:
9721       Direct changes in HW/SCU registers will not be reflected in the
9722       shadow settings and these changes will be overwritten during a next
9723       update. This can happen during evaluation. This will not be a problem
9724       for normal customer usage.
9725 */
9726 /* -------------------------------------------------------------------------- */
9727 
9728 /*
9729 * \fn int power_down_atv ()
9730 * \brief Power down ATV.
9731 * \param demod instance of demodulator
9732 * \param standard either NTSC or FM (sub strandard for ATV )
9733 * \return int.
9734 *
9735 *  Stops and thus resets ATV and IQM block
9736 *  SIF and CVBS ADC are powered down
9737 *  Calls audio power down
9738 */
9739 static int
9740 power_down_atv(struct drx_demod_instance *demod, enum drx_standard standard, bool primary)
9741 {
9742 	struct i2c_device_addr *dev_addr = demod->my_i2c_dev_addr;
9743 	struct drxjscu_cmd cmd_scu = { /* command      */ 0,
9744 		/* parameter_len */ 0,
9745 		/* result_len    */ 0,
9746 		/* *parameter   */ NULL,
9747 		/* *result      */ NULL
9748 	};
9749 	int rc;
9750 	u16 cmd_result = 0;
9751 
9752 	/* ATV NTSC */
9753 
9754 	/* Stop ATV SCU (will reset ATV and IQM hardware */
9755 	cmd_scu.command = SCU_RAM_COMMAND_STANDARD_ATV |
9756 	    SCU_RAM_COMMAND_CMD_DEMOD_STOP;
9757 	cmd_scu.parameter_len = 0;
9758 	cmd_scu.result_len = 1;
9759 	cmd_scu.parameter = NULL;
9760 	cmd_scu.result = &cmd_result;
9761 	rc = scu_command(dev_addr, &cmd_scu);
9762 	if (rc != 0) {
9763 		pr_err("error %d\n", rc);
9764 		goto rw_error;
9765 	}
9766 	/* Disable ATV outputs (ATV reset enables CVBS, undo this) */
9767 	rc = drxj_dap_write_reg16(dev_addr, ATV_TOP_STDBY__A, (ATV_TOP_STDBY_SIF_STDBY_STANDBY & (~ATV_TOP_STDBY_CVBS_STDBY_A2_ACTIVE)), 0);
9768 	if (rc != 0) {
9769 		pr_err("error %d\n", rc);
9770 		goto rw_error;
9771 	}
9772 
9773 	rc = drxj_dap_write_reg16(dev_addr, ATV_COMM_EXEC__A, ATV_COMM_EXEC_STOP, 0);
9774 	if (rc != 0) {
9775 		pr_err("error %d\n", rc);
9776 		goto rw_error;
9777 	}
9778 	if (primary) {
9779 		rc = drxj_dap_write_reg16(dev_addr, IQM_COMM_EXEC__A, IQM_COMM_EXEC_STOP, 0);
9780 		if (rc != 0) {
9781 			pr_err("error %d\n", rc);
9782 			goto rw_error;
9783 		}
9784 		rc = set_iqm_af(demod, false);
9785 		if (rc != 0) {
9786 			pr_err("error %d\n", rc);
9787 			goto rw_error;
9788 		}
9789 	} else {
9790 		rc = drxj_dap_write_reg16(dev_addr, IQM_FS_COMM_EXEC__A, IQM_FS_COMM_EXEC_STOP, 0);
9791 		if (rc != 0) {
9792 			pr_err("error %d\n", rc);
9793 			goto rw_error;
9794 		}
9795 		rc = drxj_dap_write_reg16(dev_addr, IQM_FD_COMM_EXEC__A, IQM_FD_COMM_EXEC_STOP, 0);
9796 		if (rc != 0) {
9797 			pr_err("error %d\n", rc);
9798 			goto rw_error;
9799 		}
9800 		rc = drxj_dap_write_reg16(dev_addr, IQM_RC_COMM_EXEC__A, IQM_RC_COMM_EXEC_STOP, 0);
9801 		if (rc != 0) {
9802 			pr_err("error %d\n", rc);
9803 			goto rw_error;
9804 		}
9805 		rc = drxj_dap_write_reg16(dev_addr, IQM_RT_COMM_EXEC__A, IQM_RT_COMM_EXEC_STOP, 0);
9806 		if (rc != 0) {
9807 			pr_err("error %d\n", rc);
9808 			goto rw_error;
9809 		}
9810 		rc = drxj_dap_write_reg16(dev_addr, IQM_CF_COMM_EXEC__A, IQM_CF_COMM_EXEC_STOP, 0);
9811 		if (rc != 0) {
9812 			pr_err("error %d\n", rc);
9813 			goto rw_error;
9814 		}
9815 	}
9816 	rc = power_down_aud(demod);
9817 	if (rc != 0) {
9818 		pr_err("error %d\n", rc);
9819 		goto rw_error;
9820 	}
9821 
9822 	return 0;
9823 rw_error:
9824 	return rc;
9825 }
9826 
9827 /*============================================================================*/
9828 
9829 /*
9830 * \brief Power up AUD.
9831 * \param demod instance of demodulator
9832 * \return int.
9833 *
9834 */
9835 static int power_down_aud(struct drx_demod_instance *demod)
9836 {
9837 	struct i2c_device_addr *dev_addr = NULL;
9838 	struct drxj_data *ext_attr = NULL;
9839 	int rc;
9840 
9841 	dev_addr = (struct i2c_device_addr *)demod->my_i2c_dev_addr;
9842 	ext_attr = (struct drxj_data *) demod->my_ext_attr;
9843 
9844 	rc = drxj_dap_write_reg16(dev_addr, AUD_COMM_EXEC__A, AUD_COMM_EXEC_STOP, 0);
9845 	if (rc != 0) {
9846 		pr_err("error %d\n", rc);
9847 		goto rw_error;
9848 	}
9849 
9850 	ext_attr->aud_data.audio_is_active = false;
9851 
9852 	return 0;
9853 rw_error:
9854 	return rc;
9855 }
9856 
9857 /*
9858 * \fn int set_orx_nsu_aox()
9859 * \brief Configure OrxNsuAox for OOB
9860 * \param demod instance of demodulator.
9861 * \param active
9862 * \return int.
9863 */
9864 static int set_orx_nsu_aox(struct drx_demod_instance *demod, bool active)
9865 {
9866 	struct i2c_device_addr *dev_addr = demod->my_i2c_dev_addr;
9867 	int rc;
9868 	u16 data = 0;
9869 
9870 	/* Configure NSU_AOX */
9871 	rc = drxj_dap_read_reg16(dev_addr, ORX_NSU_AOX_STDBY_W__A, &data, 0);
9872 	if (rc != 0) {
9873 		pr_err("error %d\n", rc);
9874 		goto rw_error;
9875 	}
9876 	if (!active)
9877 		data &= ((~ORX_NSU_AOX_STDBY_W_STDBYADC_A2_ON) & (~ORX_NSU_AOX_STDBY_W_STDBYAMP_A2_ON) & (~ORX_NSU_AOX_STDBY_W_STDBYBIAS_A2_ON) & (~ORX_NSU_AOX_STDBY_W_STDBYPLL_A2_ON) & (~ORX_NSU_AOX_STDBY_W_STDBYPD_A2_ON) & (~ORX_NSU_AOX_STDBY_W_STDBYTAGC_IF_A2_ON) & (~ORX_NSU_AOX_STDBY_W_STDBYTAGC_RF_A2_ON) & (~ORX_NSU_AOX_STDBY_W_STDBYFLT_A2_ON));
9878 	else
9879 		data |= (ORX_NSU_AOX_STDBY_W_STDBYADC_A2_ON | ORX_NSU_AOX_STDBY_W_STDBYAMP_A2_ON | ORX_NSU_AOX_STDBY_W_STDBYBIAS_A2_ON | ORX_NSU_AOX_STDBY_W_STDBYPLL_A2_ON | ORX_NSU_AOX_STDBY_W_STDBYPD_A2_ON | ORX_NSU_AOX_STDBY_W_STDBYTAGC_IF_A2_ON | ORX_NSU_AOX_STDBY_W_STDBYTAGC_RF_A2_ON | ORX_NSU_AOX_STDBY_W_STDBYFLT_A2_ON);
9880 	rc = drxj_dap_write_reg16(dev_addr, ORX_NSU_AOX_STDBY_W__A, data, 0);
9881 	if (rc != 0) {
9882 		pr_err("error %d\n", rc);
9883 		goto rw_error;
9884 	}
9885 
9886 	return 0;
9887 rw_error:
9888 	return rc;
9889 }
9890 
9891 /*
9892 * \fn int ctrl_set_oob()
9893 * \brief Set OOB channel to be used.
9894 * \param demod instance of demodulator
9895 * \param oob_param OOB parameters for channel setting.
9896 * \frequency should be in KHz
9897 * \return int.
9898 *
9899 * Accepts  only. Returns error otherwise.
9900 * Demapper value is written after scu_command START
9901 * because START command causes COMM_EXEC transition
9902 * from 0 to 1 which causes all registers to be
9903 * overwritten with initial value
9904 *
9905 */
9906 
9907 /* Nyquist filter impulse response */
9908 #define IMPULSE_COSINE_ALPHA_0_3    {-3, -4, -1, 6, 10, 7, -5, -20, -25, -10, 29, 79, 123, 140}	/*sqrt raised-cosine filter with alpha=0.3 */
9909 #define IMPULSE_COSINE_ALPHA_0_5    { 2, 0, -2, -2, 2, 5, 2, -10, -20, -14, 20, 74, 125, 145}	/*sqrt raised-cosine filter with alpha=0.5 */
9910 #define IMPULSE_COSINE_ALPHA_RO_0_5 { 0, 0, 1, 2, 3, 0, -7, -15, -16,  0, 34, 77, 114, 128}	/*full raised-cosine filter with alpha=0.5 (receiver only) */
9911 
9912 /* Coefficients for the nyquist fitler (total: 27 taps) */
9913 #define NYQFILTERLEN 27
9914 
9915 static int ctrl_set_oob(struct drx_demod_instance *demod, struct drxoob *oob_param)
9916 {
9917 	int rc;
9918 	s32 freq = 0;	/* KHz */
9919 	struct i2c_device_addr *dev_addr = NULL;
9920 	struct drxj_data *ext_attr = NULL;
9921 	u16 i = 0;
9922 	bool mirror_freq_spect_oob = false;
9923 	u16 trk_filter_value = 0;
9924 	struct drxjscu_cmd scu_cmd;
9925 	u16 set_param_parameters[3];
9926 	u16 cmd_result[2] = { 0, 0 };
9927 	s16 nyquist_coeffs[4][(NYQFILTERLEN + 1) / 2] = {
9928 		IMPULSE_COSINE_ALPHA_0_3,	/* Target Mode 0 */
9929 		IMPULSE_COSINE_ALPHA_0_3,	/* Target Mode 1 */
9930 		IMPULSE_COSINE_ALPHA_0_5,	/* Target Mode 2 */
9931 		IMPULSE_COSINE_ALPHA_RO_0_5	/* Target Mode 3 */
9932 	};
9933 	u8 mode_val[4] = { 2, 2, 0, 1 };
9934 	u8 pfi_coeffs[4][6] = {
9935 		{DRXJ_16TO8(-92), DRXJ_16TO8(-108), DRXJ_16TO8(100)},	/* TARGET_MODE = 0:     PFI_A = -23/32; PFI_B = -54/32;  PFI_C = 25/32; fg = 0.5 MHz (Att=26dB) */
9936 		{DRXJ_16TO8(-64), DRXJ_16TO8(-80), DRXJ_16TO8(80)},	/* TARGET_MODE = 1:     PFI_A = -16/32; PFI_B = -40/32;  PFI_C = 20/32; fg = 1.0 MHz (Att=28dB) */
9937 		{DRXJ_16TO8(-80), DRXJ_16TO8(-98), DRXJ_16TO8(92)},	/* TARGET_MODE = 2, 3:  PFI_A = -20/32; PFI_B = -49/32;  PFI_C = 23/32; fg = 0.8 MHz (Att=25dB) */
9938 		{DRXJ_16TO8(-80), DRXJ_16TO8(-98), DRXJ_16TO8(92)}	/* TARGET_MODE = 2, 3:  PFI_A = -20/32; PFI_B = -49/32;  PFI_C = 23/32; fg = 0.8 MHz (Att=25dB) */
9939 	};
9940 	u16 mode_index;
9941 
9942 	dev_addr = demod->my_i2c_dev_addr;
9943 	ext_attr = (struct drxj_data *) demod->my_ext_attr;
9944 	mirror_freq_spect_oob = ext_attr->mirror_freq_spect_oob;
9945 
9946 	/* Check parameters */
9947 	if (oob_param == NULL) {
9948 		/* power off oob module  */
9949 		scu_cmd.command = SCU_RAM_COMMAND_STANDARD_OOB
9950 		    | SCU_RAM_COMMAND_CMD_DEMOD_STOP;
9951 		scu_cmd.parameter_len = 0;
9952 		scu_cmd.result_len = 1;
9953 		scu_cmd.result = cmd_result;
9954 		rc = scu_command(dev_addr, &scu_cmd);
9955 		if (rc != 0) {
9956 			pr_err("error %d\n", rc);
9957 			goto rw_error;
9958 		}
9959 		rc = set_orx_nsu_aox(demod, false);
9960 		if (rc != 0) {
9961 			pr_err("error %d\n", rc);
9962 			goto rw_error;
9963 		}
9964 		rc = drxj_dap_write_reg16(dev_addr, ORX_COMM_EXEC__A, ORX_COMM_EXEC_STOP, 0);
9965 		if (rc != 0) {
9966 			pr_err("error %d\n", rc);
9967 			goto rw_error;
9968 		}
9969 
9970 		ext_attr->oob_power_on = false;
9971 		return 0;
9972 	}
9973 
9974 	freq = oob_param->frequency;
9975 	if ((freq < 70000) || (freq > 130000))
9976 		return -EIO;
9977 	freq = (freq - 50000) / 50;
9978 
9979 	{
9980 		u16 index = 0;
9981 		u16 remainder = 0;
9982 		u16 *trk_filtercfg = ext_attr->oob_trk_filter_cfg;
9983 
9984 		index = (u16) ((freq - 400) / 200);
9985 		remainder = (u16) ((freq - 400) % 200);
9986 		trk_filter_value =
9987 		    trk_filtercfg[index] - (trk_filtercfg[index] -
9988 					   trk_filtercfg[index +
9989 							1]) / 10 * remainder /
9990 		    20;
9991 	}
9992 
9993    /********/
9994 	/* Stop  */
9995    /********/
9996 	rc = drxj_dap_write_reg16(dev_addr, ORX_COMM_EXEC__A, ORX_COMM_EXEC_STOP, 0);
9997 	if (rc != 0) {
9998 		pr_err("error %d\n", rc);
9999 		goto rw_error;
10000 	}
10001 	scu_cmd.command = SCU_RAM_COMMAND_STANDARD_OOB
10002 	    | SCU_RAM_COMMAND_CMD_DEMOD_STOP;
10003 	scu_cmd.parameter_len = 0;
10004 	scu_cmd.result_len = 1;
10005 	scu_cmd.result = cmd_result;
10006 	rc = scu_command(dev_addr, &scu_cmd);
10007 	if (rc != 0) {
10008 		pr_err("error %d\n", rc);
10009 		goto rw_error;
10010 	}
10011    /********/
10012 	/* Reset */
10013    /********/
10014 	scu_cmd.command = SCU_RAM_COMMAND_STANDARD_OOB
10015 	    | SCU_RAM_COMMAND_CMD_DEMOD_RESET;
10016 	scu_cmd.parameter_len = 0;
10017 	scu_cmd.result_len = 1;
10018 	scu_cmd.result = cmd_result;
10019 	rc = scu_command(dev_addr, &scu_cmd);
10020 	if (rc != 0) {
10021 		pr_err("error %d\n", rc);
10022 		goto rw_error;
10023 	}
10024    /**********/
10025 	/* SET_ENV */
10026    /**********/
10027 	/* set frequency, spectrum inversion and data rate */
10028 	scu_cmd.command = SCU_RAM_COMMAND_STANDARD_OOB
10029 	    | SCU_RAM_COMMAND_CMD_DEMOD_SET_ENV;
10030 	scu_cmd.parameter_len = 3;
10031 	/* 1-data rate;2-frequency */
10032 	switch (oob_param->standard) {
10033 	case DRX_OOB_MODE_A:
10034 		if (
10035 			   /* signal is transmitted inverted */
10036 			   ((oob_param->spectrum_inverted == true) &&
10037 			    /* and tuner is not mirroring the signal */
10038 			    (!mirror_freq_spect_oob)) |
10039 			   /* or */
10040 			   /* signal is transmitted noninverted */
10041 			   ((oob_param->spectrum_inverted == false) &&
10042 			    /* and tuner is mirroring the signal */
10043 			    (mirror_freq_spect_oob))
10044 		    )
10045 			set_param_parameters[0] =
10046 			    SCU_RAM_ORX_RF_RX_DATA_RATE_2048KBPS_INVSPEC;
10047 		else
10048 			set_param_parameters[0] =
10049 			    SCU_RAM_ORX_RF_RX_DATA_RATE_2048KBPS_REGSPEC;
10050 		break;
10051 	case DRX_OOB_MODE_B_GRADE_A:
10052 		if (
10053 			   /* signal is transmitted inverted */
10054 			   ((oob_param->spectrum_inverted == true) &&
10055 			    /* and tuner is not mirroring the signal */
10056 			    (!mirror_freq_spect_oob)) |
10057 			   /* or */
10058 			   /* signal is transmitted noninverted */
10059 			   ((oob_param->spectrum_inverted == false) &&
10060 			    /* and tuner is mirroring the signal */
10061 			    (mirror_freq_spect_oob))
10062 		    )
10063 			set_param_parameters[0] =
10064 			    SCU_RAM_ORX_RF_RX_DATA_RATE_1544KBPS_INVSPEC;
10065 		else
10066 			set_param_parameters[0] =
10067 			    SCU_RAM_ORX_RF_RX_DATA_RATE_1544KBPS_REGSPEC;
10068 		break;
10069 	case DRX_OOB_MODE_B_GRADE_B:
10070 	default:
10071 		if (
10072 			   /* signal is transmitted inverted */
10073 			   ((oob_param->spectrum_inverted == true) &&
10074 			    /* and tuner is not mirroring the signal */
10075 			    (!mirror_freq_spect_oob)) |
10076 			   /* or */
10077 			   /* signal is transmitted noninverted */
10078 			   ((oob_param->spectrum_inverted == false) &&
10079 			    /* and tuner is mirroring the signal */
10080 			    (mirror_freq_spect_oob))
10081 		    )
10082 			set_param_parameters[0] =
10083 			    SCU_RAM_ORX_RF_RX_DATA_RATE_3088KBPS_INVSPEC;
10084 		else
10085 			set_param_parameters[0] =
10086 			    SCU_RAM_ORX_RF_RX_DATA_RATE_3088KBPS_REGSPEC;
10087 		break;
10088 	}
10089 	set_param_parameters[1] = (u16) (freq & 0xFFFF);
10090 	set_param_parameters[2] = trk_filter_value;
10091 	scu_cmd.parameter = set_param_parameters;
10092 	scu_cmd.result_len = 1;
10093 	scu_cmd.result = cmd_result;
10094 	mode_index = mode_val[(set_param_parameters[0] & 0xC0) >> 6];
10095 	rc = scu_command(dev_addr, &scu_cmd);
10096 	if (rc != 0) {
10097 		pr_err("error %d\n", rc);
10098 		goto rw_error;
10099 	}
10100 
10101 	rc = drxj_dap_write_reg16(dev_addr, SIO_TOP_COMM_KEY__A, 0xFABA, 0);
10102 	if (rc != 0) {
10103 		pr_err("error %d\n", rc);
10104 		goto rw_error;
10105 	}	/*  Write magic word to enable pdr reg write  */
10106 	rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_OOB_CRX_CFG__A, OOB_CRX_DRIVE_STRENGTH << SIO_PDR_OOB_CRX_CFG_DRIVE__B | 0x03 << SIO_PDR_OOB_CRX_CFG_MODE__B, 0);
10107 	if (rc != 0) {
10108 		pr_err("error %d\n", rc);
10109 		goto rw_error;
10110 	}
10111 	rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_OOB_DRX_CFG__A, OOB_DRX_DRIVE_STRENGTH << SIO_PDR_OOB_DRX_CFG_DRIVE__B | 0x03 << SIO_PDR_OOB_DRX_CFG_MODE__B, 0);
10112 	if (rc != 0) {
10113 		pr_err("error %d\n", rc);
10114 		goto rw_error;
10115 	}
10116 	rc = drxj_dap_write_reg16(dev_addr, SIO_TOP_COMM_KEY__A, 0x0000, 0);
10117 	if (rc != 0) {
10118 		pr_err("error %d\n", rc);
10119 		goto rw_error;
10120 	}	/*  Write magic word to disable pdr reg write */
10121 
10122 	rc = drxj_dap_write_reg16(dev_addr, ORX_TOP_COMM_KEY__A, 0, 0);
10123 	if (rc != 0) {
10124 		pr_err("error %d\n", rc);
10125 		goto rw_error;
10126 	}
10127 	rc = drxj_dap_write_reg16(dev_addr, ORX_FWP_AAG_LEN_W__A, 16000, 0);
10128 	if (rc != 0) {
10129 		pr_err("error %d\n", rc);
10130 		goto rw_error;
10131 	}
10132 	rc = drxj_dap_write_reg16(dev_addr, ORX_FWP_AAG_THR_W__A, 40, 0);
10133 	if (rc != 0) {
10134 		pr_err("error %d\n", rc);
10135 		goto rw_error;
10136 	}
10137 
10138 	/* ddc */
10139 	rc = drxj_dap_write_reg16(dev_addr, ORX_DDC_OFO_SET_W__A, ORX_DDC_OFO_SET_W__PRE, 0);
10140 	if (rc != 0) {
10141 		pr_err("error %d\n", rc);
10142 		goto rw_error;
10143 	}
10144 
10145 	/* nsu */
10146 	rc = drxj_dap_write_reg16(dev_addr, ORX_NSU_AOX_LOPOW_W__A, ext_attr->oob_lo_pow, 0);
10147 	if (rc != 0) {
10148 		pr_err("error %d\n", rc);
10149 		goto rw_error;
10150 	}
10151 
10152 	/* initialization for target mode */
10153 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_TARGET_MODE__A, SCU_RAM_ORX_TARGET_MODE_2048KBPS_SQRT, 0);
10154 	if (rc != 0) {
10155 		pr_err("error %d\n", rc);
10156 		goto rw_error;
10157 	}
10158 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_FREQ_GAIN_CORR__A, SCU_RAM_ORX_FREQ_GAIN_CORR_2048KBPS, 0);
10159 	if (rc != 0) {
10160 		pr_err("error %d\n", rc);
10161 		goto rw_error;
10162 	}
10163 
10164 	/* Reset bits for timing and freq. recovery */
10165 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_RST_CPH__A, 0x0001, 0);
10166 	if (rc != 0) {
10167 		pr_err("error %d\n", rc);
10168 		goto rw_error;
10169 	}
10170 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_RST_CTI__A, 0x0002, 0);
10171 	if (rc != 0) {
10172 		pr_err("error %d\n", rc);
10173 		goto rw_error;
10174 	}
10175 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_RST_KRN__A, 0x0004, 0);
10176 	if (rc != 0) {
10177 		pr_err("error %d\n", rc);
10178 		goto rw_error;
10179 	}
10180 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_RST_KRP__A, 0x0008, 0);
10181 	if (rc != 0) {
10182 		pr_err("error %d\n", rc);
10183 		goto rw_error;
10184 	}
10185 
10186 	/* AGN_LOCK = {2048>>3, -2048, 8, -8, 0, 1}; */
10187 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_AGN_LOCK_TH__A, 2048 >> 3, 0);
10188 	if (rc != 0) {
10189 		pr_err("error %d\n", rc);
10190 		goto rw_error;
10191 	}
10192 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_AGN_LOCK_TOTH__A, (u16)(-2048), 0);
10193 	if (rc != 0) {
10194 		pr_err("error %d\n", rc);
10195 		goto rw_error;
10196 	}
10197 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_AGN_ONLOCK_TTH__A, 8, 0);
10198 	if (rc != 0) {
10199 		pr_err("error %d\n", rc);
10200 		goto rw_error;
10201 	}
10202 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_AGN_UNLOCK_TTH__A, (u16)(-8), 0);
10203 	if (rc != 0) {
10204 		pr_err("error %d\n", rc);
10205 		goto rw_error;
10206 	}
10207 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_AGN_LOCK_MASK__A, 1, 0);
10208 	if (rc != 0) {
10209 		pr_err("error %d\n", rc);
10210 		goto rw_error;
10211 	}
10212 
10213 	/* DGN_LOCK = {10, -2048, 8, -8, 0, 1<<1}; */
10214 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_DGN_LOCK_TH__A, 10, 0);
10215 	if (rc != 0) {
10216 		pr_err("error %d\n", rc);
10217 		goto rw_error;
10218 	}
10219 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_DGN_LOCK_TOTH__A, (u16)(-2048), 0);
10220 	if (rc != 0) {
10221 		pr_err("error %d\n", rc);
10222 		goto rw_error;
10223 	}
10224 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_DGN_ONLOCK_TTH__A, 8, 0);
10225 	if (rc != 0) {
10226 		pr_err("error %d\n", rc);
10227 		goto rw_error;
10228 	}
10229 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_DGN_UNLOCK_TTH__A, (u16)(-8), 0);
10230 	if (rc != 0) {
10231 		pr_err("error %d\n", rc);
10232 		goto rw_error;
10233 	}
10234 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_DGN_LOCK_MASK__A, 1 << 1, 0);
10235 	if (rc != 0) {
10236 		pr_err("error %d\n", rc);
10237 		goto rw_error;
10238 	}
10239 
10240 	/* FRQ_LOCK = {15,-2048, 8, -8, 0, 1<<2}; */
10241 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_FRQ_LOCK_TH__A, 17, 0);
10242 	if (rc != 0) {
10243 		pr_err("error %d\n", rc);
10244 		goto rw_error;
10245 	}
10246 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_FRQ_LOCK_TOTH__A, (u16)(-2048), 0);
10247 	if (rc != 0) {
10248 		pr_err("error %d\n", rc);
10249 		goto rw_error;
10250 	}
10251 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_FRQ_ONLOCK_TTH__A, 8, 0);
10252 	if (rc != 0) {
10253 		pr_err("error %d\n", rc);
10254 		goto rw_error;
10255 	}
10256 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_FRQ_UNLOCK_TTH__A, (u16)(-8), 0);
10257 	if (rc != 0) {
10258 		pr_err("error %d\n", rc);
10259 		goto rw_error;
10260 	}
10261 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_FRQ_LOCK_MASK__A, 1 << 2, 0);
10262 	if (rc != 0) {
10263 		pr_err("error %d\n", rc);
10264 		goto rw_error;
10265 	}
10266 
10267 	/* PHA_LOCK = {5000, -2048, 8, -8, 0, 1<<3}; */
10268 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_PHA_LOCK_TH__A, 3000, 0);
10269 	if (rc != 0) {
10270 		pr_err("error %d\n", rc);
10271 		goto rw_error;
10272 	}
10273 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_PHA_LOCK_TOTH__A, (u16)(-2048), 0);
10274 	if (rc != 0) {
10275 		pr_err("error %d\n", rc);
10276 		goto rw_error;
10277 	}
10278 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_PHA_ONLOCK_TTH__A, 8, 0);
10279 	if (rc != 0) {
10280 		pr_err("error %d\n", rc);
10281 		goto rw_error;
10282 	}
10283 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_PHA_UNLOCK_TTH__A, (u16)(-8), 0);
10284 	if (rc != 0) {
10285 		pr_err("error %d\n", rc);
10286 		goto rw_error;
10287 	}
10288 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_PHA_LOCK_MASK__A, 1 << 3, 0);
10289 	if (rc != 0) {
10290 		pr_err("error %d\n", rc);
10291 		goto rw_error;
10292 	}
10293 
10294 	/* TIM_LOCK = {300,      -2048, 8, -8, 0, 1<<4}; */
10295 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_TIM_LOCK_TH__A, 400, 0);
10296 	if (rc != 0) {
10297 		pr_err("error %d\n", rc);
10298 		goto rw_error;
10299 	}
10300 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_TIM_LOCK_TOTH__A, (u16)(-2048), 0);
10301 	if (rc != 0) {
10302 		pr_err("error %d\n", rc);
10303 		goto rw_error;
10304 	}
10305 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_TIM_ONLOCK_TTH__A, 8, 0);
10306 	if (rc != 0) {
10307 		pr_err("error %d\n", rc);
10308 		goto rw_error;
10309 	}
10310 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_TIM_UNLOCK_TTH__A, (u16)(-8), 0);
10311 	if (rc != 0) {
10312 		pr_err("error %d\n", rc);
10313 		goto rw_error;
10314 	}
10315 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_TIM_LOCK_MASK__A, 1 << 4, 0);
10316 	if (rc != 0) {
10317 		pr_err("error %d\n", rc);
10318 		goto rw_error;
10319 	}
10320 
10321 	/* EQU_LOCK = {20,      -2048, 8, -8, 0, 1<<5}; */
10322 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_EQU_LOCK_TH__A, 20, 0);
10323 	if (rc != 0) {
10324 		pr_err("error %d\n", rc);
10325 		goto rw_error;
10326 	}
10327 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_EQU_LOCK_TOTH__A, (u16)(-2048), 0);
10328 	if (rc != 0) {
10329 		pr_err("error %d\n", rc);
10330 		goto rw_error;
10331 	}
10332 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_EQU_ONLOCK_TTH__A, 4, 0);
10333 	if (rc != 0) {
10334 		pr_err("error %d\n", rc);
10335 		goto rw_error;
10336 	}
10337 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_EQU_UNLOCK_TTH__A, (u16)(-4), 0);
10338 	if (rc != 0) {
10339 		pr_err("error %d\n", rc);
10340 		goto rw_error;
10341 	}
10342 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_EQU_LOCK_MASK__A, 1 << 5, 0);
10343 	if (rc != 0) {
10344 		pr_err("error %d\n", rc);
10345 		goto rw_error;
10346 	}
10347 
10348 	/* PRE-Filter coefficients (PFI) */
10349 	rc = drxdap_fasi_write_block(dev_addr, ORX_FWP_PFI_A_W__A, sizeof(pfi_coeffs[mode_index]), ((u8 *)pfi_coeffs[mode_index]), 0);
10350 	if (rc != 0) {
10351 		pr_err("error %d\n", rc);
10352 		goto rw_error;
10353 	}
10354 	rc = drxj_dap_write_reg16(dev_addr, ORX_TOP_MDE_W__A, mode_index, 0);
10355 	if (rc != 0) {
10356 		pr_err("error %d\n", rc);
10357 		goto rw_error;
10358 	}
10359 
10360 	/* NYQUIST-Filter coefficients (NYQ) */
10361 	for (i = 0; i < (NYQFILTERLEN + 1) / 2; i++) {
10362 		rc = drxj_dap_write_reg16(dev_addr, ORX_FWP_NYQ_ADR_W__A, i, 0);
10363 		if (rc != 0) {
10364 			pr_err("error %d\n", rc);
10365 			goto rw_error;
10366 		}
10367 		rc = drxj_dap_write_reg16(dev_addr, ORX_FWP_NYQ_COF_RW__A, nyquist_coeffs[mode_index][i], 0);
10368 		if (rc != 0) {
10369 			pr_err("error %d\n", rc);
10370 			goto rw_error;
10371 		}
10372 	}
10373 	rc = drxj_dap_write_reg16(dev_addr, ORX_FWP_NYQ_ADR_W__A, 31, 0);
10374 	if (rc != 0) {
10375 		pr_err("error %d\n", rc);
10376 		goto rw_error;
10377 	}
10378 	rc = drxj_dap_write_reg16(dev_addr, ORX_COMM_EXEC__A, ORX_COMM_EXEC_ACTIVE, 0);
10379 	if (rc != 0) {
10380 		pr_err("error %d\n", rc);
10381 		goto rw_error;
10382 	}
10383 	/********/
10384 	/* Start */
10385 	/********/
10386 	scu_cmd.command = SCU_RAM_COMMAND_STANDARD_OOB
10387 	    | SCU_RAM_COMMAND_CMD_DEMOD_START;
10388 	scu_cmd.parameter_len = 0;
10389 	scu_cmd.result_len = 1;
10390 	scu_cmd.result = cmd_result;
10391 	rc = scu_command(dev_addr, &scu_cmd);
10392 	if (rc != 0) {
10393 		pr_err("error %d\n", rc);
10394 		goto rw_error;
10395 	}
10396 
10397 	rc = set_orx_nsu_aox(demod, true);
10398 	if (rc != 0) {
10399 		pr_err("error %d\n", rc);
10400 		goto rw_error;
10401 	}
10402 	rc = drxj_dap_write_reg16(dev_addr, ORX_NSU_AOX_STHR_W__A, ext_attr->oob_pre_saw, 0);
10403 	if (rc != 0) {
10404 		pr_err("error %d\n", rc);
10405 		goto rw_error;
10406 	}
10407 
10408 	ext_attr->oob_power_on = true;
10409 
10410 	return 0;
10411 rw_error:
10412 	return rc;
10413 }
10414 
10415 /*============================================================================*/
10416 /*==                     END OOB DATAPATH FUNCTIONS                         ==*/
10417 /*============================================================================*/
10418 
10419 /*=============================================================================
10420   ===== MC command related functions ==========================================
10421   ===========================================================================*/
10422 
10423 /*=============================================================================
10424   ===== ctrl_set_channel() ==========================================================
10425   ===========================================================================*/
10426 /*
10427 * \fn int ctrl_set_channel()
10428 * \brief Select a new transmission channel.
10429 * \param demod instance of demod.
10430 * \param channel Pointer to channel data.
10431 * \return int.
10432 *
10433 * In case the tuner module is not used and in case of NTSC/FM the pogrammer
10434 * must tune the tuner to the centre frequency of the NTSC/FM channel.
10435 *
10436 */
10437 static int
10438 ctrl_set_channel(struct drx_demod_instance *demod, struct drx_channel *channel)
10439 {
10440 	int rc;
10441 	s32 tuner_freq_offset = 0;
10442 	struct drxj_data *ext_attr = NULL;
10443 	struct i2c_device_addr *dev_addr = NULL;
10444 	enum drx_standard standard = DRX_STANDARD_UNKNOWN;
10445 #ifndef DRXJ_VSB_ONLY
10446 	u32 min_symbol_rate = 0;
10447 	u32 max_symbol_rate = 0;
10448 	int bandwidth_temp = 0;
10449 	int bandwidth = 0;
10450 #endif
10451    /*== check arguments ======================================================*/
10452 	if ((demod == NULL) || (channel == NULL))
10453 		return -EINVAL;
10454 
10455 	dev_addr = demod->my_i2c_dev_addr;
10456 	ext_attr = (struct drxj_data *) demod->my_ext_attr;
10457 	standard = ext_attr->standard;
10458 
10459 	/* check valid standards */
10460 	switch (standard) {
10461 	case DRX_STANDARD_8VSB:
10462 #ifndef DRXJ_VSB_ONLY
10463 	case DRX_STANDARD_ITU_A:
10464 	case DRX_STANDARD_ITU_B:
10465 	case DRX_STANDARD_ITU_C:
10466 #endif /* DRXJ_VSB_ONLY */
10467 		break;
10468 	case DRX_STANDARD_UNKNOWN:
10469 	default:
10470 		return -EINVAL;
10471 	}
10472 
10473 	/* check bandwidth QAM annex B, NTSC and 8VSB */
10474 	if ((standard == DRX_STANDARD_ITU_B) ||
10475 	    (standard == DRX_STANDARD_8VSB) ||
10476 	    (standard == DRX_STANDARD_NTSC)) {
10477 		switch (channel->bandwidth) {
10478 		case DRX_BANDWIDTH_6MHZ:
10479 		case DRX_BANDWIDTH_UNKNOWN:	/* fall through */
10480 			channel->bandwidth = DRX_BANDWIDTH_6MHZ;
10481 			break;
10482 		case DRX_BANDWIDTH_8MHZ:	/* fall through */
10483 		case DRX_BANDWIDTH_7MHZ:	/* fall through */
10484 		default:
10485 			return -EINVAL;
10486 		}
10487 	}
10488 
10489 	/* For QAM annex A and annex C:
10490 	   -check symbolrate and constellation
10491 	   -derive bandwidth from symbolrate (input bandwidth is ignored)
10492 	 */
10493 #ifndef DRXJ_VSB_ONLY
10494 	if ((standard == DRX_STANDARD_ITU_A) ||
10495 	    (standard == DRX_STANDARD_ITU_C)) {
10496 		struct drxuio_cfg uio_cfg = { DRX_UIO1, DRX_UIO_MODE_FIRMWARE_SAW };
10497 		int bw_rolloff_factor = 0;
10498 
10499 		bw_rolloff_factor = (standard == DRX_STANDARD_ITU_A) ? 115 : 113;
10500 		min_symbol_rate = DRXJ_QAM_SYMBOLRATE_MIN;
10501 		max_symbol_rate = DRXJ_QAM_SYMBOLRATE_MAX;
10502 		/* config SMA_TX pin to SAW switch mode */
10503 		rc = ctrl_set_uio_cfg(demod, &uio_cfg);
10504 		if (rc != 0) {
10505 			pr_err("error %d\n", rc);
10506 			goto rw_error;
10507 		}
10508 
10509 		if (channel->symbolrate < min_symbol_rate ||
10510 		    channel->symbolrate > max_symbol_rate) {
10511 			return -EINVAL;
10512 		}
10513 
10514 		switch (channel->constellation) {
10515 		case DRX_CONSTELLATION_QAM16:	/* fall through */
10516 		case DRX_CONSTELLATION_QAM32:	/* fall through */
10517 		case DRX_CONSTELLATION_QAM64:	/* fall through */
10518 		case DRX_CONSTELLATION_QAM128:	/* fall through */
10519 		case DRX_CONSTELLATION_QAM256:
10520 			bandwidth_temp = channel->symbolrate * bw_rolloff_factor;
10521 			bandwidth = bandwidth_temp / 100;
10522 
10523 			if ((bandwidth_temp % 100) >= 50)
10524 				bandwidth++;
10525 
10526 			if (bandwidth <= 6100000) {
10527 				channel->bandwidth = DRX_BANDWIDTH_6MHZ;
10528 			} else if ((bandwidth > 6100000)
10529 				   && (bandwidth <= 7100000)) {
10530 				channel->bandwidth = DRX_BANDWIDTH_7MHZ;
10531 			} else if (bandwidth > 7100000) {
10532 				channel->bandwidth = DRX_BANDWIDTH_8MHZ;
10533 			}
10534 			break;
10535 		default:
10536 			return -EINVAL;
10537 		}
10538 	}
10539 
10540 	/* For QAM annex B:
10541 	   -check constellation
10542 	 */
10543 	if (standard == DRX_STANDARD_ITU_B) {
10544 		switch (channel->constellation) {
10545 		case DRX_CONSTELLATION_AUTO:
10546 		case DRX_CONSTELLATION_QAM256:
10547 		case DRX_CONSTELLATION_QAM64:
10548 			break;
10549 		default:
10550 			return -EINVAL;
10551 		}
10552 
10553 		switch (channel->interleavemode) {
10554 		case DRX_INTERLEAVEMODE_I128_J1:
10555 		case DRX_INTERLEAVEMODE_I128_J1_V2:
10556 		case DRX_INTERLEAVEMODE_I128_J2:
10557 		case DRX_INTERLEAVEMODE_I64_J2:
10558 		case DRX_INTERLEAVEMODE_I128_J3:
10559 		case DRX_INTERLEAVEMODE_I32_J4:
10560 		case DRX_INTERLEAVEMODE_I128_J4:
10561 		case DRX_INTERLEAVEMODE_I16_J8:
10562 		case DRX_INTERLEAVEMODE_I128_J5:
10563 		case DRX_INTERLEAVEMODE_I8_J16:
10564 		case DRX_INTERLEAVEMODE_I128_J6:
10565 		case DRX_INTERLEAVEMODE_I128_J7:
10566 		case DRX_INTERLEAVEMODE_I128_J8:
10567 		case DRX_INTERLEAVEMODE_I12_J17:
10568 		case DRX_INTERLEAVEMODE_I5_J4:
10569 		case DRX_INTERLEAVEMODE_B52_M240:
10570 		case DRX_INTERLEAVEMODE_B52_M720:
10571 		case DRX_INTERLEAVEMODE_UNKNOWN:
10572 		case DRX_INTERLEAVEMODE_AUTO:
10573 			break;
10574 		default:
10575 			return -EINVAL;
10576 		}
10577 	}
10578 
10579 	if ((ext_attr->uio_sma_tx_mode) == DRX_UIO_MODE_FIRMWARE_SAW) {
10580 		/* SAW SW, user UIO is used for switchable SAW */
10581 		struct drxuio_data uio1 = { DRX_UIO1, false };
10582 
10583 		switch (channel->bandwidth) {
10584 		case DRX_BANDWIDTH_8MHZ:
10585 			uio1.value = true;
10586 			break;
10587 		case DRX_BANDWIDTH_7MHZ:
10588 			uio1.value = false;
10589 			break;
10590 		case DRX_BANDWIDTH_6MHZ:
10591 			uio1.value = false;
10592 			break;
10593 		case DRX_BANDWIDTH_UNKNOWN:
10594 		default:
10595 			return -EINVAL;
10596 		}
10597 
10598 		rc = ctrl_uio_write(demod, &uio1);
10599 		if (rc != 0) {
10600 			pr_err("error %d\n", rc);
10601 			goto rw_error;
10602 		}
10603 	}
10604 #endif /* DRXJ_VSB_ONLY */
10605 	rc = drxj_dap_write_reg16(dev_addr, SCU_COMM_EXEC__A, SCU_COMM_EXEC_ACTIVE, 0);
10606 	if (rc != 0) {
10607 		pr_err("error %d\n", rc);
10608 		goto rw_error;
10609 	}
10610 
10611 	tuner_freq_offset = 0;
10612 
10613    /*== Setup demod for specific standard ====================================*/
10614 	switch (standard) {
10615 	case DRX_STANDARD_8VSB:
10616 		if (channel->mirror == DRX_MIRROR_AUTO)
10617 			ext_attr->mirror = DRX_MIRROR_NO;
10618 		else
10619 			ext_attr->mirror = channel->mirror;
10620 		rc = set_vsb(demod);
10621 		if (rc != 0) {
10622 			pr_err("error %d\n", rc);
10623 			goto rw_error;
10624 		}
10625 		rc = set_frequency(demod, channel, tuner_freq_offset);
10626 		if (rc != 0) {
10627 			pr_err("error %d\n", rc);
10628 			goto rw_error;
10629 		}
10630 		break;
10631 #ifndef DRXJ_VSB_ONLY
10632 	case DRX_STANDARD_ITU_A:	/* fallthrough */
10633 	case DRX_STANDARD_ITU_B:	/* fallthrough */
10634 	case DRX_STANDARD_ITU_C:
10635 		rc = set_qam_channel(demod, channel, tuner_freq_offset);
10636 		if (rc != 0) {
10637 			pr_err("error %d\n", rc);
10638 			goto rw_error;
10639 		}
10640 		break;
10641 #endif
10642 	case DRX_STANDARD_UNKNOWN:
10643 	default:
10644 		return -EIO;
10645 	}
10646 
10647 	/* flag the packet error counter reset */
10648 	ext_attr->reset_pkt_err_acc = true;
10649 
10650 	return 0;
10651 rw_error:
10652 	return rc;
10653 }
10654 
10655 /*=============================================================================
10656   ===== SigQuality() ==========================================================
10657   ===========================================================================*/
10658 
10659 /*
10660 * \fn int ctrl_sig_quality()
10661 * \brief Retrieve signal quality form device.
10662 * \param devmod Pointer to demodulator instance.
10663 * \param sig_quality Pointer to signal quality data.
10664 * \return int.
10665 * \retval 0 sig_quality contains valid data.
10666 * \retval -EINVAL sig_quality is NULL.
10667 * \retval -EIO Erroneous data, sig_quality contains invalid data.
10668 
10669 */
10670 static int
10671 ctrl_sig_quality(struct drx_demod_instance *demod,
10672 		 enum drx_lock_status lock_status)
10673 {
10674 	struct i2c_device_addr *dev_addr = demod->my_i2c_dev_addr;
10675 	struct drxj_data *ext_attr = demod->my_ext_attr;
10676 	struct drx39xxj_state *state = dev_addr->user_data;
10677 	struct dtv_frontend_properties *p = &state->frontend.dtv_property_cache;
10678 	enum drx_standard standard = ext_attr->standard;
10679 	int rc;
10680 	u32 ber, cnt, err, pkt;
10681 	u16 mer, strength = 0;
10682 
10683 	rc = get_sig_strength(demod, &strength);
10684 	if (rc < 0) {
10685 		pr_err("error getting signal strength %d\n", rc);
10686 		p->strength.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
10687 	} else {
10688 		p->strength.stat[0].scale = FE_SCALE_RELATIVE;
10689 		p->strength.stat[0].uvalue = 65535UL *  strength/ 100;
10690 	}
10691 
10692 	switch (standard) {
10693 	case DRX_STANDARD_8VSB:
10694 #ifdef DRXJ_SIGNAL_ACCUM_ERR
10695 		rc = get_acc_pkt_err(demod, &pkt);
10696 		if (rc != 0) {
10697 			pr_err("error %d\n", rc);
10698 			goto rw_error;
10699 		}
10700 #endif
10701 		if (lock_status != DRXJ_DEMOD_LOCK && lock_status != DRX_LOCKED) {
10702 			p->pre_bit_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
10703 			p->pre_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
10704 			p->post_bit_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
10705 			p->post_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
10706 			p->block_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
10707 			p->block_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
10708 			p->cnr.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
10709 		} else {
10710 			rc = get_vsb_post_rs_pck_err(dev_addr, &err, &pkt);
10711 			if (rc != 0) {
10712 				pr_err("error %d getting UCB\n", rc);
10713 				p->block_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
10714 			} else {
10715 				p->block_error.stat[0].scale = FE_SCALE_COUNTER;
10716 				p->block_error.stat[0].uvalue += err;
10717 				p->block_count.stat[0].scale = FE_SCALE_COUNTER;
10718 				p->block_count.stat[0].uvalue += pkt;
10719 			}
10720 
10721 			/* PostViterbi is compute in steps of 10^(-6) */
10722 			rc = get_vs_bpre_viterbi_ber(dev_addr, &ber, &cnt);
10723 			if (rc != 0) {
10724 				pr_err("error %d getting pre-ber\n", rc);
10725 				p->pre_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
10726 			} else {
10727 				p->pre_bit_error.stat[0].scale = FE_SCALE_COUNTER;
10728 				p->pre_bit_error.stat[0].uvalue += ber;
10729 				p->pre_bit_count.stat[0].scale = FE_SCALE_COUNTER;
10730 				p->pre_bit_count.stat[0].uvalue += cnt;
10731 			}
10732 
10733 			rc = get_vs_bpost_viterbi_ber(dev_addr, &ber, &cnt);
10734 			if (rc != 0) {
10735 				pr_err("error %d getting post-ber\n", rc);
10736 				p->post_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
10737 			} else {
10738 				p->post_bit_error.stat[0].scale = FE_SCALE_COUNTER;
10739 				p->post_bit_error.stat[0].uvalue += ber;
10740 				p->post_bit_count.stat[0].scale = FE_SCALE_COUNTER;
10741 				p->post_bit_count.stat[0].uvalue += cnt;
10742 			}
10743 			rc = get_vsbmer(dev_addr, &mer);
10744 			if (rc != 0) {
10745 				pr_err("error %d getting MER\n", rc);
10746 				p->cnr.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
10747 			} else {
10748 				p->cnr.stat[0].svalue = mer * 100;
10749 				p->cnr.stat[0].scale = FE_SCALE_DECIBEL;
10750 			}
10751 		}
10752 		break;
10753 #ifndef DRXJ_VSB_ONLY
10754 	case DRX_STANDARD_ITU_A:
10755 	case DRX_STANDARD_ITU_B:
10756 	case DRX_STANDARD_ITU_C:
10757 		rc = ctrl_get_qam_sig_quality(demod);
10758 		if (rc != 0) {
10759 			pr_err("error %d\n", rc);
10760 			goto rw_error;
10761 		}
10762 		break;
10763 #endif
10764 	default:
10765 		return -EIO;
10766 	}
10767 
10768 	return 0;
10769 rw_error:
10770 	return rc;
10771 }
10772 
10773 /*============================================================================*/
10774 
10775 /*
10776 * \fn int ctrl_lock_status()
10777 * \brief Retrieve lock status .
10778 * \param dev_addr Pointer to demodulator device address.
10779 * \param lock_stat Pointer to lock status structure.
10780 * \return int.
10781 *
10782 */
10783 static int
10784 ctrl_lock_status(struct drx_demod_instance *demod, enum drx_lock_status *lock_stat)
10785 {
10786 	enum drx_standard standard = DRX_STANDARD_UNKNOWN;
10787 	struct drxj_data *ext_attr = NULL;
10788 	struct i2c_device_addr *dev_addr = NULL;
10789 	struct drxjscu_cmd cmd_scu = { /* command      */ 0,
10790 		/* parameter_len */ 0,
10791 		/* result_len    */ 0,
10792 		/* *parameter   */ NULL,
10793 		/* *result      */ NULL
10794 	};
10795 	int rc;
10796 	u16 cmd_result[2] = { 0, 0 };
10797 	u16 demod_lock = SCU_RAM_PARAM_1_RES_DEMOD_GET_LOCK_DEMOD_LOCKED;
10798 
10799 	/* check arguments */
10800 	if ((demod == NULL) || (lock_stat == NULL))
10801 		return -EINVAL;
10802 
10803 	dev_addr = demod->my_i2c_dev_addr;
10804 	ext_attr = (struct drxj_data *) demod->my_ext_attr;
10805 	standard = ext_attr->standard;
10806 
10807 	*lock_stat = DRX_NOT_LOCKED;
10808 
10809 	/* define the SCU command code */
10810 	switch (standard) {
10811 	case DRX_STANDARD_8VSB:
10812 		cmd_scu.command = SCU_RAM_COMMAND_STANDARD_VSB |
10813 		    SCU_RAM_COMMAND_CMD_DEMOD_GET_LOCK;
10814 		demod_lock |= 0x6;
10815 		break;
10816 #ifndef DRXJ_VSB_ONLY
10817 	case DRX_STANDARD_ITU_A:
10818 	case DRX_STANDARD_ITU_B:
10819 	case DRX_STANDARD_ITU_C:
10820 		cmd_scu.command = SCU_RAM_COMMAND_STANDARD_QAM |
10821 		    SCU_RAM_COMMAND_CMD_DEMOD_GET_LOCK;
10822 		break;
10823 #endif
10824 	case DRX_STANDARD_UNKNOWN:	/* fallthrough */
10825 	default:
10826 		return -EIO;
10827 	}
10828 
10829 	/* define the SCU command parameters and execute the command */
10830 	cmd_scu.parameter_len = 0;
10831 	cmd_scu.result_len = 2;
10832 	cmd_scu.parameter = NULL;
10833 	cmd_scu.result = cmd_result;
10834 	rc = scu_command(dev_addr, &cmd_scu);
10835 	if (rc != 0) {
10836 		pr_err("error %d\n", rc);
10837 		goto rw_error;
10838 	}
10839 
10840 	/* set the lock status */
10841 	if (cmd_scu.result[1] < demod_lock) {
10842 		/* 0x0000 NOT LOCKED */
10843 		*lock_stat = DRX_NOT_LOCKED;
10844 	} else if (cmd_scu.result[1] < SCU_RAM_PARAM_1_RES_DEMOD_GET_LOCK_LOCKED) {
10845 		*lock_stat = DRXJ_DEMOD_LOCK;
10846 	} else if (cmd_scu.result[1] <
10847 		   SCU_RAM_PARAM_1_RES_DEMOD_GET_LOCK_NEVER_LOCK) {
10848 		/* 0x8000 DEMOD + FEC LOCKED (system lock) */
10849 		*lock_stat = DRX_LOCKED;
10850 	} else {
10851 		/* 0xC000 NEVER LOCKED */
10852 		/* (system will never be able to lock to the signal) */
10853 		*lock_stat = DRX_NEVER_LOCK;
10854 	}
10855 
10856 	return 0;
10857 rw_error:
10858 	return rc;
10859 }
10860 
10861 /*============================================================================*/
10862 
10863 /*
10864 * \fn int ctrl_set_standard()
10865 * \brief Set modulation standard to be used.
10866 * \param standard Modulation standard.
10867 * \return int.
10868 *
10869 * Setup stuff for the desired demodulation standard.
10870 * Disable and power down the previous selected demodulation standard
10871 *
10872 */
10873 static int
10874 ctrl_set_standard(struct drx_demod_instance *demod, enum drx_standard *standard)
10875 {
10876 	struct drxj_data *ext_attr = NULL;
10877 	int rc;
10878 	enum drx_standard prev_standard;
10879 
10880 	/* check arguments */
10881 	if ((standard == NULL) || (demod == NULL))
10882 		return -EINVAL;
10883 
10884 	ext_attr = (struct drxj_data *) demod->my_ext_attr;
10885 	prev_standard = ext_attr->standard;
10886 
10887 	/*
10888 	   Stop and power down previous standard
10889 	 */
10890 	switch (prev_standard) {
10891 #ifndef DRXJ_VSB_ONLY
10892 	case DRX_STANDARD_ITU_A:	/* fallthrough */
10893 	case DRX_STANDARD_ITU_B:	/* fallthrough */
10894 	case DRX_STANDARD_ITU_C:
10895 		rc = power_down_qam(demod, false);
10896 		if (rc != 0) {
10897 			pr_err("error %d\n", rc);
10898 			goto rw_error;
10899 		}
10900 		break;
10901 #endif
10902 	case DRX_STANDARD_8VSB:
10903 		rc = power_down_vsb(demod, false);
10904 		if (rc != 0) {
10905 			pr_err("error %d\n", rc);
10906 			goto rw_error;
10907 		}
10908 		break;
10909 	case DRX_STANDARD_UNKNOWN:
10910 		/* Do nothing */
10911 		break;
10912 	case DRX_STANDARD_AUTO:	/* fallthrough */
10913 	default:
10914 		return -EINVAL;
10915 	}
10916 
10917 	/*
10918 	   Initialize channel independent registers
10919 	   Power up new standard
10920 	 */
10921 	ext_attr->standard = *standard;
10922 
10923 	switch (*standard) {
10924 #ifndef DRXJ_VSB_ONLY
10925 	case DRX_STANDARD_ITU_A:	/* fallthrough */
10926 	case DRX_STANDARD_ITU_B:	/* fallthrough */
10927 	case DRX_STANDARD_ITU_C:
10928 		do {
10929 			u16 dummy;
10930 			rc = drxj_dap_read_reg16(demod->my_i2c_dev_addr, SCU_RAM_VERSION_HI__A, &dummy, 0);
10931 			if (rc != 0) {
10932 				pr_err("error %d\n", rc);
10933 				goto rw_error;
10934 			}
10935 		} while (0);
10936 		break;
10937 #endif
10938 	case DRX_STANDARD_8VSB:
10939 		rc = set_vsb_leak_n_gain(demod);
10940 		if (rc != 0) {
10941 			pr_err("error %d\n", rc);
10942 			goto rw_error;
10943 		}
10944 		break;
10945 	default:
10946 		ext_attr->standard = DRX_STANDARD_UNKNOWN;
10947 		return -EINVAL;
10948 		break;
10949 	}
10950 
10951 	return 0;
10952 rw_error:
10953 	/* Don't know what the standard is now ... try again */
10954 	ext_attr->standard = DRX_STANDARD_UNKNOWN;
10955 	return rc;
10956 }
10957 
10958 /*============================================================================*/
10959 
10960 static void drxj_reset_mode(struct drxj_data *ext_attr)
10961 {
10962 	/* Initialize default AFE configuration for QAM */
10963 	if (ext_attr->has_lna) {
10964 		/* IF AGC off, PGA active */
10965 #ifndef DRXJ_VSB_ONLY
10966 		ext_attr->qam_if_agc_cfg.standard = DRX_STANDARD_ITU_B;
10967 		ext_attr->qam_if_agc_cfg.ctrl_mode = DRX_AGC_CTRL_OFF;
10968 		ext_attr->qam_pga_cfg = 140 + (11 * 13);
10969 #endif
10970 		ext_attr->vsb_if_agc_cfg.standard = DRX_STANDARD_8VSB;
10971 		ext_attr->vsb_if_agc_cfg.ctrl_mode = DRX_AGC_CTRL_OFF;
10972 		ext_attr->vsb_pga_cfg = 140 + (11 * 13);
10973 	} else {
10974 		/* IF AGC on, PGA not active */
10975 #ifndef DRXJ_VSB_ONLY
10976 		ext_attr->qam_if_agc_cfg.standard = DRX_STANDARD_ITU_B;
10977 		ext_attr->qam_if_agc_cfg.ctrl_mode = DRX_AGC_CTRL_AUTO;
10978 		ext_attr->qam_if_agc_cfg.min_output_level = 0;
10979 		ext_attr->qam_if_agc_cfg.max_output_level = 0x7FFF;
10980 		ext_attr->qam_if_agc_cfg.speed = 3;
10981 		ext_attr->qam_if_agc_cfg.top = 1297;
10982 		ext_attr->qam_pga_cfg = 140;
10983 #endif
10984 		ext_attr->vsb_if_agc_cfg.standard = DRX_STANDARD_8VSB;
10985 		ext_attr->vsb_if_agc_cfg.ctrl_mode = DRX_AGC_CTRL_AUTO;
10986 		ext_attr->vsb_if_agc_cfg.min_output_level = 0;
10987 		ext_attr->vsb_if_agc_cfg.max_output_level = 0x7FFF;
10988 		ext_attr->vsb_if_agc_cfg.speed = 3;
10989 		ext_attr->vsb_if_agc_cfg.top = 1024;
10990 		ext_attr->vsb_pga_cfg = 140;
10991 	}
10992 	/* TODO: remove min_output_level and max_output_level for both QAM and VSB after */
10993 	/* mc has not used them */
10994 #ifndef DRXJ_VSB_ONLY
10995 	ext_attr->qam_rf_agc_cfg.standard = DRX_STANDARD_ITU_B;
10996 	ext_attr->qam_rf_agc_cfg.ctrl_mode = DRX_AGC_CTRL_AUTO;
10997 	ext_attr->qam_rf_agc_cfg.min_output_level = 0;
10998 	ext_attr->qam_rf_agc_cfg.max_output_level = 0x7FFF;
10999 	ext_attr->qam_rf_agc_cfg.speed = 3;
11000 	ext_attr->qam_rf_agc_cfg.top = 9500;
11001 	ext_attr->qam_rf_agc_cfg.cut_off_current = 4000;
11002 	ext_attr->qam_pre_saw_cfg.standard = DRX_STANDARD_ITU_B;
11003 	ext_attr->qam_pre_saw_cfg.reference = 0x07;
11004 	ext_attr->qam_pre_saw_cfg.use_pre_saw = true;
11005 #endif
11006 	/* Initialize default AFE configuration for VSB */
11007 	ext_attr->vsb_rf_agc_cfg.standard = DRX_STANDARD_8VSB;
11008 	ext_attr->vsb_rf_agc_cfg.ctrl_mode = DRX_AGC_CTRL_AUTO;
11009 	ext_attr->vsb_rf_agc_cfg.min_output_level = 0;
11010 	ext_attr->vsb_rf_agc_cfg.max_output_level = 0x7FFF;
11011 	ext_attr->vsb_rf_agc_cfg.speed = 3;
11012 	ext_attr->vsb_rf_agc_cfg.top = 9500;
11013 	ext_attr->vsb_rf_agc_cfg.cut_off_current = 4000;
11014 	ext_attr->vsb_pre_saw_cfg.standard = DRX_STANDARD_8VSB;
11015 	ext_attr->vsb_pre_saw_cfg.reference = 0x07;
11016 	ext_attr->vsb_pre_saw_cfg.use_pre_saw = true;
11017 }
11018 
11019 /*
11020 * \fn int ctrl_power_mode()
11021 * \brief Set the power mode of the device to the specified power mode
11022 * \param demod Pointer to demodulator instance.
11023 * \param mode  Pointer to new power mode.
11024 * \return int.
11025 * \retval 0          Success
11026 * \retval -EIO       I2C error or other failure
11027 * \retval -EINVAL Invalid mode argument.
11028 *
11029 *
11030 */
11031 static int
11032 ctrl_power_mode(struct drx_demod_instance *demod, enum drx_power_mode *mode)
11033 {
11034 	struct drx_common_attr *common_attr = (struct drx_common_attr *) NULL;
11035 	struct drxj_data *ext_attr = (struct drxj_data *) NULL;
11036 	struct i2c_device_addr *dev_addr = (struct i2c_device_addr *)NULL;
11037 	int rc;
11038 	u16 sio_cc_pwd_mode = 0;
11039 
11040 	common_attr = (struct drx_common_attr *) demod->my_common_attr;
11041 	ext_attr = (struct drxj_data *) demod->my_ext_attr;
11042 	dev_addr = demod->my_i2c_dev_addr;
11043 
11044 	/* Check arguments */
11045 	if (mode == NULL)
11046 		return -EINVAL;
11047 
11048 	/* If already in requested power mode, do nothing */
11049 	if (common_attr->current_power_mode == *mode)
11050 		return 0;
11051 
11052 	switch (*mode) {
11053 	case DRX_POWER_UP:
11054 	case DRXJ_POWER_DOWN_MAIN_PATH:
11055 		sio_cc_pwd_mode = SIO_CC_PWD_MODE_LEVEL_NONE;
11056 		break;
11057 	case DRXJ_POWER_DOWN_CORE:
11058 		sio_cc_pwd_mode = SIO_CC_PWD_MODE_LEVEL_CLOCK;
11059 		break;
11060 	case DRXJ_POWER_DOWN_PLL:
11061 		sio_cc_pwd_mode = SIO_CC_PWD_MODE_LEVEL_PLL;
11062 		break;
11063 	case DRX_POWER_DOWN:
11064 		sio_cc_pwd_mode = SIO_CC_PWD_MODE_LEVEL_OSC;
11065 		break;
11066 	default:
11067 		/* Unknow sleep mode */
11068 		return -EINVAL;
11069 		break;
11070 	}
11071 
11072 	/* Check if device needs to be powered up */
11073 	if ((common_attr->current_power_mode != DRX_POWER_UP)) {
11074 		rc = power_up_device(demod);
11075 		if (rc != 0) {
11076 			pr_err("error %d\n", rc);
11077 			goto rw_error;
11078 		}
11079 	}
11080 
11081 	if (*mode == DRX_POWER_UP) {
11082 		/* Restore analog & pin configuration */
11083 
11084 		/* Initialize default AFE configuration for VSB */
11085 		drxj_reset_mode(ext_attr);
11086 	} else {
11087 		/* Power down to requested mode */
11088 		/* Backup some register settings */
11089 		/* Set pins with possible pull-ups connected to them in input mode */
11090 		/* Analog power down */
11091 		/* ADC power down */
11092 		/* Power down device */
11093 		/* stop all comm_exec */
11094 		/*
11095 		   Stop and power down previous standard
11096 		 */
11097 
11098 		switch (ext_attr->standard) {
11099 		case DRX_STANDARD_ITU_A:
11100 		case DRX_STANDARD_ITU_B:
11101 		case DRX_STANDARD_ITU_C:
11102 			rc = power_down_qam(demod, true);
11103 			if (rc != 0) {
11104 				pr_err("error %d\n", rc);
11105 				goto rw_error;
11106 			}
11107 			break;
11108 		case DRX_STANDARD_8VSB:
11109 			rc = power_down_vsb(demod, true);
11110 			if (rc != 0) {
11111 				pr_err("error %d\n", rc);
11112 				goto rw_error;
11113 			}
11114 			break;
11115 		case DRX_STANDARD_PAL_SECAM_BG:	/* fallthrough */
11116 		case DRX_STANDARD_PAL_SECAM_DK:	/* fallthrough */
11117 		case DRX_STANDARD_PAL_SECAM_I:	/* fallthrough */
11118 		case DRX_STANDARD_PAL_SECAM_L:	/* fallthrough */
11119 		case DRX_STANDARD_PAL_SECAM_LP:	/* fallthrough */
11120 		case DRX_STANDARD_NTSC:	/* fallthrough */
11121 		case DRX_STANDARD_FM:
11122 			rc = power_down_atv(demod, ext_attr->standard, true);
11123 			if (rc != 0) {
11124 				pr_err("error %d\n", rc);
11125 				goto rw_error;
11126 			}
11127 			break;
11128 		case DRX_STANDARD_UNKNOWN:
11129 			/* Do nothing */
11130 			break;
11131 		case DRX_STANDARD_AUTO:	/* fallthrough */
11132 		default:
11133 			return -EIO;
11134 		}
11135 		ext_attr->standard = DRX_STANDARD_UNKNOWN;
11136 	}
11137 
11138 	if (*mode != DRXJ_POWER_DOWN_MAIN_PATH) {
11139 		rc = drxj_dap_write_reg16(dev_addr, SIO_CC_PWD_MODE__A, sio_cc_pwd_mode, 0);
11140 		if (rc != 0) {
11141 			pr_err("error %d\n", rc);
11142 			goto rw_error;
11143 		}
11144 		rc = drxj_dap_write_reg16(dev_addr, SIO_CC_UPDATE__A, SIO_CC_UPDATE_KEY, 0);
11145 		if (rc != 0) {
11146 			pr_err("error %d\n", rc);
11147 			goto rw_error;
11148 		}
11149 
11150 		if ((*mode != DRX_POWER_UP)) {
11151 			/* Initialize HI, wakeup key especially before put IC to sleep */
11152 			rc = init_hi(demod);
11153 			if (rc != 0) {
11154 				pr_err("error %d\n", rc);
11155 				goto rw_error;
11156 			}
11157 
11158 			ext_attr->hi_cfg_ctrl |= SIO_HI_RA_RAM_PAR_5_CFG_SLEEP_ZZZ;
11159 			rc = hi_cfg_command(demod);
11160 			if (rc != 0) {
11161 				pr_err("error %d\n", rc);
11162 				goto rw_error;
11163 			}
11164 		}
11165 	}
11166 
11167 	common_attr->current_power_mode = *mode;
11168 
11169 	return 0;
11170 rw_error:
11171 	return rc;
11172 }
11173 
11174 /*============================================================================*/
11175 /*== CTRL Set/Get Config related functions ===================================*/
11176 /*============================================================================*/
11177 
11178 /*
11179 * \fn int ctrl_set_cfg_pre_saw()
11180 * \brief Set Pre-saw reference.
11181 * \param demod demod instance
11182 * \param u16 *
11183 * \return int.
11184 *
11185 * Check arguments
11186 * Dispatch handling to standard specific function.
11187 *
11188 */
11189 static int
11190 ctrl_set_cfg_pre_saw(struct drx_demod_instance *demod, struct drxj_cfg_pre_saw *pre_saw)
11191 {
11192 	struct i2c_device_addr *dev_addr = NULL;
11193 	struct drxj_data *ext_attr = NULL;
11194 	int rc;
11195 
11196 	dev_addr = demod->my_i2c_dev_addr;
11197 	ext_attr = (struct drxj_data *) demod->my_ext_attr;
11198 
11199 	/* check arguments */
11200 	if ((pre_saw == NULL) || (pre_saw->reference > IQM_AF_PDREF__M)
11201 	    ) {
11202 		return -EINVAL;
11203 	}
11204 
11205 	/* Only if standard is currently active */
11206 	if ((ext_attr->standard == pre_saw->standard) ||
11207 	    (DRXJ_ISQAMSTD(ext_attr->standard) &&
11208 	     DRXJ_ISQAMSTD(pre_saw->standard)) ||
11209 	    (DRXJ_ISATVSTD(ext_attr->standard) &&
11210 	     DRXJ_ISATVSTD(pre_saw->standard))) {
11211 		rc = drxj_dap_write_reg16(dev_addr, IQM_AF_PDREF__A, pre_saw->reference, 0);
11212 		if (rc != 0) {
11213 			pr_err("error %d\n", rc);
11214 			goto rw_error;
11215 		}
11216 	}
11217 
11218 	/* Store pre-saw settings */
11219 	switch (pre_saw->standard) {
11220 	case DRX_STANDARD_8VSB:
11221 		ext_attr->vsb_pre_saw_cfg = *pre_saw;
11222 		break;
11223 #ifndef DRXJ_VSB_ONLY
11224 	case DRX_STANDARD_ITU_A:	/* fallthrough */
11225 	case DRX_STANDARD_ITU_B:	/* fallthrough */
11226 	case DRX_STANDARD_ITU_C:
11227 		ext_attr->qam_pre_saw_cfg = *pre_saw;
11228 		break;
11229 #endif
11230 	default:
11231 		return -EINVAL;
11232 	}
11233 
11234 	return 0;
11235 rw_error:
11236 	return rc;
11237 }
11238 
11239 /*============================================================================*/
11240 
11241 /*
11242 * \fn int ctrl_set_cfg_afe_gain()
11243 * \brief Set AFE Gain.
11244 * \param demod demod instance
11245 * \param u16 *
11246 * \return int.
11247 *
11248 * Check arguments
11249 * Dispatch handling to standard specific function.
11250 *
11251 */
11252 static int
11253 ctrl_set_cfg_afe_gain(struct drx_demod_instance *demod, struct drxj_cfg_afe_gain *afe_gain)
11254 {
11255 	struct i2c_device_addr *dev_addr = NULL;
11256 	struct drxj_data *ext_attr = NULL;
11257 	int rc;
11258 	u8 gain = 0;
11259 
11260 	/* check arguments */
11261 	if (afe_gain == NULL)
11262 		return -EINVAL;
11263 
11264 	dev_addr = demod->my_i2c_dev_addr;
11265 	ext_attr = (struct drxj_data *) demod->my_ext_attr;
11266 
11267 	switch (afe_gain->standard) {
11268 	case DRX_STANDARD_8VSB:	/* fallthrough */
11269 #ifndef DRXJ_VSB_ONLY
11270 	case DRX_STANDARD_ITU_A:	/* fallthrough */
11271 	case DRX_STANDARD_ITU_B:	/* fallthrough */
11272 	case DRX_STANDARD_ITU_C:
11273 #endif
11274 		/* Do nothing */
11275 		break;
11276 	default:
11277 		return -EINVAL;
11278 	}
11279 
11280 	/* TODO PGA gain is also written by microcode (at least by QAM and VSB)
11281 	   So I (PJ) think interface requires choice between auto, user mode */
11282 
11283 	if (afe_gain->gain >= 329)
11284 		gain = 15;
11285 	else if (afe_gain->gain <= 147)
11286 		gain = 0;
11287 	else
11288 		gain = (afe_gain->gain - 140 + 6) / 13;
11289 
11290 	/* Only if standard is currently active */
11291 	if (ext_attr->standard == afe_gain->standard) {
11292 			rc = drxj_dap_write_reg16(dev_addr, IQM_AF_PGA_GAIN__A, gain, 0);
11293 			if (rc != 0) {
11294 				pr_err("error %d\n", rc);
11295 				goto rw_error;
11296 			}
11297 		}
11298 
11299 	/* Store AFE Gain settings */
11300 	switch (afe_gain->standard) {
11301 	case DRX_STANDARD_8VSB:
11302 		ext_attr->vsb_pga_cfg = gain * 13 + 140;
11303 		break;
11304 #ifndef DRXJ_VSB_ONLY
11305 	case DRX_STANDARD_ITU_A:	/* fallthrough */
11306 	case DRX_STANDARD_ITU_B:	/* fallthrough */
11307 	case DRX_STANDARD_ITU_C:
11308 		ext_attr->qam_pga_cfg = gain * 13 + 140;
11309 		break;
11310 #endif
11311 	default:
11312 		return -EIO;
11313 	}
11314 
11315 	return 0;
11316 rw_error:
11317 	return rc;
11318 }
11319 
11320 /*============================================================================*/
11321 
11322 
11323 /*=============================================================================
11324 ===== EXPORTED FUNCTIONS ====================================================*/
11325 
11326 static int drx_ctrl_u_code(struct drx_demod_instance *demod,
11327 		       struct drxu_code_info *mc_info,
11328 		       enum drxu_code_action action);
11329 static int drxj_set_lna_state(struct drx_demod_instance *demod, bool state);
11330 
11331 /*
11332 * \fn drxj_open()
11333 * \brief Open the demod instance, configure device, configure drxdriver
11334 * \return Status_t Return status.
11335 *
11336 * drxj_open() can be called with a NULL ucode image => no ucode upload.
11337 * This means that drxj_open() must NOT contain SCU commands or, in general,
11338 * rely on SCU or AUD ucode to be present.
11339 *
11340 */
11341 
11342 static int drxj_open(struct drx_demod_instance *demod)
11343 {
11344 	struct i2c_device_addr *dev_addr = NULL;
11345 	struct drxj_data *ext_attr = NULL;
11346 	struct drx_common_attr *common_attr = NULL;
11347 	u32 driver_version = 0;
11348 	struct drxu_code_info ucode_info;
11349 	struct drx_cfg_mpeg_output cfg_mpeg_output;
11350 	int rc;
11351 	enum drx_power_mode power_mode = DRX_POWER_UP;
11352 
11353 	if ((demod == NULL) ||
11354 	    (demod->my_common_attr == NULL) ||
11355 	    (demod->my_ext_attr == NULL) ||
11356 	    (demod->my_i2c_dev_addr == NULL) ||
11357 	    (demod->my_common_attr->is_opened)) {
11358 		return -EINVAL;
11359 	}
11360 
11361 	/* Check arguments */
11362 	if (demod->my_ext_attr == NULL)
11363 		return -EINVAL;
11364 
11365 	dev_addr = demod->my_i2c_dev_addr;
11366 	ext_attr = (struct drxj_data *) demod->my_ext_attr;
11367 	common_attr = (struct drx_common_attr *) demod->my_common_attr;
11368 
11369 	rc = ctrl_power_mode(demod, &power_mode);
11370 	if (rc != 0) {
11371 		pr_err("error %d\n", rc);
11372 		goto rw_error;
11373 	}
11374 	if (power_mode != DRX_POWER_UP) {
11375 		rc = -EINVAL;
11376 		pr_err("failed to powerup device\n");
11377 		goto rw_error;
11378 	}
11379 
11380 	/* has to be in front of setIqmAf and setOrxNsuAox */
11381 	rc = get_device_capabilities(demod);
11382 	if (rc != 0) {
11383 		pr_err("error %d\n", rc);
11384 		goto rw_error;
11385 	}
11386 
11387 	/*
11388 	 * Soft reset of sys- and osc-clockdomain
11389 	 *
11390 	 * HACK: On windows, it writes a 0x07 here, instead of just 0x03.
11391 	 * As we didn't load the firmware here yet, we should do the same.
11392 	 * Btw, this is coherent with DRX-K, where we send reset codes
11393 	 * for modulation (OFTM, in DRX-k), SYS and OSC clock domains.
11394 	 */
11395 	rc = drxj_dap_write_reg16(dev_addr, SIO_CC_SOFT_RST__A, (0x04 | SIO_CC_SOFT_RST_SYS__M | SIO_CC_SOFT_RST_OSC__M), 0);
11396 	if (rc != 0) {
11397 		pr_err("error %d\n", rc);
11398 		goto rw_error;
11399 	}
11400 	rc = drxj_dap_write_reg16(dev_addr, SIO_CC_UPDATE__A, SIO_CC_UPDATE_KEY, 0);
11401 	if (rc != 0) {
11402 		pr_err("error %d\n", rc);
11403 		goto rw_error;
11404 	}
11405 	msleep(1);
11406 
11407 	/* TODO first make sure that everything keeps working before enabling this */
11408 	/* PowerDownAnalogBlocks() */
11409 	rc = drxj_dap_write_reg16(dev_addr, ATV_TOP_STDBY__A, (~ATV_TOP_STDBY_CVBS_STDBY_A2_ACTIVE) | ATV_TOP_STDBY_SIF_STDBY_STANDBY, 0);
11410 	if (rc != 0) {
11411 		pr_err("error %d\n", rc);
11412 		goto rw_error;
11413 	}
11414 
11415 	rc = set_iqm_af(demod, false);
11416 	if (rc != 0) {
11417 		pr_err("error %d\n", rc);
11418 		goto rw_error;
11419 	}
11420 	rc = set_orx_nsu_aox(demod, false);
11421 	if (rc != 0) {
11422 		pr_err("error %d\n", rc);
11423 		goto rw_error;
11424 	}
11425 
11426 	rc = init_hi(demod);
11427 	if (rc != 0) {
11428 		pr_err("error %d\n", rc);
11429 		goto rw_error;
11430 	}
11431 
11432 	/* disable mpegoutput pins */
11433 	memcpy(&cfg_mpeg_output, &common_attr->mpeg_cfg, sizeof(cfg_mpeg_output));
11434 	cfg_mpeg_output.enable_mpeg_output = false;
11435 
11436 	rc = ctrl_set_cfg_mpeg_output(demod, &cfg_mpeg_output);
11437 	if (rc != 0) {
11438 		pr_err("error %d\n", rc);
11439 		goto rw_error;
11440 	}
11441 	/* Stop AUD Inform SetAudio it will need to do all setting */
11442 	rc = power_down_aud(demod);
11443 	if (rc != 0) {
11444 		pr_err("error %d\n", rc);
11445 		goto rw_error;
11446 	}
11447 	/* Stop SCU */
11448 	rc = drxj_dap_write_reg16(dev_addr, SCU_COMM_EXEC__A, SCU_COMM_EXEC_STOP, 0);
11449 	if (rc != 0) {
11450 		pr_err("error %d\n", rc);
11451 		goto rw_error;
11452 	}
11453 
11454 	/* Upload microcode */
11455 	if (common_attr->microcode_file != NULL) {
11456 		/* Dirty trick to use common ucode upload & verify,
11457 		   pretend device is already open */
11458 		common_attr->is_opened = true;
11459 		ucode_info.mc_file = common_attr->microcode_file;
11460 
11461 		if (DRX_ISPOWERDOWNMODE(demod->my_common_attr->current_power_mode)) {
11462 			pr_err("Should powerup before loading the firmware.");
11463 			return -EINVAL;
11464 		}
11465 
11466 		rc = drx_ctrl_u_code(demod, &ucode_info, UCODE_UPLOAD);
11467 		if (rc != 0) {
11468 			pr_err("error %d while uploading the firmware\n", rc);
11469 			goto rw_error;
11470 		}
11471 		if (common_attr->verify_microcode == true) {
11472 			rc = drx_ctrl_u_code(demod, &ucode_info, UCODE_VERIFY);
11473 			if (rc != 0) {
11474 				pr_err("error %d while verifying the firmware\n",
11475 				       rc);
11476 				goto rw_error;
11477 			}
11478 		}
11479 		common_attr->is_opened = false;
11480 	}
11481 
11482 	/* Run SCU for a little while to initialize microcode version numbers */
11483 	rc = drxj_dap_write_reg16(dev_addr, SCU_COMM_EXEC__A, SCU_COMM_EXEC_ACTIVE, 0);
11484 	if (rc != 0) {
11485 		pr_err("error %d\n", rc);
11486 		goto rw_error;
11487 	}
11488 
11489 	/* Initialize scan timeout */
11490 	common_attr->scan_demod_lock_timeout = DRXJ_SCAN_TIMEOUT;
11491 	common_attr->scan_desired_lock = DRX_LOCKED;
11492 
11493 	drxj_reset_mode(ext_attr);
11494 	ext_attr->standard = DRX_STANDARD_UNKNOWN;
11495 
11496 	rc = smart_ant_init(demod);
11497 	if (rc != 0) {
11498 		pr_err("error %d\n", rc);
11499 		goto rw_error;
11500 	}
11501 
11502 	/* Stamp driver version number in SCU data RAM in BCD code
11503 	   Done to enable field application engineers to retrieve drxdriver version
11504 	   via I2C from SCU RAM
11505 	 */
11506 	driver_version = (VERSION_MAJOR / 100) % 10;
11507 	driver_version <<= 4;
11508 	driver_version += (VERSION_MAJOR / 10) % 10;
11509 	driver_version <<= 4;
11510 	driver_version += (VERSION_MAJOR % 10);
11511 	driver_version <<= 4;
11512 	driver_version += (VERSION_MINOR % 10);
11513 	driver_version <<= 4;
11514 	driver_version += (VERSION_PATCH / 1000) % 10;
11515 	driver_version <<= 4;
11516 	driver_version += (VERSION_PATCH / 100) % 10;
11517 	driver_version <<= 4;
11518 	driver_version += (VERSION_PATCH / 10) % 10;
11519 	driver_version <<= 4;
11520 	driver_version += (VERSION_PATCH % 10);
11521 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_DRIVER_VER_HI__A, (u16)(driver_version >> 16), 0);
11522 	if (rc != 0) {
11523 		pr_err("error %d\n", rc);
11524 		goto rw_error;
11525 	}
11526 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_DRIVER_VER_LO__A, (u16)(driver_version & 0xFFFF), 0);
11527 	if (rc != 0) {
11528 		pr_err("error %d\n", rc);
11529 		goto rw_error;
11530 	}
11531 
11532 	rc = ctrl_set_oob(demod, NULL);
11533 	if (rc != 0) {
11534 		pr_err("error %d\n", rc);
11535 		goto rw_error;
11536 	}
11537 
11538 	/* refresh the audio data structure with default */
11539 	ext_attr->aud_data = drxj_default_aud_data_g;
11540 
11541 	demod->my_common_attr->is_opened = true;
11542 	drxj_set_lna_state(demod, false);
11543 	return 0;
11544 rw_error:
11545 	common_attr->is_opened = false;
11546 	return rc;
11547 }
11548 
11549 /*============================================================================*/
11550 /*
11551 * \fn drxj_close()
11552 * \brief Close the demod instance, power down the device
11553 * \return Status_t Return status.
11554 *
11555 */
11556 static int drxj_close(struct drx_demod_instance *demod)
11557 {
11558 	struct i2c_device_addr *dev_addr = demod->my_i2c_dev_addr;
11559 	int rc;
11560 	enum drx_power_mode power_mode = DRX_POWER_UP;
11561 
11562 	if ((demod->my_common_attr == NULL) ||
11563 	    (demod->my_ext_attr == NULL) ||
11564 	    (demod->my_i2c_dev_addr == NULL) ||
11565 	    (!demod->my_common_attr->is_opened)) {
11566 		return -EINVAL;
11567 	}
11568 
11569 	/* power up */
11570 	rc = ctrl_power_mode(demod, &power_mode);
11571 	if (rc != 0) {
11572 		pr_err("error %d\n", rc);
11573 		goto rw_error;
11574 	}
11575 
11576 	rc = drxj_dap_write_reg16(dev_addr, SCU_COMM_EXEC__A, SCU_COMM_EXEC_ACTIVE, 0);
11577 	if (rc != 0) {
11578 		pr_err("error %d\n", rc);
11579 		goto rw_error;
11580 	}
11581 	power_mode = DRX_POWER_DOWN;
11582 	rc = ctrl_power_mode(demod, &power_mode);
11583 	if (rc != 0) {
11584 		pr_err("error %d\n", rc);
11585 		goto rw_error;
11586 	}
11587 
11588 	DRX_ATTR_ISOPENED(demod) = false;
11589 
11590 	return 0;
11591 rw_error:
11592 	DRX_ATTR_ISOPENED(demod) = false;
11593 
11594 	return rc;
11595 }
11596 
11597 /*
11598  * Microcode related functions
11599  */
11600 
11601 /*
11602  * drx_u_code_compute_crc	- Compute CRC of block of microcode data.
11603  * @block_data: Pointer to microcode data.
11604  * @nr_words:   Size of microcode block (number of 16 bits words).
11605  *
11606  * returns The computed CRC residue.
11607  */
11608 static u16 drx_u_code_compute_crc(u8 *block_data, u16 nr_words)
11609 {
11610 	u16 i = 0;
11611 	u16 j = 0;
11612 	u32 crc_word = 0;
11613 	u32 carry = 0;
11614 
11615 	while (i < nr_words) {
11616 		crc_word |= (u32)be16_to_cpu(*(__be16 *)(block_data));
11617 		for (j = 0; j < 16; j++) {
11618 			crc_word <<= 1;
11619 			if (carry != 0)
11620 				crc_word ^= 0x80050000UL;
11621 			carry = crc_word & 0x80000000UL;
11622 		}
11623 		i++;
11624 		block_data += (sizeof(u16));
11625 	}
11626 	return (u16)(crc_word >> 16);
11627 }
11628 
11629 /*
11630  * drx_check_firmware - checks if the loaded firmware is valid
11631  *
11632  * @demod:	demod structure
11633  * @mc_data:	pointer to the start of the firmware
11634  * @size:	firmware size
11635  */
11636 static int drx_check_firmware(struct drx_demod_instance *demod, u8 *mc_data,
11637 			  unsigned size)
11638 {
11639 	struct drxu_code_block_hdr block_hdr;
11640 	int i;
11641 	unsigned count = 2 * sizeof(u16);
11642 	u32 mc_dev_type, mc_version, mc_base_version;
11643 	u16 mc_nr_of_blks = be16_to_cpu(*(__be16 *)(mc_data + sizeof(u16)));
11644 
11645 	/*
11646 	 * Scan microcode blocks first for version info
11647 	 * and firmware check
11648 	 */
11649 
11650 	/* Clear version block */
11651 	DRX_ATTR_MCRECORD(demod).aux_type = 0;
11652 	DRX_ATTR_MCRECORD(demod).mc_dev_type = 0;
11653 	DRX_ATTR_MCRECORD(demod).mc_version = 0;
11654 	DRX_ATTR_MCRECORD(demod).mc_base_version = 0;
11655 
11656 	for (i = 0; i < mc_nr_of_blks; i++) {
11657 		if (count + 3 * sizeof(u16) + sizeof(u32) > size)
11658 			goto eof;
11659 
11660 		/* Process block header */
11661 		block_hdr.addr = be32_to_cpu(*(__be32 *)(mc_data + count));
11662 		count += sizeof(u32);
11663 		block_hdr.size = be16_to_cpu(*(__be16 *)(mc_data + count));
11664 		count += sizeof(u16);
11665 		block_hdr.flags = be16_to_cpu(*(__be16 *)(mc_data + count));
11666 		count += sizeof(u16);
11667 		block_hdr.CRC = be16_to_cpu(*(__be16 *)(mc_data + count));
11668 		count += sizeof(u16);
11669 
11670 		pr_debug("%u: addr %u, size %u, flags 0x%04x, CRC 0x%04x\n",
11671 			count, block_hdr.addr, block_hdr.size, block_hdr.flags,
11672 			block_hdr.CRC);
11673 
11674 		if (block_hdr.flags & 0x8) {
11675 			u8 *auxblk = ((void *)mc_data) + block_hdr.addr;
11676 			u16 auxtype;
11677 
11678 			if (block_hdr.addr + sizeof(u16) > size)
11679 				goto eof;
11680 
11681 			auxtype = be16_to_cpu(*(__be16 *)(auxblk));
11682 
11683 			/* Aux block. Check type */
11684 			if (DRX_ISMCVERTYPE(auxtype)) {
11685 				if (block_hdr.addr + 2 * sizeof(u16) + 2 * sizeof (u32) > size)
11686 					goto eof;
11687 
11688 				auxblk += sizeof(u16);
11689 				mc_dev_type = be32_to_cpu(*(__be32 *)(auxblk));
11690 				auxblk += sizeof(u32);
11691 				mc_version = be32_to_cpu(*(__be32 *)(auxblk));
11692 				auxblk += sizeof(u32);
11693 				mc_base_version = be32_to_cpu(*(__be32 *)(auxblk));
11694 
11695 				DRX_ATTR_MCRECORD(demod).aux_type = auxtype;
11696 				DRX_ATTR_MCRECORD(demod).mc_dev_type = mc_dev_type;
11697 				DRX_ATTR_MCRECORD(demod).mc_version = mc_version;
11698 				DRX_ATTR_MCRECORD(demod).mc_base_version = mc_base_version;
11699 
11700 				pr_info("Firmware dev %x, ver %x, base ver %x\n",
11701 					mc_dev_type, mc_version, mc_base_version);
11702 
11703 			}
11704 		} else if (count + block_hdr.size * sizeof(u16) > size)
11705 			goto eof;
11706 
11707 		count += block_hdr.size * sizeof(u16);
11708 	}
11709 	return 0;
11710 eof:
11711 	pr_err("Firmware is truncated at pos %u/%u\n", count, size);
11712 	return -EINVAL;
11713 }
11714 
11715 /*
11716  * drx_ctrl_u_code - Handle microcode upload or verify.
11717  * @dev_addr: Address of device.
11718  * @mc_info:  Pointer to information about microcode data.
11719  * @action:  Either UCODE_UPLOAD or UCODE_VERIFY
11720  *
11721  * This function returns:
11722  *	0:
11723  *		- In case of UCODE_UPLOAD: code is successfully uploaded.
11724  *               - In case of UCODE_VERIFY: image on device is equal to
11725  *		  image provided to this control function.
11726  *	-EIO:
11727  *		- In case of UCODE_UPLOAD: I2C error.
11728  *		- In case of UCODE_VERIFY: I2C error or image on device
11729  *		  is not equal to image provided to this control function.
11730  *	-EINVAL:
11731  *		- Invalid arguments.
11732  *		- Provided image is corrupt
11733  */
11734 static int drx_ctrl_u_code(struct drx_demod_instance *demod,
11735 		       struct drxu_code_info *mc_info,
11736 		       enum drxu_code_action action)
11737 {
11738 	struct i2c_device_addr *dev_addr = demod->my_i2c_dev_addr;
11739 	int rc;
11740 	u16 i = 0;
11741 	u16 mc_nr_of_blks = 0;
11742 	u16 mc_magic_word = 0;
11743 	const u8 *mc_data_init = NULL;
11744 	u8 *mc_data = NULL;
11745 	unsigned size;
11746 	char *mc_file;
11747 
11748 	/* Check arguments */
11749 	if (!mc_info || !mc_info->mc_file)
11750 		return -EINVAL;
11751 
11752 	mc_file = mc_info->mc_file;
11753 
11754 	if (!demod->firmware) {
11755 		const struct firmware *fw = NULL;
11756 
11757 		rc = request_firmware(&fw, mc_file, demod->i2c->dev.parent);
11758 		if (rc < 0) {
11759 			pr_err("Couldn't read firmware %s\n", mc_file);
11760 			return rc;
11761 		}
11762 		demod->firmware = fw;
11763 
11764 		if (demod->firmware->size < 2 * sizeof(u16)) {
11765 			rc = -EINVAL;
11766 			pr_err("Firmware is too short!\n");
11767 			goto release;
11768 		}
11769 
11770 		pr_info("Firmware %s, size %zu\n",
11771 			mc_file, demod->firmware->size);
11772 	}
11773 
11774 	mc_data_init = demod->firmware->data;
11775 	size = demod->firmware->size;
11776 
11777 	mc_data = (void *)mc_data_init;
11778 	/* Check data */
11779 	mc_magic_word = be16_to_cpu(*(__be16 *)(mc_data));
11780 	mc_data += sizeof(u16);
11781 	mc_nr_of_blks = be16_to_cpu(*(__be16 *)(mc_data));
11782 	mc_data += sizeof(u16);
11783 
11784 	if ((mc_magic_word != DRX_UCODE_MAGIC_WORD) || (mc_nr_of_blks == 0)) {
11785 		rc = -EINVAL;
11786 		pr_err("Firmware magic word doesn't match\n");
11787 		goto release;
11788 	}
11789 
11790 	if (action == UCODE_UPLOAD) {
11791 		rc = drx_check_firmware(demod, (u8 *)mc_data_init, size);
11792 		if (rc)
11793 			goto release;
11794 		pr_info("Uploading firmware %s\n", mc_file);
11795 	} else {
11796 		pr_info("Verifying if firmware upload was ok.\n");
11797 	}
11798 
11799 	/* Process microcode blocks */
11800 	for (i = 0; i < mc_nr_of_blks; i++) {
11801 		struct drxu_code_block_hdr block_hdr;
11802 		u16 mc_block_nr_bytes = 0;
11803 
11804 		/* Process block header */
11805 		block_hdr.addr = be32_to_cpu(*(__be32 *)(mc_data));
11806 		mc_data += sizeof(u32);
11807 		block_hdr.size = be16_to_cpu(*(__be16 *)(mc_data));
11808 		mc_data += sizeof(u16);
11809 		block_hdr.flags = be16_to_cpu(*(__be16 *)(mc_data));
11810 		mc_data += sizeof(u16);
11811 		block_hdr.CRC = be16_to_cpu(*(__be16 *)(mc_data));
11812 		mc_data += sizeof(u16);
11813 
11814 		pr_debug("%u: addr %u, size %u, flags 0x%04x, CRC 0x%04x\n",
11815 			(unsigned)(mc_data - mc_data_init), block_hdr.addr,
11816 			 block_hdr.size, block_hdr.flags, block_hdr.CRC);
11817 
11818 		/* Check block header on:
11819 		   - data larger than 64Kb
11820 		   - if CRC enabled check CRC
11821 		 */
11822 		if ((block_hdr.size > 0x7FFF) ||
11823 		    (((block_hdr.flags & DRX_UCODE_CRC_FLAG) != 0) &&
11824 		     (block_hdr.CRC != drx_u_code_compute_crc(mc_data, block_hdr.size)))
11825 		    ) {
11826 			/* Wrong data ! */
11827 			rc = -EINVAL;
11828 			pr_err("firmware CRC is wrong\n");
11829 			goto release;
11830 		}
11831 
11832 		if (!block_hdr.size)
11833 			continue;
11834 
11835 		mc_block_nr_bytes = block_hdr.size * ((u16) sizeof(u16));
11836 
11837 		/* Perform the desired action */
11838 		switch (action) {
11839 		case UCODE_UPLOAD:	/* Upload microcode */
11840 			if (drxdap_fasi_write_block(dev_addr,
11841 							block_hdr.addr,
11842 							mc_block_nr_bytes,
11843 							mc_data, 0x0000)) {
11844 				rc = -EIO;
11845 				pr_err("error writing firmware at pos %u\n",
11846 				       (unsigned)(mc_data - mc_data_init));
11847 				goto release;
11848 			}
11849 			break;
11850 		case UCODE_VERIFY: {	/* Verify uploaded microcode */
11851 			int result = 0;
11852 			u8 mc_data_buffer[DRX_UCODE_MAX_BUF_SIZE];
11853 			u32 bytes_to_comp = 0;
11854 			u32 bytes_left = mc_block_nr_bytes;
11855 			u32 curr_addr = block_hdr.addr;
11856 			u8 *curr_ptr = mc_data;
11857 
11858 			while (bytes_left != 0) {
11859 				if (bytes_left > DRX_UCODE_MAX_BUF_SIZE)
11860 					bytes_to_comp = DRX_UCODE_MAX_BUF_SIZE;
11861 				else
11862 					bytes_to_comp = bytes_left;
11863 
11864 				if (drxdap_fasi_read_block(dev_addr,
11865 						    curr_addr,
11866 						    (u16)bytes_to_comp,
11867 						    (u8 *)mc_data_buffer,
11868 						    0x0000)) {
11869 					pr_err("error reading firmware at pos %u\n",
11870 					       (unsigned)(mc_data - mc_data_init));
11871 					return -EIO;
11872 				}
11873 
11874 				result = memcmp(curr_ptr, mc_data_buffer,
11875 						bytes_to_comp);
11876 
11877 				if (result) {
11878 					pr_err("error verifying firmware at pos %u\n",
11879 					       (unsigned)(mc_data - mc_data_init));
11880 					return -EIO;
11881 				}
11882 
11883 				curr_addr += ((dr_xaddr_t)(bytes_to_comp / 2));
11884 				curr_ptr =&(curr_ptr[bytes_to_comp]);
11885 				bytes_left -=((u32) bytes_to_comp);
11886 			}
11887 			break;
11888 		}
11889 		default:
11890 			return -EINVAL;
11891 			break;
11892 
11893 		}
11894 		mc_data += mc_block_nr_bytes;
11895 	}
11896 
11897 	return 0;
11898 
11899 release:
11900 	release_firmware(demod->firmware);
11901 	demod->firmware = NULL;
11902 
11903 	return rc;
11904 }
11905 
11906 /* caller is expected to check if lna is supported before enabling */
11907 static int drxj_set_lna_state(struct drx_demod_instance *demod, bool state)
11908 {
11909 	struct drxuio_cfg uio_cfg;
11910 	struct drxuio_data uio_data;
11911 	int result;
11912 
11913 	uio_cfg.uio = DRX_UIO1;
11914 	uio_cfg.mode = DRX_UIO_MODE_READWRITE;
11915 	/* Configure user-I/O #3: enable read/write */
11916 	result = ctrl_set_uio_cfg(demod, &uio_cfg);
11917 	if (result) {
11918 		pr_err("Failed to setup LNA GPIO!\n");
11919 		return result;
11920 	}
11921 
11922 	uio_data.uio = DRX_UIO1;
11923 	uio_data.value = state;
11924 	result = ctrl_uio_write(demod, &uio_data);
11925 	if (result != 0) {
11926 		pr_err("Failed to %sable LNA!\n",
11927 		       state ? "en" : "dis");
11928 		return result;
11929 	}
11930 	return 0;
11931 }
11932 
11933 /*
11934  * The Linux DVB Driver for Micronas DRX39xx family (drx3933j)
11935  *
11936  * Written by Devin Heitmueller <devin.heitmueller@kernellabs.com>
11937  */
11938 
11939 static int drx39xxj_set_powerstate(struct dvb_frontend *fe, int enable)
11940 {
11941 	struct drx39xxj_state *state = fe->demodulator_priv;
11942 	struct drx_demod_instance *demod = state->demod;
11943 	int result;
11944 	enum drx_power_mode power_mode;
11945 
11946 	if (enable)
11947 		power_mode = DRX_POWER_UP;
11948 	else
11949 		power_mode = DRX_POWER_DOWN;
11950 
11951 	result = ctrl_power_mode(demod, &power_mode);
11952 	if (result != 0) {
11953 		pr_err("Power state change failed\n");
11954 		return 0;
11955 	}
11956 
11957 	return 0;
11958 }
11959 
11960 static int drx39xxj_read_status(struct dvb_frontend *fe, enum fe_status *status)
11961 {
11962 	struct drx39xxj_state *state = fe->demodulator_priv;
11963 	struct drx_demod_instance *demod = state->demod;
11964 	int result;
11965 	enum drx_lock_status lock_status;
11966 
11967 	*status = 0;
11968 
11969 	result = ctrl_lock_status(demod, &lock_status);
11970 	if (result != 0) {
11971 		pr_err("drx39xxj: could not get lock status!\n");
11972 		*status = 0;
11973 	}
11974 
11975 	switch (lock_status) {
11976 	case DRX_NEVER_LOCK:
11977 		*status = 0;
11978 		pr_err("drx says NEVER_LOCK\n");
11979 		break;
11980 	case DRX_NOT_LOCKED:
11981 		*status = 0;
11982 		break;
11983 	case DRX_LOCK_STATE_1:
11984 	case DRX_LOCK_STATE_2:
11985 	case DRX_LOCK_STATE_3:
11986 	case DRX_LOCK_STATE_4:
11987 	case DRX_LOCK_STATE_5:
11988 	case DRX_LOCK_STATE_6:
11989 	case DRX_LOCK_STATE_7:
11990 	case DRX_LOCK_STATE_8:
11991 	case DRX_LOCK_STATE_9:
11992 		*status = FE_HAS_SIGNAL
11993 		    | FE_HAS_CARRIER | FE_HAS_VITERBI | FE_HAS_SYNC;
11994 		break;
11995 	case DRX_LOCKED:
11996 		*status = FE_HAS_SIGNAL
11997 		    | FE_HAS_CARRIER
11998 		    | FE_HAS_VITERBI | FE_HAS_SYNC | FE_HAS_LOCK;
11999 		break;
12000 	default:
12001 		pr_err("Lock state unknown %d\n", lock_status);
12002 	}
12003 	ctrl_sig_quality(demod, lock_status);
12004 
12005 	return 0;
12006 }
12007 
12008 static int drx39xxj_read_ber(struct dvb_frontend *fe, u32 *ber)
12009 {
12010 	struct dtv_frontend_properties *p = &fe->dtv_property_cache;
12011 
12012 	if (p->pre_bit_error.stat[0].scale == FE_SCALE_NOT_AVAILABLE) {
12013 		*ber = 0;
12014 		return 0;
12015 	}
12016 
12017 	if (!p->pre_bit_count.stat[0].uvalue) {
12018 		if (!p->pre_bit_error.stat[0].uvalue)
12019 			*ber = 0;
12020 		else
12021 			*ber = 1000000;
12022 	} else {
12023 		*ber = frac_times1e6(p->pre_bit_error.stat[0].uvalue,
12024 				     p->pre_bit_count.stat[0].uvalue);
12025 	}
12026 	return 0;
12027 }
12028 
12029 static int drx39xxj_read_signal_strength(struct dvb_frontend *fe,
12030 					 u16 *strength)
12031 {
12032 	struct dtv_frontend_properties *p = &fe->dtv_property_cache;
12033 
12034 	if (p->strength.stat[0].scale == FE_SCALE_NOT_AVAILABLE) {
12035 		*strength = 0;
12036 		return 0;
12037 	}
12038 
12039 	*strength = p->strength.stat[0].uvalue;
12040 	return 0;
12041 }
12042 
12043 static int drx39xxj_read_snr(struct dvb_frontend *fe, u16 *snr)
12044 {
12045 	struct dtv_frontend_properties *p = &fe->dtv_property_cache;
12046 	u64 tmp64;
12047 
12048 	if (p->cnr.stat[0].scale == FE_SCALE_NOT_AVAILABLE) {
12049 		*snr = 0;
12050 		return 0;
12051 	}
12052 
12053 	tmp64 = p->cnr.stat[0].svalue;
12054 	do_div(tmp64, 10);
12055 	*snr = tmp64;
12056 	return 0;
12057 }
12058 
12059 static int drx39xxj_read_ucblocks(struct dvb_frontend *fe, u32 *ucb)
12060 {
12061 	struct dtv_frontend_properties *p = &fe->dtv_property_cache;
12062 
12063 	if (p->block_error.stat[0].scale == FE_SCALE_NOT_AVAILABLE) {
12064 		*ucb = 0;
12065 		return 0;
12066 	}
12067 
12068 	*ucb = p->block_error.stat[0].uvalue;
12069 	return 0;
12070 }
12071 
12072 static int drx39xxj_set_frontend(struct dvb_frontend *fe)
12073 {
12074 #ifdef DJH_DEBUG
12075 	int i;
12076 #endif
12077 	struct dtv_frontend_properties *p = &fe->dtv_property_cache;
12078 	struct drx39xxj_state *state = fe->demodulator_priv;
12079 	struct drx_demod_instance *demod = state->demod;
12080 	enum drx_standard standard = DRX_STANDARD_8VSB;
12081 	struct drx_channel channel;
12082 	int result;
12083 	static const struct drx_channel def_channel = {
12084 		/* frequency      */ 0,
12085 		/* bandwidth      */ DRX_BANDWIDTH_6MHZ,
12086 		/* mirror         */ DRX_MIRROR_NO,
12087 		/* constellation  */ DRX_CONSTELLATION_AUTO,
12088 		/* hierarchy      */ DRX_HIERARCHY_UNKNOWN,
12089 		/* priority       */ DRX_PRIORITY_UNKNOWN,
12090 		/* coderate       */ DRX_CODERATE_UNKNOWN,
12091 		/* guard          */ DRX_GUARD_UNKNOWN,
12092 		/* fftmode        */ DRX_FFTMODE_UNKNOWN,
12093 		/* classification */ DRX_CLASSIFICATION_AUTO,
12094 		/* symbolrate     */ 5057000,
12095 		/* interleavemode */ DRX_INTERLEAVEMODE_UNKNOWN,
12096 		/* ldpc           */ DRX_LDPC_UNKNOWN,
12097 		/* carrier        */ DRX_CARRIER_UNKNOWN,
12098 		/* frame mode     */ DRX_FRAMEMODE_UNKNOWN
12099 	};
12100 	u32 constellation = DRX_CONSTELLATION_AUTO;
12101 
12102 	/* Bring the demod out of sleep */
12103 	drx39xxj_set_powerstate(fe, 1);
12104 
12105 	if (fe->ops.tuner_ops.set_params) {
12106 		u32 int_freq;
12107 
12108 		if (fe->ops.i2c_gate_ctrl)
12109 			fe->ops.i2c_gate_ctrl(fe, 1);
12110 
12111 		/* Set tuner to desired frequency and standard */
12112 		fe->ops.tuner_ops.set_params(fe);
12113 
12114 		/* Use the tuner's IF */
12115 		if (fe->ops.tuner_ops.get_if_frequency) {
12116 			fe->ops.tuner_ops.get_if_frequency(fe, &int_freq);
12117 			demod->my_common_attr->intermediate_freq = int_freq / 1000;
12118 		}
12119 
12120 		if (fe->ops.i2c_gate_ctrl)
12121 			fe->ops.i2c_gate_ctrl(fe, 0);
12122 	}
12123 
12124 	switch (p->delivery_system) {
12125 	case SYS_ATSC:
12126 		standard = DRX_STANDARD_8VSB;
12127 		break;
12128 	case SYS_DVBC_ANNEX_B:
12129 		standard = DRX_STANDARD_ITU_B;
12130 
12131 		switch (p->modulation) {
12132 		case QAM_64:
12133 			constellation = DRX_CONSTELLATION_QAM64;
12134 			break;
12135 		case QAM_256:
12136 			constellation = DRX_CONSTELLATION_QAM256;
12137 			break;
12138 		default:
12139 			constellation = DRX_CONSTELLATION_AUTO;
12140 			break;
12141 		}
12142 		break;
12143 	default:
12144 		return -EINVAL;
12145 	}
12146 	/* Set the standard (will be powered up if necessary */
12147 	result = ctrl_set_standard(demod, &standard);
12148 	if (result != 0) {
12149 		pr_err("Failed to set standard! result=%02x\n",
12150 			result);
12151 		return -EINVAL;
12152 	}
12153 
12154 	/* set channel parameters */
12155 	channel = def_channel;
12156 	channel.frequency = p->frequency / 1000;
12157 	channel.bandwidth = DRX_BANDWIDTH_6MHZ;
12158 	channel.constellation = constellation;
12159 
12160 	/* program channel */
12161 	result = ctrl_set_channel(demod, &channel);
12162 	if (result != 0) {
12163 		pr_err("Failed to set channel!\n");
12164 		return -EINVAL;
12165 	}
12166 	/* Just for giggles, let's shut off the LNA again.... */
12167 	drxj_set_lna_state(demod, false);
12168 
12169 	/* After set_frontend, except for strength, stats aren't available */
12170 	p->strength.stat[0].scale = FE_SCALE_RELATIVE;
12171 
12172 	return 0;
12173 }
12174 
12175 static int drx39xxj_sleep(struct dvb_frontend *fe)
12176 {
12177 	/* power-down the demodulator */
12178 	return drx39xxj_set_powerstate(fe, 0);
12179 }
12180 
12181 static int drx39xxj_i2c_gate_ctrl(struct dvb_frontend *fe, int enable)
12182 {
12183 	struct drx39xxj_state *state = fe->demodulator_priv;
12184 	struct drx_demod_instance *demod = state->demod;
12185 	bool i2c_gate_state;
12186 	int result;
12187 
12188 #ifdef DJH_DEBUG
12189 	pr_debug("i2c gate call: enable=%d state=%d\n", enable,
12190 	       state->i2c_gate_open);
12191 #endif
12192 
12193 	if (enable)
12194 		i2c_gate_state = true;
12195 	else
12196 		i2c_gate_state = false;
12197 
12198 	if (state->i2c_gate_open == enable) {
12199 		/* We're already in the desired state */
12200 		return 0;
12201 	}
12202 
12203 	result = ctrl_i2c_bridge(demod, &i2c_gate_state);
12204 	if (result != 0) {
12205 		pr_err("drx39xxj: could not open i2c gate [%d]\n",
12206 		       result);
12207 		dump_stack();
12208 	} else {
12209 		state->i2c_gate_open = enable;
12210 	}
12211 	return 0;
12212 }
12213 
12214 static int drx39xxj_init(struct dvb_frontend *fe)
12215 {
12216 	struct drx39xxj_state *state = fe->demodulator_priv;
12217 	struct drx_demod_instance *demod = state->demod;
12218 	int rc = 0;
12219 
12220 	if (fe->exit == DVB_FE_DEVICE_RESUME) {
12221 		/* so drxj_open() does what it needs to do */
12222 		demod->my_common_attr->is_opened = false;
12223 		rc = drxj_open(demod);
12224 		if (rc != 0)
12225 			pr_err("drx39xxj_init(): DRX open failed rc=%d!\n", rc);
12226 	} else
12227 		drx39xxj_set_powerstate(fe, 1);
12228 
12229 	return rc;
12230 }
12231 
12232 static int drx39xxj_set_lna(struct dvb_frontend *fe)
12233 {
12234 	struct dtv_frontend_properties *c = &fe->dtv_property_cache;
12235 	struct drx39xxj_state *state = fe->demodulator_priv;
12236 	struct drx_demod_instance *demod = state->demod;
12237 	struct drxj_data *ext_attr = demod->my_ext_attr;
12238 
12239 	if (c->lna) {
12240 		if (!ext_attr->has_lna) {
12241 			pr_err("LNA is not supported on this device!\n");
12242 			return -EINVAL;
12243 
12244 		}
12245 	}
12246 
12247 	return drxj_set_lna_state(demod, c->lna);
12248 }
12249 
12250 static int drx39xxj_get_tune_settings(struct dvb_frontend *fe,
12251 				      struct dvb_frontend_tune_settings *tune)
12252 {
12253 	tune->min_delay_ms = 1000;
12254 	return 0;
12255 }
12256 
12257 static void drx39xxj_release(struct dvb_frontend *fe)
12258 {
12259 	struct drx39xxj_state *state = fe->demodulator_priv;
12260 	struct drx_demod_instance *demod = state->demod;
12261 
12262 	/* if device is removed don't access it */
12263 	if (fe->exit != DVB_FE_DEVICE_REMOVED)
12264 		drxj_close(demod);
12265 
12266 	kfree(demod->my_ext_attr);
12267 	kfree(demod->my_common_attr);
12268 	kfree(demod->my_i2c_dev_addr);
12269 	release_firmware(demod->firmware);
12270 	kfree(demod);
12271 	kfree(state);
12272 }
12273 
12274 static const struct dvb_frontend_ops drx39xxj_ops;
12275 
12276 struct dvb_frontend *drx39xxj_attach(struct i2c_adapter *i2c)
12277 {
12278 	struct drx39xxj_state *state = NULL;
12279 	struct i2c_device_addr *demod_addr = NULL;
12280 	struct drx_common_attr *demod_comm_attr = NULL;
12281 	struct drxj_data *demod_ext_attr = NULL;
12282 	struct drx_demod_instance *demod = NULL;
12283 	struct dtv_frontend_properties *p;
12284 	int result;
12285 
12286 	/* allocate memory for the internal state */
12287 	state = kzalloc(sizeof(struct drx39xxj_state), GFP_KERNEL);
12288 	if (state == NULL)
12289 		goto error;
12290 
12291 	demod = kmalloc(sizeof(struct drx_demod_instance), GFP_KERNEL);
12292 	if (demod == NULL)
12293 		goto error;
12294 
12295 	demod_addr = kmemdup(&drxj_default_addr_g,
12296 			     sizeof(struct i2c_device_addr), GFP_KERNEL);
12297 	if (demod_addr == NULL)
12298 		goto error;
12299 
12300 	demod_comm_attr = kmemdup(&drxj_default_comm_attr_g,
12301 				  sizeof(struct drx_common_attr), GFP_KERNEL);
12302 	if (demod_comm_attr == NULL)
12303 		goto error;
12304 
12305 	demod_ext_attr = kmemdup(&drxj_data_g, sizeof(struct drxj_data),
12306 				 GFP_KERNEL);
12307 	if (demod_ext_attr == NULL)
12308 		goto error;
12309 
12310 	/* setup the state */
12311 	state->i2c = i2c;
12312 	state->demod = demod;
12313 
12314 	/* setup the demod data */
12315 	memcpy(demod, &drxj_default_demod_g, sizeof(struct drx_demod_instance));
12316 
12317 	demod->my_i2c_dev_addr = demod_addr;
12318 	demod->my_common_attr = demod_comm_attr;
12319 	demod->my_i2c_dev_addr->user_data = state;
12320 	demod->my_common_attr->microcode_file = DRX39XX_MAIN_FIRMWARE;
12321 	demod->my_common_attr->verify_microcode = true;
12322 	demod->my_common_attr->intermediate_freq = 5000;
12323 	demod->my_common_attr->current_power_mode = DRX_POWER_DOWN;
12324 	demod->my_ext_attr = demod_ext_attr;
12325 	((struct drxj_data *)demod_ext_attr)->uio_sma_tx_mode = DRX_UIO_MODE_READWRITE;
12326 	demod->i2c = i2c;
12327 
12328 	result = drxj_open(demod);
12329 	if (result != 0) {
12330 		pr_err("DRX open failed!  Aborting\n");
12331 		goto error;
12332 	}
12333 
12334 	/* create dvb_frontend */
12335 	memcpy(&state->frontend.ops, &drx39xxj_ops,
12336 	       sizeof(struct dvb_frontend_ops));
12337 
12338 	state->frontend.demodulator_priv = state;
12339 
12340 	/* Initialize stats - needed for DVBv5 stats to work */
12341 	p = &state->frontend.dtv_property_cache;
12342 	p->strength.len = 1;
12343 	p->pre_bit_count.len = 1;
12344 	p->pre_bit_error.len = 1;
12345 	p->post_bit_count.len = 1;
12346 	p->post_bit_error.len = 1;
12347 	p->block_count.len = 1;
12348 	p->block_error.len = 1;
12349 	p->cnr.len = 1;
12350 
12351 	p->strength.stat[0].scale = FE_SCALE_RELATIVE;
12352 	p->pre_bit_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
12353 	p->pre_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
12354 	p->post_bit_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
12355 	p->post_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
12356 	p->block_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
12357 	p->block_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
12358 	p->cnr.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
12359 
12360 	return &state->frontend;
12361 
12362 error:
12363 	kfree(demod_ext_attr);
12364 	kfree(demod_comm_attr);
12365 	kfree(demod_addr);
12366 	kfree(demod);
12367 	kfree(state);
12368 
12369 	return NULL;
12370 }
12371 EXPORT_SYMBOL(drx39xxj_attach);
12372 
12373 static const struct dvb_frontend_ops drx39xxj_ops = {
12374 	.delsys = { SYS_ATSC, SYS_DVBC_ANNEX_B },
12375 	.info = {
12376 		 .name = "Micronas DRX39xxj family Frontend",
12377 		 .frequency_stepsize = 62500,
12378 		 .frequency_min = 51000000,
12379 		 .frequency_max = 858000000,
12380 		 .caps = FE_CAN_QAM_64 | FE_CAN_QAM_256 | FE_CAN_8VSB
12381 	},
12382 
12383 	.init = drx39xxj_init,
12384 	.i2c_gate_ctrl = drx39xxj_i2c_gate_ctrl,
12385 	.sleep = drx39xxj_sleep,
12386 	.set_frontend = drx39xxj_set_frontend,
12387 	.get_tune_settings = drx39xxj_get_tune_settings,
12388 	.read_status = drx39xxj_read_status,
12389 	.read_ber = drx39xxj_read_ber,
12390 	.read_signal_strength = drx39xxj_read_signal_strength,
12391 	.read_snr = drx39xxj_read_snr,
12392 	.read_ucblocks = drx39xxj_read_ucblocks,
12393 	.release = drx39xxj_release,
12394 	.set_lna = drx39xxj_set_lna,
12395 };
12396 
12397 MODULE_DESCRIPTION("Micronas DRX39xxj Frontend");
12398 MODULE_AUTHOR("Devin Heitmueller");
12399 MODULE_LICENSE("GPL");
12400 MODULE_FIRMWARE(DRX39XX_MAIN_FIRMWARE);
12401