1 /* 2 Copyright (c), 2004-2005,2007-2010 Trident Microsystems, Inc. 3 All rights reserved. 4 5 Redistribution and use in source and binary forms, with or without 6 modification, are permitted provided that the following conditions are met: 7 8 * Redistributions of source code must retain the above copyright notice, 9 this list of conditions and the following disclaimer. 10 * Redistributions in binary form must reproduce the above copyright notice, 11 this list of conditions and the following disclaimer in the documentation 12 and/or other materials provided with the distribution. 13 * Neither the name of Trident Microsystems nor Hauppauge Computer Works 14 nor the names of its contributors may be used to endorse or promote 15 products derived from this software without specific prior written 16 permission. 17 18 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 19 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 22 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28 POSSIBILITY OF SUCH DAMAGE. 29 30 DRXJ specific implementation of DRX driver 31 authors: Dragan Savic, Milos Nikolic, Mihajlo Katona, Tao Ding, Paul Janssen 32 33 The Linux DVB Driver for Micronas DRX39xx family (drx3933j) was 34 written by Devin Heitmueller <devin.heitmueller@kernellabs.com> 35 36 This program is free software; you can redistribute it and/or modify 37 it under the terms of the GNU General Public License as published by 38 the Free Software Foundation; either version 2 of the License, or 39 (at your option) any later version. 40 41 This program is distributed in the hope that it will be useful, 42 but WITHOUT ANY WARRANTY; without even the implied warranty of 43 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 44 45 GNU General Public License for more details. 46 47 You should have received a copy of the GNU General Public License 48 along with this program; if not, write to the Free Software 49 Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. 50 */ 51 52 /*----------------------------------------------------------------------------- 53 INCLUDE FILES 54 ----------------------------------------------------------------------------*/ 55 56 #define pr_fmt(fmt) KBUILD_MODNAME ":%s: " fmt, __func__ 57 58 #include <linux/module.h> 59 #include <linux/firmware.h> 60 #include <linux/init.h> 61 #include <linux/string.h> 62 #include <linux/slab.h> 63 #include <asm/div64.h> 64 65 #include <media/dvb_frontend.h> 66 #include "drx39xxj.h" 67 68 #include "drxj.h" 69 #include "drxj_map.h" 70 71 /*============================================================================*/ 72 /*=== DEFINES ================================================================*/ 73 /*============================================================================*/ 74 75 #define DRX39XX_MAIN_FIRMWARE "dvb-fe-drxj-mc-1.0.8.fw" 76 77 /* 78 * \brief Maximum u32 value. 79 */ 80 #ifndef MAX_U32 81 #define MAX_U32 ((u32) (0xFFFFFFFFL)) 82 #endif 83 84 /* Customer configurable hardware settings, etc */ 85 #ifndef MPEG_SERIAL_OUTPUT_PIN_DRIVE_STRENGTH 86 #define MPEG_SERIAL_OUTPUT_PIN_DRIVE_STRENGTH 0x02 87 #endif 88 89 #ifndef MPEG_PARALLEL_OUTPUT_PIN_DRIVE_STRENGTH 90 #define MPEG_PARALLEL_OUTPUT_PIN_DRIVE_STRENGTH 0x02 91 #endif 92 93 #ifndef MPEG_OUTPUT_CLK_DRIVE_STRENGTH 94 #define MPEG_OUTPUT_CLK_DRIVE_STRENGTH 0x06 95 #endif 96 97 #ifndef OOB_CRX_DRIVE_STRENGTH 98 #define OOB_CRX_DRIVE_STRENGTH 0x02 99 #endif 100 101 #ifndef OOB_DRX_DRIVE_STRENGTH 102 #define OOB_DRX_DRIVE_STRENGTH 0x02 103 #endif 104 /*** START DJCOMBO patches to DRXJ registermap constants *********************/ 105 /*** registermap 200706071303 from drxj **************************************/ 106 #define ATV_TOP_CR_AMP_TH_FM 0x0 107 #define ATV_TOP_CR_AMP_TH_L 0xA 108 #define ATV_TOP_CR_AMP_TH_LP 0xA 109 #define ATV_TOP_CR_AMP_TH_BG 0x8 110 #define ATV_TOP_CR_AMP_TH_DK 0x8 111 #define ATV_TOP_CR_AMP_TH_I 0x8 112 #define ATV_TOP_CR_CONT_CR_D_MN 0x18 113 #define ATV_TOP_CR_CONT_CR_D_FM 0x0 114 #define ATV_TOP_CR_CONT_CR_D_L 0x20 115 #define ATV_TOP_CR_CONT_CR_D_LP 0x20 116 #define ATV_TOP_CR_CONT_CR_D_BG 0x18 117 #define ATV_TOP_CR_CONT_CR_D_DK 0x18 118 #define ATV_TOP_CR_CONT_CR_D_I 0x18 119 #define ATV_TOP_CR_CONT_CR_I_MN 0x80 120 #define ATV_TOP_CR_CONT_CR_I_FM 0x0 121 #define ATV_TOP_CR_CONT_CR_I_L 0x80 122 #define ATV_TOP_CR_CONT_CR_I_LP 0x80 123 #define ATV_TOP_CR_CONT_CR_I_BG 0x80 124 #define ATV_TOP_CR_CONT_CR_I_DK 0x80 125 #define ATV_TOP_CR_CONT_CR_I_I 0x80 126 #define ATV_TOP_CR_CONT_CR_P_MN 0x4 127 #define ATV_TOP_CR_CONT_CR_P_FM 0x0 128 #define ATV_TOP_CR_CONT_CR_P_L 0x4 129 #define ATV_TOP_CR_CONT_CR_P_LP 0x4 130 #define ATV_TOP_CR_CONT_CR_P_BG 0x4 131 #define ATV_TOP_CR_CONT_CR_P_DK 0x4 132 #define ATV_TOP_CR_CONT_CR_P_I 0x4 133 #define ATV_TOP_CR_OVM_TH_MN 0xA0 134 #define ATV_TOP_CR_OVM_TH_FM 0x0 135 #define ATV_TOP_CR_OVM_TH_L 0xA0 136 #define ATV_TOP_CR_OVM_TH_LP 0xA0 137 #define ATV_TOP_CR_OVM_TH_BG 0xA0 138 #define ATV_TOP_CR_OVM_TH_DK 0xA0 139 #define ATV_TOP_CR_OVM_TH_I 0xA0 140 #define ATV_TOP_EQU0_EQU_C0_FM 0x0 141 #define ATV_TOP_EQU0_EQU_C0_L 0x3 142 #define ATV_TOP_EQU0_EQU_C0_LP 0x3 143 #define ATV_TOP_EQU0_EQU_C0_BG 0x7 144 #define ATV_TOP_EQU0_EQU_C0_DK 0x0 145 #define ATV_TOP_EQU0_EQU_C0_I 0x3 146 #define ATV_TOP_EQU1_EQU_C1_FM 0x0 147 #define ATV_TOP_EQU1_EQU_C1_L 0x1F6 148 #define ATV_TOP_EQU1_EQU_C1_LP 0x1F6 149 #define ATV_TOP_EQU1_EQU_C1_BG 0x197 150 #define ATV_TOP_EQU1_EQU_C1_DK 0x198 151 #define ATV_TOP_EQU1_EQU_C1_I 0x1F6 152 #define ATV_TOP_EQU2_EQU_C2_FM 0x0 153 #define ATV_TOP_EQU2_EQU_C2_L 0x28 154 #define ATV_TOP_EQU2_EQU_C2_LP 0x28 155 #define ATV_TOP_EQU2_EQU_C2_BG 0xC5 156 #define ATV_TOP_EQU2_EQU_C2_DK 0xB0 157 #define ATV_TOP_EQU2_EQU_C2_I 0x28 158 #define ATV_TOP_EQU3_EQU_C3_FM 0x0 159 #define ATV_TOP_EQU3_EQU_C3_L 0x192 160 #define ATV_TOP_EQU3_EQU_C3_LP 0x192 161 #define ATV_TOP_EQU3_EQU_C3_BG 0x12E 162 #define ATV_TOP_EQU3_EQU_C3_DK 0x18E 163 #define ATV_TOP_EQU3_EQU_C3_I 0x192 164 #define ATV_TOP_STD_MODE_MN 0x0 165 #define ATV_TOP_STD_MODE_FM 0x1 166 #define ATV_TOP_STD_MODE_L 0x0 167 #define ATV_TOP_STD_MODE_LP 0x0 168 #define ATV_TOP_STD_MODE_BG 0x0 169 #define ATV_TOP_STD_MODE_DK 0x0 170 #define ATV_TOP_STD_MODE_I 0x0 171 #define ATV_TOP_STD_VID_POL_MN 0x0 172 #define ATV_TOP_STD_VID_POL_FM 0x0 173 #define ATV_TOP_STD_VID_POL_L 0x2 174 #define ATV_TOP_STD_VID_POL_LP 0x2 175 #define ATV_TOP_STD_VID_POL_BG 0x0 176 #define ATV_TOP_STD_VID_POL_DK 0x0 177 #define ATV_TOP_STD_VID_POL_I 0x0 178 #define ATV_TOP_VID_AMP_MN 0x380 179 #define ATV_TOP_VID_AMP_FM 0x0 180 #define ATV_TOP_VID_AMP_L 0xF50 181 #define ATV_TOP_VID_AMP_LP 0xF50 182 #define ATV_TOP_VID_AMP_BG 0x380 183 #define ATV_TOP_VID_AMP_DK 0x394 184 #define ATV_TOP_VID_AMP_I 0x3D8 185 #define IQM_CF_OUT_ENA_OFDM__M 0x4 186 #define IQM_FS_ADJ_SEL_B_QAM 0x1 187 #define IQM_FS_ADJ_SEL_B_OFF 0x0 188 #define IQM_FS_ADJ_SEL_B_VSB 0x2 189 #define IQM_RC_ADJ_SEL_B_OFF 0x0 190 #define IQM_RC_ADJ_SEL_B_QAM 0x1 191 #define IQM_RC_ADJ_SEL_B_VSB 0x2 192 /*** END DJCOMBO patches to DRXJ registermap *********************************/ 193 194 #include "drx_driver_version.h" 195 196 /* #define DRX_DEBUG */ 197 #ifdef DRX_DEBUG 198 #include <stdio.h> 199 #endif 200 201 /*----------------------------------------------------------------------------- 202 ENUMS 203 ----------------------------------------------------------------------------*/ 204 205 /*----------------------------------------------------------------------------- 206 DEFINES 207 ----------------------------------------------------------------------------*/ 208 #ifndef DRXJ_WAKE_UP_KEY 209 #define DRXJ_WAKE_UP_KEY (demod->my_i2c_dev_addr->i2c_addr) 210 #endif 211 212 /* 213 * \def DRXJ_DEF_I2C_ADDR 214 * \brief Default I2C address of a demodulator instance. 215 */ 216 #define DRXJ_DEF_I2C_ADDR (0x52) 217 218 /* 219 * \def DRXJ_DEF_DEMOD_DEV_ID 220 * \brief Default device identifier of a demodultor instance. 221 */ 222 #define DRXJ_DEF_DEMOD_DEV_ID (1) 223 224 /* 225 * \def DRXJ_SCAN_TIMEOUT 226 * \brief Timeout value for waiting on demod lock during channel scan (millisec). 227 */ 228 #define DRXJ_SCAN_TIMEOUT 1000 229 230 /* 231 * \def HI_I2C_DELAY 232 * \brief HI timing delay for I2C timing (in nano seconds) 233 * 234 * Used to compute HI_CFG_DIV 235 */ 236 #define HI_I2C_DELAY 42 237 238 /* 239 * \def HI_I2C_BRIDGE_DELAY 240 * \brief HI timing delay for I2C timing (in nano seconds) 241 * 242 * Used to compute HI_CFG_BDL 243 */ 244 #define HI_I2C_BRIDGE_DELAY 750 245 246 /* 247 * \brief Time Window for MER and SER Measurement in Units of Segment duration. 248 */ 249 #define VSB_TOP_MEASUREMENT_PERIOD 64 250 #define SYMBOLS_PER_SEGMENT 832 251 252 /* 253 * \brief bit rate and segment rate constants used for SER and BER. 254 */ 255 /* values taken from the QAM microcode */ 256 #define DRXJ_QAM_SL_SIG_POWER_QAM_UNKNOWN 0 257 #define DRXJ_QAM_SL_SIG_POWER_QPSK 32768 258 #define DRXJ_QAM_SL_SIG_POWER_QAM8 24576 259 #define DRXJ_QAM_SL_SIG_POWER_QAM16 40960 260 #define DRXJ_QAM_SL_SIG_POWER_QAM32 20480 261 #define DRXJ_QAM_SL_SIG_POWER_QAM64 43008 262 #define DRXJ_QAM_SL_SIG_POWER_QAM128 20992 263 #define DRXJ_QAM_SL_SIG_POWER_QAM256 43520 264 /* 265 * \brief Min supported symbolrates. 266 */ 267 #ifndef DRXJ_QAM_SYMBOLRATE_MIN 268 #define DRXJ_QAM_SYMBOLRATE_MIN (520000) 269 #endif 270 271 /* 272 * \brief Max supported symbolrates. 273 */ 274 #ifndef DRXJ_QAM_SYMBOLRATE_MAX 275 #define DRXJ_QAM_SYMBOLRATE_MAX (7233000) 276 #endif 277 278 /* 279 * \def DRXJ_QAM_MAX_WAITTIME 280 * \brief Maximal wait time for QAM auto constellation in ms 281 */ 282 #ifndef DRXJ_QAM_MAX_WAITTIME 283 #define DRXJ_QAM_MAX_WAITTIME 900 284 #endif 285 286 #ifndef DRXJ_QAM_FEC_LOCK_WAITTIME 287 #define DRXJ_QAM_FEC_LOCK_WAITTIME 150 288 #endif 289 290 #ifndef DRXJ_QAM_DEMOD_LOCK_EXT_WAITTIME 291 #define DRXJ_QAM_DEMOD_LOCK_EXT_WAITTIME 200 292 #endif 293 294 /* 295 * \def SCU status and results 296 * \brief SCU 297 */ 298 #define DRX_SCU_READY 0 299 #define DRXJ_MAX_WAITTIME 100 /* ms */ 300 #define FEC_RS_MEASUREMENT_PERIOD 12894 /* 1 sec */ 301 #define FEC_RS_MEASUREMENT_PRESCALE 1 /* n sec */ 302 303 /* 304 * \def DRX_AUD_MAX_DEVIATION 305 * \brief Needed for calculation of prescale feature in AUD 306 */ 307 #ifndef DRXJ_AUD_MAX_FM_DEVIATION 308 #define DRXJ_AUD_MAX_FM_DEVIATION 100 /* kHz */ 309 #endif 310 311 /* 312 * \brief Needed for calculation of NICAM prescale feature in AUD 313 */ 314 #ifndef DRXJ_AUD_MAX_NICAM_PRESCALE 315 #define DRXJ_AUD_MAX_NICAM_PRESCALE (9) /* dB */ 316 #endif 317 318 /* 319 * \brief Needed for calculation of NICAM prescale feature in AUD 320 */ 321 #ifndef DRXJ_AUD_MAX_WAITTIME 322 #define DRXJ_AUD_MAX_WAITTIME 250 /* ms */ 323 #endif 324 325 /* ATV config changed flags */ 326 #define DRXJ_ATV_CHANGED_COEF (0x00000001UL) 327 #define DRXJ_ATV_CHANGED_PEAK_FLT (0x00000008UL) 328 #define DRXJ_ATV_CHANGED_NOISE_FLT (0x00000010UL) 329 #define DRXJ_ATV_CHANGED_OUTPUT (0x00000020UL) 330 #define DRXJ_ATV_CHANGED_SIF_ATT (0x00000040UL) 331 332 /* UIO define */ 333 #define DRX_UIO_MODE_FIRMWARE_SMA DRX_UIO_MODE_FIRMWARE0 334 #define DRX_UIO_MODE_FIRMWARE_SAW DRX_UIO_MODE_FIRMWARE1 335 336 /* 337 * MICROCODE RELATED DEFINES 338 */ 339 340 /* Magic word for checking correct Endianness of microcode data */ 341 #define DRX_UCODE_MAGIC_WORD ((((u16)'H')<<8)+((u16)'L')) 342 343 /* CRC flag in ucode header, flags field. */ 344 #define DRX_UCODE_CRC_FLAG (0x0001) 345 346 /* 347 * Maximum size of buffer used to verify the microcode. 348 * Must be an even number 349 */ 350 #define DRX_UCODE_MAX_BUF_SIZE (DRXDAP_MAX_RCHUNKSIZE) 351 352 #if DRX_UCODE_MAX_BUF_SIZE & 1 353 #error DRX_UCODE_MAX_BUF_SIZE must be an even number 354 #endif 355 356 /* 357 * Power mode macros 358 */ 359 360 #define DRX_ISPOWERDOWNMODE(mode) ((mode == DRX_POWER_MODE_9) || \ 361 (mode == DRX_POWER_MODE_10) || \ 362 (mode == DRX_POWER_MODE_11) || \ 363 (mode == DRX_POWER_MODE_12) || \ 364 (mode == DRX_POWER_MODE_13) || \ 365 (mode == DRX_POWER_MODE_14) || \ 366 (mode == DRX_POWER_MODE_15) || \ 367 (mode == DRX_POWER_MODE_16) || \ 368 (mode == DRX_POWER_DOWN)) 369 370 /* Pin safe mode macro */ 371 #define DRXJ_PIN_SAFE_MODE 0x0000 372 /*============================================================================*/ 373 /*=== GLOBAL VARIABLEs =======================================================*/ 374 /*============================================================================*/ 375 /* 376 */ 377 378 /* 379 * \brief Temporary register definitions. 380 * (register definitions that are not yet available in register master) 381 */ 382 383 /*****************************************************************************/ 384 /* Audio block 0x103 is write only. To avoid shadowing in driver accessing */ 385 /* RAM addresses directly. This must be READ ONLY to avoid problems. */ 386 /* Writing to the interface addresses are more than only writing the RAM */ 387 /* locations */ 388 /*****************************************************************************/ 389 /* 390 * \brief RAM location of MODUS registers 391 */ 392 #define AUD_DEM_RAM_MODUS_HI__A 0x10204A3 393 #define AUD_DEM_RAM_MODUS_HI__M 0xF000 394 395 #define AUD_DEM_RAM_MODUS_LO__A 0x10204A4 396 #define AUD_DEM_RAM_MODUS_LO__M 0x0FFF 397 398 /* 399 * \brief RAM location of I2S config registers 400 */ 401 #define AUD_DEM_RAM_I2S_CONFIG1__A 0x10204B1 402 #define AUD_DEM_RAM_I2S_CONFIG2__A 0x10204B2 403 404 /* 405 * \brief RAM location of DCO config registers 406 */ 407 #define AUD_DEM_RAM_DCO_B_HI__A 0x1020461 408 #define AUD_DEM_RAM_DCO_B_LO__A 0x1020462 409 #define AUD_DEM_RAM_DCO_A_HI__A 0x1020463 410 #define AUD_DEM_RAM_DCO_A_LO__A 0x1020464 411 412 /* 413 * \brief RAM location of Threshold registers 414 */ 415 #define AUD_DEM_RAM_NICAM_THRSHLD__A 0x102045A 416 #define AUD_DEM_RAM_A2_THRSHLD__A 0x10204BB 417 #define AUD_DEM_RAM_BTSC_THRSHLD__A 0x10204A6 418 419 /* 420 * \brief RAM location of Carrier Threshold registers 421 */ 422 #define AUD_DEM_RAM_CM_A_THRSHLD__A 0x10204AF 423 #define AUD_DEM_RAM_CM_B_THRSHLD__A 0x10204B0 424 425 /* 426 * \brief FM Matrix register fix 427 */ 428 #ifdef AUD_DEM_WR_FM_MATRIX__A 429 #undef AUD_DEM_WR_FM_MATRIX__A 430 #endif 431 #define AUD_DEM_WR_FM_MATRIX__A 0x105006F 432 433 /*============================================================================*/ 434 /* 435 * \brief Defines required for audio 436 */ 437 #define AUD_VOLUME_ZERO_DB 115 438 #define AUD_VOLUME_DB_MIN -60 439 #define AUD_VOLUME_DB_MAX 12 440 #define AUD_CARRIER_STRENGTH_QP_0DB 0x4000 441 #define AUD_CARRIER_STRENGTH_QP_0DB_LOG10T100 421 442 #define AUD_MAX_AVC_REF_LEVEL 15 443 #define AUD_I2S_FREQUENCY_MAX 48000UL 444 #define AUD_I2S_FREQUENCY_MIN 12000UL 445 #define AUD_RDS_ARRAY_SIZE 18 446 447 /* 448 * \brief Needed for calculation of prescale feature in AUD 449 */ 450 #ifndef DRX_AUD_MAX_FM_DEVIATION 451 #define DRX_AUD_MAX_FM_DEVIATION (100) /* kHz */ 452 #endif 453 454 /* 455 * \brief Needed for calculation of NICAM prescale feature in AUD 456 */ 457 #ifndef DRX_AUD_MAX_NICAM_PRESCALE 458 #define DRX_AUD_MAX_NICAM_PRESCALE (9) /* dB */ 459 #endif 460 461 /*============================================================================*/ 462 /* Values for I2S Master/Slave pin configurations */ 463 #define SIO_PDR_I2S_CL_CFG_MODE__MASTER 0x0004 464 #define SIO_PDR_I2S_CL_CFG_DRIVE__MASTER 0x0008 465 #define SIO_PDR_I2S_CL_CFG_MODE__SLAVE 0x0004 466 #define SIO_PDR_I2S_CL_CFG_DRIVE__SLAVE 0x0000 467 468 #define SIO_PDR_I2S_DA_CFG_MODE__MASTER 0x0003 469 #define SIO_PDR_I2S_DA_CFG_DRIVE__MASTER 0x0008 470 #define SIO_PDR_I2S_DA_CFG_MODE__SLAVE 0x0003 471 #define SIO_PDR_I2S_DA_CFG_DRIVE__SLAVE 0x0008 472 473 #define SIO_PDR_I2S_WS_CFG_MODE__MASTER 0x0004 474 #define SIO_PDR_I2S_WS_CFG_DRIVE__MASTER 0x0008 475 #define SIO_PDR_I2S_WS_CFG_MODE__SLAVE 0x0004 476 #define SIO_PDR_I2S_WS_CFG_DRIVE__SLAVE 0x0000 477 478 /*============================================================================*/ 479 /*=== REGISTER ACCESS MACROS =================================================*/ 480 /*============================================================================*/ 481 482 /* 483 * This macro is used to create byte arrays for block writes. 484 * Block writes speed up I2C traffic between host and demod. 485 * The macro takes care of the required byte order in a 16 bits word. 486 * x -> lowbyte(x), highbyte(x) 487 */ 488 #define DRXJ_16TO8(x) ((u8) (((u16)x) & 0xFF)), \ 489 ((u8)((((u16)x)>>8)&0xFF)) 490 /* 491 * This macro is used to convert byte array to 16 bit register value for block read. 492 * Block read speed up I2C traffic between host and demod. 493 * The macro takes care of the required byte order in a 16 bits word. 494 */ 495 #define DRXJ_8TO16(x) ((u16) (x[0] | (x[1] << 8))) 496 497 /*============================================================================*/ 498 /*=== MISC DEFINES ===========================================================*/ 499 /*============================================================================*/ 500 501 /*============================================================================*/ 502 /*=== HI COMMAND RELATED DEFINES =============================================*/ 503 /*============================================================================*/ 504 505 /* 506 * \brief General maximum number of retries for ucode command interfaces 507 */ 508 #define DRXJ_MAX_RETRIES (100) 509 510 /*============================================================================*/ 511 /*=== STANDARD RELATED MACROS ================================================*/ 512 /*============================================================================*/ 513 514 #define DRXJ_ISATVSTD(std) ((std == DRX_STANDARD_PAL_SECAM_BG) || \ 515 (std == DRX_STANDARD_PAL_SECAM_DK) || \ 516 (std == DRX_STANDARD_PAL_SECAM_I) || \ 517 (std == DRX_STANDARD_PAL_SECAM_L) || \ 518 (std == DRX_STANDARD_PAL_SECAM_LP) || \ 519 (std == DRX_STANDARD_NTSC) || \ 520 (std == DRX_STANDARD_FM)) 521 522 #define DRXJ_ISQAMSTD(std) ((std == DRX_STANDARD_ITU_A) || \ 523 (std == DRX_STANDARD_ITU_B) || \ 524 (std == DRX_STANDARD_ITU_C) || \ 525 (std == DRX_STANDARD_ITU_D)) 526 527 /*----------------------------------------------------------------------------- 528 GLOBAL VARIABLES 529 ----------------------------------------------------------------------------*/ 530 /* 531 * DRXJ DAP structures 532 */ 533 534 static int drxdap_fasi_read_block(struct i2c_device_addr *dev_addr, 535 u32 addr, 536 u16 datasize, 537 u8 *data, u32 flags); 538 539 540 static int drxj_dap_read_modify_write_reg16(struct i2c_device_addr *dev_addr, 541 u32 waddr, 542 u32 raddr, 543 u16 wdata, u16 *rdata); 544 545 static int drxj_dap_read_reg16(struct i2c_device_addr *dev_addr, 546 u32 addr, 547 u16 *data, u32 flags); 548 549 static int drxdap_fasi_read_reg32(struct i2c_device_addr *dev_addr, 550 u32 addr, 551 u32 *data, u32 flags); 552 553 static int drxdap_fasi_write_block(struct i2c_device_addr *dev_addr, 554 u32 addr, 555 u16 datasize, 556 u8 *data, u32 flags); 557 558 static int drxj_dap_write_reg16(struct i2c_device_addr *dev_addr, 559 u32 addr, 560 u16 data, u32 flags); 561 562 static int drxdap_fasi_write_reg32(struct i2c_device_addr *dev_addr, 563 u32 addr, 564 u32 data, u32 flags); 565 566 static struct drxj_data drxj_data_g = { 567 false, /* has_lna : true if LNA (aka PGA) present */ 568 false, /* has_oob : true if OOB supported */ 569 false, /* has_ntsc: true if NTSC supported */ 570 false, /* has_btsc: true if BTSC supported */ 571 false, /* has_smatx: true if SMA_TX pin is available */ 572 false, /* has_smarx: true if SMA_RX pin is available */ 573 false, /* has_gpio : true if GPIO pin is available */ 574 false, /* has_irqn : true if IRQN pin is available */ 575 0, /* mfx A1/A2/A... */ 576 577 /* tuner settings */ 578 false, /* tuner mirrors RF signal */ 579 /* standard/channel settings */ 580 DRX_STANDARD_UNKNOWN, /* current standard */ 581 DRX_CONSTELLATION_AUTO, /* constellation */ 582 0, /* frequency in KHz */ 583 DRX_BANDWIDTH_UNKNOWN, /* curr_bandwidth */ 584 DRX_MIRROR_NO, /* mirror */ 585 586 /* signal quality information: */ 587 /* default values taken from the QAM Programming guide */ 588 /* fec_bits_desired should not be less than 4000000 */ 589 4000000, /* fec_bits_desired */ 590 5, /* fec_vd_plen */ 591 4, /* qam_vd_prescale */ 592 0xFFFF, /* qamVDPeriod */ 593 204 * 8, /* fec_rs_plen annex A */ 594 1, /* fec_rs_prescale */ 595 FEC_RS_MEASUREMENT_PERIOD, /* fec_rs_period */ 596 true, /* reset_pkt_err_acc */ 597 0, /* pkt_err_acc_start */ 598 599 /* HI configuration */ 600 0, /* hi_cfg_timing_div */ 601 0, /* hi_cfg_bridge_delay */ 602 0, /* hi_cfg_wake_up_key */ 603 0, /* hi_cfg_ctrl */ 604 0, /* HICfgTimeout */ 605 /* UIO configuration */ 606 DRX_UIO_MODE_DISABLE, /* uio_sma_rx_mode */ 607 DRX_UIO_MODE_DISABLE, /* uio_sma_tx_mode */ 608 DRX_UIO_MODE_DISABLE, /* uioASELMode */ 609 DRX_UIO_MODE_DISABLE, /* uio_irqn_mode */ 610 /* FS setting */ 611 0UL, /* iqm_fs_rate_ofs */ 612 false, /* pos_image */ 613 /* RC setting */ 614 0UL, /* iqm_rc_rate_ofs */ 615 /* AUD information */ 616 /* false, * flagSetAUDdone */ 617 /* false, * detectedRDS */ 618 /* true, * flagASDRequest */ 619 /* false, * flagHDevClear */ 620 /* false, * flagHDevSet */ 621 /* (u16) 0xFFF, * rdsLastCount */ 622 623 /* ATV configuration */ 624 0UL, /* flags cfg changes */ 625 /* shadow of ATV_TOP_EQU0__A */ 626 {-5, 627 ATV_TOP_EQU0_EQU_C0_FM, 628 ATV_TOP_EQU0_EQU_C0_L, 629 ATV_TOP_EQU0_EQU_C0_LP, 630 ATV_TOP_EQU0_EQU_C0_BG, 631 ATV_TOP_EQU0_EQU_C0_DK, 632 ATV_TOP_EQU0_EQU_C0_I}, 633 /* shadow of ATV_TOP_EQU1__A */ 634 {-50, 635 ATV_TOP_EQU1_EQU_C1_FM, 636 ATV_TOP_EQU1_EQU_C1_L, 637 ATV_TOP_EQU1_EQU_C1_LP, 638 ATV_TOP_EQU1_EQU_C1_BG, 639 ATV_TOP_EQU1_EQU_C1_DK, 640 ATV_TOP_EQU1_EQU_C1_I}, 641 /* shadow of ATV_TOP_EQU2__A */ 642 {210, 643 ATV_TOP_EQU2_EQU_C2_FM, 644 ATV_TOP_EQU2_EQU_C2_L, 645 ATV_TOP_EQU2_EQU_C2_LP, 646 ATV_TOP_EQU2_EQU_C2_BG, 647 ATV_TOP_EQU2_EQU_C2_DK, 648 ATV_TOP_EQU2_EQU_C2_I}, 649 /* shadow of ATV_TOP_EQU3__A */ 650 {-160, 651 ATV_TOP_EQU3_EQU_C3_FM, 652 ATV_TOP_EQU3_EQU_C3_L, 653 ATV_TOP_EQU3_EQU_C3_LP, 654 ATV_TOP_EQU3_EQU_C3_BG, 655 ATV_TOP_EQU3_EQU_C3_DK, 656 ATV_TOP_EQU3_EQU_C3_I}, 657 false, /* flag: true=bypass */ 658 ATV_TOP_VID_PEAK__PRE, /* shadow of ATV_TOP_VID_PEAK__A */ 659 ATV_TOP_NOISE_TH__PRE, /* shadow of ATV_TOP_NOISE_TH__A */ 660 true, /* flag CVBS output enable */ 661 false, /* flag SIF output enable */ 662 DRXJ_SIF_ATTENUATION_0DB, /* current SIF att setting */ 663 { /* qam_rf_agc_cfg */ 664 DRX_STANDARD_ITU_B, /* standard */ 665 DRX_AGC_CTRL_AUTO, /* ctrl_mode */ 666 0, /* output_level */ 667 0, /* min_output_level */ 668 0xFFFF, /* max_output_level */ 669 0x0000, /* speed */ 670 0x0000, /* top */ 671 0x0000 /* c.o.c. */ 672 }, 673 { /* qam_if_agc_cfg */ 674 DRX_STANDARD_ITU_B, /* standard */ 675 DRX_AGC_CTRL_AUTO, /* ctrl_mode */ 676 0, /* output_level */ 677 0, /* min_output_level */ 678 0xFFFF, /* max_output_level */ 679 0x0000, /* speed */ 680 0x0000, /* top (don't care) */ 681 0x0000 /* c.o.c. (don't care) */ 682 }, 683 { /* vsb_rf_agc_cfg */ 684 DRX_STANDARD_8VSB, /* standard */ 685 DRX_AGC_CTRL_AUTO, /* ctrl_mode */ 686 0, /* output_level */ 687 0, /* min_output_level */ 688 0xFFFF, /* max_output_level */ 689 0x0000, /* speed */ 690 0x0000, /* top (don't care) */ 691 0x0000 /* c.o.c. (don't care) */ 692 }, 693 { /* vsb_if_agc_cfg */ 694 DRX_STANDARD_8VSB, /* standard */ 695 DRX_AGC_CTRL_AUTO, /* ctrl_mode */ 696 0, /* output_level */ 697 0, /* min_output_level */ 698 0xFFFF, /* max_output_level */ 699 0x0000, /* speed */ 700 0x0000, /* top (don't care) */ 701 0x0000 /* c.o.c. (don't care) */ 702 }, 703 0, /* qam_pga_cfg */ 704 0, /* vsb_pga_cfg */ 705 { /* qam_pre_saw_cfg */ 706 DRX_STANDARD_ITU_B, /* standard */ 707 0, /* reference */ 708 false /* use_pre_saw */ 709 }, 710 { /* vsb_pre_saw_cfg */ 711 DRX_STANDARD_8VSB, /* standard */ 712 0, /* reference */ 713 false /* use_pre_saw */ 714 }, 715 716 /* Version information */ 717 #ifndef _CH_ 718 { 719 "01234567890", /* human readable version microcode */ 720 "01234567890" /* human readable version device specific code */ 721 }, 722 { 723 { /* struct drx_version for microcode */ 724 DRX_MODULE_UNKNOWN, 725 (char *)(NULL), 726 0, 727 0, 728 0, 729 (char *)(NULL) 730 }, 731 { /* struct drx_version for device specific code */ 732 DRX_MODULE_UNKNOWN, 733 (char *)(NULL), 734 0, 735 0, 736 0, 737 (char *)(NULL) 738 } 739 }, 740 { 741 { /* struct drx_version_list for microcode */ 742 (struct drx_version *) (NULL), 743 (struct drx_version_list *) (NULL) 744 }, 745 { /* struct drx_version_list for device specific code */ 746 (struct drx_version *) (NULL), 747 (struct drx_version_list *) (NULL) 748 } 749 }, 750 #endif 751 false, /* smart_ant_inverted */ 752 /* Tracking filter setting for OOB */ 753 { 754 12000, 755 9300, 756 6600, 757 5280, 758 3700, 759 3000, 760 2000, 761 0}, 762 false, /* oob_power_on */ 763 0, /* mpeg_ts_static_bitrate */ 764 false, /* disable_te_ihandling */ 765 false, /* bit_reverse_mpeg_outout */ 766 DRXJ_MPEGOUTPUT_CLOCK_RATE_AUTO, /* mpeg_output_clock_rate */ 767 DRXJ_MPEG_START_WIDTH_1CLKCYC, /* mpeg_start_width */ 768 769 /* Pre SAW & Agc configuration for ATV */ 770 { 771 DRX_STANDARD_NTSC, /* standard */ 772 7, /* reference */ 773 true /* use_pre_saw */ 774 }, 775 { /* ATV RF-AGC */ 776 DRX_STANDARD_NTSC, /* standard */ 777 DRX_AGC_CTRL_AUTO, /* ctrl_mode */ 778 0, /* output_level */ 779 0, /* min_output_level (d.c.) */ 780 0, /* max_output_level (d.c.) */ 781 3, /* speed */ 782 9500, /* top */ 783 4000 /* cut-off current */ 784 }, 785 { /* ATV IF-AGC */ 786 DRX_STANDARD_NTSC, /* standard */ 787 DRX_AGC_CTRL_AUTO, /* ctrl_mode */ 788 0, /* output_level */ 789 0, /* min_output_level (d.c.) */ 790 0, /* max_output_level (d.c.) */ 791 3, /* speed */ 792 2400, /* top */ 793 0 /* c.o.c. (d.c.) */ 794 }, 795 140, /* ATV PGA config */ 796 0, /* curr_symbol_rate */ 797 798 false, /* pdr_safe_mode */ 799 SIO_PDR_GPIO_CFG__PRE, /* pdr_safe_restore_val_gpio */ 800 SIO_PDR_VSYNC_CFG__PRE, /* pdr_safe_restore_val_v_sync */ 801 SIO_PDR_SMA_RX_CFG__PRE, /* pdr_safe_restore_val_sma_rx */ 802 SIO_PDR_SMA_TX_CFG__PRE, /* pdr_safe_restore_val_sma_tx */ 803 804 4, /* oob_pre_saw */ 805 DRXJ_OOB_LO_POW_MINUS10DB, /* oob_lo_pow */ 806 { 807 false /* aud_data, only first member */ 808 }, 809 }; 810 811 /* 812 * \var drxj_default_addr_g 813 * \brief Default I2C address and device identifier. 814 */ 815 static struct i2c_device_addr drxj_default_addr_g = { 816 DRXJ_DEF_I2C_ADDR, /* i2c address */ 817 DRXJ_DEF_DEMOD_DEV_ID /* device id */ 818 }; 819 820 /* 821 * \var drxj_default_comm_attr_g 822 * \brief Default common attributes of a drxj demodulator instance. 823 */ 824 static struct drx_common_attr drxj_default_comm_attr_g = { 825 NULL, /* ucode file */ 826 true, /* ucode verify switch */ 827 {0}, /* version record */ 828 829 44000, /* IF in kHz in case no tuner instance is used */ 830 (151875 - 0), /* system clock frequency in kHz */ 831 0, /* oscillator frequency kHz */ 832 0, /* oscillator deviation in ppm, signed */ 833 false, /* If true mirror frequency spectrum */ 834 { 835 /* MPEG output configuration */ 836 true, /* If true, enable MPEG output */ 837 false, /* If true, insert RS byte */ 838 false, /* If true, parallel out otherwise serial */ 839 false, /* If true, invert DATA signals */ 840 false, /* If true, invert ERR signal */ 841 false, /* If true, invert STR signals */ 842 false, /* If true, invert VAL signals */ 843 false, /* If true, invert CLK signals */ 844 true, /* If true, static MPEG clockrate will 845 be used, otherwise clockrate will 846 adapt to the bitrate of the TS */ 847 19392658UL, /* Maximum bitrate in b/s in case 848 static clockrate is selected */ 849 DRX_MPEG_STR_WIDTH_1 /* MPEG Start width in clock cycles */ 850 }, 851 /* Initilisations below can be omitted, they require no user input and 852 are initially 0, NULL or false. The compiler will initialize them to these 853 values when omitted. */ 854 false, /* is_opened */ 855 856 /* SCAN */ 857 NULL, /* no scan params yet */ 858 0, /* current scan index */ 859 0, /* next scan frequency */ 860 false, /* scan ready flag */ 861 0, /* max channels to scan */ 862 0, /* nr of channels scanned */ 863 NULL, /* default scan function */ 864 NULL, /* default context pointer */ 865 0, /* millisec to wait for demod lock */ 866 DRXJ_DEMOD_LOCK, /* desired lock */ 867 false, 868 869 /* Power management */ 870 DRX_POWER_UP, 871 872 /* Tuner */ 873 1, /* nr of I2C port to which tuner is */ 874 0L, /* minimum RF input frequency, in kHz */ 875 0L, /* maximum RF input frequency, in kHz */ 876 false, /* Rf Agc Polarity */ 877 false, /* If Agc Polarity */ 878 false, /* tuner slow mode */ 879 880 { /* current channel (all 0) */ 881 0UL /* channel.frequency */ 882 }, 883 DRX_STANDARD_UNKNOWN, /* current standard */ 884 DRX_STANDARD_UNKNOWN, /* previous standard */ 885 DRX_STANDARD_UNKNOWN, /* di_cache_standard */ 886 false, /* use_bootloader */ 887 0UL, /* capabilities */ 888 0 /* mfx */ 889 }; 890 891 /* 892 * \var drxj_default_demod_g 893 * \brief Default drxj demodulator instance. 894 */ 895 static struct drx_demod_instance drxj_default_demod_g = { 896 &drxj_default_addr_g, /* i2c address & device id */ 897 &drxj_default_comm_attr_g, /* demod common attributes */ 898 &drxj_data_g /* demod device specific attributes */ 899 }; 900 901 /* 902 * \brief Default audio data structure for DRK demodulator instance. 903 * 904 * This structure is DRXK specific. 905 * 906 */ 907 static struct drx_aud_data drxj_default_aud_data_g = { 908 false, /* audio_is_active */ 909 DRX_AUD_STANDARD_AUTO, /* audio_standard */ 910 911 /* i2sdata */ 912 { 913 false, /* output_enable */ 914 48000, /* frequency */ 915 DRX_I2S_MODE_MASTER, /* mode */ 916 DRX_I2S_WORDLENGTH_32, /* word_length */ 917 DRX_I2S_POLARITY_RIGHT, /* polarity */ 918 DRX_I2S_FORMAT_WS_WITH_DATA /* format */ 919 }, 920 /* volume */ 921 { 922 true, /* mute; */ 923 0, /* volume */ 924 DRX_AUD_AVC_OFF, /* avc_mode */ 925 0, /* avc_ref_level */ 926 DRX_AUD_AVC_MAX_GAIN_12DB, /* avc_max_gain */ 927 DRX_AUD_AVC_MAX_ATTEN_24DB, /* avc_max_atten */ 928 0, /* strength_left */ 929 0 /* strength_right */ 930 }, 931 DRX_AUD_AUTO_SOUND_SELECT_ON_CHANGE_ON, /* auto_sound */ 932 /* ass_thresholds */ 933 { 934 440, /* A2 */ 935 12, /* BTSC */ 936 700, /* NICAM */ 937 }, 938 /* carrier */ 939 { 940 /* a */ 941 { 942 42, /* thres */ 943 DRX_NO_CARRIER_NOISE, /* opt */ 944 0, /* shift */ 945 0 /* dco */ 946 }, 947 /* b */ 948 { 949 42, /* thres */ 950 DRX_NO_CARRIER_MUTE, /* opt */ 951 0, /* shift */ 952 0 /* dco */ 953 }, 954 955 }, 956 /* mixer */ 957 { 958 DRX_AUD_SRC_STEREO_OR_A, /* source_i2s */ 959 DRX_AUD_I2S_MATRIX_STEREO, /* matrix_i2s */ 960 DRX_AUD_FM_MATRIX_SOUND_A /* matrix_fm */ 961 }, 962 DRX_AUD_DEVIATION_NORMAL, /* deviation */ 963 DRX_AUD_AVSYNC_OFF, /* av_sync */ 964 965 /* prescale */ 966 { 967 DRX_AUD_MAX_FM_DEVIATION, /* fm_deviation */ 968 DRX_AUD_MAX_NICAM_PRESCALE /* nicam_gain */ 969 }, 970 DRX_AUD_FM_DEEMPH_75US, /* deemph */ 971 DRX_BTSC_STEREO, /* btsc_detect */ 972 0, /* rds_data_counter */ 973 false /* rds_data_present */ 974 }; 975 976 /*----------------------------------------------------------------------------- 977 STRUCTURES 978 ----------------------------------------------------------------------------*/ 979 struct drxjeq_stat { 980 u16 eq_mse; 981 u8 eq_mode; 982 u8 eq_ctrl; 983 u8 eq_stat; 984 }; 985 986 /* HI command */ 987 struct drxj_hi_cmd { 988 u16 cmd; 989 u16 param1; 990 u16 param2; 991 u16 param3; 992 u16 param4; 993 u16 param5; 994 u16 param6; 995 }; 996 997 /*============================================================================*/ 998 /*=== MICROCODE RELATED STRUCTURES ===========================================*/ 999 /*============================================================================*/ 1000 1001 /* 1002 * struct drxu_code_block_hdr - Structure of the microcode block headers 1003 * 1004 * @addr: Destination address of the data in this block 1005 * @size: Size of the block data following this header counted in 1006 * 16 bits words 1007 * @CRC: CRC value of the data block, only valid if CRC flag is 1008 * set. 1009 */ 1010 struct drxu_code_block_hdr { 1011 u32 addr; 1012 u16 size; 1013 u16 flags; 1014 u16 CRC; 1015 }; 1016 1017 /*----------------------------------------------------------------------------- 1018 FUNCTIONS 1019 ----------------------------------------------------------------------------*/ 1020 /* Some prototypes */ 1021 static int 1022 hi_command(struct i2c_device_addr *dev_addr, 1023 const struct drxj_hi_cmd *cmd, u16 *result); 1024 1025 static int 1026 ctrl_lock_status(struct drx_demod_instance *demod, enum drx_lock_status *lock_stat); 1027 1028 static int 1029 ctrl_power_mode(struct drx_demod_instance *demod, enum drx_power_mode *mode); 1030 1031 static int power_down_aud(struct drx_demod_instance *demod); 1032 1033 static int 1034 ctrl_set_cfg_pre_saw(struct drx_demod_instance *demod, struct drxj_cfg_pre_saw *pre_saw); 1035 1036 static int 1037 ctrl_set_cfg_afe_gain(struct drx_demod_instance *demod, struct drxj_cfg_afe_gain *afe_gain); 1038 1039 /*============================================================================*/ 1040 /*============================================================================*/ 1041 /*== HELPER FUNCTIONS ==*/ 1042 /*============================================================================*/ 1043 /*============================================================================*/ 1044 1045 1046 /*============================================================================*/ 1047 1048 /* 1049 * \fn u32 frac28(u32 N, u32 D) 1050 * \brief Compute: (1<<28)*N/D 1051 * \param N 32 bits 1052 * \param D 32 bits 1053 * \return (1<<28)*N/D 1054 * This function is used to avoid floating-point calculations as they may 1055 * not be present on the target platform. 1056 1057 * frac28 performs an unsigned 28/28 bits division to 32-bit fixed point 1058 * fraction used for setting the Frequency Shifter registers. 1059 * N and D can hold numbers up to width: 28-bits. 1060 * The 4 bits integer part and the 28 bits fractional part are calculated. 1061 1062 * Usage condition: ((1<<28)*n)/d < ((1<<32)-1) => (n/d) < 15.999 1063 1064 * N: 0...(1<<28)-1 = 268435454 1065 * D: 0...(1<<28)-1 1066 * Q: 0...(1<<32)-1 1067 */ 1068 static u32 frac28(u32 N, u32 D) 1069 { 1070 int i = 0; 1071 u32 Q1 = 0; 1072 u32 R0 = 0; 1073 1074 R0 = (N % D) << 4; /* 32-28 == 4 shifts possible at max */ 1075 Q1 = N / D; /* integer part, only the 4 least significant bits 1076 will be visible in the result */ 1077 1078 /* division using radix 16, 7 nibbles in the result */ 1079 for (i = 0; i < 7; i++) { 1080 Q1 = (Q1 << 4) | R0 / D; 1081 R0 = (R0 % D) << 4; 1082 } 1083 /* rounding */ 1084 if ((R0 >> 3) >= D) 1085 Q1++; 1086 1087 return Q1; 1088 } 1089 1090 /* 1091 * \fn u32 log1_times100( u32 x) 1092 * \brief Compute: 100*log10(x) 1093 * \param x 32 bits 1094 * \return 100*log10(x) 1095 * 1096 * 100*log10(x) 1097 * = 100*(log2(x)/log2(10))) 1098 * = (100*(2^15)*log2(x))/((2^15)*log2(10)) 1099 * = ((200*(2^15)*log2(x))/((2^15)*log2(10)))/2 1100 * = ((200*(2^15)*(log2(x/y)+log2(y)))/((2^15)*log2(10)))/2 1101 * = ((200*(2^15)*log2(x/y))+(200*(2^15)*log2(y)))/((2^15)*log2(10)))/2 1102 * 1103 * where y = 2^k and 1<= (x/y) < 2 1104 */ 1105 1106 static u32 log1_times100(u32 x) 1107 { 1108 static const u8 scale = 15; 1109 static const u8 index_width = 5; 1110 /* 1111 log2lut[n] = (1<<scale) * 200 * log2( 1.0 + ( (1.0/(1<<INDEXWIDTH)) * n )) 1112 0 <= n < ((1<<INDEXWIDTH)+1) 1113 */ 1114 1115 static const u32 log2lut[] = { 1116 0, /* 0.000000 */ 1117 290941, /* 290941.300628 */ 1118 573196, /* 573196.476418 */ 1119 847269, /* 847269.179851 */ 1120 1113620, /* 1113620.489452 */ 1121 1372674, /* 1372673.576986 */ 1122 1624818, /* 1624817.752104 */ 1123 1870412, /* 1870411.981536 */ 1124 2109788, /* 2109787.962654 */ 1125 2343253, /* 2343252.817465 */ 1126 2571091, /* 2571091.461923 */ 1127 2793569, /* 2793568.696416 */ 1128 3010931, /* 3010931.055901 */ 1129 3223408, /* 3223408.452106 */ 1130 3431216, /* 3431215.635215 */ 1131 3634553, /* 3634553.498355 */ 1132 3833610, /* 3833610.244726 */ 1133 4028562, /* 4028562.434393 */ 1134 4219576, /* 4219575.925308 */ 1135 4406807, /* 4406806.721144 */ 1136 4590402, /* 4590401.736809 */ 1137 4770499, /* 4770499.491025 */ 1138 4947231, /* 4947230.734179 */ 1139 5120719, /* 5120719.018555 */ 1140 5291081, /* 5291081.217197 */ 1141 5458428, /* 5458427.996830 */ 1142 5622864, /* 5622864.249668 */ 1143 5784489, /* 5784489.488298 */ 1144 5943398, /* 5943398.207380 */ 1145 6099680, /* 6099680.215452 */ 1146 6253421, /* 6253420.939751 */ 1147 6404702, /* 6404701.706649 */ 1148 6553600, /* 6553600.000000 */ 1149 }; 1150 1151 u8 i = 0; 1152 u32 y = 0; 1153 u32 d = 0; 1154 u32 k = 0; 1155 u32 r = 0; 1156 1157 if (x == 0) 1158 return 0; 1159 1160 /* Scale x (normalize) */ 1161 /* computing y in log(x/y) = log(x) - log(y) */ 1162 if ((x & (((u32) (-1)) << (scale + 1))) == 0) { 1163 for (k = scale; k > 0; k--) { 1164 if (x & (((u32) 1) << scale)) 1165 break; 1166 x <<= 1; 1167 } 1168 } else { 1169 for (k = scale; k < 31; k++) { 1170 if ((x & (((u32) (-1)) << (scale + 1))) == 0) 1171 break; 1172 x >>= 1; 1173 } 1174 } 1175 /* 1176 Now x has binary point between bit[scale] and bit[scale-1] 1177 and 1.0 <= x < 2.0 */ 1178 1179 /* correction for division: log(x) = log(x/y)+log(y) */ 1180 y = k * ((((u32) 1) << scale) * 200); 1181 1182 /* remove integer part */ 1183 x &= ((((u32) 1) << scale) - 1); 1184 /* get index */ 1185 i = (u8) (x >> (scale - index_width)); 1186 /* compute delta (x-a) */ 1187 d = x & ((((u32) 1) << (scale - index_width)) - 1); 1188 /* compute log, multiplication ( d* (.. )) must be within range ! */ 1189 y += log2lut[i] + 1190 ((d * (log2lut[i + 1] - log2lut[i])) >> (scale - index_width)); 1191 /* Conver to log10() */ 1192 y /= 108853; /* (log2(10) << scale) */ 1193 r = (y >> 1); 1194 /* rounding */ 1195 if (y & ((u32)1)) 1196 r++; 1197 1198 return r; 1199 1200 } 1201 1202 /* 1203 * \fn u32 frac_times1e6( u16 N, u32 D) 1204 * \brief Compute: (N/D) * 1000000. 1205 * \param N nominator 16-bits. 1206 * \param D denominator 32-bits. 1207 * \return u32 1208 * \retval ((N/D) * 1000000), 32 bits 1209 * 1210 * No check on D=0! 1211 */ 1212 static u32 frac_times1e6(u32 N, u32 D) 1213 { 1214 u32 remainder = 0; 1215 u32 frac = 0; 1216 1217 /* 1218 frac = (N * 1000000) / D 1219 To let it fit in a 32 bits computation: 1220 frac = (N * (1000000 >> 4)) / (D >> 4) 1221 This would result in a problem in case D < 16 (div by 0). 1222 So we do it more elaborate as shown below. 1223 */ 1224 frac = (((u32) N) * (1000000 >> 4)) / D; 1225 frac <<= 4; 1226 remainder = (((u32) N) * (1000000 >> 4)) % D; 1227 remainder <<= 4; 1228 frac += remainder / D; 1229 remainder = remainder % D; 1230 if ((remainder * 2) > D) 1231 frac++; 1232 1233 return frac; 1234 } 1235 1236 /*============================================================================*/ 1237 1238 1239 /* 1240 * \brief Values for NICAM prescaler gain. Computed from dB to integer 1241 * and rounded. For calc used formula: 16*10^(prescaleGain[dB]/20). 1242 * 1243 */ 1244 #if 0 1245 /* Currently, unused as we lack support for analog TV */ 1246 static const u16 nicam_presc_table_val[43] = { 1247 1, 1, 1, 1, 2, 2, 2, 2, 3, 3, 3, 4, 4, 1248 5, 5, 6, 6, 7, 8, 9, 10, 11, 13, 14, 16, 1249 18, 20, 23, 25, 28, 32, 36, 40, 45, 1250 51, 57, 64, 71, 80, 90, 101, 113, 127 1251 }; 1252 #endif 1253 1254 /*============================================================================*/ 1255 /*== END HELPER FUNCTIONS ==*/ 1256 /*============================================================================*/ 1257 1258 /*============================================================================*/ 1259 /*============================================================================*/ 1260 /*== DRXJ DAP FUNCTIONS ==*/ 1261 /*============================================================================*/ 1262 /*============================================================================*/ 1263 1264 /* 1265 This layer takes care of some device specific register access protocols: 1266 -conversion to short address format 1267 -access to audio block 1268 This layer is placed between the drx_dap_fasi and the rest of the drxj 1269 specific implementation. This layer can use address map knowledge whereas 1270 dap_fasi may not use memory map knowledge. 1271 1272 * For audio currently only 16 bits read and write register access is 1273 supported. More is not needed. RMW and 32 or 8 bit access on audio 1274 registers will have undefined behaviour. Flags (RMW, CRC reset, broadcast 1275 single/multi master) will be ignored. 1276 1277 TODO: check ignoring single/multimaster is ok for AUD access ? 1278 */ 1279 1280 #define DRXJ_ISAUDWRITE(addr) (((((addr)>>16)&1) == 1) ? true : false) 1281 #define DRXJ_DAP_AUDTRIF_TIMEOUT 80 /* millisec */ 1282 /*============================================================================*/ 1283 1284 /* 1285 * \fn bool is_handled_by_aud_tr_if( u32 addr ) 1286 * \brief Check if this address is handled by the audio token ring interface. 1287 * \param addr 1288 * \return bool 1289 * \retval true Yes, handled by audio token ring interface 1290 * \retval false No, not handled by audio token ring interface 1291 * 1292 */ 1293 static 1294 bool is_handled_by_aud_tr_if(u32 addr) 1295 { 1296 bool retval = false; 1297 1298 if ((DRXDAP_FASI_ADDR2BLOCK(addr) == 4) && 1299 (DRXDAP_FASI_ADDR2BANK(addr) > 1) && 1300 (DRXDAP_FASI_ADDR2BANK(addr) < 6)) { 1301 retval = true; 1302 } 1303 1304 return retval; 1305 } 1306 1307 /*============================================================================*/ 1308 1309 int drxbsp_i2c_write_read(struct i2c_device_addr *w_dev_addr, 1310 u16 w_count, 1311 u8 *wData, 1312 struct i2c_device_addr *r_dev_addr, 1313 u16 r_count, u8 *r_data) 1314 { 1315 struct drx39xxj_state *state; 1316 struct i2c_msg msg[2]; 1317 unsigned int num_msgs; 1318 1319 if (w_dev_addr == NULL) { 1320 /* Read only */ 1321 state = r_dev_addr->user_data; 1322 msg[0].addr = r_dev_addr->i2c_addr >> 1; 1323 msg[0].flags = I2C_M_RD; 1324 msg[0].buf = r_data; 1325 msg[0].len = r_count; 1326 num_msgs = 1; 1327 } else if (r_dev_addr == NULL) { 1328 /* Write only */ 1329 state = w_dev_addr->user_data; 1330 msg[0].addr = w_dev_addr->i2c_addr >> 1; 1331 msg[0].flags = 0; 1332 msg[0].buf = wData; 1333 msg[0].len = w_count; 1334 num_msgs = 1; 1335 } else { 1336 /* Both write and read */ 1337 state = w_dev_addr->user_data; 1338 msg[0].addr = w_dev_addr->i2c_addr >> 1; 1339 msg[0].flags = 0; 1340 msg[0].buf = wData; 1341 msg[0].len = w_count; 1342 msg[1].addr = r_dev_addr->i2c_addr >> 1; 1343 msg[1].flags = I2C_M_RD; 1344 msg[1].buf = r_data; 1345 msg[1].len = r_count; 1346 num_msgs = 2; 1347 } 1348 1349 if (state->i2c == NULL) { 1350 pr_err("i2c was zero, aborting\n"); 1351 return 0; 1352 } 1353 if (i2c_transfer(state->i2c, msg, num_msgs) != num_msgs) { 1354 pr_warn("drx3933: I2C write/read failed\n"); 1355 return -EREMOTEIO; 1356 } 1357 1358 #ifdef DJH_DEBUG 1359 if (w_dev_addr == NULL || r_dev_addr == NULL) 1360 return 0; 1361 1362 state = w_dev_addr->user_data; 1363 1364 if (state->i2c == NULL) 1365 return 0; 1366 1367 msg[0].addr = w_dev_addr->i2c_addr; 1368 msg[0].flags = 0; 1369 msg[0].buf = wData; 1370 msg[0].len = w_count; 1371 msg[1].addr = r_dev_addr->i2c_addr; 1372 msg[1].flags = I2C_M_RD; 1373 msg[1].buf = r_data; 1374 msg[1].len = r_count; 1375 num_msgs = 2; 1376 1377 pr_debug("drx3933 i2c operation addr=%x i2c=%p, wc=%x rc=%x\n", 1378 w_dev_addr->i2c_addr, state->i2c, w_count, r_count); 1379 1380 if (i2c_transfer(state->i2c, msg, 2) != 2) { 1381 pr_warn("drx3933: I2C write/read failed\n"); 1382 return -EREMOTEIO; 1383 } 1384 #endif 1385 return 0; 1386 } 1387 1388 /*============================================================================*/ 1389 1390 /***************************** 1391 * 1392 * int drxdap_fasi_read_block ( 1393 * struct i2c_device_addr *dev_addr, -- address of I2C device 1394 * u32 addr, -- address of chip register/memory 1395 * u16 datasize, -- number of bytes to read 1396 * u8 *data, -- data to receive 1397 * u32 flags) -- special device flags 1398 * 1399 * Read block data from chip address. Because the chip is word oriented, 1400 * the number of bytes to read must be even. 1401 * 1402 * Make sure that the buffer to receive the data is large enough. 1403 * 1404 * Although this function expects an even number of bytes, it is still byte 1405 * oriented, and the data read back is NOT translated to the endianness of 1406 * the target platform. 1407 * 1408 * Output: 1409 * - 0 if reading was successful 1410 * in that case: data read is in *data. 1411 * - -EIO if anything went wrong 1412 * 1413 ******************************/ 1414 1415 static int drxdap_fasi_read_block(struct i2c_device_addr *dev_addr, 1416 u32 addr, 1417 u16 datasize, 1418 u8 *data, u32 flags) 1419 { 1420 u8 buf[4]; 1421 u16 bufx; 1422 int rc; 1423 u16 overhead_size = 0; 1424 1425 /* Check parameters ******************************************************* */ 1426 if (dev_addr == NULL) 1427 return -EINVAL; 1428 1429 overhead_size = (IS_I2C_10BIT(dev_addr->i2c_addr) ? 2 : 1) + 1430 (DRXDAP_FASI_LONG_FORMAT(addr) ? 4 : 2); 1431 1432 if ((DRXDAP_FASI_OFFSET_TOO_LARGE(addr)) || 1433 ((!(DRXDAPFASI_LONG_ADDR_ALLOWED)) && 1434 DRXDAP_FASI_LONG_FORMAT(addr)) || 1435 (overhead_size > (DRXDAP_MAX_WCHUNKSIZE)) || 1436 ((datasize != 0) && (data == NULL)) || ((datasize & 1) == 1)) { 1437 return -EINVAL; 1438 } 1439 1440 /* ReadModifyWrite & mode flag bits are not allowed */ 1441 flags &= (~DRXDAP_FASI_RMW & ~DRXDAP_FASI_MODEFLAGS); 1442 #if DRXDAP_SINGLE_MASTER 1443 flags |= DRXDAP_FASI_SINGLE_MASTER; 1444 #endif 1445 1446 /* Read block from I2C **************************************************** */ 1447 do { 1448 u16 todo = min(datasize, DRXDAP_MAX_RCHUNKSIZE); 1449 1450 bufx = 0; 1451 1452 addr &= ~DRXDAP_FASI_FLAGS; 1453 addr |= flags; 1454 1455 #if ((DRXDAPFASI_LONG_ADDR_ALLOWED == 1) && (DRXDAPFASI_SHORT_ADDR_ALLOWED == 1)) 1456 /* short format address preferred but long format otherwise */ 1457 if (DRXDAP_FASI_LONG_FORMAT(addr)) { 1458 #endif 1459 #if (DRXDAPFASI_LONG_ADDR_ALLOWED == 1) 1460 buf[bufx++] = (u8) (((addr << 1) & 0xFF) | 0x01); 1461 buf[bufx++] = (u8) ((addr >> 16) & 0xFF); 1462 buf[bufx++] = (u8) ((addr >> 24) & 0xFF); 1463 buf[bufx++] = (u8) ((addr >> 7) & 0xFF); 1464 #endif 1465 #if ((DRXDAPFASI_LONG_ADDR_ALLOWED == 1) && (DRXDAPFASI_SHORT_ADDR_ALLOWED == 1)) 1466 } else { 1467 #endif 1468 #if (DRXDAPFASI_SHORT_ADDR_ALLOWED == 1) 1469 buf[bufx++] = (u8) ((addr << 1) & 0xFF); 1470 buf[bufx++] = 1471 (u8) (((addr >> 16) & 0x0F) | 1472 ((addr >> 18) & 0xF0)); 1473 #endif 1474 #if ((DRXDAPFASI_LONG_ADDR_ALLOWED == 1) && (DRXDAPFASI_SHORT_ADDR_ALLOWED == 1)) 1475 } 1476 #endif 1477 1478 #if DRXDAP_SINGLE_MASTER 1479 /* 1480 * In single master mode, split the read and write actions. 1481 * No special action is needed for write chunks here. 1482 */ 1483 rc = drxbsp_i2c_write_read(dev_addr, bufx, buf, 1484 NULL, 0, NULL); 1485 if (rc == 0) 1486 rc = drxbsp_i2c_write_read(NULL, 0, NULL, dev_addr, todo, data); 1487 #else 1488 /* In multi master mode, do everything in one RW action */ 1489 rc = drxbsp_i2c_write_read(dev_addr, bufx, buf, dev_addr, todo, 1490 data); 1491 #endif 1492 data += todo; 1493 addr += (todo >> 1); 1494 datasize -= todo; 1495 } while (datasize && rc == 0); 1496 1497 return rc; 1498 } 1499 1500 1501 /***************************** 1502 * 1503 * int drxdap_fasi_read_reg16 ( 1504 * struct i2c_device_addr *dev_addr, -- address of I2C device 1505 * u32 addr, -- address of chip register/memory 1506 * u16 *data, -- data to receive 1507 * u32 flags) -- special device flags 1508 * 1509 * Read one 16-bit register or memory location. The data received back is 1510 * converted back to the target platform's endianness. 1511 * 1512 * Output: 1513 * - 0 if reading was successful 1514 * in that case: read data is at *data 1515 * - -EIO if anything went wrong 1516 * 1517 ******************************/ 1518 1519 static int drxdap_fasi_read_reg16(struct i2c_device_addr *dev_addr, 1520 u32 addr, 1521 u16 *data, u32 flags) 1522 { 1523 u8 buf[sizeof(*data)]; 1524 int rc; 1525 1526 if (!data) 1527 return -EINVAL; 1528 1529 rc = drxdap_fasi_read_block(dev_addr, addr, sizeof(*data), buf, flags); 1530 *data = buf[0] + (((u16) buf[1]) << 8); 1531 return rc; 1532 } 1533 1534 /***************************** 1535 * 1536 * int drxdap_fasi_read_reg32 ( 1537 * struct i2c_device_addr *dev_addr, -- address of I2C device 1538 * u32 addr, -- address of chip register/memory 1539 * u32 *data, -- data to receive 1540 * u32 flags) -- special device flags 1541 * 1542 * Read one 32-bit register or memory location. The data received back is 1543 * converted back to the target platform's endianness. 1544 * 1545 * Output: 1546 * - 0 if reading was successful 1547 * in that case: read data is at *data 1548 * - -EIO if anything went wrong 1549 * 1550 ******************************/ 1551 1552 static int drxdap_fasi_read_reg32(struct i2c_device_addr *dev_addr, 1553 u32 addr, 1554 u32 *data, u32 flags) 1555 { 1556 u8 buf[sizeof(*data)]; 1557 int rc; 1558 1559 if (!data) 1560 return -EINVAL; 1561 1562 rc = drxdap_fasi_read_block(dev_addr, addr, sizeof(*data), buf, flags); 1563 *data = (((u32) buf[0]) << 0) + 1564 (((u32) buf[1]) << 8) + 1565 (((u32) buf[2]) << 16) + (((u32) buf[3]) << 24); 1566 return rc; 1567 } 1568 1569 /***************************** 1570 * 1571 * int drxdap_fasi_write_block ( 1572 * struct i2c_device_addr *dev_addr, -- address of I2C device 1573 * u32 addr, -- address of chip register/memory 1574 * u16 datasize, -- number of bytes to read 1575 * u8 *data, -- data to receive 1576 * u32 flags) -- special device flags 1577 * 1578 * Write block data to chip address. Because the chip is word oriented, 1579 * the number of bytes to write must be even. 1580 * 1581 * Although this function expects an even number of bytes, it is still byte 1582 * oriented, and the data being written is NOT translated from the endianness of 1583 * the target platform. 1584 * 1585 * Output: 1586 * - 0 if writing was successful 1587 * - -EIO if anything went wrong 1588 * 1589 ******************************/ 1590 1591 static int drxdap_fasi_write_block(struct i2c_device_addr *dev_addr, 1592 u32 addr, 1593 u16 datasize, 1594 u8 *data, u32 flags) 1595 { 1596 u8 buf[DRXDAP_MAX_WCHUNKSIZE]; 1597 int st = -EIO; 1598 int first_err = 0; 1599 u16 overhead_size = 0; 1600 u16 block_size = 0; 1601 1602 /* Check parameters ******************************************************* */ 1603 if (dev_addr == NULL) 1604 return -EINVAL; 1605 1606 overhead_size = (IS_I2C_10BIT(dev_addr->i2c_addr) ? 2 : 1) + 1607 (DRXDAP_FASI_LONG_FORMAT(addr) ? 4 : 2); 1608 1609 if ((DRXDAP_FASI_OFFSET_TOO_LARGE(addr)) || 1610 ((!(DRXDAPFASI_LONG_ADDR_ALLOWED)) && 1611 DRXDAP_FASI_LONG_FORMAT(addr)) || 1612 (overhead_size > (DRXDAP_MAX_WCHUNKSIZE)) || 1613 ((datasize != 0) && (data == NULL)) || ((datasize & 1) == 1)) 1614 return -EINVAL; 1615 1616 flags &= DRXDAP_FASI_FLAGS; 1617 flags &= ~DRXDAP_FASI_MODEFLAGS; 1618 #if DRXDAP_SINGLE_MASTER 1619 flags |= DRXDAP_FASI_SINGLE_MASTER; 1620 #endif 1621 1622 /* Write block to I2C ***************************************************** */ 1623 block_size = ((DRXDAP_MAX_WCHUNKSIZE) - overhead_size) & ~1; 1624 do { 1625 u16 todo = 0; 1626 u16 bufx = 0; 1627 1628 /* Buffer device address */ 1629 addr &= ~DRXDAP_FASI_FLAGS; 1630 addr |= flags; 1631 #if (((DRXDAPFASI_LONG_ADDR_ALLOWED) == 1) && ((DRXDAPFASI_SHORT_ADDR_ALLOWED) == 1)) 1632 /* short format address preferred but long format otherwise */ 1633 if (DRXDAP_FASI_LONG_FORMAT(addr)) { 1634 #endif 1635 #if ((DRXDAPFASI_LONG_ADDR_ALLOWED) == 1) 1636 buf[bufx++] = (u8) (((addr << 1) & 0xFF) | 0x01); 1637 buf[bufx++] = (u8) ((addr >> 16) & 0xFF); 1638 buf[bufx++] = (u8) ((addr >> 24) & 0xFF); 1639 buf[bufx++] = (u8) ((addr >> 7) & 0xFF); 1640 #endif 1641 #if (((DRXDAPFASI_LONG_ADDR_ALLOWED) == 1) && ((DRXDAPFASI_SHORT_ADDR_ALLOWED) == 1)) 1642 } else { 1643 #endif 1644 #if ((DRXDAPFASI_SHORT_ADDR_ALLOWED) == 1) 1645 buf[bufx++] = (u8) ((addr << 1) & 0xFF); 1646 buf[bufx++] = 1647 (u8) (((addr >> 16) & 0x0F) | 1648 ((addr >> 18) & 0xF0)); 1649 #endif 1650 #if (((DRXDAPFASI_LONG_ADDR_ALLOWED) == 1) && ((DRXDAPFASI_SHORT_ADDR_ALLOWED) == 1)) 1651 } 1652 #endif 1653 1654 /* 1655 In single master mode block_size can be 0. In such a case this I2C 1656 sequense will be visible: (1) write address {i2c addr, 1657 4 bytes chip address} (2) write data {i2c addr, 4 bytes data } 1658 (3) write address (4) write data etc... 1659 Address must be rewritten because HI is reset after data transport and 1660 expects an address. 1661 */ 1662 todo = min(block_size, datasize); 1663 if (todo == 0) { 1664 u16 overhead_size_i2c_addr = 0; 1665 u16 data_block_size = 0; 1666 1667 overhead_size_i2c_addr = 1668 (IS_I2C_10BIT(dev_addr->i2c_addr) ? 2 : 1); 1669 data_block_size = 1670 (DRXDAP_MAX_WCHUNKSIZE - overhead_size_i2c_addr) & ~1; 1671 1672 /* write device address */ 1673 st = drxbsp_i2c_write_read(dev_addr, 1674 (u16) (bufx), 1675 buf, 1676 (struct i2c_device_addr *)(NULL), 1677 0, (u8 *)(NULL)); 1678 1679 if ((st != 0) && (first_err == 0)) { 1680 /* at the end, return the first error encountered */ 1681 first_err = st; 1682 } 1683 bufx = 0; 1684 todo = min(data_block_size, datasize); 1685 } 1686 memcpy(&buf[bufx], data, todo); 1687 /* write (address if can do and) data */ 1688 st = drxbsp_i2c_write_read(dev_addr, 1689 (u16) (bufx + todo), 1690 buf, 1691 (struct i2c_device_addr *)(NULL), 1692 0, (u8 *)(NULL)); 1693 1694 if ((st != 0) && (first_err == 0)) { 1695 /* at the end, return the first error encountered */ 1696 first_err = st; 1697 } 1698 datasize -= todo; 1699 data += todo; 1700 addr += (todo >> 1); 1701 } while (datasize); 1702 1703 return first_err; 1704 } 1705 1706 /***************************** 1707 * 1708 * int drxdap_fasi_write_reg16 ( 1709 * struct i2c_device_addr *dev_addr, -- address of I2C device 1710 * u32 addr, -- address of chip register/memory 1711 * u16 data, -- data to send 1712 * u32 flags) -- special device flags 1713 * 1714 * Write one 16-bit register or memory location. The data being written is 1715 * converted from the target platform's endianness to little endian. 1716 * 1717 * Output: 1718 * - 0 if writing was successful 1719 * - -EIO if anything went wrong 1720 * 1721 ******************************/ 1722 1723 static int drxdap_fasi_write_reg16(struct i2c_device_addr *dev_addr, 1724 u32 addr, 1725 u16 data, u32 flags) 1726 { 1727 u8 buf[sizeof(data)]; 1728 1729 buf[0] = (u8) ((data >> 0) & 0xFF); 1730 buf[1] = (u8) ((data >> 8) & 0xFF); 1731 1732 return drxdap_fasi_write_block(dev_addr, addr, sizeof(data), buf, flags); 1733 } 1734 1735 /***************************** 1736 * 1737 * int drxdap_fasi_read_modify_write_reg16 ( 1738 * struct i2c_device_addr *dev_addr, -- address of I2C device 1739 * u32 waddr, -- address of chip register/memory 1740 * u32 raddr, -- chip address to read back from 1741 * u16 wdata, -- data to send 1742 * u16 *rdata) -- data to receive back 1743 * 1744 * Write 16-bit data, then read back the original contents of that location. 1745 * Requires long addressing format to be allowed. 1746 * 1747 * Before sending data, the data is converted to little endian. The 1748 * data received back is converted back to the target platform's endianness. 1749 * 1750 * WARNING: This function is only guaranteed to work if there is one 1751 * master on the I2C bus. 1752 * 1753 * Output: 1754 * - 0 if reading was successful 1755 * in that case: read back data is at *rdata 1756 * - -EIO if anything went wrong 1757 * 1758 ******************************/ 1759 1760 static int drxdap_fasi_read_modify_write_reg16(struct i2c_device_addr *dev_addr, 1761 u32 waddr, 1762 u32 raddr, 1763 u16 wdata, u16 *rdata) 1764 { 1765 int rc = -EIO; 1766 1767 #if (DRXDAPFASI_LONG_ADDR_ALLOWED == 1) 1768 if (rdata == NULL) 1769 return -EINVAL; 1770 1771 rc = drxdap_fasi_write_reg16(dev_addr, waddr, wdata, DRXDAP_FASI_RMW); 1772 if (rc == 0) 1773 rc = drxdap_fasi_read_reg16(dev_addr, raddr, rdata, 0); 1774 #endif 1775 1776 return rc; 1777 } 1778 1779 /***************************** 1780 * 1781 * int drxdap_fasi_write_reg32 ( 1782 * struct i2c_device_addr *dev_addr, -- address of I2C device 1783 * u32 addr, -- address of chip register/memory 1784 * u32 data, -- data to send 1785 * u32 flags) -- special device flags 1786 * 1787 * Write one 32-bit register or memory location. The data being written is 1788 * converted from the target platform's endianness to little endian. 1789 * 1790 * Output: 1791 * - 0 if writing was successful 1792 * - -EIO if anything went wrong 1793 * 1794 ******************************/ 1795 1796 static int drxdap_fasi_write_reg32(struct i2c_device_addr *dev_addr, 1797 u32 addr, 1798 u32 data, u32 flags) 1799 { 1800 u8 buf[sizeof(data)]; 1801 1802 buf[0] = (u8) ((data >> 0) & 0xFF); 1803 buf[1] = (u8) ((data >> 8) & 0xFF); 1804 buf[2] = (u8) ((data >> 16) & 0xFF); 1805 buf[3] = (u8) ((data >> 24) & 0xFF); 1806 1807 return drxdap_fasi_write_block(dev_addr, addr, sizeof(data), buf, flags); 1808 } 1809 1810 /*============================================================================*/ 1811 1812 /* 1813 * \fn int drxj_dap_rm_write_reg16short 1814 * \brief Read modify write 16 bits audio register using short format only. 1815 * \param dev_addr 1816 * \param waddr Address to write to 1817 * \param raddr Address to read from (usually SIO_HI_RA_RAM_S0_RMWBUF__A) 1818 * \param wdata Data to write 1819 * \param rdata Buffer for data to read 1820 * \return int 1821 * \retval 0 Success 1822 * \retval -EIO Timeout, I2C error, illegal bank 1823 * 1824 * 16 bits register read modify write access using short addressing format only. 1825 * Requires knowledge of the registermap, thus device dependent. 1826 * Using DAP FASI directly to avoid endless recursion of RMWs to audio registers. 1827 * 1828 */ 1829 1830 /* TODO correct define should be #if ( DRXDAPFASI_SHORT_ADDR_ALLOWED==1 ) 1831 See comments drxj_dap_read_modify_write_reg16 */ 1832 #if (DRXDAPFASI_LONG_ADDR_ALLOWED == 0) 1833 static int drxj_dap_rm_write_reg16short(struct i2c_device_addr *dev_addr, 1834 u32 waddr, 1835 u32 raddr, 1836 u16 wdata, u16 *rdata) 1837 { 1838 int rc; 1839 1840 if (rdata == NULL) 1841 return -EINVAL; 1842 1843 /* Set RMW flag */ 1844 rc = drxdap_fasi_write_reg16(dev_addr, 1845 SIO_HI_RA_RAM_S0_FLG_ACC__A, 1846 SIO_HI_RA_RAM_S0_FLG_ACC_S0_RWM__M, 1847 0x0000); 1848 if (rc == 0) { 1849 /* Write new data: triggers RMW */ 1850 rc = drxdap_fasi_write_reg16(dev_addr, waddr, wdata, 1851 0x0000); 1852 } 1853 if (rc == 0) { 1854 /* Read old data */ 1855 rc = drxdap_fasi_read_reg16(dev_addr, raddr, rdata, 1856 0x0000); 1857 } 1858 if (rc == 0) { 1859 /* Reset RMW flag */ 1860 rc = drxdap_fasi_write_reg16(dev_addr, 1861 SIO_HI_RA_RAM_S0_FLG_ACC__A, 1862 0, 0x0000); 1863 } 1864 1865 return rc; 1866 } 1867 #endif 1868 1869 /*============================================================================*/ 1870 1871 static int drxj_dap_read_modify_write_reg16(struct i2c_device_addr *dev_addr, 1872 u32 waddr, 1873 u32 raddr, 1874 u16 wdata, u16 *rdata) 1875 { 1876 /* TODO: correct short/long addressing format decision, 1877 now long format has higher prio then short because short also 1878 needs virt bnks (not impl yet) for certain audio registers */ 1879 #if (DRXDAPFASI_LONG_ADDR_ALLOWED == 1) 1880 return drxdap_fasi_read_modify_write_reg16(dev_addr, 1881 waddr, 1882 raddr, wdata, rdata); 1883 #else 1884 return drxj_dap_rm_write_reg16short(dev_addr, waddr, raddr, wdata, rdata); 1885 #endif 1886 } 1887 1888 1889 /*============================================================================*/ 1890 1891 /* 1892 * \fn int drxj_dap_read_aud_reg16 1893 * \brief Read 16 bits audio register 1894 * \param dev_addr 1895 * \param addr 1896 * \param data 1897 * \return int 1898 * \retval 0 Success 1899 * \retval -EIO Timeout, I2C error, illegal bank 1900 * 1901 * 16 bits register read access via audio token ring interface. 1902 * 1903 */ 1904 static int drxj_dap_read_aud_reg16(struct i2c_device_addr *dev_addr, 1905 u32 addr, u16 *data) 1906 { 1907 u32 start_timer = 0; 1908 u32 current_timer = 0; 1909 u32 delta_timer = 0; 1910 u16 tr_status = 0; 1911 int stat = -EIO; 1912 1913 /* No read possible for bank 3, return with error */ 1914 if (DRXDAP_FASI_ADDR2BANK(addr) == 3) { 1915 stat = -EINVAL; 1916 } else { 1917 const u32 write_bit = ((dr_xaddr_t) 1) << 16; 1918 1919 /* Force reset write bit */ 1920 addr &= (~write_bit); 1921 1922 /* Set up read */ 1923 start_timer = jiffies_to_msecs(jiffies); 1924 do { 1925 /* RMW to aud TR IF until request is granted or timeout */ 1926 stat = drxj_dap_read_modify_write_reg16(dev_addr, 1927 addr, 1928 SIO_HI_RA_RAM_S0_RMWBUF__A, 1929 0x0000, &tr_status); 1930 1931 if (stat != 0) 1932 break; 1933 1934 current_timer = jiffies_to_msecs(jiffies); 1935 delta_timer = current_timer - start_timer; 1936 if (delta_timer > DRXJ_DAP_AUDTRIF_TIMEOUT) { 1937 stat = -EIO; 1938 break; 1939 } 1940 1941 } while (((tr_status & AUD_TOP_TR_CTR_FIFO_LOCK__M) == 1942 AUD_TOP_TR_CTR_FIFO_LOCK_LOCKED) || 1943 ((tr_status & AUD_TOP_TR_CTR_FIFO_FULL__M) == 1944 AUD_TOP_TR_CTR_FIFO_FULL_FULL)); 1945 } /* if ( DRXDAP_FASI_ADDR2BANK(addr)!=3 ) */ 1946 1947 /* Wait for read ready status or timeout */ 1948 if (stat == 0) { 1949 start_timer = jiffies_to_msecs(jiffies); 1950 1951 while ((tr_status & AUD_TOP_TR_CTR_FIFO_RD_RDY__M) != 1952 AUD_TOP_TR_CTR_FIFO_RD_RDY_READY) { 1953 stat = drxj_dap_read_reg16(dev_addr, 1954 AUD_TOP_TR_CTR__A, 1955 &tr_status, 0x0000); 1956 if (stat != 0) 1957 break; 1958 1959 current_timer = jiffies_to_msecs(jiffies); 1960 delta_timer = current_timer - start_timer; 1961 if (delta_timer > DRXJ_DAP_AUDTRIF_TIMEOUT) { 1962 stat = -EIO; 1963 break; 1964 } 1965 } /* while ( ... ) */ 1966 } 1967 1968 /* Read value */ 1969 if (stat == 0) 1970 stat = drxj_dap_read_modify_write_reg16(dev_addr, 1971 AUD_TOP_TR_RD_REG__A, 1972 SIO_HI_RA_RAM_S0_RMWBUF__A, 1973 0x0000, data); 1974 return stat; 1975 } 1976 1977 /*============================================================================*/ 1978 1979 static int drxj_dap_read_reg16(struct i2c_device_addr *dev_addr, 1980 u32 addr, 1981 u16 *data, u32 flags) 1982 { 1983 int stat = -EIO; 1984 1985 /* Check param */ 1986 if ((dev_addr == NULL) || (data == NULL)) 1987 return -EINVAL; 1988 1989 if (is_handled_by_aud_tr_if(addr)) 1990 stat = drxj_dap_read_aud_reg16(dev_addr, addr, data); 1991 else 1992 stat = drxdap_fasi_read_reg16(dev_addr, addr, data, flags); 1993 1994 return stat; 1995 } 1996 /*============================================================================*/ 1997 1998 /* 1999 * \fn int drxj_dap_write_aud_reg16 2000 * \brief Write 16 bits audio register 2001 * \param dev_addr 2002 * \param addr 2003 * \param data 2004 * \return int 2005 * \retval 0 Success 2006 * \retval -EIO Timeout, I2C error, illegal bank 2007 * 2008 * 16 bits register write access via audio token ring interface. 2009 * 2010 */ 2011 static int drxj_dap_write_aud_reg16(struct i2c_device_addr *dev_addr, 2012 u32 addr, u16 data) 2013 { 2014 int stat = -EIO; 2015 2016 /* No write possible for bank 2, return with error */ 2017 if (DRXDAP_FASI_ADDR2BANK(addr) == 2) { 2018 stat = -EINVAL; 2019 } else { 2020 u32 start_timer = 0; 2021 u32 current_timer = 0; 2022 u32 delta_timer = 0; 2023 u16 tr_status = 0; 2024 const u32 write_bit = ((dr_xaddr_t) 1) << 16; 2025 2026 /* Force write bit */ 2027 addr |= write_bit; 2028 start_timer = jiffies_to_msecs(jiffies); 2029 do { 2030 /* RMW to aud TR IF until request is granted or timeout */ 2031 stat = drxj_dap_read_modify_write_reg16(dev_addr, 2032 addr, 2033 SIO_HI_RA_RAM_S0_RMWBUF__A, 2034 data, &tr_status); 2035 if (stat != 0) 2036 break; 2037 2038 current_timer = jiffies_to_msecs(jiffies); 2039 delta_timer = current_timer - start_timer; 2040 if (delta_timer > DRXJ_DAP_AUDTRIF_TIMEOUT) { 2041 stat = -EIO; 2042 break; 2043 } 2044 2045 } while (((tr_status & AUD_TOP_TR_CTR_FIFO_LOCK__M) == 2046 AUD_TOP_TR_CTR_FIFO_LOCK_LOCKED) || 2047 ((tr_status & AUD_TOP_TR_CTR_FIFO_FULL__M) == 2048 AUD_TOP_TR_CTR_FIFO_FULL_FULL)); 2049 2050 } /* if ( DRXDAP_FASI_ADDR2BANK(addr)!=2 ) */ 2051 2052 return stat; 2053 } 2054 2055 /*============================================================================*/ 2056 2057 static int drxj_dap_write_reg16(struct i2c_device_addr *dev_addr, 2058 u32 addr, 2059 u16 data, u32 flags) 2060 { 2061 int stat = -EIO; 2062 2063 /* Check param */ 2064 if (dev_addr == NULL) 2065 return -EINVAL; 2066 2067 if (is_handled_by_aud_tr_if(addr)) 2068 stat = drxj_dap_write_aud_reg16(dev_addr, addr, data); 2069 else 2070 stat = drxdap_fasi_write_reg16(dev_addr, 2071 addr, data, flags); 2072 2073 return stat; 2074 } 2075 2076 /*============================================================================*/ 2077 2078 /* Free data ram in SIO HI */ 2079 #define SIO_HI_RA_RAM_USR_BEGIN__A 0x420040 2080 #define SIO_HI_RA_RAM_USR_END__A 0x420060 2081 2082 #define DRXJ_HI_ATOMIC_BUF_START (SIO_HI_RA_RAM_USR_BEGIN__A) 2083 #define DRXJ_HI_ATOMIC_BUF_END (SIO_HI_RA_RAM_USR_BEGIN__A + 7) 2084 #define DRXJ_HI_ATOMIC_READ SIO_HI_RA_RAM_PAR_3_ACP_RW_READ 2085 #define DRXJ_HI_ATOMIC_WRITE SIO_HI_RA_RAM_PAR_3_ACP_RW_WRITE 2086 2087 /* 2088 * \fn int drxj_dap_atomic_read_write_block() 2089 * \brief Basic access routine for atomic read or write access 2090 * \param dev_addr pointer to i2c dev address 2091 * \param addr destination/source address 2092 * \param datasize size of data buffer in bytes 2093 * \param data pointer to data buffer 2094 * \return int 2095 * \retval 0 Success 2096 * \retval -EIO Timeout, I2C error, illegal bank 2097 * 2098 */ 2099 static 2100 int drxj_dap_atomic_read_write_block(struct i2c_device_addr *dev_addr, 2101 u32 addr, 2102 u16 datasize, 2103 u8 *data, bool read_flag) 2104 { 2105 struct drxj_hi_cmd hi_cmd; 2106 int rc; 2107 u16 word; 2108 u16 dummy = 0; 2109 u16 i = 0; 2110 2111 /* Parameter check */ 2112 if (!data || !dev_addr || ((datasize % 2)) || ((datasize / 2) > 8)) 2113 return -EINVAL; 2114 2115 /* Set up HI parameters to read or write n bytes */ 2116 hi_cmd.cmd = SIO_HI_RA_RAM_CMD_ATOMIC_COPY; 2117 hi_cmd.param1 = 2118 (u16) ((DRXDAP_FASI_ADDR2BLOCK(DRXJ_HI_ATOMIC_BUF_START) << 6) + 2119 DRXDAP_FASI_ADDR2BANK(DRXJ_HI_ATOMIC_BUF_START)); 2120 hi_cmd.param2 = 2121 (u16) DRXDAP_FASI_ADDR2OFFSET(DRXJ_HI_ATOMIC_BUF_START); 2122 hi_cmd.param3 = (u16) ((datasize / 2) - 1); 2123 if (!read_flag) 2124 hi_cmd.param3 |= DRXJ_HI_ATOMIC_WRITE; 2125 else 2126 hi_cmd.param3 |= DRXJ_HI_ATOMIC_READ; 2127 hi_cmd.param4 = (u16) ((DRXDAP_FASI_ADDR2BLOCK(addr) << 6) + 2128 DRXDAP_FASI_ADDR2BANK(addr)); 2129 hi_cmd.param5 = (u16) DRXDAP_FASI_ADDR2OFFSET(addr); 2130 2131 if (!read_flag) { 2132 /* write data to buffer */ 2133 for (i = 0; i < (datasize / 2); i++) { 2134 2135 word = ((u16) data[2 * i]); 2136 word += (((u16) data[(2 * i) + 1]) << 8); 2137 drxj_dap_write_reg16(dev_addr, 2138 (DRXJ_HI_ATOMIC_BUF_START + i), 2139 word, 0); 2140 } 2141 } 2142 2143 rc = hi_command(dev_addr, &hi_cmd, &dummy); 2144 if (rc != 0) { 2145 pr_err("error %d\n", rc); 2146 goto rw_error; 2147 } 2148 2149 if (read_flag) { 2150 /* read data from buffer */ 2151 for (i = 0; i < (datasize / 2); i++) { 2152 rc = drxj_dap_read_reg16(dev_addr, 2153 (DRXJ_HI_ATOMIC_BUF_START + i), 2154 &word, 0); 2155 if (rc) { 2156 pr_err("error %d\n", rc); 2157 goto rw_error; 2158 } 2159 data[2 * i] = (u8) (word & 0xFF); 2160 data[(2 * i) + 1] = (u8) (word >> 8); 2161 } 2162 } 2163 2164 return 0; 2165 2166 rw_error: 2167 return rc; 2168 2169 } 2170 2171 /*============================================================================*/ 2172 2173 /* 2174 * \fn int drxj_dap_atomic_read_reg32() 2175 * \brief Atomic read of 32 bits words 2176 */ 2177 static 2178 int drxj_dap_atomic_read_reg32(struct i2c_device_addr *dev_addr, 2179 u32 addr, 2180 u32 *data, u32 flags) 2181 { 2182 u8 buf[sizeof(*data)] = { 0 }; 2183 int rc; 2184 u32 word = 0; 2185 2186 if (!data) 2187 return -EINVAL; 2188 2189 rc = drxj_dap_atomic_read_write_block(dev_addr, addr, 2190 sizeof(*data), buf, true); 2191 2192 if (rc < 0) 2193 return 0; 2194 2195 word = (u32) buf[3]; 2196 word <<= 8; 2197 word |= (u32) buf[2]; 2198 word <<= 8; 2199 word |= (u32) buf[1]; 2200 word <<= 8; 2201 word |= (u32) buf[0]; 2202 2203 *data = word; 2204 2205 return rc; 2206 } 2207 2208 /*============================================================================*/ 2209 2210 /*============================================================================*/ 2211 /*== END DRXJ DAP FUNCTIONS ==*/ 2212 /*============================================================================*/ 2213 2214 /*============================================================================*/ 2215 /*============================================================================*/ 2216 /*== HOST INTERFACE FUNCTIONS ==*/ 2217 /*============================================================================*/ 2218 /*============================================================================*/ 2219 2220 /* 2221 * \fn int hi_cfg_command() 2222 * \brief Configure HI with settings stored in the demod structure. 2223 * \param demod Demodulator. 2224 * \return int. 2225 * 2226 * This routine was created because to much orthogonal settings have 2227 * been put into one HI API function (configure). Especially the I2C bridge 2228 * enable/disable should not need re-configuration of the HI. 2229 * 2230 */ 2231 static int hi_cfg_command(const struct drx_demod_instance *demod) 2232 { 2233 struct drxj_data *ext_attr = (struct drxj_data *) (NULL); 2234 struct drxj_hi_cmd hi_cmd; 2235 u16 result = 0; 2236 int rc; 2237 2238 ext_attr = (struct drxj_data *) demod->my_ext_attr; 2239 2240 hi_cmd.cmd = SIO_HI_RA_RAM_CMD_CONFIG; 2241 hi_cmd.param1 = SIO_HI_RA_RAM_PAR_1_PAR1_SEC_KEY; 2242 hi_cmd.param2 = ext_attr->hi_cfg_timing_div; 2243 hi_cmd.param3 = ext_attr->hi_cfg_bridge_delay; 2244 hi_cmd.param4 = ext_attr->hi_cfg_wake_up_key; 2245 hi_cmd.param5 = ext_attr->hi_cfg_ctrl; 2246 hi_cmd.param6 = ext_attr->hi_cfg_transmit; 2247 2248 rc = hi_command(demod->my_i2c_dev_addr, &hi_cmd, &result); 2249 if (rc != 0) { 2250 pr_err("error %d\n", rc); 2251 goto rw_error; 2252 } 2253 2254 /* Reset power down flag (set one call only) */ 2255 ext_attr->hi_cfg_ctrl &= (~(SIO_HI_RA_RAM_PAR_5_CFG_SLEEP_ZZZ)); 2256 2257 return 0; 2258 2259 rw_error: 2260 return rc; 2261 } 2262 2263 /* 2264 * \fn int hi_command() 2265 * \brief Configure HI with settings stored in the demod structure. 2266 * \param dev_addr I2C address. 2267 * \param cmd HI command. 2268 * \param result HI command result. 2269 * \return int. 2270 * 2271 * Sends command to HI 2272 * 2273 */ 2274 static int 2275 hi_command(struct i2c_device_addr *dev_addr, const struct drxj_hi_cmd *cmd, u16 *result) 2276 { 2277 u16 wait_cmd = 0; 2278 u16 nr_retries = 0; 2279 bool powerdown_cmd = false; 2280 int rc; 2281 2282 /* Write parameters */ 2283 switch (cmd->cmd) { 2284 2285 case SIO_HI_RA_RAM_CMD_CONFIG: 2286 case SIO_HI_RA_RAM_CMD_ATOMIC_COPY: 2287 rc = drxj_dap_write_reg16(dev_addr, SIO_HI_RA_RAM_PAR_6__A, cmd->param6, 0); 2288 if (rc != 0) { 2289 pr_err("error %d\n", rc); 2290 goto rw_error; 2291 } 2292 rc = drxj_dap_write_reg16(dev_addr, SIO_HI_RA_RAM_PAR_5__A, cmd->param5, 0); 2293 if (rc != 0) { 2294 pr_err("error %d\n", rc); 2295 goto rw_error; 2296 } 2297 rc = drxj_dap_write_reg16(dev_addr, SIO_HI_RA_RAM_PAR_4__A, cmd->param4, 0); 2298 if (rc != 0) { 2299 pr_err("error %d\n", rc); 2300 goto rw_error; 2301 } 2302 rc = drxj_dap_write_reg16(dev_addr, SIO_HI_RA_RAM_PAR_3__A, cmd->param3, 0); 2303 if (rc != 0) { 2304 pr_err("error %d\n", rc); 2305 goto rw_error; 2306 } 2307 fallthrough; 2308 case SIO_HI_RA_RAM_CMD_BRDCTRL: 2309 rc = drxj_dap_write_reg16(dev_addr, SIO_HI_RA_RAM_PAR_2__A, cmd->param2, 0); 2310 if (rc != 0) { 2311 pr_err("error %d\n", rc); 2312 goto rw_error; 2313 } 2314 rc = drxj_dap_write_reg16(dev_addr, SIO_HI_RA_RAM_PAR_1__A, cmd->param1, 0); 2315 if (rc != 0) { 2316 pr_err("error %d\n", rc); 2317 goto rw_error; 2318 } 2319 fallthrough; 2320 case SIO_HI_RA_RAM_CMD_NULL: 2321 /* No parameters */ 2322 break; 2323 2324 default: 2325 return -EINVAL; 2326 } 2327 2328 /* Write command */ 2329 rc = drxj_dap_write_reg16(dev_addr, SIO_HI_RA_RAM_CMD__A, cmd->cmd, 0); 2330 if (rc != 0) { 2331 pr_err("error %d\n", rc); 2332 goto rw_error; 2333 } 2334 2335 if ((cmd->cmd) == SIO_HI_RA_RAM_CMD_RESET) 2336 msleep(1); 2337 2338 /* Detect power down to omit reading result */ 2339 powerdown_cmd = (bool) ((cmd->cmd == SIO_HI_RA_RAM_CMD_CONFIG) && 2340 (((cmd-> 2341 param5) & SIO_HI_RA_RAM_PAR_5_CFG_SLEEP__M) 2342 == SIO_HI_RA_RAM_PAR_5_CFG_SLEEP_ZZZ)); 2343 if (!powerdown_cmd) { 2344 /* Wait until command rdy */ 2345 do { 2346 nr_retries++; 2347 if (nr_retries > DRXJ_MAX_RETRIES) { 2348 rc = -ETIMEDOUT; 2349 pr_err("timeout\n"); 2350 goto rw_error; 2351 } 2352 2353 rc = drxj_dap_read_reg16(dev_addr, SIO_HI_RA_RAM_CMD__A, &wait_cmd, 0); 2354 if (rc != 0) { 2355 pr_err("error %d\n", rc); 2356 goto rw_error; 2357 } 2358 } while (wait_cmd != 0); 2359 2360 /* Read result */ 2361 rc = drxj_dap_read_reg16(dev_addr, SIO_HI_RA_RAM_RES__A, result, 0); 2362 if (rc != 0) { 2363 pr_err("error %d\n", rc); 2364 goto rw_error; 2365 } 2366 2367 } 2368 /* if ( powerdown_cmd == true ) */ 2369 return 0; 2370 rw_error: 2371 return rc; 2372 } 2373 2374 /* 2375 * \fn int init_hi( const struct drx_demod_instance *demod ) 2376 * \brief Initialise and configurate HI. 2377 * \param demod pointer to demod data. 2378 * \return int Return status. 2379 * \retval 0 Success. 2380 * \retval -EIO Failure. 2381 * 2382 * Needs to know Psys (System Clock period) and Posc (Osc Clock period) 2383 * Need to store configuration in driver because of the way I2C 2384 * bridging is controlled. 2385 * 2386 */ 2387 static int init_hi(const struct drx_demod_instance *demod) 2388 { 2389 struct drxj_data *ext_attr = (struct drxj_data *) (NULL); 2390 struct drx_common_attr *common_attr = (struct drx_common_attr *) (NULL); 2391 struct i2c_device_addr *dev_addr = (struct i2c_device_addr *)(NULL); 2392 int rc; 2393 2394 ext_attr = (struct drxj_data *) demod->my_ext_attr; 2395 common_attr = (struct drx_common_attr *) demod->my_common_attr; 2396 dev_addr = demod->my_i2c_dev_addr; 2397 2398 /* PATCH for bug 5003, HI ucode v3.1.0 */ 2399 rc = drxj_dap_write_reg16(dev_addr, 0x4301D7, 0x801, 0); 2400 if (rc != 0) { 2401 pr_err("error %d\n", rc); 2402 goto rw_error; 2403 } 2404 2405 /* Timing div, 250ns/Psys */ 2406 /* Timing div, = ( delay (nano seconds) * sysclk (kHz) )/ 1000 */ 2407 ext_attr->hi_cfg_timing_div = 2408 (u16) ((common_attr->sys_clock_freq / 1000) * HI_I2C_DELAY) / 1000; 2409 /* Clipping */ 2410 if ((ext_attr->hi_cfg_timing_div) > SIO_HI_RA_RAM_PAR_2_CFG_DIV__M) 2411 ext_attr->hi_cfg_timing_div = SIO_HI_RA_RAM_PAR_2_CFG_DIV__M; 2412 /* Bridge delay, uses oscilator clock */ 2413 /* Delay = ( delay (nano seconds) * oscclk (kHz) )/ 1000 */ 2414 /* SDA brdige delay */ 2415 ext_attr->hi_cfg_bridge_delay = 2416 (u16) ((common_attr->osc_clock_freq / 1000) * HI_I2C_BRIDGE_DELAY) / 2417 1000; 2418 /* Clipping */ 2419 if ((ext_attr->hi_cfg_bridge_delay) > SIO_HI_RA_RAM_PAR_3_CFG_DBL_SDA__M) 2420 ext_attr->hi_cfg_bridge_delay = SIO_HI_RA_RAM_PAR_3_CFG_DBL_SDA__M; 2421 /* SCL bridge delay, same as SDA for now */ 2422 ext_attr->hi_cfg_bridge_delay += ((ext_attr->hi_cfg_bridge_delay) << 2423 SIO_HI_RA_RAM_PAR_3_CFG_DBL_SCL__B); 2424 /* Wakeup key, setting the read flag (as suggest in the documentation) does 2425 not always result into a working solution (barebones worked VI2C failed). 2426 Not setting the bit works in all cases . */ 2427 ext_attr->hi_cfg_wake_up_key = DRXJ_WAKE_UP_KEY; 2428 /* port/bridge/power down ctrl */ 2429 ext_attr->hi_cfg_ctrl = (SIO_HI_RA_RAM_PAR_5_CFG_SLV0_SLAVE); 2430 /* transit mode time out delay and watch dog divider */ 2431 ext_attr->hi_cfg_transmit = SIO_HI_RA_RAM_PAR_6__PRE; 2432 2433 rc = hi_cfg_command(demod); 2434 if (rc != 0) { 2435 pr_err("error %d\n", rc); 2436 goto rw_error; 2437 } 2438 2439 return 0; 2440 2441 rw_error: 2442 return rc; 2443 } 2444 2445 /*============================================================================*/ 2446 /*== END HOST INTERFACE FUNCTIONS ==*/ 2447 /*============================================================================*/ 2448 2449 /*============================================================================*/ 2450 /*============================================================================*/ 2451 /*== AUXILIARY FUNCTIONS ==*/ 2452 /*============================================================================*/ 2453 /*============================================================================*/ 2454 2455 /* 2456 * \fn int get_device_capabilities() 2457 * \brief Get and store device capabilities. 2458 * \param demod Pointer to demodulator instance. 2459 * \return int. 2460 * \return 0 Success 2461 * \retval -EIO Failure 2462 * 2463 * Depending on pulldowns on MDx pins the following internals are set: 2464 * * common_attr->osc_clock_freq 2465 * * ext_attr->has_lna 2466 * * ext_attr->has_ntsc 2467 * * ext_attr->has_btsc 2468 * * ext_attr->has_oob 2469 * 2470 */ 2471 static int get_device_capabilities(struct drx_demod_instance *demod) 2472 { 2473 struct drx_common_attr *common_attr = (struct drx_common_attr *) (NULL); 2474 struct drxj_data *ext_attr = (struct drxj_data *) NULL; 2475 struct i2c_device_addr *dev_addr = (struct i2c_device_addr *)(NULL); 2476 u16 sio_pdr_ohw_cfg = 0; 2477 u32 sio_top_jtagid_lo = 0; 2478 u16 bid = 0; 2479 int rc; 2480 2481 common_attr = (struct drx_common_attr *) demod->my_common_attr; 2482 ext_attr = (struct drxj_data *) demod->my_ext_attr; 2483 dev_addr = demod->my_i2c_dev_addr; 2484 2485 rc = drxj_dap_write_reg16(dev_addr, SIO_TOP_COMM_KEY__A, SIO_TOP_COMM_KEY_KEY, 0); 2486 if (rc != 0) { 2487 pr_err("error %d\n", rc); 2488 goto rw_error; 2489 } 2490 rc = drxj_dap_read_reg16(dev_addr, SIO_PDR_OHW_CFG__A, &sio_pdr_ohw_cfg, 0); 2491 if (rc != 0) { 2492 pr_err("error %d\n", rc); 2493 goto rw_error; 2494 } 2495 rc = drxj_dap_write_reg16(dev_addr, SIO_TOP_COMM_KEY__A, SIO_TOP_COMM_KEY__PRE, 0); 2496 if (rc != 0) { 2497 pr_err("error %d\n", rc); 2498 goto rw_error; 2499 } 2500 2501 switch ((sio_pdr_ohw_cfg & SIO_PDR_OHW_CFG_FREF_SEL__M)) { 2502 case 0: 2503 /* ignore (bypass ?) */ 2504 break; 2505 case 1: 2506 /* 27 MHz */ 2507 common_attr->osc_clock_freq = 27000; 2508 break; 2509 case 2: 2510 /* 20.25 MHz */ 2511 common_attr->osc_clock_freq = 20250; 2512 break; 2513 case 3: 2514 /* 4 MHz */ 2515 common_attr->osc_clock_freq = 4000; 2516 break; 2517 default: 2518 return -EIO; 2519 } 2520 2521 /* 2522 Determine device capabilities 2523 Based on pinning v47 2524 */ 2525 rc = drxdap_fasi_read_reg32(dev_addr, SIO_TOP_JTAGID_LO__A, &sio_top_jtagid_lo, 0); 2526 if (rc != 0) { 2527 pr_err("error %d\n", rc); 2528 goto rw_error; 2529 } 2530 ext_attr->mfx = (u8) ((sio_top_jtagid_lo >> 29) & 0xF); 2531 2532 switch ((sio_top_jtagid_lo >> 12) & 0xFF) { 2533 case 0x31: 2534 rc = drxj_dap_write_reg16(dev_addr, SIO_TOP_COMM_KEY__A, SIO_TOP_COMM_KEY_KEY, 0); 2535 if (rc != 0) { 2536 pr_err("error %d\n", rc); 2537 goto rw_error; 2538 } 2539 rc = drxj_dap_read_reg16(dev_addr, SIO_PDR_UIO_IN_HI__A, &bid, 0); 2540 if (rc != 0) { 2541 pr_err("error %d\n", rc); 2542 goto rw_error; 2543 } 2544 bid = (bid >> 10) & 0xf; 2545 rc = drxj_dap_write_reg16(dev_addr, SIO_TOP_COMM_KEY__A, SIO_TOP_COMM_KEY__PRE, 0); 2546 if (rc != 0) { 2547 pr_err("error %d\n", rc); 2548 goto rw_error; 2549 } 2550 2551 ext_attr->has_lna = true; 2552 ext_attr->has_ntsc = false; 2553 ext_attr->has_btsc = false; 2554 ext_attr->has_oob = false; 2555 ext_attr->has_smatx = true; 2556 ext_attr->has_smarx = false; 2557 ext_attr->has_gpio = false; 2558 ext_attr->has_irqn = false; 2559 break; 2560 case 0x33: 2561 ext_attr->has_lna = false; 2562 ext_attr->has_ntsc = false; 2563 ext_attr->has_btsc = false; 2564 ext_attr->has_oob = false; 2565 ext_attr->has_smatx = true; 2566 ext_attr->has_smarx = false; 2567 ext_attr->has_gpio = false; 2568 ext_attr->has_irqn = false; 2569 break; 2570 case 0x45: 2571 ext_attr->has_lna = true; 2572 ext_attr->has_ntsc = true; 2573 ext_attr->has_btsc = false; 2574 ext_attr->has_oob = false; 2575 ext_attr->has_smatx = true; 2576 ext_attr->has_smarx = true; 2577 ext_attr->has_gpio = true; 2578 ext_attr->has_irqn = false; 2579 break; 2580 case 0x46: 2581 ext_attr->has_lna = false; 2582 ext_attr->has_ntsc = true; 2583 ext_attr->has_btsc = false; 2584 ext_attr->has_oob = false; 2585 ext_attr->has_smatx = true; 2586 ext_attr->has_smarx = true; 2587 ext_attr->has_gpio = true; 2588 ext_attr->has_irqn = false; 2589 break; 2590 case 0x41: 2591 ext_attr->has_lna = true; 2592 ext_attr->has_ntsc = true; 2593 ext_attr->has_btsc = true; 2594 ext_attr->has_oob = false; 2595 ext_attr->has_smatx = true; 2596 ext_attr->has_smarx = true; 2597 ext_attr->has_gpio = true; 2598 ext_attr->has_irqn = false; 2599 break; 2600 case 0x43: 2601 ext_attr->has_lna = false; 2602 ext_attr->has_ntsc = true; 2603 ext_attr->has_btsc = true; 2604 ext_attr->has_oob = false; 2605 ext_attr->has_smatx = true; 2606 ext_attr->has_smarx = true; 2607 ext_attr->has_gpio = true; 2608 ext_attr->has_irqn = false; 2609 break; 2610 case 0x32: 2611 ext_attr->has_lna = true; 2612 ext_attr->has_ntsc = false; 2613 ext_attr->has_btsc = false; 2614 ext_attr->has_oob = true; 2615 ext_attr->has_smatx = true; 2616 ext_attr->has_smarx = true; 2617 ext_attr->has_gpio = true; 2618 ext_attr->has_irqn = true; 2619 break; 2620 case 0x34: 2621 ext_attr->has_lna = false; 2622 ext_attr->has_ntsc = true; 2623 ext_attr->has_btsc = true; 2624 ext_attr->has_oob = true; 2625 ext_attr->has_smatx = true; 2626 ext_attr->has_smarx = true; 2627 ext_attr->has_gpio = true; 2628 ext_attr->has_irqn = true; 2629 break; 2630 case 0x42: 2631 ext_attr->has_lna = true; 2632 ext_attr->has_ntsc = true; 2633 ext_attr->has_btsc = true; 2634 ext_attr->has_oob = true; 2635 ext_attr->has_smatx = true; 2636 ext_attr->has_smarx = true; 2637 ext_attr->has_gpio = true; 2638 ext_attr->has_irqn = true; 2639 break; 2640 case 0x44: 2641 ext_attr->has_lna = false; 2642 ext_attr->has_ntsc = true; 2643 ext_attr->has_btsc = true; 2644 ext_attr->has_oob = true; 2645 ext_attr->has_smatx = true; 2646 ext_attr->has_smarx = true; 2647 ext_attr->has_gpio = true; 2648 ext_attr->has_irqn = true; 2649 break; 2650 default: 2651 /* Unknown device variant */ 2652 return -EIO; 2653 break; 2654 } 2655 2656 return 0; 2657 rw_error: 2658 return rc; 2659 } 2660 2661 /* 2662 * \fn int power_up_device() 2663 * \brief Power up device. 2664 * \param demod Pointer to demodulator instance. 2665 * \return int. 2666 * \return 0 Success 2667 * \retval -EIO Failure, I2C or max retries reached 2668 * 2669 */ 2670 2671 #ifndef DRXJ_MAX_RETRIES_POWERUP 2672 #define DRXJ_MAX_RETRIES_POWERUP 10 2673 #endif 2674 2675 static int power_up_device(struct drx_demod_instance *demod) 2676 { 2677 struct i2c_device_addr *dev_addr = (struct i2c_device_addr *)(NULL); 2678 u8 data = 0; 2679 u16 retry_count = 0; 2680 struct i2c_device_addr wake_up_addr; 2681 2682 dev_addr = demod->my_i2c_dev_addr; 2683 wake_up_addr.i2c_addr = DRXJ_WAKE_UP_KEY; 2684 wake_up_addr.i2c_dev_id = dev_addr->i2c_dev_id; 2685 wake_up_addr.user_data = dev_addr->user_data; 2686 /* 2687 * I2C access may fail in this case: no ack 2688 * dummy write must be used to wake uop device, dummy read must be used to 2689 * reset HI state machine (avoiding actual writes) 2690 */ 2691 do { 2692 data = 0; 2693 drxbsp_i2c_write_read(&wake_up_addr, 1, &data, 2694 (struct i2c_device_addr *)(NULL), 0, 2695 (u8 *)(NULL)); 2696 msleep(10); 2697 retry_count++; 2698 } while ((drxbsp_i2c_write_read 2699 ((struct i2c_device_addr *) (NULL), 0, (u8 *)(NULL), dev_addr, 1, 2700 &data) 2701 != 0) && (retry_count < DRXJ_MAX_RETRIES_POWERUP)); 2702 2703 /* Need some recovery time .... */ 2704 msleep(10); 2705 2706 if (retry_count == DRXJ_MAX_RETRIES_POWERUP) 2707 return -EIO; 2708 2709 return 0; 2710 } 2711 2712 /*----------------------------------------------------------------------------*/ 2713 /* MPEG Output Configuration Functions - begin */ 2714 /*----------------------------------------------------------------------------*/ 2715 /* 2716 * \fn int ctrl_set_cfg_mpeg_output() 2717 * \brief Set MPEG output configuration of the device. 2718 * \param devmod Pointer to demodulator instance. 2719 * \param cfg_data Pointer to mpeg output configuaration. 2720 * \return int. 2721 * 2722 * Configure MPEG output parameters. 2723 * 2724 */ 2725 static int 2726 ctrl_set_cfg_mpeg_output(struct drx_demod_instance *demod, struct drx_cfg_mpeg_output *cfg_data) 2727 { 2728 struct i2c_device_addr *dev_addr = (struct i2c_device_addr *)(NULL); 2729 struct drxj_data *ext_attr = (struct drxj_data *) (NULL); 2730 struct drx_common_attr *common_attr = (struct drx_common_attr *) (NULL); 2731 int rc; 2732 u16 fec_oc_reg_mode = 0; 2733 u16 fec_oc_reg_ipr_mode = 0; 2734 u16 fec_oc_reg_ipr_invert = 0; 2735 u32 max_bit_rate = 0; 2736 u32 rcn_rate = 0; 2737 u32 nr_bits = 0; 2738 u16 sio_pdr_md_cfg = 0; 2739 /* data mask for the output data byte */ 2740 u16 invert_data_mask = 2741 FEC_OC_IPR_INVERT_MD7__M | FEC_OC_IPR_INVERT_MD6__M | 2742 FEC_OC_IPR_INVERT_MD5__M | FEC_OC_IPR_INVERT_MD4__M | 2743 FEC_OC_IPR_INVERT_MD3__M | FEC_OC_IPR_INVERT_MD2__M | 2744 FEC_OC_IPR_INVERT_MD1__M | FEC_OC_IPR_INVERT_MD0__M; 2745 2746 /* check arguments */ 2747 if ((demod == NULL) || (cfg_data == NULL)) 2748 return -EINVAL; 2749 2750 dev_addr = demod->my_i2c_dev_addr; 2751 ext_attr = (struct drxj_data *) demod->my_ext_attr; 2752 common_attr = (struct drx_common_attr *) demod->my_common_attr; 2753 2754 if (cfg_data->enable_mpeg_output == true) { 2755 /* quick and dirty patch to set MPEG in case current std is not 2756 producing MPEG */ 2757 switch (ext_attr->standard) { 2758 case DRX_STANDARD_8VSB: 2759 case DRX_STANDARD_ITU_A: 2760 case DRX_STANDARD_ITU_B: 2761 case DRX_STANDARD_ITU_C: 2762 break; 2763 default: 2764 return 0; 2765 } 2766 2767 rc = drxj_dap_write_reg16(dev_addr, FEC_OC_OCR_INVERT__A, 0, 0); 2768 if (rc != 0) { 2769 pr_err("error %d\n", rc); 2770 goto rw_error; 2771 } 2772 switch (ext_attr->standard) { 2773 case DRX_STANDARD_8VSB: 2774 rc = drxj_dap_write_reg16(dev_addr, FEC_OC_FCT_USAGE__A, 7, 0); 2775 if (rc != 0) { 2776 pr_err("error %d\n", rc); 2777 goto rw_error; 2778 } /* 2048 bytes fifo ram */ 2779 rc = drxj_dap_write_reg16(dev_addr, FEC_OC_TMD_CTL_UPD_RATE__A, 10, 0); 2780 if (rc != 0) { 2781 pr_err("error %d\n", rc); 2782 goto rw_error; 2783 } 2784 rc = drxj_dap_write_reg16(dev_addr, FEC_OC_TMD_INT_UPD_RATE__A, 10, 0); 2785 if (rc != 0) { 2786 pr_err("error %d\n", rc); 2787 goto rw_error; 2788 } 2789 rc = drxj_dap_write_reg16(dev_addr, FEC_OC_AVR_PARM_A__A, 5, 0); 2790 if (rc != 0) { 2791 pr_err("error %d\n", rc); 2792 goto rw_error; 2793 } 2794 rc = drxj_dap_write_reg16(dev_addr, FEC_OC_AVR_PARM_B__A, 7, 0); 2795 if (rc != 0) { 2796 pr_err("error %d\n", rc); 2797 goto rw_error; 2798 } 2799 rc = drxj_dap_write_reg16(dev_addr, FEC_OC_RCN_GAIN__A, 10, 0); 2800 if (rc != 0) { 2801 pr_err("error %d\n", rc); 2802 goto rw_error; 2803 } 2804 /* Low Water Mark for synchronization */ 2805 rc = drxj_dap_write_reg16(dev_addr, FEC_OC_SNC_LWM__A, 3, 0); 2806 if (rc != 0) { 2807 pr_err("error %d\n", rc); 2808 goto rw_error; 2809 } 2810 /* High Water Mark for synchronization */ 2811 rc = drxj_dap_write_reg16(dev_addr, FEC_OC_SNC_HWM__A, 5, 0); 2812 if (rc != 0) { 2813 pr_err("error %d\n", rc); 2814 goto rw_error; 2815 } 2816 break; 2817 case DRX_STANDARD_ITU_A: 2818 case DRX_STANDARD_ITU_C: 2819 switch (ext_attr->constellation) { 2820 case DRX_CONSTELLATION_QAM256: 2821 nr_bits = 8; 2822 break; 2823 case DRX_CONSTELLATION_QAM128: 2824 nr_bits = 7; 2825 break; 2826 case DRX_CONSTELLATION_QAM64: 2827 nr_bits = 6; 2828 break; 2829 case DRX_CONSTELLATION_QAM32: 2830 nr_bits = 5; 2831 break; 2832 case DRX_CONSTELLATION_QAM16: 2833 nr_bits = 4; 2834 break; 2835 default: 2836 return -EIO; 2837 } /* ext_attr->constellation */ 2838 /* max_bit_rate = symbol_rate * nr_bits * coef */ 2839 /* coef = 188/204 */ 2840 max_bit_rate = 2841 (ext_attr->curr_symbol_rate / 8) * nr_bits * 188; 2842 fallthrough; /* as b/c Annex A/C need following settings */ 2843 case DRX_STANDARD_ITU_B: 2844 rc = drxj_dap_write_reg16(dev_addr, FEC_OC_FCT_USAGE__A, FEC_OC_FCT_USAGE__PRE, 0); 2845 if (rc != 0) { 2846 pr_err("error %d\n", rc); 2847 goto rw_error; 2848 } 2849 rc = drxj_dap_write_reg16(dev_addr, FEC_OC_TMD_CTL_UPD_RATE__A, FEC_OC_TMD_CTL_UPD_RATE__PRE, 0); 2850 if (rc != 0) { 2851 pr_err("error %d\n", rc); 2852 goto rw_error; 2853 } 2854 rc = drxj_dap_write_reg16(dev_addr, FEC_OC_TMD_INT_UPD_RATE__A, 5, 0); 2855 if (rc != 0) { 2856 pr_err("error %d\n", rc); 2857 goto rw_error; 2858 } 2859 rc = drxj_dap_write_reg16(dev_addr, FEC_OC_AVR_PARM_A__A, FEC_OC_AVR_PARM_A__PRE, 0); 2860 if (rc != 0) { 2861 pr_err("error %d\n", rc); 2862 goto rw_error; 2863 } 2864 rc = drxj_dap_write_reg16(dev_addr, FEC_OC_AVR_PARM_B__A, FEC_OC_AVR_PARM_B__PRE, 0); 2865 if (rc != 0) { 2866 pr_err("error %d\n", rc); 2867 goto rw_error; 2868 } 2869 if (cfg_data->static_clk == true) { 2870 rc = drxj_dap_write_reg16(dev_addr, FEC_OC_RCN_GAIN__A, 0xD, 0); 2871 if (rc != 0) { 2872 pr_err("error %d\n", rc); 2873 goto rw_error; 2874 } 2875 } else { 2876 rc = drxj_dap_write_reg16(dev_addr, FEC_OC_RCN_GAIN__A, FEC_OC_RCN_GAIN__PRE, 0); 2877 if (rc != 0) { 2878 pr_err("error %d\n", rc); 2879 goto rw_error; 2880 } 2881 } 2882 rc = drxj_dap_write_reg16(dev_addr, FEC_OC_SNC_LWM__A, 2, 0); 2883 if (rc != 0) { 2884 pr_err("error %d\n", rc); 2885 goto rw_error; 2886 } 2887 rc = drxj_dap_write_reg16(dev_addr, FEC_OC_SNC_HWM__A, 12, 0); 2888 if (rc != 0) { 2889 pr_err("error %d\n", rc); 2890 goto rw_error; 2891 } 2892 break; 2893 default: 2894 break; 2895 } /* switch (standard) */ 2896 2897 /* Check insertion of the Reed-Solomon parity bytes */ 2898 rc = drxj_dap_read_reg16(dev_addr, FEC_OC_MODE__A, &fec_oc_reg_mode, 0); 2899 if (rc != 0) { 2900 pr_err("error %d\n", rc); 2901 goto rw_error; 2902 } 2903 rc = drxj_dap_read_reg16(dev_addr, FEC_OC_IPR_MODE__A, &fec_oc_reg_ipr_mode, 0); 2904 if (rc != 0) { 2905 pr_err("error %d\n", rc); 2906 goto rw_error; 2907 } 2908 if (cfg_data->insert_rs_byte == true) { 2909 /* enable parity symbol forward */ 2910 fec_oc_reg_mode |= FEC_OC_MODE_PARITY__M; 2911 /* MVAL disable during parity bytes */ 2912 fec_oc_reg_ipr_mode |= FEC_OC_IPR_MODE_MVAL_DIS_PAR__M; 2913 switch (ext_attr->standard) { 2914 case DRX_STANDARD_8VSB: 2915 rcn_rate = 0x004854D3; 2916 break; 2917 case DRX_STANDARD_ITU_B: 2918 fec_oc_reg_mode |= FEC_OC_MODE_TRANSPARENT__M; 2919 switch (ext_attr->constellation) { 2920 case DRX_CONSTELLATION_QAM256: 2921 rcn_rate = 0x008945E7; 2922 break; 2923 case DRX_CONSTELLATION_QAM64: 2924 rcn_rate = 0x005F64D4; 2925 break; 2926 default: 2927 return -EIO; 2928 } 2929 break; 2930 case DRX_STANDARD_ITU_A: 2931 case DRX_STANDARD_ITU_C: 2932 /* insert_rs_byte = true -> coef = 188/188 -> 1, RS bits are in MPEG output */ 2933 rcn_rate = 2934 (frac28 2935 (max_bit_rate, 2936 (u32) (common_attr->sys_clock_freq / 8))) / 2937 188; 2938 break; 2939 default: 2940 return -EIO; 2941 } /* ext_attr->standard */ 2942 } else { /* insert_rs_byte == false */ 2943 2944 /* disable parity symbol forward */ 2945 fec_oc_reg_mode &= (~FEC_OC_MODE_PARITY__M); 2946 /* MVAL enable during parity bytes */ 2947 fec_oc_reg_ipr_mode &= (~FEC_OC_IPR_MODE_MVAL_DIS_PAR__M); 2948 switch (ext_attr->standard) { 2949 case DRX_STANDARD_8VSB: 2950 rcn_rate = 0x0041605C; 2951 break; 2952 case DRX_STANDARD_ITU_B: 2953 fec_oc_reg_mode &= (~FEC_OC_MODE_TRANSPARENT__M); 2954 switch (ext_attr->constellation) { 2955 case DRX_CONSTELLATION_QAM256: 2956 rcn_rate = 0x0082D6A0; 2957 break; 2958 case DRX_CONSTELLATION_QAM64: 2959 rcn_rate = 0x005AEC1A; 2960 break; 2961 default: 2962 return -EIO; 2963 } 2964 break; 2965 case DRX_STANDARD_ITU_A: 2966 case DRX_STANDARD_ITU_C: 2967 /* insert_rs_byte = false -> coef = 188/204, RS bits not in MPEG output */ 2968 rcn_rate = 2969 (frac28 2970 (max_bit_rate, 2971 (u32) (common_attr->sys_clock_freq / 8))) / 2972 204; 2973 break; 2974 default: 2975 return -EIO; 2976 } /* ext_attr->standard */ 2977 } 2978 2979 if (cfg_data->enable_parallel == true) { /* MPEG data output is parallel -> clear ipr_mode[0] */ 2980 fec_oc_reg_ipr_mode &= (~(FEC_OC_IPR_MODE_SERIAL__M)); 2981 } else { /* MPEG data output is serial -> set ipr_mode[0] */ 2982 fec_oc_reg_ipr_mode |= FEC_OC_IPR_MODE_SERIAL__M; 2983 } 2984 2985 /* Control slective inversion of output bits */ 2986 if (cfg_data->invert_data == true) 2987 fec_oc_reg_ipr_invert |= invert_data_mask; 2988 else 2989 fec_oc_reg_ipr_invert &= (~(invert_data_mask)); 2990 2991 if (cfg_data->invert_err == true) 2992 fec_oc_reg_ipr_invert |= FEC_OC_IPR_INVERT_MERR__M; 2993 else 2994 fec_oc_reg_ipr_invert &= (~(FEC_OC_IPR_INVERT_MERR__M)); 2995 2996 if (cfg_data->invert_str == true) 2997 fec_oc_reg_ipr_invert |= FEC_OC_IPR_INVERT_MSTRT__M; 2998 else 2999 fec_oc_reg_ipr_invert &= (~(FEC_OC_IPR_INVERT_MSTRT__M)); 3000 3001 if (cfg_data->invert_val == true) 3002 fec_oc_reg_ipr_invert |= FEC_OC_IPR_INVERT_MVAL__M; 3003 else 3004 fec_oc_reg_ipr_invert &= (~(FEC_OC_IPR_INVERT_MVAL__M)); 3005 3006 if (cfg_data->invert_clk == true) 3007 fec_oc_reg_ipr_invert |= FEC_OC_IPR_INVERT_MCLK__M; 3008 else 3009 fec_oc_reg_ipr_invert &= (~(FEC_OC_IPR_INVERT_MCLK__M)); 3010 3011 3012 if (cfg_data->static_clk == true) { /* Static mode */ 3013 u32 dto_rate = 0; 3014 u32 bit_rate = 0; 3015 u16 fec_oc_dto_burst_len = 0; 3016 u16 fec_oc_dto_period = 0; 3017 3018 fec_oc_dto_burst_len = FEC_OC_DTO_BURST_LEN__PRE; 3019 3020 switch (ext_attr->standard) { 3021 case DRX_STANDARD_8VSB: 3022 fec_oc_dto_period = 4; 3023 if (cfg_data->insert_rs_byte == true) 3024 fec_oc_dto_burst_len = 208; 3025 break; 3026 case DRX_STANDARD_ITU_A: 3027 { 3028 u32 symbol_rate_th = 6400000; 3029 if (cfg_data->insert_rs_byte == true) { 3030 fec_oc_dto_burst_len = 204; 3031 symbol_rate_th = 5900000; 3032 } 3033 if (ext_attr->curr_symbol_rate >= 3034 symbol_rate_th) { 3035 fec_oc_dto_period = 0; 3036 } else { 3037 fec_oc_dto_period = 1; 3038 } 3039 } 3040 break; 3041 case DRX_STANDARD_ITU_B: 3042 fec_oc_dto_period = 1; 3043 if (cfg_data->insert_rs_byte == true) 3044 fec_oc_dto_burst_len = 128; 3045 break; 3046 case DRX_STANDARD_ITU_C: 3047 fec_oc_dto_period = 1; 3048 if (cfg_data->insert_rs_byte == true) 3049 fec_oc_dto_burst_len = 204; 3050 break; 3051 default: 3052 return -EIO; 3053 } 3054 bit_rate = 3055 common_attr->sys_clock_freq * 1000 / (fec_oc_dto_period + 3056 2); 3057 dto_rate = 3058 frac28(bit_rate, common_attr->sys_clock_freq * 1000); 3059 dto_rate >>= 3; 3060 rc = drxj_dap_write_reg16(dev_addr, FEC_OC_DTO_RATE_HI__A, (u16)((dto_rate >> 16) & FEC_OC_DTO_RATE_HI__M), 0); 3061 if (rc != 0) { 3062 pr_err("error %d\n", rc); 3063 goto rw_error; 3064 } 3065 rc = drxj_dap_write_reg16(dev_addr, FEC_OC_DTO_RATE_LO__A, (u16)(dto_rate & FEC_OC_DTO_RATE_LO_RATE_LO__M), 0); 3066 if (rc != 0) { 3067 pr_err("error %d\n", rc); 3068 goto rw_error; 3069 } 3070 rc = drxj_dap_write_reg16(dev_addr, FEC_OC_DTO_MODE__A, FEC_OC_DTO_MODE_DYNAMIC__M | FEC_OC_DTO_MODE_OFFSET_ENABLE__M, 0); 3071 if (rc != 0) { 3072 pr_err("error %d\n", rc); 3073 goto rw_error; 3074 } 3075 rc = drxj_dap_write_reg16(dev_addr, FEC_OC_FCT_MODE__A, FEC_OC_FCT_MODE_RAT_ENA__M | FEC_OC_FCT_MODE_VIRT_ENA__M, 0); 3076 if (rc != 0) { 3077 pr_err("error %d\n", rc); 3078 goto rw_error; 3079 } 3080 rc = drxj_dap_write_reg16(dev_addr, FEC_OC_DTO_BURST_LEN__A, fec_oc_dto_burst_len, 0); 3081 if (rc != 0) { 3082 pr_err("error %d\n", rc); 3083 goto rw_error; 3084 } 3085 if (ext_attr->mpeg_output_clock_rate != DRXJ_MPEGOUTPUT_CLOCK_RATE_AUTO) 3086 fec_oc_dto_period = ext_attr->mpeg_output_clock_rate - 1; 3087 rc = drxj_dap_write_reg16(dev_addr, FEC_OC_DTO_PERIOD__A, fec_oc_dto_period, 0); 3088 if (rc != 0) { 3089 pr_err("error %d\n", rc); 3090 goto rw_error; 3091 } 3092 } else { /* Dynamic mode */ 3093 3094 rc = drxj_dap_write_reg16(dev_addr, FEC_OC_DTO_MODE__A, FEC_OC_DTO_MODE_DYNAMIC__M, 0); 3095 if (rc != 0) { 3096 pr_err("error %d\n", rc); 3097 goto rw_error; 3098 } 3099 rc = drxj_dap_write_reg16(dev_addr, FEC_OC_FCT_MODE__A, 0, 0); 3100 if (rc != 0) { 3101 pr_err("error %d\n", rc); 3102 goto rw_error; 3103 } 3104 } 3105 3106 rc = drxdap_fasi_write_reg32(dev_addr, FEC_OC_RCN_CTL_RATE_LO__A, rcn_rate, 0); 3107 if (rc != 0) { 3108 pr_err("error %d\n", rc); 3109 goto rw_error; 3110 } 3111 3112 /* Write appropriate registers with requested configuration */ 3113 rc = drxj_dap_write_reg16(dev_addr, FEC_OC_MODE__A, fec_oc_reg_mode, 0); 3114 if (rc != 0) { 3115 pr_err("error %d\n", rc); 3116 goto rw_error; 3117 } 3118 rc = drxj_dap_write_reg16(dev_addr, FEC_OC_IPR_MODE__A, fec_oc_reg_ipr_mode, 0); 3119 if (rc != 0) { 3120 pr_err("error %d\n", rc); 3121 goto rw_error; 3122 } 3123 rc = drxj_dap_write_reg16(dev_addr, FEC_OC_IPR_INVERT__A, fec_oc_reg_ipr_invert, 0); 3124 if (rc != 0) { 3125 pr_err("error %d\n", rc); 3126 goto rw_error; 3127 } 3128 3129 /* enabling for both parallel and serial now */ 3130 /* Write magic word to enable pdr reg write */ 3131 rc = drxj_dap_write_reg16(dev_addr, SIO_TOP_COMM_KEY__A, 0xFABA, 0); 3132 if (rc != 0) { 3133 pr_err("error %d\n", rc); 3134 goto rw_error; 3135 } 3136 /* Set MPEG TS pads to outputmode */ 3137 rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MSTRT_CFG__A, 0x0013, 0); 3138 if (rc != 0) { 3139 pr_err("error %d\n", rc); 3140 goto rw_error; 3141 } 3142 rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MERR_CFG__A, 0x0013, 0); 3143 if (rc != 0) { 3144 pr_err("error %d\n", rc); 3145 goto rw_error; 3146 } 3147 rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MCLK_CFG__A, MPEG_OUTPUT_CLK_DRIVE_STRENGTH << SIO_PDR_MCLK_CFG_DRIVE__B | 0x03 << SIO_PDR_MCLK_CFG_MODE__B, 0); 3148 if (rc != 0) { 3149 pr_err("error %d\n", rc); 3150 goto rw_error; 3151 } 3152 rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MVAL_CFG__A, 0x0013, 0); 3153 if (rc != 0) { 3154 pr_err("error %d\n", rc); 3155 goto rw_error; 3156 } 3157 sio_pdr_md_cfg = 3158 MPEG_SERIAL_OUTPUT_PIN_DRIVE_STRENGTH << 3159 SIO_PDR_MD0_CFG_DRIVE__B | 0x03 << SIO_PDR_MD0_CFG_MODE__B; 3160 rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MD0_CFG__A, sio_pdr_md_cfg, 0); 3161 if (rc != 0) { 3162 pr_err("error %d\n", rc); 3163 goto rw_error; 3164 } 3165 if (cfg_data->enable_parallel == true) { /* MPEG data output is parallel -> set MD1 to MD7 to output mode */ 3166 sio_pdr_md_cfg = 3167 MPEG_PARALLEL_OUTPUT_PIN_DRIVE_STRENGTH << 3168 SIO_PDR_MD0_CFG_DRIVE__B | 0x03 << 3169 SIO_PDR_MD0_CFG_MODE__B; 3170 rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MD0_CFG__A, sio_pdr_md_cfg, 0); 3171 if (rc != 0) { 3172 pr_err("error %d\n", rc); 3173 goto rw_error; 3174 } 3175 rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MD1_CFG__A, sio_pdr_md_cfg, 0); 3176 if (rc != 0) { 3177 pr_err("error %d\n", rc); 3178 goto rw_error; 3179 } 3180 rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MD2_CFG__A, sio_pdr_md_cfg, 0); 3181 if (rc != 0) { 3182 pr_err("error %d\n", rc); 3183 goto rw_error; 3184 } 3185 rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MD3_CFG__A, sio_pdr_md_cfg, 0); 3186 if (rc != 0) { 3187 pr_err("error %d\n", rc); 3188 goto rw_error; 3189 } 3190 rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MD4_CFG__A, sio_pdr_md_cfg, 0); 3191 if (rc != 0) { 3192 pr_err("error %d\n", rc); 3193 goto rw_error; 3194 } 3195 rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MD5_CFG__A, sio_pdr_md_cfg, 0); 3196 if (rc != 0) { 3197 pr_err("error %d\n", rc); 3198 goto rw_error; 3199 } 3200 rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MD6_CFG__A, sio_pdr_md_cfg, 0); 3201 if (rc != 0) { 3202 pr_err("error %d\n", rc); 3203 goto rw_error; 3204 } 3205 rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MD7_CFG__A, sio_pdr_md_cfg, 0); 3206 if (rc != 0) { 3207 pr_err("error %d\n", rc); 3208 goto rw_error; 3209 } 3210 } else { /* MPEG data output is serial -> set MD1 to MD7 to tri-state */ 3211 rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MD1_CFG__A, 0x0000, 0); 3212 if (rc != 0) { 3213 pr_err("error %d\n", rc); 3214 goto rw_error; 3215 } 3216 rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MD2_CFG__A, 0x0000, 0); 3217 if (rc != 0) { 3218 pr_err("error %d\n", rc); 3219 goto rw_error; 3220 } 3221 rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MD3_CFG__A, 0x0000, 0); 3222 if (rc != 0) { 3223 pr_err("error %d\n", rc); 3224 goto rw_error; 3225 } 3226 rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MD4_CFG__A, 0x0000, 0); 3227 if (rc != 0) { 3228 pr_err("error %d\n", rc); 3229 goto rw_error; 3230 } 3231 rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MD5_CFG__A, 0x0000, 0); 3232 if (rc != 0) { 3233 pr_err("error %d\n", rc); 3234 goto rw_error; 3235 } 3236 rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MD6_CFG__A, 0x0000, 0); 3237 if (rc != 0) { 3238 pr_err("error %d\n", rc); 3239 goto rw_error; 3240 } 3241 rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MD7_CFG__A, 0x0000, 0); 3242 if (rc != 0) { 3243 pr_err("error %d\n", rc); 3244 goto rw_error; 3245 } 3246 } 3247 /* Enable Monitor Bus output over MPEG pads and ctl input */ 3248 rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MON_CFG__A, 0x0000, 0); 3249 if (rc != 0) { 3250 pr_err("error %d\n", rc); 3251 goto rw_error; 3252 } 3253 /* Write nomagic word to enable pdr reg write */ 3254 rc = drxj_dap_write_reg16(dev_addr, SIO_TOP_COMM_KEY__A, 0x0000, 0); 3255 if (rc != 0) { 3256 pr_err("error %d\n", rc); 3257 goto rw_error; 3258 } 3259 } else { 3260 /* Write magic word to enable pdr reg write */ 3261 rc = drxj_dap_write_reg16(dev_addr, SIO_TOP_COMM_KEY__A, 0xFABA, 0); 3262 if (rc != 0) { 3263 pr_err("error %d\n", rc); 3264 goto rw_error; 3265 } 3266 /* Set MPEG TS pads to inputmode */ 3267 rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MSTRT_CFG__A, 0x0000, 0); 3268 if (rc != 0) { 3269 pr_err("error %d\n", rc); 3270 goto rw_error; 3271 } 3272 rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MERR_CFG__A, 0x0000, 0); 3273 if (rc != 0) { 3274 pr_err("error %d\n", rc); 3275 goto rw_error; 3276 } 3277 rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MCLK_CFG__A, 0x0000, 0); 3278 if (rc != 0) { 3279 pr_err("error %d\n", rc); 3280 goto rw_error; 3281 } 3282 rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MVAL_CFG__A, 0x0000, 0); 3283 if (rc != 0) { 3284 pr_err("error %d\n", rc); 3285 goto rw_error; 3286 } 3287 rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MD0_CFG__A, 0x0000, 0); 3288 if (rc != 0) { 3289 pr_err("error %d\n", rc); 3290 goto rw_error; 3291 } 3292 rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MD1_CFG__A, 0x0000, 0); 3293 if (rc != 0) { 3294 pr_err("error %d\n", rc); 3295 goto rw_error; 3296 } 3297 rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MD2_CFG__A, 0x0000, 0); 3298 if (rc != 0) { 3299 pr_err("error %d\n", rc); 3300 goto rw_error; 3301 } 3302 rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MD3_CFG__A, 0x0000, 0); 3303 if (rc != 0) { 3304 pr_err("error %d\n", rc); 3305 goto rw_error; 3306 } 3307 rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MD4_CFG__A, 0x0000, 0); 3308 if (rc != 0) { 3309 pr_err("error %d\n", rc); 3310 goto rw_error; 3311 } 3312 rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MD5_CFG__A, 0x0000, 0); 3313 if (rc != 0) { 3314 pr_err("error %d\n", rc); 3315 goto rw_error; 3316 } 3317 rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MD6_CFG__A, 0x0000, 0); 3318 if (rc != 0) { 3319 pr_err("error %d\n", rc); 3320 goto rw_error; 3321 } 3322 rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MD7_CFG__A, 0x0000, 0); 3323 if (rc != 0) { 3324 pr_err("error %d\n", rc); 3325 goto rw_error; 3326 } 3327 /* Enable Monitor Bus output over MPEG pads and ctl input */ 3328 rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MON_CFG__A, 0x0000, 0); 3329 if (rc != 0) { 3330 pr_err("error %d\n", rc); 3331 goto rw_error; 3332 } 3333 /* Write nomagic word to enable pdr reg write */ 3334 rc = drxj_dap_write_reg16(dev_addr, SIO_TOP_COMM_KEY__A, 0x0000, 0); 3335 if (rc != 0) { 3336 pr_err("error %d\n", rc); 3337 goto rw_error; 3338 } 3339 } 3340 3341 /* save values for restore after re-acquire */ 3342 common_attr->mpeg_cfg.enable_mpeg_output = cfg_data->enable_mpeg_output; 3343 3344 return 0; 3345 rw_error: 3346 return rc; 3347 } 3348 3349 /*----------------------------------------------------------------------------*/ 3350 3351 3352 /*----------------------------------------------------------------------------*/ 3353 /* MPEG Output Configuration Functions - end */ 3354 /*----------------------------------------------------------------------------*/ 3355 3356 /*----------------------------------------------------------------------------*/ 3357 /* miscellaneous configurations - begin */ 3358 /*----------------------------------------------------------------------------*/ 3359 3360 /* 3361 * \fn int set_mpegtei_handling() 3362 * \brief Activate MPEG TEI handling settings. 3363 * \param devmod Pointer to demodulator instance. 3364 * \return int. 3365 * 3366 * This routine should be called during a set channel of QAM/VSB 3367 * 3368 */ 3369 static int set_mpegtei_handling(struct drx_demod_instance *demod) 3370 { 3371 struct drxj_data *ext_attr = (struct drxj_data *) (NULL); 3372 struct i2c_device_addr *dev_addr = (struct i2c_device_addr *)(NULL); 3373 int rc; 3374 u16 fec_oc_dpr_mode = 0; 3375 u16 fec_oc_snc_mode = 0; 3376 u16 fec_oc_ems_mode = 0; 3377 3378 dev_addr = demod->my_i2c_dev_addr; 3379 ext_attr = (struct drxj_data *) demod->my_ext_attr; 3380 3381 rc = drxj_dap_read_reg16(dev_addr, FEC_OC_DPR_MODE__A, &fec_oc_dpr_mode, 0); 3382 if (rc != 0) { 3383 pr_err("error %d\n", rc); 3384 goto rw_error; 3385 } 3386 rc = drxj_dap_read_reg16(dev_addr, FEC_OC_SNC_MODE__A, &fec_oc_snc_mode, 0); 3387 if (rc != 0) { 3388 pr_err("error %d\n", rc); 3389 goto rw_error; 3390 } 3391 rc = drxj_dap_read_reg16(dev_addr, FEC_OC_EMS_MODE__A, &fec_oc_ems_mode, 0); 3392 if (rc != 0) { 3393 pr_err("error %d\n", rc); 3394 goto rw_error; 3395 } 3396 3397 /* reset to default, allow TEI bit to be changed */ 3398 fec_oc_dpr_mode &= (~FEC_OC_DPR_MODE_ERR_DISABLE__M); 3399 fec_oc_snc_mode &= (~(FEC_OC_SNC_MODE_ERROR_CTL__M | 3400 FEC_OC_SNC_MODE_CORR_DISABLE__M)); 3401 fec_oc_ems_mode &= (~FEC_OC_EMS_MODE_MODE__M); 3402 3403 if (ext_attr->disable_te_ihandling) { 3404 /* do not change TEI bit */ 3405 fec_oc_dpr_mode |= FEC_OC_DPR_MODE_ERR_DISABLE__M; 3406 fec_oc_snc_mode |= FEC_OC_SNC_MODE_CORR_DISABLE__M | 3407 ((0x2) << (FEC_OC_SNC_MODE_ERROR_CTL__B)); 3408 fec_oc_ems_mode |= ((0x01) << (FEC_OC_EMS_MODE_MODE__B)); 3409 } 3410 3411 rc = drxj_dap_write_reg16(dev_addr, FEC_OC_DPR_MODE__A, fec_oc_dpr_mode, 0); 3412 if (rc != 0) { 3413 pr_err("error %d\n", rc); 3414 goto rw_error; 3415 } 3416 rc = drxj_dap_write_reg16(dev_addr, FEC_OC_SNC_MODE__A, fec_oc_snc_mode, 0); 3417 if (rc != 0) { 3418 pr_err("error %d\n", rc); 3419 goto rw_error; 3420 } 3421 rc = drxj_dap_write_reg16(dev_addr, FEC_OC_EMS_MODE__A, fec_oc_ems_mode, 0); 3422 if (rc != 0) { 3423 pr_err("error %d\n", rc); 3424 goto rw_error; 3425 } 3426 3427 return 0; 3428 rw_error: 3429 return rc; 3430 } 3431 3432 /*----------------------------------------------------------------------------*/ 3433 /* 3434 * \fn int bit_reverse_mpeg_output() 3435 * \brief Set MPEG output bit-endian settings. 3436 * \param devmod Pointer to demodulator instance. 3437 * \return int. 3438 * 3439 * This routine should be called during a set channel of QAM/VSB 3440 * 3441 */ 3442 static int bit_reverse_mpeg_output(struct drx_demod_instance *demod) 3443 { 3444 struct drxj_data *ext_attr = (struct drxj_data *) (NULL); 3445 struct i2c_device_addr *dev_addr = (struct i2c_device_addr *)(NULL); 3446 int rc; 3447 u16 fec_oc_ipr_mode = 0; 3448 3449 dev_addr = demod->my_i2c_dev_addr; 3450 ext_attr = (struct drxj_data *) demod->my_ext_attr; 3451 3452 rc = drxj_dap_read_reg16(dev_addr, FEC_OC_IPR_MODE__A, &fec_oc_ipr_mode, 0); 3453 if (rc != 0) { 3454 pr_err("error %d\n", rc); 3455 goto rw_error; 3456 } 3457 3458 /* reset to default (normal bit order) */ 3459 fec_oc_ipr_mode &= (~FEC_OC_IPR_MODE_REVERSE_ORDER__M); 3460 3461 if (ext_attr->bit_reverse_mpeg_outout) 3462 fec_oc_ipr_mode |= FEC_OC_IPR_MODE_REVERSE_ORDER__M; 3463 3464 rc = drxj_dap_write_reg16(dev_addr, FEC_OC_IPR_MODE__A, fec_oc_ipr_mode, 0); 3465 if (rc != 0) { 3466 pr_err("error %d\n", rc); 3467 goto rw_error; 3468 } 3469 3470 return 0; 3471 rw_error: 3472 return rc; 3473 } 3474 3475 /*----------------------------------------------------------------------------*/ 3476 /* 3477 * \fn int set_mpeg_start_width() 3478 * \brief Set MPEG start width. 3479 * \param devmod Pointer to demodulator instance. 3480 * \return int. 3481 * 3482 * This routine should be called during a set channel of QAM/VSB 3483 * 3484 */ 3485 static int set_mpeg_start_width(struct drx_demod_instance *demod) 3486 { 3487 struct drxj_data *ext_attr = (struct drxj_data *) (NULL); 3488 struct i2c_device_addr *dev_addr = (struct i2c_device_addr *)(NULL); 3489 struct drx_common_attr *common_attr = (struct drx_common_attr *) NULL; 3490 int rc; 3491 u16 fec_oc_comm_mb = 0; 3492 3493 dev_addr = demod->my_i2c_dev_addr; 3494 ext_attr = (struct drxj_data *) demod->my_ext_attr; 3495 common_attr = demod->my_common_attr; 3496 3497 if ((common_attr->mpeg_cfg.static_clk == true) 3498 && (common_attr->mpeg_cfg.enable_parallel == false)) { 3499 rc = drxj_dap_read_reg16(dev_addr, FEC_OC_COMM_MB__A, &fec_oc_comm_mb, 0); 3500 if (rc != 0) { 3501 pr_err("error %d\n", rc); 3502 goto rw_error; 3503 } 3504 fec_oc_comm_mb &= ~FEC_OC_COMM_MB_CTL_ON; 3505 if (ext_attr->mpeg_start_width == DRXJ_MPEG_START_WIDTH_8CLKCYC) 3506 fec_oc_comm_mb |= FEC_OC_COMM_MB_CTL_ON; 3507 rc = drxj_dap_write_reg16(dev_addr, FEC_OC_COMM_MB__A, fec_oc_comm_mb, 0); 3508 if (rc != 0) { 3509 pr_err("error %d\n", rc); 3510 goto rw_error; 3511 } 3512 } 3513 3514 return 0; 3515 rw_error: 3516 return rc; 3517 } 3518 3519 /*----------------------------------------------------------------------------*/ 3520 /* miscellaneous configurations - end */ 3521 /*----------------------------------------------------------------------------*/ 3522 3523 /*----------------------------------------------------------------------------*/ 3524 /* UIO Configuration Functions - begin */ 3525 /*----------------------------------------------------------------------------*/ 3526 /* 3527 * \fn int ctrl_set_uio_cfg() 3528 * \brief Configure modus oprandi UIO. 3529 * \param demod Pointer to demodulator instance. 3530 * \param uio_cfg Pointer to a configuration setting for a certain UIO. 3531 * \return int. 3532 */ 3533 static int ctrl_set_uio_cfg(struct drx_demod_instance *demod, struct drxuio_cfg *uio_cfg) 3534 { 3535 struct drxj_data *ext_attr = (struct drxj_data *) (NULL); 3536 int rc; 3537 3538 if ((uio_cfg == NULL) || (demod == NULL)) 3539 return -EINVAL; 3540 3541 ext_attr = (struct drxj_data *) demod->my_ext_attr; 3542 3543 /* Write magic word to enable pdr reg write */ 3544 rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, SIO_TOP_COMM_KEY__A, SIO_TOP_COMM_KEY_KEY, 0); 3545 if (rc != 0) { 3546 pr_err("error %d\n", rc); 3547 goto rw_error; 3548 } 3549 switch (uio_cfg->uio) { 3550 /*====================================================================*/ 3551 case DRX_UIO1: 3552 /* DRX_UIO1: SMA_TX UIO-1 */ 3553 if (!ext_attr->has_smatx) 3554 return -EIO; 3555 switch (uio_cfg->mode) { 3556 case DRX_UIO_MODE_FIRMWARE_SMA: 3557 case DRX_UIO_MODE_FIRMWARE_SAW: 3558 case DRX_UIO_MODE_READWRITE: 3559 ext_attr->uio_sma_tx_mode = uio_cfg->mode; 3560 break; 3561 case DRX_UIO_MODE_DISABLE: 3562 ext_attr->uio_sma_tx_mode = uio_cfg->mode; 3563 /* pad configuration register is set 0 - input mode */ 3564 rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, SIO_PDR_SMA_TX_CFG__A, 0, 0); 3565 if (rc != 0) { 3566 pr_err("error %d\n", rc); 3567 goto rw_error; 3568 } 3569 break; 3570 default: 3571 return -EINVAL; 3572 } /* switch ( uio_cfg->mode ) */ 3573 break; 3574 /*====================================================================*/ 3575 case DRX_UIO2: 3576 /* DRX_UIO2: SMA_RX UIO-2 */ 3577 if (!ext_attr->has_smarx) 3578 return -EIO; 3579 switch (uio_cfg->mode) { 3580 case DRX_UIO_MODE_FIRMWARE0: 3581 case DRX_UIO_MODE_READWRITE: 3582 ext_attr->uio_sma_rx_mode = uio_cfg->mode; 3583 break; 3584 case DRX_UIO_MODE_DISABLE: 3585 ext_attr->uio_sma_rx_mode = uio_cfg->mode; 3586 /* pad configuration register is set 0 - input mode */ 3587 rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, SIO_PDR_SMA_RX_CFG__A, 0, 0); 3588 if (rc != 0) { 3589 pr_err("error %d\n", rc); 3590 goto rw_error; 3591 } 3592 break; 3593 default: 3594 return -EINVAL; 3595 } /* switch ( uio_cfg->mode ) */ 3596 break; 3597 /*====================================================================*/ 3598 case DRX_UIO3: 3599 /* DRX_UIO3: GPIO UIO-3 */ 3600 if (!ext_attr->has_gpio) 3601 return -EIO; 3602 switch (uio_cfg->mode) { 3603 case DRX_UIO_MODE_FIRMWARE0: 3604 case DRX_UIO_MODE_READWRITE: 3605 ext_attr->uio_gpio_mode = uio_cfg->mode; 3606 break; 3607 case DRX_UIO_MODE_DISABLE: 3608 ext_attr->uio_gpio_mode = uio_cfg->mode; 3609 /* pad configuration register is set 0 - input mode */ 3610 rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, SIO_PDR_GPIO_CFG__A, 0, 0); 3611 if (rc != 0) { 3612 pr_err("error %d\n", rc); 3613 goto rw_error; 3614 } 3615 break; 3616 default: 3617 return -EINVAL; 3618 } /* switch ( uio_cfg->mode ) */ 3619 break; 3620 /*====================================================================*/ 3621 case DRX_UIO4: 3622 /* DRX_UIO4: IRQN UIO-4 */ 3623 if (!ext_attr->has_irqn) 3624 return -EIO; 3625 switch (uio_cfg->mode) { 3626 case DRX_UIO_MODE_READWRITE: 3627 ext_attr->uio_irqn_mode = uio_cfg->mode; 3628 break; 3629 case DRX_UIO_MODE_DISABLE: 3630 /* pad configuration register is set 0 - input mode */ 3631 rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, SIO_PDR_IRQN_CFG__A, 0, 0); 3632 if (rc != 0) { 3633 pr_err("error %d\n", rc); 3634 goto rw_error; 3635 } 3636 ext_attr->uio_irqn_mode = uio_cfg->mode; 3637 break; 3638 case DRX_UIO_MODE_FIRMWARE0: 3639 default: 3640 return -EINVAL; 3641 } /* switch ( uio_cfg->mode ) */ 3642 break; 3643 /*====================================================================*/ 3644 default: 3645 return -EINVAL; 3646 } /* switch ( uio_cfg->uio ) */ 3647 3648 /* Write magic word to disable pdr reg write */ 3649 rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, SIO_TOP_COMM_KEY__A, 0x0000, 0); 3650 if (rc != 0) { 3651 pr_err("error %d\n", rc); 3652 goto rw_error; 3653 } 3654 3655 return 0; 3656 rw_error: 3657 return rc; 3658 } 3659 3660 /* 3661 * \fn int ctrl_uio_write() 3662 * \brief Write to a UIO. 3663 * \param demod Pointer to demodulator instance. 3664 * \param uio_data Pointer to data container for a certain UIO. 3665 * \return int. 3666 */ 3667 static int 3668 ctrl_uio_write(struct drx_demod_instance *demod, struct drxuio_data *uio_data) 3669 { 3670 struct drxj_data *ext_attr = (struct drxj_data *) (NULL); 3671 int rc; 3672 u16 pin_cfg_value = 0; 3673 u16 value = 0; 3674 3675 if ((uio_data == NULL) || (demod == NULL)) 3676 return -EINVAL; 3677 3678 ext_attr = (struct drxj_data *) demod->my_ext_attr; 3679 3680 /* Write magic word to enable pdr reg write */ 3681 rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, SIO_TOP_COMM_KEY__A, SIO_TOP_COMM_KEY_KEY, 0); 3682 if (rc != 0) { 3683 pr_err("error %d\n", rc); 3684 goto rw_error; 3685 } 3686 switch (uio_data->uio) { 3687 /*====================================================================*/ 3688 case DRX_UIO1: 3689 /* DRX_UIO1: SMA_TX UIO-1 */ 3690 if (!ext_attr->has_smatx) 3691 return -EIO; 3692 if ((ext_attr->uio_sma_tx_mode != DRX_UIO_MODE_READWRITE) 3693 && (ext_attr->uio_sma_tx_mode != DRX_UIO_MODE_FIRMWARE_SAW)) { 3694 return -EIO; 3695 } 3696 pin_cfg_value = 0; 3697 /* io_pad_cfg register (8 bit reg.) MSB bit is 1 (default value) */ 3698 pin_cfg_value |= 0x0113; 3699 /* io_pad_cfg_mode output mode is drive always */ 3700 /* io_pad_cfg_drive is set to power 2 (23 mA) */ 3701 3702 /* write to io pad configuration register - output mode */ 3703 rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, SIO_PDR_SMA_TX_CFG__A, pin_cfg_value, 0); 3704 if (rc != 0) { 3705 pr_err("error %d\n", rc); 3706 goto rw_error; 3707 } 3708 3709 /* use corresponding bit in io data output registar */ 3710 rc = drxj_dap_read_reg16(demod->my_i2c_dev_addr, SIO_PDR_UIO_OUT_LO__A, &value, 0); 3711 if (rc != 0) { 3712 pr_err("error %d\n", rc); 3713 goto rw_error; 3714 } 3715 if (!uio_data->value) 3716 value &= 0x7FFF; /* write zero to 15th bit - 1st UIO */ 3717 else 3718 value |= 0x8000; /* write one to 15th bit - 1st UIO */ 3719 3720 /* write back to io data output register */ 3721 rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, SIO_PDR_UIO_OUT_LO__A, value, 0); 3722 if (rc != 0) { 3723 pr_err("error %d\n", rc); 3724 goto rw_error; 3725 } 3726 break; 3727 /*======================================================================*/ 3728 case DRX_UIO2: 3729 /* DRX_UIO2: SMA_RX UIO-2 */ 3730 if (!ext_attr->has_smarx) 3731 return -EIO; 3732 if (ext_attr->uio_sma_rx_mode != DRX_UIO_MODE_READWRITE) 3733 return -EIO; 3734 3735 pin_cfg_value = 0; 3736 /* io_pad_cfg register (8 bit reg.) MSB bit is 1 (default value) */ 3737 pin_cfg_value |= 0x0113; 3738 /* io_pad_cfg_mode output mode is drive always */ 3739 /* io_pad_cfg_drive is set to power 2 (23 mA) */ 3740 3741 /* write to io pad configuration register - output mode */ 3742 rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, SIO_PDR_SMA_RX_CFG__A, pin_cfg_value, 0); 3743 if (rc != 0) { 3744 pr_err("error %d\n", rc); 3745 goto rw_error; 3746 } 3747 3748 /* use corresponding bit in io data output registar */ 3749 rc = drxj_dap_read_reg16(demod->my_i2c_dev_addr, SIO_PDR_UIO_OUT_LO__A, &value, 0); 3750 if (rc != 0) { 3751 pr_err("error %d\n", rc); 3752 goto rw_error; 3753 } 3754 if (!uio_data->value) 3755 value &= 0xBFFF; /* write zero to 14th bit - 2nd UIO */ 3756 else 3757 value |= 0x4000; /* write one to 14th bit - 2nd UIO */ 3758 3759 /* write back to io data output register */ 3760 rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, SIO_PDR_UIO_OUT_LO__A, value, 0); 3761 if (rc != 0) { 3762 pr_err("error %d\n", rc); 3763 goto rw_error; 3764 } 3765 break; 3766 /*====================================================================*/ 3767 case DRX_UIO3: 3768 /* DRX_UIO3: ASEL UIO-3 */ 3769 if (!ext_attr->has_gpio) 3770 return -EIO; 3771 if (ext_attr->uio_gpio_mode != DRX_UIO_MODE_READWRITE) 3772 return -EIO; 3773 3774 pin_cfg_value = 0; 3775 /* io_pad_cfg register (8 bit reg.) MSB bit is 1 (default value) */ 3776 pin_cfg_value |= 0x0113; 3777 /* io_pad_cfg_mode output mode is drive always */ 3778 /* io_pad_cfg_drive is set to power 2 (23 mA) */ 3779 3780 /* write to io pad configuration register - output mode */ 3781 rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, SIO_PDR_GPIO_CFG__A, pin_cfg_value, 0); 3782 if (rc != 0) { 3783 pr_err("error %d\n", rc); 3784 goto rw_error; 3785 } 3786 3787 /* use corresponding bit in io data output registar */ 3788 rc = drxj_dap_read_reg16(demod->my_i2c_dev_addr, SIO_PDR_UIO_OUT_HI__A, &value, 0); 3789 if (rc != 0) { 3790 pr_err("error %d\n", rc); 3791 goto rw_error; 3792 } 3793 if (!uio_data->value) 3794 value &= 0xFFFB; /* write zero to 2nd bit - 3rd UIO */ 3795 else 3796 value |= 0x0004; /* write one to 2nd bit - 3rd UIO */ 3797 3798 /* write back to io data output register */ 3799 rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, SIO_PDR_UIO_OUT_HI__A, value, 0); 3800 if (rc != 0) { 3801 pr_err("error %d\n", rc); 3802 goto rw_error; 3803 } 3804 break; 3805 /*=====================================================================*/ 3806 case DRX_UIO4: 3807 /* DRX_UIO4: IRQN UIO-4 */ 3808 if (!ext_attr->has_irqn) 3809 return -EIO; 3810 3811 if (ext_attr->uio_irqn_mode != DRX_UIO_MODE_READWRITE) 3812 return -EIO; 3813 3814 pin_cfg_value = 0; 3815 /* io_pad_cfg register (8 bit reg.) MSB bit is 1 (default value) */ 3816 pin_cfg_value |= 0x0113; 3817 /* io_pad_cfg_mode output mode is drive always */ 3818 /* io_pad_cfg_drive is set to power 2 (23 mA) */ 3819 3820 /* write to io pad configuration register - output mode */ 3821 rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, SIO_PDR_IRQN_CFG__A, pin_cfg_value, 0); 3822 if (rc != 0) { 3823 pr_err("error %d\n", rc); 3824 goto rw_error; 3825 } 3826 3827 /* use corresponding bit in io data output registar */ 3828 rc = drxj_dap_read_reg16(demod->my_i2c_dev_addr, SIO_PDR_UIO_OUT_LO__A, &value, 0); 3829 if (rc != 0) { 3830 pr_err("error %d\n", rc); 3831 goto rw_error; 3832 } 3833 if (uio_data->value == false) 3834 value &= 0xEFFF; /* write zero to 12th bit - 4th UIO */ 3835 else 3836 value |= 0x1000; /* write one to 12th bit - 4th UIO */ 3837 3838 /* write back to io data output register */ 3839 rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, SIO_PDR_UIO_OUT_LO__A, value, 0); 3840 if (rc != 0) { 3841 pr_err("error %d\n", rc); 3842 goto rw_error; 3843 } 3844 break; 3845 /*=====================================================================*/ 3846 default: 3847 return -EINVAL; 3848 } /* switch ( uio_data->uio ) */ 3849 3850 /* Write magic word to disable pdr reg write */ 3851 rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, SIO_TOP_COMM_KEY__A, 0x0000, 0); 3852 if (rc != 0) { 3853 pr_err("error %d\n", rc); 3854 goto rw_error; 3855 } 3856 3857 return 0; 3858 rw_error: 3859 return rc; 3860 } 3861 3862 /*---------------------------------------------------------------------------*/ 3863 /* UIO Configuration Functions - end */ 3864 /*---------------------------------------------------------------------------*/ 3865 3866 /*----------------------------------------------------------------------------*/ 3867 /* I2C Bridge Functions - begin */ 3868 /*----------------------------------------------------------------------------*/ 3869 /* 3870 * \fn int ctrl_i2c_bridge() 3871 * \brief Open or close the I2C switch to tuner. 3872 * \param demod Pointer to demodulator instance. 3873 * \param bridge_closed Pointer to bool indication if bridge is closed not. 3874 * \return int. 3875 3876 */ 3877 static int 3878 ctrl_i2c_bridge(struct drx_demod_instance *demod, bool *bridge_closed) 3879 { 3880 struct drxj_hi_cmd hi_cmd; 3881 u16 result = 0; 3882 3883 /* check arguments */ 3884 if (bridge_closed == NULL) 3885 return -EINVAL; 3886 3887 hi_cmd.cmd = SIO_HI_RA_RAM_CMD_BRDCTRL; 3888 hi_cmd.param1 = SIO_HI_RA_RAM_PAR_1_PAR1_SEC_KEY; 3889 if (*bridge_closed) 3890 hi_cmd.param2 = SIO_HI_RA_RAM_PAR_2_BRD_CFG_CLOSED; 3891 else 3892 hi_cmd.param2 = SIO_HI_RA_RAM_PAR_2_BRD_CFG_OPEN; 3893 3894 return hi_command(demod->my_i2c_dev_addr, &hi_cmd, &result); 3895 } 3896 3897 /*----------------------------------------------------------------------------*/ 3898 /* I2C Bridge Functions - end */ 3899 /*----------------------------------------------------------------------------*/ 3900 3901 /*----------------------------------------------------------------------------*/ 3902 /* Smart antenna Functions - begin */ 3903 /*----------------------------------------------------------------------------*/ 3904 /* 3905 * \fn int smart_ant_init() 3906 * \brief Initialize Smart Antenna. 3907 * \param pointer to struct drx_demod_instance. 3908 * \return int. 3909 * 3910 */ 3911 static int smart_ant_init(struct drx_demod_instance *demod) 3912 { 3913 struct drxj_data *ext_attr = NULL; 3914 struct i2c_device_addr *dev_addr = NULL; 3915 struct drxuio_cfg uio_cfg = { DRX_UIO1, DRX_UIO_MODE_FIRMWARE_SMA }; 3916 int rc; 3917 u16 data = 0; 3918 3919 dev_addr = demod->my_i2c_dev_addr; 3920 ext_attr = (struct drxj_data *) demod->my_ext_attr; 3921 3922 /* Write magic word to enable pdr reg write */ 3923 rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, SIO_TOP_COMM_KEY__A, SIO_TOP_COMM_KEY_KEY, 0); 3924 if (rc != 0) { 3925 pr_err("error %d\n", rc); 3926 goto rw_error; 3927 } 3928 /* init smart antenna */ 3929 rc = drxj_dap_read_reg16(dev_addr, SIO_SA_TX_COMMAND__A, &data, 0); 3930 if (rc != 0) { 3931 pr_err("error %d\n", rc); 3932 goto rw_error; 3933 } 3934 if (ext_attr->smart_ant_inverted) { 3935 rc = drxj_dap_write_reg16(dev_addr, SIO_SA_TX_COMMAND__A, (data | SIO_SA_TX_COMMAND_TX_INVERT__M) | SIO_SA_TX_COMMAND_TX_ENABLE__M, 0); 3936 if (rc != 0) { 3937 pr_err("error %d\n", rc); 3938 goto rw_error; 3939 } 3940 } else { 3941 rc = drxj_dap_write_reg16(dev_addr, SIO_SA_TX_COMMAND__A, (data & (~SIO_SA_TX_COMMAND_TX_INVERT__M)) | SIO_SA_TX_COMMAND_TX_ENABLE__M, 0); 3942 if (rc != 0) { 3943 pr_err("error %d\n", rc); 3944 goto rw_error; 3945 } 3946 } 3947 3948 /* config SMA_TX pin to smart antenna mode */ 3949 rc = ctrl_set_uio_cfg(demod, &uio_cfg); 3950 if (rc != 0) { 3951 pr_err("error %d\n", rc); 3952 goto rw_error; 3953 } 3954 rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, SIO_PDR_SMA_TX_CFG__A, 0x13, 0); 3955 if (rc != 0) { 3956 pr_err("error %d\n", rc); 3957 goto rw_error; 3958 } 3959 rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, SIO_PDR_SMA_TX_GPIO_FNC__A, 0x03, 0); 3960 if (rc != 0) { 3961 pr_err("error %d\n", rc); 3962 goto rw_error; 3963 } 3964 3965 /* Write magic word to disable pdr reg write */ 3966 rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, SIO_TOP_COMM_KEY__A, 0x0000, 0); 3967 if (rc != 0) { 3968 pr_err("error %d\n", rc); 3969 goto rw_error; 3970 } 3971 3972 return 0; 3973 rw_error: 3974 return rc; 3975 } 3976 3977 static int scu_command(struct i2c_device_addr *dev_addr, struct drxjscu_cmd *cmd) 3978 { 3979 int rc; 3980 u16 cur_cmd = 0; 3981 unsigned long timeout; 3982 3983 /* Check param */ 3984 if (cmd == NULL) 3985 return -EINVAL; 3986 3987 /* Wait until SCU command interface is ready to receive command */ 3988 rc = drxj_dap_read_reg16(dev_addr, SCU_RAM_COMMAND__A, &cur_cmd, 0); 3989 if (rc != 0) { 3990 pr_err("error %d\n", rc); 3991 goto rw_error; 3992 } 3993 if (cur_cmd != DRX_SCU_READY) 3994 return -EIO; 3995 3996 switch (cmd->parameter_len) { 3997 case 5: 3998 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_PARAM_4__A, *(cmd->parameter + 4), 0); 3999 if (rc != 0) { 4000 pr_err("error %d\n", rc); 4001 goto rw_error; 4002 } 4003 fallthrough; 4004 case 4: 4005 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_PARAM_3__A, *(cmd->parameter + 3), 0); 4006 if (rc != 0) { 4007 pr_err("error %d\n", rc); 4008 goto rw_error; 4009 } 4010 fallthrough; 4011 case 3: 4012 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_PARAM_2__A, *(cmd->parameter + 2), 0); 4013 if (rc != 0) { 4014 pr_err("error %d\n", rc); 4015 goto rw_error; 4016 } 4017 fallthrough; 4018 case 2: 4019 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_PARAM_1__A, *(cmd->parameter + 1), 0); 4020 if (rc != 0) { 4021 pr_err("error %d\n", rc); 4022 goto rw_error; 4023 } 4024 fallthrough; 4025 case 1: 4026 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_PARAM_0__A, *(cmd->parameter + 0), 0); 4027 if (rc != 0) { 4028 pr_err("error %d\n", rc); 4029 goto rw_error; 4030 } 4031 fallthrough; 4032 case 0: 4033 /* do nothing */ 4034 break; 4035 default: 4036 /* this number of parameters is not supported */ 4037 return -EIO; 4038 } 4039 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_COMMAND__A, cmd->command, 0); 4040 if (rc != 0) { 4041 pr_err("error %d\n", rc); 4042 goto rw_error; 4043 } 4044 4045 /* Wait until SCU has processed command */ 4046 timeout = jiffies + msecs_to_jiffies(DRXJ_MAX_WAITTIME); 4047 while (time_is_after_jiffies(timeout)) { 4048 rc = drxj_dap_read_reg16(dev_addr, SCU_RAM_COMMAND__A, &cur_cmd, 0); 4049 if (rc != 0) { 4050 pr_err("error %d\n", rc); 4051 goto rw_error; 4052 } 4053 if (cur_cmd == DRX_SCU_READY) 4054 break; 4055 usleep_range(1000, 2000); 4056 } 4057 4058 if (cur_cmd != DRX_SCU_READY) 4059 return -EIO; 4060 4061 /* read results */ 4062 if ((cmd->result_len > 0) && (cmd->result != NULL)) { 4063 s16 err; 4064 4065 switch (cmd->result_len) { 4066 case 4: 4067 rc = drxj_dap_read_reg16(dev_addr, SCU_RAM_PARAM_3__A, cmd->result + 3, 0); 4068 if (rc != 0) { 4069 pr_err("error %d\n", rc); 4070 goto rw_error; 4071 } 4072 fallthrough; 4073 case 3: 4074 rc = drxj_dap_read_reg16(dev_addr, SCU_RAM_PARAM_2__A, cmd->result + 2, 0); 4075 if (rc != 0) { 4076 pr_err("error %d\n", rc); 4077 goto rw_error; 4078 } 4079 fallthrough; 4080 case 2: 4081 rc = drxj_dap_read_reg16(dev_addr, SCU_RAM_PARAM_1__A, cmd->result + 1, 0); 4082 if (rc != 0) { 4083 pr_err("error %d\n", rc); 4084 goto rw_error; 4085 } 4086 fallthrough; 4087 case 1: 4088 rc = drxj_dap_read_reg16(dev_addr, SCU_RAM_PARAM_0__A, cmd->result + 0, 0); 4089 if (rc != 0) { 4090 pr_err("error %d\n", rc); 4091 goto rw_error; 4092 } 4093 fallthrough; 4094 case 0: 4095 /* do nothing */ 4096 break; 4097 default: 4098 /* this number of parameters is not supported */ 4099 return -EIO; 4100 } 4101 4102 /* Check if an error was reported by SCU */ 4103 err = cmd->result[0]; 4104 4105 /* check a few fixed error codes */ 4106 if ((err == (s16) SCU_RAM_PARAM_0_RESULT_UNKSTD) 4107 || (err == (s16) SCU_RAM_PARAM_0_RESULT_UNKCMD) 4108 || (err == (s16) SCU_RAM_PARAM_0_RESULT_INVPAR) 4109 || (err == (s16) SCU_RAM_PARAM_0_RESULT_SIZE) 4110 ) { 4111 return -EINVAL; 4112 } 4113 /* here it is assumed that negative means error, and positive no error */ 4114 else if (err < 0) 4115 return -EIO; 4116 else 4117 return 0; 4118 } 4119 4120 return 0; 4121 4122 rw_error: 4123 return rc; 4124 } 4125 4126 /* 4127 * \fn int DRXJ_DAP_SCUAtomicReadWriteBlock() 4128 * \brief Basic access routine for SCU atomic read or write access 4129 * \param dev_addr pointer to i2c dev address 4130 * \param addr destination/source address 4131 * \param datasize size of data buffer in bytes 4132 * \param data pointer to data buffer 4133 * \return int 4134 * \retval 0 Success 4135 * \retval -EIO Timeout, I2C error, illegal bank 4136 * 4137 */ 4138 #define ADDR_AT_SCU_SPACE(x) ((x - 0x82E000) * 2) 4139 static 4140 int drxj_dap_scu_atomic_read_write_block(struct i2c_device_addr *dev_addr, u32 addr, u16 datasize, /* max 30 bytes because the limit of SCU parameter */ 4141 u8 *data, bool read_flag) 4142 { 4143 struct drxjscu_cmd scu_cmd; 4144 int rc; 4145 u16 set_param_parameters[18]; 4146 u16 cmd_result[15]; 4147 4148 /* Parameter check */ 4149 if (!data || !dev_addr || (datasize % 2) || ((datasize / 2) > 16)) 4150 return -EINVAL; 4151 4152 set_param_parameters[1] = (u16) ADDR_AT_SCU_SPACE(addr); 4153 if (read_flag) { /* read */ 4154 set_param_parameters[0] = ((~(0x0080)) & datasize); 4155 scu_cmd.parameter_len = 2; 4156 scu_cmd.result_len = datasize / 2 + 2; 4157 } else { 4158 int i = 0; 4159 4160 set_param_parameters[0] = 0x0080 | datasize; 4161 for (i = 0; i < (datasize / 2); i++) { 4162 set_param_parameters[i + 2] = 4163 (data[2 * i] | (data[(2 * i) + 1] << 8)); 4164 } 4165 scu_cmd.parameter_len = datasize / 2 + 2; 4166 scu_cmd.result_len = 1; 4167 } 4168 4169 scu_cmd.command = 4170 SCU_RAM_COMMAND_STANDARD_TOP | 4171 SCU_RAM_COMMAND_CMD_AUX_SCU_ATOMIC_ACCESS; 4172 scu_cmd.result = cmd_result; 4173 scu_cmd.parameter = set_param_parameters; 4174 rc = scu_command(dev_addr, &scu_cmd); 4175 if (rc != 0) { 4176 pr_err("error %d\n", rc); 4177 goto rw_error; 4178 } 4179 4180 if (read_flag) { 4181 int i = 0; 4182 /* read data from buffer */ 4183 for (i = 0; i < (datasize / 2); i++) { 4184 data[2 * i] = (u8) (scu_cmd.result[i + 2] & 0xFF); 4185 data[(2 * i) + 1] = (u8) (scu_cmd.result[i + 2] >> 8); 4186 } 4187 } 4188 4189 return 0; 4190 4191 rw_error: 4192 return rc; 4193 4194 } 4195 4196 /*============================================================================*/ 4197 4198 /* 4199 * \fn int DRXJ_DAP_AtomicReadReg16() 4200 * \brief Atomic read of 16 bits words 4201 */ 4202 static 4203 int drxj_dap_scu_atomic_read_reg16(struct i2c_device_addr *dev_addr, 4204 u32 addr, 4205 u16 *data, u32 flags) 4206 { 4207 u8 buf[2] = { 0 }; 4208 int rc; 4209 u16 word = 0; 4210 4211 if (!data) 4212 return -EINVAL; 4213 4214 rc = drxj_dap_scu_atomic_read_write_block(dev_addr, addr, 2, buf, true); 4215 if (rc < 0) 4216 return rc; 4217 4218 word = (u16) (buf[0] + (buf[1] << 8)); 4219 4220 *data = word; 4221 4222 return rc; 4223 } 4224 4225 /*============================================================================*/ 4226 /* 4227 * \fn int drxj_dap_scu_atomic_write_reg16() 4228 * \brief Atomic read of 16 bits words 4229 */ 4230 static 4231 int drxj_dap_scu_atomic_write_reg16(struct i2c_device_addr *dev_addr, 4232 u32 addr, 4233 u16 data, u32 flags) 4234 { 4235 u8 buf[2]; 4236 int rc; 4237 4238 buf[0] = (u8) (data & 0xff); 4239 buf[1] = (u8) ((data >> 8) & 0xff); 4240 4241 rc = drxj_dap_scu_atomic_read_write_block(dev_addr, addr, 2, buf, false); 4242 4243 return rc; 4244 } 4245 4246 /* -------------------------------------------------------------------------- */ 4247 /* 4248 * \brief Measure result of ADC synchronisation 4249 * \param demod demod instance 4250 * \param count (returned) count 4251 * \return int. 4252 * \retval 0 Success 4253 * \retval -EIO Failure: I2C error 4254 * 4255 */ 4256 static int adc_sync_measurement(struct drx_demod_instance *demod, u16 *count) 4257 { 4258 struct i2c_device_addr *dev_addr = NULL; 4259 int rc; 4260 u16 data = 0; 4261 4262 dev_addr = demod->my_i2c_dev_addr; 4263 4264 /* Start measurement */ 4265 rc = drxj_dap_write_reg16(dev_addr, IQM_AF_COMM_EXEC__A, IQM_AF_COMM_EXEC_ACTIVE, 0); 4266 if (rc != 0) { 4267 pr_err("error %d\n", rc); 4268 goto rw_error; 4269 } 4270 rc = drxj_dap_write_reg16(dev_addr, IQM_AF_START_LOCK__A, 1, 0); 4271 if (rc != 0) { 4272 pr_err("error %d\n", rc); 4273 goto rw_error; 4274 } 4275 4276 /* Wait at least 3*128*(1/sysclk) <<< 1 millisec */ 4277 msleep(1); 4278 4279 *count = 0; 4280 rc = drxj_dap_read_reg16(dev_addr, IQM_AF_PHASE0__A, &data, 0); 4281 if (rc != 0) { 4282 pr_err("error %d\n", rc); 4283 goto rw_error; 4284 } 4285 if (data == 127) 4286 *count = *count + 1; 4287 rc = drxj_dap_read_reg16(dev_addr, IQM_AF_PHASE1__A, &data, 0); 4288 if (rc != 0) { 4289 pr_err("error %d\n", rc); 4290 goto rw_error; 4291 } 4292 if (data == 127) 4293 *count = *count + 1; 4294 rc = drxj_dap_read_reg16(dev_addr, IQM_AF_PHASE2__A, &data, 0); 4295 if (rc != 0) { 4296 pr_err("error %d\n", rc); 4297 goto rw_error; 4298 } 4299 if (data == 127) 4300 *count = *count + 1; 4301 4302 return 0; 4303 rw_error: 4304 return rc; 4305 } 4306 4307 /* 4308 * \brief Synchronize analog and digital clock domains 4309 * \param demod demod instance 4310 * \return int. 4311 * \retval 0 Success 4312 * \retval -EIO Failure: I2C error or failure to synchronize 4313 * 4314 * An IQM reset will also reset the results of this synchronization. 4315 * After an IQM reset this routine needs to be called again. 4316 * 4317 */ 4318 4319 static int adc_synchronization(struct drx_demod_instance *demod) 4320 { 4321 struct i2c_device_addr *dev_addr = NULL; 4322 int rc; 4323 u16 count = 0; 4324 4325 dev_addr = demod->my_i2c_dev_addr; 4326 4327 rc = adc_sync_measurement(demod, &count); 4328 if (rc != 0) { 4329 pr_err("error %d\n", rc); 4330 goto rw_error; 4331 } 4332 4333 if (count == 1) { 4334 /* Try sampling on a different edge */ 4335 u16 clk_neg = 0; 4336 4337 rc = drxj_dap_read_reg16(dev_addr, IQM_AF_CLKNEG__A, &clk_neg, 0); 4338 if (rc != 0) { 4339 pr_err("error %d\n", rc); 4340 goto rw_error; 4341 } 4342 4343 clk_neg ^= IQM_AF_CLKNEG_CLKNEGDATA__M; 4344 rc = drxj_dap_write_reg16(dev_addr, IQM_AF_CLKNEG__A, clk_neg, 0); 4345 if (rc != 0) { 4346 pr_err("error %d\n", rc); 4347 goto rw_error; 4348 } 4349 4350 rc = adc_sync_measurement(demod, &count); 4351 if (rc != 0) { 4352 pr_err("error %d\n", rc); 4353 goto rw_error; 4354 } 4355 } 4356 4357 /* TODO: implement fallback scenarios */ 4358 if (count < 2) 4359 return -EIO; 4360 4361 return 0; 4362 rw_error: 4363 return rc; 4364 } 4365 4366 /*============================================================================*/ 4367 /*== END AUXILIARY FUNCTIONS ==*/ 4368 /*============================================================================*/ 4369 4370 /*============================================================================*/ 4371 /*============================================================================*/ 4372 /*== 8VSB & QAM COMMON DATAPATH FUNCTIONS ==*/ 4373 /*============================================================================*/ 4374 /*============================================================================*/ 4375 /* 4376 * \fn int init_agc () 4377 * \brief Initialize AGC for all standards. 4378 * \param demod instance of demodulator. 4379 * \param channel pointer to channel data. 4380 * \return int. 4381 */ 4382 static int init_agc(struct drx_demod_instance *demod) 4383 { 4384 struct i2c_device_addr *dev_addr = NULL; 4385 struct drx_common_attr *common_attr = NULL; 4386 struct drxj_data *ext_attr = NULL; 4387 struct drxj_cfg_agc *p_agc_rf_settings = NULL; 4388 struct drxj_cfg_agc *p_agc_if_settings = NULL; 4389 int rc; 4390 u16 ingain_tgt_max = 0; 4391 u16 clp_dir_to = 0; 4392 u16 sns_sum_max = 0; 4393 u16 clp_sum_max = 0; 4394 u16 sns_dir_to = 0; 4395 u16 ki_innergain_min = 0; 4396 u16 agc_ki = 0; 4397 u16 ki_max = 0; 4398 u16 if_iaccu_hi_tgt_min = 0; 4399 u16 data = 0; 4400 u16 agc_ki_dgain = 0; 4401 u16 ki_min = 0; 4402 u16 clp_ctrl_mode = 0; 4403 u16 agc_rf = 0; 4404 u16 agc_if = 0; 4405 4406 dev_addr = demod->my_i2c_dev_addr; 4407 common_attr = (struct drx_common_attr *) demod->my_common_attr; 4408 ext_attr = (struct drxj_data *) demod->my_ext_attr; 4409 4410 switch (ext_attr->standard) { 4411 case DRX_STANDARD_8VSB: 4412 clp_sum_max = 1023; 4413 clp_dir_to = (u16) (-9); 4414 sns_sum_max = 1023; 4415 sns_dir_to = (u16) (-9); 4416 ki_innergain_min = (u16) (-32768); 4417 ki_max = 0x032C; 4418 agc_ki_dgain = 0xC; 4419 if_iaccu_hi_tgt_min = 2047; 4420 ki_min = 0x0117; 4421 ingain_tgt_max = 16383; 4422 clp_ctrl_mode = 0; 4423 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_KI_MINGAIN__A, 0x7fff, 0); 4424 if (rc != 0) { 4425 pr_err("error %d\n", rc); 4426 goto rw_error; 4427 } 4428 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_KI_MAXGAIN__A, 0x0, 0); 4429 if (rc != 0) { 4430 pr_err("error %d\n", rc); 4431 goto rw_error; 4432 } 4433 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_CLP_SUM__A, 0, 0); 4434 if (rc != 0) { 4435 pr_err("error %d\n", rc); 4436 goto rw_error; 4437 } 4438 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_CLP_CYCCNT__A, 0, 0); 4439 if (rc != 0) { 4440 pr_err("error %d\n", rc); 4441 goto rw_error; 4442 } 4443 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_CLP_DIR_WD__A, 0, 0); 4444 if (rc != 0) { 4445 pr_err("error %d\n", rc); 4446 goto rw_error; 4447 } 4448 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_CLP_DIR_STP__A, 1, 0); 4449 if (rc != 0) { 4450 pr_err("error %d\n", rc); 4451 goto rw_error; 4452 } 4453 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_SNS_SUM__A, 0, 0); 4454 if (rc != 0) { 4455 pr_err("error %d\n", rc); 4456 goto rw_error; 4457 } 4458 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_SNS_CYCCNT__A, 0, 0); 4459 if (rc != 0) { 4460 pr_err("error %d\n", rc); 4461 goto rw_error; 4462 } 4463 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_SNS_DIR_WD__A, 0, 0); 4464 if (rc != 0) { 4465 pr_err("error %d\n", rc); 4466 goto rw_error; 4467 } 4468 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_SNS_DIR_STP__A, 1, 0); 4469 if (rc != 0) { 4470 pr_err("error %d\n", rc); 4471 goto rw_error; 4472 } 4473 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_INGAIN__A, 1024, 0); 4474 if (rc != 0) { 4475 pr_err("error %d\n", rc); 4476 goto rw_error; 4477 } 4478 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_VSB_AGC_POW_TGT__A, 22600, 0); 4479 if (rc != 0) { 4480 pr_err("error %d\n", rc); 4481 goto rw_error; 4482 } 4483 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_INGAIN_TGT__A, 13200, 0); 4484 if (rc != 0) { 4485 pr_err("error %d\n", rc); 4486 goto rw_error; 4487 } 4488 p_agc_if_settings = &(ext_attr->vsb_if_agc_cfg); 4489 p_agc_rf_settings = &(ext_attr->vsb_rf_agc_cfg); 4490 break; 4491 #ifndef DRXJ_VSB_ONLY 4492 case DRX_STANDARD_ITU_A: 4493 case DRX_STANDARD_ITU_C: 4494 case DRX_STANDARD_ITU_B: 4495 ingain_tgt_max = 5119; 4496 clp_sum_max = 1023; 4497 clp_dir_to = (u16) (-5); 4498 sns_sum_max = 127; 4499 sns_dir_to = (u16) (-3); 4500 ki_innergain_min = 0; 4501 ki_max = 0x0657; 4502 if_iaccu_hi_tgt_min = 2047; 4503 agc_ki_dgain = 0x7; 4504 ki_min = 0x0117; 4505 clp_ctrl_mode = 0; 4506 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_KI_MINGAIN__A, 0x7fff, 0); 4507 if (rc != 0) { 4508 pr_err("error %d\n", rc); 4509 goto rw_error; 4510 } 4511 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_KI_MAXGAIN__A, 0x0, 0); 4512 if (rc != 0) { 4513 pr_err("error %d\n", rc); 4514 goto rw_error; 4515 } 4516 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_CLP_SUM__A, 0, 0); 4517 if (rc != 0) { 4518 pr_err("error %d\n", rc); 4519 goto rw_error; 4520 } 4521 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_CLP_CYCCNT__A, 0, 0); 4522 if (rc != 0) { 4523 pr_err("error %d\n", rc); 4524 goto rw_error; 4525 } 4526 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_CLP_DIR_WD__A, 0, 0); 4527 if (rc != 0) { 4528 pr_err("error %d\n", rc); 4529 goto rw_error; 4530 } 4531 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_CLP_DIR_STP__A, 1, 0); 4532 if (rc != 0) { 4533 pr_err("error %d\n", rc); 4534 goto rw_error; 4535 } 4536 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_SNS_SUM__A, 0, 0); 4537 if (rc != 0) { 4538 pr_err("error %d\n", rc); 4539 goto rw_error; 4540 } 4541 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_SNS_CYCCNT__A, 0, 0); 4542 if (rc != 0) { 4543 pr_err("error %d\n", rc); 4544 goto rw_error; 4545 } 4546 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_SNS_DIR_WD__A, 0, 0); 4547 if (rc != 0) { 4548 pr_err("error %d\n", rc); 4549 goto rw_error; 4550 } 4551 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_SNS_DIR_STP__A, 1, 0); 4552 if (rc != 0) { 4553 pr_err("error %d\n", rc); 4554 goto rw_error; 4555 } 4556 p_agc_if_settings = &(ext_attr->qam_if_agc_cfg); 4557 p_agc_rf_settings = &(ext_attr->qam_rf_agc_cfg); 4558 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_INGAIN_TGT__A, p_agc_if_settings->top, 0); 4559 if (rc != 0) { 4560 pr_err("error %d\n", rc); 4561 goto rw_error; 4562 } 4563 4564 rc = drxj_dap_read_reg16(dev_addr, SCU_RAM_AGC_KI__A, &agc_ki, 0); 4565 if (rc != 0) { 4566 pr_err("error %d\n", rc); 4567 goto rw_error; 4568 } 4569 agc_ki &= 0xf000; 4570 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_KI__A, agc_ki, 0); 4571 if (rc != 0) { 4572 pr_err("error %d\n", rc); 4573 goto rw_error; 4574 } 4575 break; 4576 #endif 4577 default: 4578 return -EINVAL; 4579 } 4580 4581 /* for new AGC interface */ 4582 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_INGAIN_TGT_MIN__A, p_agc_if_settings->top, 0); 4583 if (rc != 0) { 4584 pr_err("error %d\n", rc); 4585 goto rw_error; 4586 } 4587 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_INGAIN__A, p_agc_if_settings->top, 0); 4588 if (rc != 0) { 4589 pr_err("error %d\n", rc); 4590 goto rw_error; 4591 } /* Gain fed from inner to outer AGC */ 4592 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_INGAIN_TGT_MAX__A, ingain_tgt_max, 0); 4593 if (rc != 0) { 4594 pr_err("error %d\n", rc); 4595 goto rw_error; 4596 } 4597 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_IF_IACCU_HI_TGT_MIN__A, if_iaccu_hi_tgt_min, 0); 4598 if (rc != 0) { 4599 pr_err("error %d\n", rc); 4600 goto rw_error; 4601 } 4602 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_IF_IACCU_HI__A, 0, 0); 4603 if (rc != 0) { 4604 pr_err("error %d\n", rc); 4605 goto rw_error; 4606 } /* set to p_agc_settings->top before */ 4607 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_IF_IACCU_LO__A, 0, 0); 4608 if (rc != 0) { 4609 pr_err("error %d\n", rc); 4610 goto rw_error; 4611 } 4612 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_RF_IACCU_HI__A, 0, 0); 4613 if (rc != 0) { 4614 pr_err("error %d\n", rc); 4615 goto rw_error; 4616 } 4617 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_RF_IACCU_LO__A, 0, 0); 4618 if (rc != 0) { 4619 pr_err("error %d\n", rc); 4620 goto rw_error; 4621 } 4622 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_RF_MAX__A, 32767, 0); 4623 if (rc != 0) { 4624 pr_err("error %d\n", rc); 4625 goto rw_error; 4626 } 4627 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_CLP_SUM_MAX__A, clp_sum_max, 0); 4628 if (rc != 0) { 4629 pr_err("error %d\n", rc); 4630 goto rw_error; 4631 } 4632 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_SNS_SUM_MAX__A, sns_sum_max, 0); 4633 if (rc != 0) { 4634 pr_err("error %d\n", rc); 4635 goto rw_error; 4636 } 4637 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_KI_INNERGAIN_MIN__A, ki_innergain_min, 0); 4638 if (rc != 0) { 4639 pr_err("error %d\n", rc); 4640 goto rw_error; 4641 } 4642 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_FAST_SNS_CTRL_DELAY__A, 50, 0); 4643 if (rc != 0) { 4644 pr_err("error %d\n", rc); 4645 goto rw_error; 4646 } 4647 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_KI_CYCLEN__A, 500, 0); 4648 if (rc != 0) { 4649 pr_err("error %d\n", rc); 4650 goto rw_error; 4651 } 4652 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_SNS_CYCLEN__A, 500, 0); 4653 if (rc != 0) { 4654 pr_err("error %d\n", rc); 4655 goto rw_error; 4656 } 4657 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_KI_MAXMINGAIN_TH__A, 20, 0); 4658 if (rc != 0) { 4659 pr_err("error %d\n", rc); 4660 goto rw_error; 4661 } 4662 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_KI_MIN__A, ki_min, 0); 4663 if (rc != 0) { 4664 pr_err("error %d\n", rc); 4665 goto rw_error; 4666 } 4667 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_KI_MAX__A, ki_max, 0); 4668 if (rc != 0) { 4669 pr_err("error %d\n", rc); 4670 goto rw_error; 4671 } 4672 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_KI_RED__A, 0, 0); 4673 if (rc != 0) { 4674 pr_err("error %d\n", rc); 4675 goto rw_error; 4676 } 4677 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_CLP_SUM_MIN__A, 8, 0); 4678 if (rc != 0) { 4679 pr_err("error %d\n", rc); 4680 goto rw_error; 4681 } 4682 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_CLP_CYCLEN__A, 500, 0); 4683 if (rc != 0) { 4684 pr_err("error %d\n", rc); 4685 goto rw_error; 4686 } 4687 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_CLP_DIR_TO__A, clp_dir_to, 0); 4688 if (rc != 0) { 4689 pr_err("error %d\n", rc); 4690 goto rw_error; 4691 } 4692 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_SNS_SUM_MIN__A, 8, 0); 4693 if (rc != 0) { 4694 pr_err("error %d\n", rc); 4695 goto rw_error; 4696 } 4697 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_SNS_DIR_TO__A, sns_dir_to, 0); 4698 if (rc != 0) { 4699 pr_err("error %d\n", rc); 4700 goto rw_error; 4701 } 4702 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_FAST_CLP_CTRL_DELAY__A, 50, 0); 4703 if (rc != 0) { 4704 pr_err("error %d\n", rc); 4705 goto rw_error; 4706 } 4707 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_CLP_CTRL_MODE__A, clp_ctrl_mode, 0); 4708 if (rc != 0) { 4709 pr_err("error %d\n", rc); 4710 goto rw_error; 4711 } 4712 4713 agc_rf = 0x800 + p_agc_rf_settings->cut_off_current; 4714 if (common_attr->tuner_rf_agc_pol == true) 4715 agc_rf = 0x87ff - agc_rf; 4716 4717 agc_if = 0x800; 4718 if (common_attr->tuner_if_agc_pol == true) 4719 agc_rf = 0x87ff - agc_rf; 4720 4721 rc = drxj_dap_write_reg16(dev_addr, IQM_AF_AGC_RF__A, agc_rf, 0); 4722 if (rc != 0) { 4723 pr_err("error %d\n", rc); 4724 goto rw_error; 4725 } 4726 rc = drxj_dap_write_reg16(dev_addr, IQM_AF_AGC_IF__A, agc_if, 0); 4727 if (rc != 0) { 4728 pr_err("error %d\n", rc); 4729 goto rw_error; 4730 } 4731 4732 /* Set/restore Ki DGAIN factor */ 4733 rc = drxj_dap_read_reg16(dev_addr, SCU_RAM_AGC_KI__A, &data, 0); 4734 if (rc != 0) { 4735 pr_err("error %d\n", rc); 4736 goto rw_error; 4737 } 4738 data &= ~SCU_RAM_AGC_KI_DGAIN__M; 4739 data |= (agc_ki_dgain << SCU_RAM_AGC_KI_DGAIN__B); 4740 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_KI__A, data, 0); 4741 if (rc != 0) { 4742 pr_err("error %d\n", rc); 4743 goto rw_error; 4744 } 4745 4746 return 0; 4747 rw_error: 4748 return rc; 4749 } 4750 4751 /* 4752 * \fn int set_frequency () 4753 * \brief Set frequency shift. 4754 * \param demod instance of demodulator. 4755 * \param channel pointer to channel data. 4756 * \param tuner_freq_offset residual frequency from tuner. 4757 * \return int. 4758 */ 4759 static int 4760 set_frequency(struct drx_demod_instance *demod, 4761 struct drx_channel *channel, s32 tuner_freq_offset) 4762 { 4763 struct i2c_device_addr *dev_addr = demod->my_i2c_dev_addr; 4764 struct drxj_data *ext_attr = demod->my_ext_attr; 4765 int rc; 4766 s32 sampling_frequency = 0; 4767 s32 frequency_shift = 0; 4768 s32 if_freq_actual = 0; 4769 s32 rf_freq_residual = -1 * tuner_freq_offset; 4770 s32 adc_freq = 0; 4771 s32 intermediate_freq = 0; 4772 u32 iqm_fs_rate_ofs = 0; 4773 bool adc_flip = true; 4774 bool select_pos_image = false; 4775 bool rf_mirror; 4776 bool tuner_mirror; 4777 bool image_to_select; 4778 s32 fm_frequency_shift = 0; 4779 4780 rf_mirror = ext_attr->mirror == DRX_MIRROR_YES; 4781 tuner_mirror = !demod->my_common_attr->mirror_freq_spect; 4782 /* 4783 Program frequency shifter 4784 No need to account for mirroring on RF 4785 */ 4786 switch (ext_attr->standard) { 4787 case DRX_STANDARD_ITU_A: 4788 case DRX_STANDARD_ITU_C: 4789 case DRX_STANDARD_PAL_SECAM_LP: 4790 case DRX_STANDARD_8VSB: 4791 select_pos_image = true; 4792 break; 4793 case DRX_STANDARD_FM: 4794 /* After IQM FS sound carrier must appear at 4 Mhz in spect. 4795 Sound carrier is already 3Mhz above centre frequency due 4796 to tuner setting so now add an extra shift of 1MHz... */ 4797 fm_frequency_shift = 1000; 4798 fallthrough; 4799 case DRX_STANDARD_ITU_B: 4800 case DRX_STANDARD_NTSC: 4801 case DRX_STANDARD_PAL_SECAM_BG: 4802 case DRX_STANDARD_PAL_SECAM_DK: 4803 case DRX_STANDARD_PAL_SECAM_I: 4804 case DRX_STANDARD_PAL_SECAM_L: 4805 select_pos_image = false; 4806 break; 4807 default: 4808 return -EINVAL; 4809 } 4810 intermediate_freq = demod->my_common_attr->intermediate_freq; 4811 sampling_frequency = demod->my_common_attr->sys_clock_freq / 3; 4812 if (tuner_mirror) 4813 if_freq_actual = intermediate_freq + rf_freq_residual + fm_frequency_shift; 4814 else 4815 if_freq_actual = intermediate_freq - rf_freq_residual - fm_frequency_shift; 4816 if (if_freq_actual > sampling_frequency / 2) { 4817 /* adc mirrors */ 4818 adc_freq = sampling_frequency - if_freq_actual; 4819 adc_flip = true; 4820 } else { 4821 /* adc doesn't mirror */ 4822 adc_freq = if_freq_actual; 4823 adc_flip = false; 4824 } 4825 4826 frequency_shift = adc_freq; 4827 image_to_select = 4828 (bool) (rf_mirror ^ tuner_mirror ^ adc_flip ^ select_pos_image); 4829 iqm_fs_rate_ofs = frac28(frequency_shift, sampling_frequency); 4830 4831 if (image_to_select) 4832 iqm_fs_rate_ofs = ~iqm_fs_rate_ofs + 1; 4833 4834 /* Program frequency shifter with tuner offset compensation */ 4835 /* frequency_shift += tuner_freq_offset; TODO */ 4836 rc = drxdap_fasi_write_reg32(dev_addr, IQM_FS_RATE_OFS_LO__A, iqm_fs_rate_ofs, 0); 4837 if (rc != 0) { 4838 pr_err("error %d\n", rc); 4839 goto rw_error; 4840 } 4841 ext_attr->iqm_fs_rate_ofs = iqm_fs_rate_ofs; 4842 ext_attr->pos_image = (bool) (rf_mirror ^ tuner_mirror ^ select_pos_image); 4843 4844 return 0; 4845 rw_error: 4846 return rc; 4847 } 4848 4849 /* 4850 * \fn int get_acc_pkt_err() 4851 * \brief Retrieve signal strength for VSB and QAM. 4852 * \param demod Pointer to demod instance 4853 * \param packet_err Pointer to packet error 4854 * \return int. 4855 * \retval 0 sig_strength contains valid data. 4856 * \retval -EINVAL sig_strength is NULL. 4857 * \retval -EIO Erroneous data, sig_strength contains invalid data. 4858 */ 4859 #ifdef DRXJ_SIGNAL_ACCUM_ERR 4860 static int get_acc_pkt_err(struct drx_demod_instance *demod, u16 *packet_err) 4861 { 4862 int rc; 4863 static u16 pkt_err; 4864 static u16 last_pkt_err; 4865 u16 data = 0; 4866 struct drxj_data *ext_attr = NULL; 4867 struct i2c_device_addr *dev_addr = NULL; 4868 4869 ext_attr = (struct drxj_data *) demod->my_ext_attr; 4870 dev_addr = demod->my_i2c_dev_addr; 4871 4872 rc = drxj_dap_read_reg16(dev_addr, SCU_RAM_FEC_ACCUM_PKT_FAILURES__A, &data, 0); 4873 if (rc != 0) { 4874 pr_err("error %d\n", rc); 4875 goto rw_error; 4876 } 4877 if (ext_attr->reset_pkt_err_acc) { 4878 last_pkt_err = data; 4879 pkt_err = 0; 4880 ext_attr->reset_pkt_err_acc = false; 4881 } 4882 4883 if (data < last_pkt_err) { 4884 pkt_err += 0xffff - last_pkt_err; 4885 pkt_err += data; 4886 } else { 4887 pkt_err += (data - last_pkt_err); 4888 } 4889 *packet_err = pkt_err; 4890 last_pkt_err = data; 4891 4892 return 0; 4893 rw_error: 4894 return rc; 4895 } 4896 #endif 4897 4898 4899 /*============================================================================*/ 4900 4901 /* 4902 * \fn int set_agc_rf () 4903 * \brief Configure RF AGC 4904 * \param demod instance of demodulator. 4905 * \param agc_settings AGC configuration structure 4906 * \return int. 4907 */ 4908 static int 4909 set_agc_rf(struct drx_demod_instance *demod, struct drxj_cfg_agc *agc_settings, bool atomic) 4910 { 4911 struct i2c_device_addr *dev_addr = NULL; 4912 struct drxj_data *ext_attr = NULL; 4913 struct drxj_cfg_agc *p_agc_settings = NULL; 4914 struct drx_common_attr *common_attr = NULL; 4915 int rc; 4916 drx_write_reg16func_t scu_wr16 = NULL; 4917 drx_read_reg16func_t scu_rr16 = NULL; 4918 4919 common_attr = (struct drx_common_attr *) demod->my_common_attr; 4920 dev_addr = demod->my_i2c_dev_addr; 4921 ext_attr = (struct drxj_data *) demod->my_ext_attr; 4922 4923 if (atomic) { 4924 scu_rr16 = drxj_dap_scu_atomic_read_reg16; 4925 scu_wr16 = drxj_dap_scu_atomic_write_reg16; 4926 } else { 4927 scu_rr16 = drxj_dap_read_reg16; 4928 scu_wr16 = drxj_dap_write_reg16; 4929 } 4930 4931 /* Configure AGC only if standard is currently active */ 4932 if ((ext_attr->standard == agc_settings->standard) || 4933 (DRXJ_ISQAMSTD(ext_attr->standard) && 4934 DRXJ_ISQAMSTD(agc_settings->standard)) || 4935 (DRXJ_ISATVSTD(ext_attr->standard) && 4936 DRXJ_ISATVSTD(agc_settings->standard))) { 4937 u16 data = 0; 4938 4939 switch (agc_settings->ctrl_mode) { 4940 case DRX_AGC_CTRL_AUTO: 4941 4942 /* Enable RF AGC DAC */ 4943 rc = drxj_dap_read_reg16(dev_addr, IQM_AF_STDBY__A, &data, 0); 4944 if (rc != 0) { 4945 pr_err("error %d\n", rc); 4946 goto rw_error; 4947 } 4948 data |= IQM_AF_STDBY_STDBY_TAGC_RF_A2_ACTIVE; 4949 rc = drxj_dap_write_reg16(dev_addr, IQM_AF_STDBY__A, data, 0); 4950 if (rc != 0) { 4951 pr_err("error %d\n", rc); 4952 goto rw_error; 4953 } 4954 4955 /* Enable SCU RF AGC loop */ 4956 rc = (*scu_rr16)(dev_addr, SCU_RAM_AGC_KI__A, &data, 0); 4957 if (rc != 0) { 4958 pr_err("error %d\n", rc); 4959 goto rw_error; 4960 } 4961 data &= ~SCU_RAM_AGC_KI_RF__M; 4962 if (ext_attr->standard == DRX_STANDARD_8VSB) 4963 data |= (2 << SCU_RAM_AGC_KI_RF__B); 4964 else if (DRXJ_ISQAMSTD(ext_attr->standard)) 4965 data |= (5 << SCU_RAM_AGC_KI_RF__B); 4966 else 4967 data |= (4 << SCU_RAM_AGC_KI_RF__B); 4968 4969 if (common_attr->tuner_rf_agc_pol) 4970 data |= SCU_RAM_AGC_KI_INV_RF_POL__M; 4971 else 4972 data &= ~SCU_RAM_AGC_KI_INV_RF_POL__M; 4973 rc = (*scu_wr16)(dev_addr, SCU_RAM_AGC_KI__A, data, 0); 4974 if (rc != 0) { 4975 pr_err("error %d\n", rc); 4976 goto rw_error; 4977 } 4978 4979 /* Set speed ( using complementary reduction value ) */ 4980 rc = (*scu_rr16)(dev_addr, SCU_RAM_AGC_KI_RED__A, &data, 0); 4981 if (rc != 0) { 4982 pr_err("error %d\n", rc); 4983 goto rw_error; 4984 } 4985 data &= ~SCU_RAM_AGC_KI_RED_RAGC_RED__M; 4986 rc = (*scu_wr16)(dev_addr, SCU_RAM_AGC_KI_RED__A, (~(agc_settings->speed << SCU_RAM_AGC_KI_RED_RAGC_RED__B) & SCU_RAM_AGC_KI_RED_RAGC_RED__M) | data, 0); 4987 if (rc != 0) { 4988 pr_err("error %d\n", rc); 4989 goto rw_error; 4990 } 4991 4992 if (agc_settings->standard == DRX_STANDARD_8VSB) 4993 p_agc_settings = &(ext_attr->vsb_if_agc_cfg); 4994 else if (DRXJ_ISQAMSTD(agc_settings->standard)) 4995 p_agc_settings = &(ext_attr->qam_if_agc_cfg); 4996 else if (DRXJ_ISATVSTD(agc_settings->standard)) 4997 p_agc_settings = &(ext_attr->atv_if_agc_cfg); 4998 else 4999 return -EINVAL; 5000 5001 /* Set TOP, only if IF-AGC is in AUTO mode */ 5002 if (p_agc_settings->ctrl_mode == DRX_AGC_CTRL_AUTO) { 5003 rc = (*scu_wr16)(dev_addr, SCU_RAM_AGC_IF_IACCU_HI_TGT_MAX__A, agc_settings->top, 0); 5004 if (rc != 0) { 5005 pr_err("error %d\n", rc); 5006 goto rw_error; 5007 } 5008 rc = (*scu_wr16)(dev_addr, SCU_RAM_AGC_IF_IACCU_HI_TGT__A, agc_settings->top, 0); 5009 if (rc != 0) { 5010 pr_err("error %d\n", rc); 5011 goto rw_error; 5012 } 5013 } 5014 5015 /* Cut-Off current */ 5016 rc = (*scu_wr16)(dev_addr, SCU_RAM_AGC_RF_IACCU_HI_CO__A, agc_settings->cut_off_current, 0); 5017 if (rc != 0) { 5018 pr_err("error %d\n", rc); 5019 goto rw_error; 5020 } 5021 break; 5022 case DRX_AGC_CTRL_USER: 5023 5024 /* Enable RF AGC DAC */ 5025 rc = drxj_dap_read_reg16(dev_addr, IQM_AF_STDBY__A, &data, 0); 5026 if (rc != 0) { 5027 pr_err("error %d\n", rc); 5028 goto rw_error; 5029 } 5030 data |= IQM_AF_STDBY_STDBY_TAGC_RF_A2_ACTIVE; 5031 rc = drxj_dap_write_reg16(dev_addr, IQM_AF_STDBY__A, data, 0); 5032 if (rc != 0) { 5033 pr_err("error %d\n", rc); 5034 goto rw_error; 5035 } 5036 5037 /* Disable SCU RF AGC loop */ 5038 rc = (*scu_rr16)(dev_addr, SCU_RAM_AGC_KI__A, &data, 0); 5039 if (rc != 0) { 5040 pr_err("error %d\n", rc); 5041 goto rw_error; 5042 } 5043 data &= ~SCU_RAM_AGC_KI_RF__M; 5044 if (common_attr->tuner_rf_agc_pol) 5045 data |= SCU_RAM_AGC_KI_INV_RF_POL__M; 5046 else 5047 data &= ~SCU_RAM_AGC_KI_INV_RF_POL__M; 5048 rc = (*scu_wr16)(dev_addr, SCU_RAM_AGC_KI__A, data, 0); 5049 if (rc != 0) { 5050 pr_err("error %d\n", rc); 5051 goto rw_error; 5052 } 5053 5054 /* Write value to output pin */ 5055 rc = (*scu_wr16)(dev_addr, SCU_RAM_AGC_RF_IACCU_HI__A, agc_settings->output_level, 0); 5056 if (rc != 0) { 5057 pr_err("error %d\n", rc); 5058 goto rw_error; 5059 } 5060 break; 5061 case DRX_AGC_CTRL_OFF: 5062 5063 /* Disable RF AGC DAC */ 5064 rc = drxj_dap_read_reg16(dev_addr, IQM_AF_STDBY__A, &data, 0); 5065 if (rc != 0) { 5066 pr_err("error %d\n", rc); 5067 goto rw_error; 5068 } 5069 data &= (~IQM_AF_STDBY_STDBY_TAGC_RF_A2_ACTIVE); 5070 rc = drxj_dap_write_reg16(dev_addr, IQM_AF_STDBY__A, data, 0); 5071 if (rc != 0) { 5072 pr_err("error %d\n", rc); 5073 goto rw_error; 5074 } 5075 5076 /* Disable SCU RF AGC loop */ 5077 rc = (*scu_rr16)(dev_addr, SCU_RAM_AGC_KI__A, &data, 0); 5078 if (rc != 0) { 5079 pr_err("error %d\n", rc); 5080 goto rw_error; 5081 } 5082 data &= ~SCU_RAM_AGC_KI_RF__M; 5083 rc = (*scu_wr16)(dev_addr, SCU_RAM_AGC_KI__A, data, 0); 5084 if (rc != 0) { 5085 pr_err("error %d\n", rc); 5086 goto rw_error; 5087 } 5088 break; 5089 default: 5090 return -EINVAL; 5091 } /* switch ( agcsettings->ctrl_mode ) */ 5092 } 5093 5094 /* Store rf agc settings */ 5095 switch (agc_settings->standard) { 5096 case DRX_STANDARD_8VSB: 5097 ext_attr->vsb_rf_agc_cfg = *agc_settings; 5098 break; 5099 #ifndef DRXJ_VSB_ONLY 5100 case DRX_STANDARD_ITU_A: 5101 case DRX_STANDARD_ITU_B: 5102 case DRX_STANDARD_ITU_C: 5103 ext_attr->qam_rf_agc_cfg = *agc_settings; 5104 break; 5105 #endif 5106 default: 5107 return -EIO; 5108 } 5109 5110 return 0; 5111 rw_error: 5112 return rc; 5113 } 5114 5115 /* 5116 * \fn int set_agc_if () 5117 * \brief Configure If AGC 5118 * \param demod instance of demodulator. 5119 * \param agc_settings AGC configuration structure 5120 * \return int. 5121 */ 5122 static int 5123 set_agc_if(struct drx_demod_instance *demod, struct drxj_cfg_agc *agc_settings, bool atomic) 5124 { 5125 struct i2c_device_addr *dev_addr = NULL; 5126 struct drxj_data *ext_attr = NULL; 5127 struct drxj_cfg_agc *p_agc_settings = NULL; 5128 struct drx_common_attr *common_attr = NULL; 5129 drx_write_reg16func_t scu_wr16 = NULL; 5130 drx_read_reg16func_t scu_rr16 = NULL; 5131 int rc; 5132 5133 common_attr = (struct drx_common_attr *) demod->my_common_attr; 5134 dev_addr = demod->my_i2c_dev_addr; 5135 ext_attr = (struct drxj_data *) demod->my_ext_attr; 5136 5137 if (atomic) { 5138 scu_rr16 = drxj_dap_scu_atomic_read_reg16; 5139 scu_wr16 = drxj_dap_scu_atomic_write_reg16; 5140 } else { 5141 scu_rr16 = drxj_dap_read_reg16; 5142 scu_wr16 = drxj_dap_write_reg16; 5143 } 5144 5145 /* Configure AGC only if standard is currently active */ 5146 if ((ext_attr->standard == agc_settings->standard) || 5147 (DRXJ_ISQAMSTD(ext_attr->standard) && 5148 DRXJ_ISQAMSTD(agc_settings->standard)) || 5149 (DRXJ_ISATVSTD(ext_attr->standard) && 5150 DRXJ_ISATVSTD(agc_settings->standard))) { 5151 u16 data = 0; 5152 5153 switch (agc_settings->ctrl_mode) { 5154 case DRX_AGC_CTRL_AUTO: 5155 /* Enable IF AGC DAC */ 5156 rc = drxj_dap_read_reg16(dev_addr, IQM_AF_STDBY__A, &data, 0); 5157 if (rc != 0) { 5158 pr_err("error %d\n", rc); 5159 goto rw_error; 5160 } 5161 data |= IQM_AF_STDBY_STDBY_TAGC_IF_A2_ACTIVE; 5162 rc = drxj_dap_write_reg16(dev_addr, IQM_AF_STDBY__A, data, 0); 5163 if (rc != 0) { 5164 pr_err("error %d\n", rc); 5165 goto rw_error; 5166 } 5167 5168 /* Enable SCU IF AGC loop */ 5169 rc = (*scu_rr16)(dev_addr, SCU_RAM_AGC_KI__A, &data, 0); 5170 if (rc != 0) { 5171 pr_err("error %d\n", rc); 5172 goto rw_error; 5173 } 5174 data &= ~SCU_RAM_AGC_KI_IF_AGC_DISABLE__M; 5175 data &= ~SCU_RAM_AGC_KI_IF__M; 5176 if (ext_attr->standard == DRX_STANDARD_8VSB) 5177 data |= (3 << SCU_RAM_AGC_KI_IF__B); 5178 else if (DRXJ_ISQAMSTD(ext_attr->standard)) 5179 data |= (6 << SCU_RAM_AGC_KI_IF__B); 5180 else 5181 data |= (5 << SCU_RAM_AGC_KI_IF__B); 5182 5183 if (common_attr->tuner_if_agc_pol) 5184 data |= SCU_RAM_AGC_KI_INV_IF_POL__M; 5185 else 5186 data &= ~SCU_RAM_AGC_KI_INV_IF_POL__M; 5187 rc = (*scu_wr16)(dev_addr, SCU_RAM_AGC_KI__A, data, 0); 5188 if (rc != 0) { 5189 pr_err("error %d\n", rc); 5190 goto rw_error; 5191 } 5192 5193 /* Set speed (using complementary reduction value) */ 5194 rc = (*scu_rr16)(dev_addr, SCU_RAM_AGC_KI_RED__A, &data, 0); 5195 if (rc != 0) { 5196 pr_err("error %d\n", rc); 5197 goto rw_error; 5198 } 5199 data &= ~SCU_RAM_AGC_KI_RED_IAGC_RED__M; 5200 rc = (*scu_wr16) (dev_addr, SCU_RAM_AGC_KI_RED__A, (~(agc_settings->speed << SCU_RAM_AGC_KI_RED_IAGC_RED__B) & SCU_RAM_AGC_KI_RED_IAGC_RED__M) | data, 0); 5201 if (rc != 0) { 5202 pr_err("error %d\n", rc); 5203 goto rw_error; 5204 } 5205 5206 if (agc_settings->standard == DRX_STANDARD_8VSB) 5207 p_agc_settings = &(ext_attr->vsb_rf_agc_cfg); 5208 else if (DRXJ_ISQAMSTD(agc_settings->standard)) 5209 p_agc_settings = &(ext_attr->qam_rf_agc_cfg); 5210 else if (DRXJ_ISATVSTD(agc_settings->standard)) 5211 p_agc_settings = &(ext_attr->atv_rf_agc_cfg); 5212 else 5213 return -EINVAL; 5214 5215 /* Restore TOP */ 5216 if (p_agc_settings->ctrl_mode == DRX_AGC_CTRL_AUTO) { 5217 rc = (*scu_wr16)(dev_addr, SCU_RAM_AGC_IF_IACCU_HI_TGT_MAX__A, p_agc_settings->top, 0); 5218 if (rc != 0) { 5219 pr_err("error %d\n", rc); 5220 goto rw_error; 5221 } 5222 rc = (*scu_wr16)(dev_addr, SCU_RAM_AGC_IF_IACCU_HI_TGT__A, p_agc_settings->top, 0); 5223 if (rc != 0) { 5224 pr_err("error %d\n", rc); 5225 goto rw_error; 5226 } 5227 } else { 5228 rc = (*scu_wr16)(dev_addr, SCU_RAM_AGC_IF_IACCU_HI_TGT_MAX__A, 0, 0); 5229 if (rc != 0) { 5230 pr_err("error %d\n", rc); 5231 goto rw_error; 5232 } 5233 rc = (*scu_wr16)(dev_addr, SCU_RAM_AGC_IF_IACCU_HI_TGT__A, 0, 0); 5234 if (rc != 0) { 5235 pr_err("error %d\n", rc); 5236 goto rw_error; 5237 } 5238 } 5239 break; 5240 5241 case DRX_AGC_CTRL_USER: 5242 5243 /* Enable IF AGC DAC */ 5244 rc = drxj_dap_read_reg16(dev_addr, IQM_AF_STDBY__A, &data, 0); 5245 if (rc != 0) { 5246 pr_err("error %d\n", rc); 5247 goto rw_error; 5248 } 5249 data |= IQM_AF_STDBY_STDBY_TAGC_IF_A2_ACTIVE; 5250 rc = drxj_dap_write_reg16(dev_addr, IQM_AF_STDBY__A, data, 0); 5251 if (rc != 0) { 5252 pr_err("error %d\n", rc); 5253 goto rw_error; 5254 } 5255 5256 /* Disable SCU IF AGC loop */ 5257 rc = (*scu_rr16)(dev_addr, SCU_RAM_AGC_KI__A, &data, 0); 5258 if (rc != 0) { 5259 pr_err("error %d\n", rc); 5260 goto rw_error; 5261 } 5262 data &= ~SCU_RAM_AGC_KI_IF_AGC_DISABLE__M; 5263 data |= SCU_RAM_AGC_KI_IF_AGC_DISABLE__M; 5264 if (common_attr->tuner_if_agc_pol) 5265 data |= SCU_RAM_AGC_KI_INV_IF_POL__M; 5266 else 5267 data &= ~SCU_RAM_AGC_KI_INV_IF_POL__M; 5268 rc = (*scu_wr16)(dev_addr, SCU_RAM_AGC_KI__A, data, 0); 5269 if (rc != 0) { 5270 pr_err("error %d\n", rc); 5271 goto rw_error; 5272 } 5273 5274 /* Write value to output pin */ 5275 rc = (*scu_wr16)(dev_addr, SCU_RAM_AGC_IF_IACCU_HI_TGT_MAX__A, agc_settings->output_level, 0); 5276 if (rc != 0) { 5277 pr_err("error %d\n", rc); 5278 goto rw_error; 5279 } 5280 break; 5281 5282 case DRX_AGC_CTRL_OFF: 5283 5284 /* Disable If AGC DAC */ 5285 rc = drxj_dap_read_reg16(dev_addr, IQM_AF_STDBY__A, &data, 0); 5286 if (rc != 0) { 5287 pr_err("error %d\n", rc); 5288 goto rw_error; 5289 } 5290 data &= (~IQM_AF_STDBY_STDBY_TAGC_IF_A2_ACTIVE); 5291 rc = drxj_dap_write_reg16(dev_addr, IQM_AF_STDBY__A, data, 0); 5292 if (rc != 0) { 5293 pr_err("error %d\n", rc); 5294 goto rw_error; 5295 } 5296 5297 /* Disable SCU IF AGC loop */ 5298 rc = (*scu_rr16)(dev_addr, SCU_RAM_AGC_KI__A, &data, 0); 5299 if (rc != 0) { 5300 pr_err("error %d\n", rc); 5301 goto rw_error; 5302 } 5303 data &= ~SCU_RAM_AGC_KI_IF_AGC_DISABLE__M; 5304 data |= SCU_RAM_AGC_KI_IF_AGC_DISABLE__M; 5305 rc = (*scu_wr16)(dev_addr, SCU_RAM_AGC_KI__A, data, 0); 5306 if (rc != 0) { 5307 pr_err("error %d\n", rc); 5308 goto rw_error; 5309 } 5310 break; 5311 default: 5312 return -EINVAL; 5313 } /* switch ( agcsettings->ctrl_mode ) */ 5314 5315 /* always set the top to support configurations without if-loop */ 5316 rc = (*scu_wr16) (dev_addr, SCU_RAM_AGC_INGAIN_TGT_MIN__A, agc_settings->top, 0); 5317 if (rc != 0) { 5318 pr_err("error %d\n", rc); 5319 goto rw_error; 5320 } 5321 } 5322 5323 /* Store if agc settings */ 5324 switch (agc_settings->standard) { 5325 case DRX_STANDARD_8VSB: 5326 ext_attr->vsb_if_agc_cfg = *agc_settings; 5327 break; 5328 #ifndef DRXJ_VSB_ONLY 5329 case DRX_STANDARD_ITU_A: 5330 case DRX_STANDARD_ITU_B: 5331 case DRX_STANDARD_ITU_C: 5332 ext_attr->qam_if_agc_cfg = *agc_settings; 5333 break; 5334 #endif 5335 default: 5336 return -EIO; 5337 } 5338 5339 return 0; 5340 rw_error: 5341 return rc; 5342 } 5343 5344 /* 5345 * \fn int set_iqm_af () 5346 * \brief Configure IQM AF registers 5347 * \param demod instance of demodulator. 5348 * \param active 5349 * \return int. 5350 */ 5351 static int set_iqm_af(struct drx_demod_instance *demod, bool active) 5352 { 5353 u16 data = 0; 5354 struct i2c_device_addr *dev_addr = NULL; 5355 int rc; 5356 5357 dev_addr = demod->my_i2c_dev_addr; 5358 5359 /* Configure IQM */ 5360 rc = drxj_dap_read_reg16(dev_addr, IQM_AF_STDBY__A, &data, 0); 5361 if (rc != 0) { 5362 pr_err("error %d\n", rc); 5363 goto rw_error; 5364 } 5365 if (!active) 5366 data &= ((~IQM_AF_STDBY_STDBY_ADC_A2_ACTIVE) & (~IQM_AF_STDBY_STDBY_AMP_A2_ACTIVE) & (~IQM_AF_STDBY_STDBY_PD_A2_ACTIVE) & (~IQM_AF_STDBY_STDBY_TAGC_IF_A2_ACTIVE) & (~IQM_AF_STDBY_STDBY_TAGC_RF_A2_ACTIVE)); 5367 else 5368 data |= (IQM_AF_STDBY_STDBY_ADC_A2_ACTIVE | IQM_AF_STDBY_STDBY_AMP_A2_ACTIVE | IQM_AF_STDBY_STDBY_PD_A2_ACTIVE | IQM_AF_STDBY_STDBY_TAGC_IF_A2_ACTIVE | IQM_AF_STDBY_STDBY_TAGC_RF_A2_ACTIVE); 5369 rc = drxj_dap_write_reg16(dev_addr, IQM_AF_STDBY__A, data, 0); 5370 if (rc != 0) { 5371 pr_err("error %d\n", rc); 5372 goto rw_error; 5373 } 5374 5375 return 0; 5376 rw_error: 5377 return rc; 5378 } 5379 5380 /*============================================================================*/ 5381 /*== END 8VSB & QAM COMMON DATAPATH FUNCTIONS ==*/ 5382 /*============================================================================*/ 5383 5384 /*============================================================================*/ 5385 /*============================================================================*/ 5386 /*== 8VSB DATAPATH FUNCTIONS ==*/ 5387 /*============================================================================*/ 5388 /*============================================================================*/ 5389 5390 /* 5391 * \fn int power_down_vsb () 5392 * \brief Powr down QAM related blocks. 5393 * \param demod instance of demodulator. 5394 * \param channel pointer to channel data. 5395 * \return int. 5396 */ 5397 static int power_down_vsb(struct drx_demod_instance *demod, bool primary) 5398 { 5399 struct i2c_device_addr *dev_addr = demod->my_i2c_dev_addr; 5400 struct drxjscu_cmd cmd_scu = { /* command */ 0, 5401 /* parameter_len */ 0, 5402 /* result_len */ 0, 5403 /* *parameter */ NULL, 5404 /* *result */ NULL 5405 }; 5406 struct drx_cfg_mpeg_output cfg_mpeg_output; 5407 int rc; 5408 u16 cmd_result = 0; 5409 5410 /* 5411 STOP demodulator 5412 reset of FEC and VSB HW 5413 */ 5414 cmd_scu.command = SCU_RAM_COMMAND_STANDARD_VSB | 5415 SCU_RAM_COMMAND_CMD_DEMOD_STOP; 5416 cmd_scu.parameter_len = 0; 5417 cmd_scu.result_len = 1; 5418 cmd_scu.parameter = NULL; 5419 cmd_scu.result = &cmd_result; 5420 rc = scu_command(dev_addr, &cmd_scu); 5421 if (rc != 0) { 5422 pr_err("error %d\n", rc); 5423 goto rw_error; 5424 } 5425 5426 /* stop all comm_exec */ 5427 rc = drxj_dap_write_reg16(dev_addr, FEC_COMM_EXEC__A, FEC_COMM_EXEC_STOP, 0); 5428 if (rc != 0) { 5429 pr_err("error %d\n", rc); 5430 goto rw_error; 5431 } 5432 rc = drxj_dap_write_reg16(dev_addr, VSB_COMM_EXEC__A, VSB_COMM_EXEC_STOP, 0); 5433 if (rc != 0) { 5434 pr_err("error %d\n", rc); 5435 goto rw_error; 5436 } 5437 if (primary) { 5438 rc = drxj_dap_write_reg16(dev_addr, IQM_COMM_EXEC__A, IQM_COMM_EXEC_STOP, 0); 5439 if (rc != 0) { 5440 pr_err("error %d\n", rc); 5441 goto rw_error; 5442 } 5443 rc = set_iqm_af(demod, false); 5444 if (rc != 0) { 5445 pr_err("error %d\n", rc); 5446 goto rw_error; 5447 } 5448 } else { 5449 rc = drxj_dap_write_reg16(dev_addr, IQM_FS_COMM_EXEC__A, IQM_FS_COMM_EXEC_STOP, 0); 5450 if (rc != 0) { 5451 pr_err("error %d\n", rc); 5452 goto rw_error; 5453 } 5454 rc = drxj_dap_write_reg16(dev_addr, IQM_FD_COMM_EXEC__A, IQM_FD_COMM_EXEC_STOP, 0); 5455 if (rc != 0) { 5456 pr_err("error %d\n", rc); 5457 goto rw_error; 5458 } 5459 rc = drxj_dap_write_reg16(dev_addr, IQM_RC_COMM_EXEC__A, IQM_RC_COMM_EXEC_STOP, 0); 5460 if (rc != 0) { 5461 pr_err("error %d\n", rc); 5462 goto rw_error; 5463 } 5464 rc = drxj_dap_write_reg16(dev_addr, IQM_RT_COMM_EXEC__A, IQM_RT_COMM_EXEC_STOP, 0); 5465 if (rc != 0) { 5466 pr_err("error %d\n", rc); 5467 goto rw_error; 5468 } 5469 rc = drxj_dap_write_reg16(dev_addr, IQM_CF_COMM_EXEC__A, IQM_CF_COMM_EXEC_STOP, 0); 5470 if (rc != 0) { 5471 pr_err("error %d\n", rc); 5472 goto rw_error; 5473 } 5474 } 5475 5476 cfg_mpeg_output.enable_mpeg_output = false; 5477 rc = ctrl_set_cfg_mpeg_output(demod, &cfg_mpeg_output); 5478 if (rc != 0) { 5479 pr_err("error %d\n", rc); 5480 goto rw_error; 5481 } 5482 5483 return 0; 5484 rw_error: 5485 return rc; 5486 } 5487 5488 /* 5489 * \fn int set_vsb_leak_n_gain () 5490 * \brief Set ATSC demod. 5491 * \param demod instance of demodulator. 5492 * \return int. 5493 */ 5494 static int set_vsb_leak_n_gain(struct drx_demod_instance *demod) 5495 { 5496 struct i2c_device_addr *dev_addr = NULL; 5497 int rc; 5498 5499 static const u8 vsb_ffe_leak_gain_ram0[] = { 5500 DRXJ_16TO8(0x8), /* FFETRAINLKRATIO1 */ 5501 DRXJ_16TO8(0x8), /* FFETRAINLKRATIO2 */ 5502 DRXJ_16TO8(0x8), /* FFETRAINLKRATIO3 */ 5503 DRXJ_16TO8(0xf), /* FFETRAINLKRATIO4 */ 5504 DRXJ_16TO8(0xf), /* FFETRAINLKRATIO5 */ 5505 DRXJ_16TO8(0xf), /* FFETRAINLKRATIO6 */ 5506 DRXJ_16TO8(0xf), /* FFETRAINLKRATIO7 */ 5507 DRXJ_16TO8(0xf), /* FFETRAINLKRATIO8 */ 5508 DRXJ_16TO8(0xf), /* FFETRAINLKRATIO9 */ 5509 DRXJ_16TO8(0x8), /* FFETRAINLKRATIO10 */ 5510 DRXJ_16TO8(0x8), /* FFETRAINLKRATIO11 */ 5511 DRXJ_16TO8(0x8), /* FFETRAINLKRATIO12 */ 5512 DRXJ_16TO8(0x10), /* FFERCA1TRAINLKRATIO1 */ 5513 DRXJ_16TO8(0x10), /* FFERCA1TRAINLKRATIO2 */ 5514 DRXJ_16TO8(0x10), /* FFERCA1TRAINLKRATIO3 */ 5515 DRXJ_16TO8(0x20), /* FFERCA1TRAINLKRATIO4 */ 5516 DRXJ_16TO8(0x20), /* FFERCA1TRAINLKRATIO5 */ 5517 DRXJ_16TO8(0x20), /* FFERCA1TRAINLKRATIO6 */ 5518 DRXJ_16TO8(0x20), /* FFERCA1TRAINLKRATIO7 */ 5519 DRXJ_16TO8(0x20), /* FFERCA1TRAINLKRATIO8 */ 5520 DRXJ_16TO8(0x20), /* FFERCA1TRAINLKRATIO9 */ 5521 DRXJ_16TO8(0x10), /* FFERCA1TRAINLKRATIO10 */ 5522 DRXJ_16TO8(0x10), /* FFERCA1TRAINLKRATIO11 */ 5523 DRXJ_16TO8(0x10), /* FFERCA1TRAINLKRATIO12 */ 5524 DRXJ_16TO8(0x10), /* FFERCA1DATALKRATIO1 */ 5525 DRXJ_16TO8(0x10), /* FFERCA1DATALKRATIO2 */ 5526 DRXJ_16TO8(0x10), /* FFERCA1DATALKRATIO3 */ 5527 DRXJ_16TO8(0x20), /* FFERCA1DATALKRATIO4 */ 5528 DRXJ_16TO8(0x20), /* FFERCA1DATALKRATIO5 */ 5529 DRXJ_16TO8(0x20), /* FFERCA1DATALKRATIO6 */ 5530 DRXJ_16TO8(0x20), /* FFERCA1DATALKRATIO7 */ 5531 DRXJ_16TO8(0x20), /* FFERCA1DATALKRATIO8 */ 5532 DRXJ_16TO8(0x20), /* FFERCA1DATALKRATIO9 */ 5533 DRXJ_16TO8(0x10), /* FFERCA1DATALKRATIO10 */ 5534 DRXJ_16TO8(0x10), /* FFERCA1DATALKRATIO11 */ 5535 DRXJ_16TO8(0x10), /* FFERCA1DATALKRATIO12 */ 5536 DRXJ_16TO8(0x10), /* FFERCA2TRAINLKRATIO1 */ 5537 DRXJ_16TO8(0x10), /* FFERCA2TRAINLKRATIO2 */ 5538 DRXJ_16TO8(0x10), /* FFERCA2TRAINLKRATIO3 */ 5539 DRXJ_16TO8(0x20), /* FFERCA2TRAINLKRATIO4 */ 5540 DRXJ_16TO8(0x20), /* FFERCA2TRAINLKRATIO5 */ 5541 DRXJ_16TO8(0x20), /* FFERCA2TRAINLKRATIO6 */ 5542 DRXJ_16TO8(0x20), /* FFERCA2TRAINLKRATIO7 */ 5543 DRXJ_16TO8(0x20), /* FFERCA2TRAINLKRATIO8 */ 5544 DRXJ_16TO8(0x20), /* FFERCA2TRAINLKRATIO9 */ 5545 DRXJ_16TO8(0x10), /* FFERCA2TRAINLKRATIO10 */ 5546 DRXJ_16TO8(0x10), /* FFERCA2TRAINLKRATIO11 */ 5547 DRXJ_16TO8(0x10), /* FFERCA2TRAINLKRATIO12 */ 5548 DRXJ_16TO8(0x10), /* FFERCA2DATALKRATIO1 */ 5549 DRXJ_16TO8(0x10), /* FFERCA2DATALKRATIO2 */ 5550 DRXJ_16TO8(0x10), /* FFERCA2DATALKRATIO3 */ 5551 DRXJ_16TO8(0x20), /* FFERCA2DATALKRATIO4 */ 5552 DRXJ_16TO8(0x20), /* FFERCA2DATALKRATIO5 */ 5553 DRXJ_16TO8(0x20), /* FFERCA2DATALKRATIO6 */ 5554 DRXJ_16TO8(0x20), /* FFERCA2DATALKRATIO7 */ 5555 DRXJ_16TO8(0x20), /* FFERCA2DATALKRATIO8 */ 5556 DRXJ_16TO8(0x20), /* FFERCA2DATALKRATIO9 */ 5557 DRXJ_16TO8(0x10), /* FFERCA2DATALKRATIO10 */ 5558 DRXJ_16TO8(0x10), /* FFERCA2DATALKRATIO11 */ 5559 DRXJ_16TO8(0x10), /* FFERCA2DATALKRATIO12 */ 5560 DRXJ_16TO8(0x07), /* FFEDDM1TRAINLKRATIO1 */ 5561 DRXJ_16TO8(0x07), /* FFEDDM1TRAINLKRATIO2 */ 5562 DRXJ_16TO8(0x07), /* FFEDDM1TRAINLKRATIO3 */ 5563 DRXJ_16TO8(0x0e), /* FFEDDM1TRAINLKRATIO4 */ 5564 DRXJ_16TO8(0x0e), /* FFEDDM1TRAINLKRATIO5 */ 5565 DRXJ_16TO8(0x0e), /* FFEDDM1TRAINLKRATIO6 */ 5566 DRXJ_16TO8(0x0e), /* FFEDDM1TRAINLKRATIO7 */ 5567 DRXJ_16TO8(0x0e), /* FFEDDM1TRAINLKRATIO8 */ 5568 DRXJ_16TO8(0x0e), /* FFEDDM1TRAINLKRATIO9 */ 5569 DRXJ_16TO8(0x07), /* FFEDDM1TRAINLKRATIO10 */ 5570 DRXJ_16TO8(0x07), /* FFEDDM1TRAINLKRATIO11 */ 5571 DRXJ_16TO8(0x07), /* FFEDDM1TRAINLKRATIO12 */ 5572 DRXJ_16TO8(0x07), /* FFEDDM1DATALKRATIO1 */ 5573 DRXJ_16TO8(0x07), /* FFEDDM1DATALKRATIO2 */ 5574 DRXJ_16TO8(0x07), /* FFEDDM1DATALKRATIO3 */ 5575 DRXJ_16TO8(0x0e), /* FFEDDM1DATALKRATIO4 */ 5576 DRXJ_16TO8(0x0e), /* FFEDDM1DATALKRATIO5 */ 5577 DRXJ_16TO8(0x0e), /* FFEDDM1DATALKRATIO6 */ 5578 DRXJ_16TO8(0x0e), /* FFEDDM1DATALKRATIO7 */ 5579 DRXJ_16TO8(0x0e), /* FFEDDM1DATALKRATIO8 */ 5580 DRXJ_16TO8(0x0e), /* FFEDDM1DATALKRATIO9 */ 5581 DRXJ_16TO8(0x07), /* FFEDDM1DATALKRATIO10 */ 5582 DRXJ_16TO8(0x07), /* FFEDDM1DATALKRATIO11 */ 5583 DRXJ_16TO8(0x07), /* FFEDDM1DATALKRATIO12 */ 5584 DRXJ_16TO8(0x06), /* FFEDDM2TRAINLKRATIO1 */ 5585 DRXJ_16TO8(0x06), /* FFEDDM2TRAINLKRATIO2 */ 5586 DRXJ_16TO8(0x06), /* FFEDDM2TRAINLKRATIO3 */ 5587 DRXJ_16TO8(0x0c), /* FFEDDM2TRAINLKRATIO4 */ 5588 DRXJ_16TO8(0x0c), /* FFEDDM2TRAINLKRATIO5 */ 5589 DRXJ_16TO8(0x0c), /* FFEDDM2TRAINLKRATIO6 */ 5590 DRXJ_16TO8(0x0c), /* FFEDDM2TRAINLKRATIO7 */ 5591 DRXJ_16TO8(0x0c), /* FFEDDM2TRAINLKRATIO8 */ 5592 DRXJ_16TO8(0x0c), /* FFEDDM2TRAINLKRATIO9 */ 5593 DRXJ_16TO8(0x06), /* FFEDDM2TRAINLKRATIO10 */ 5594 DRXJ_16TO8(0x06), /* FFEDDM2TRAINLKRATIO11 */ 5595 DRXJ_16TO8(0x06), /* FFEDDM2TRAINLKRATIO12 */ 5596 DRXJ_16TO8(0x06), /* FFEDDM2DATALKRATIO1 */ 5597 DRXJ_16TO8(0x06), /* FFEDDM2DATALKRATIO2 */ 5598 DRXJ_16TO8(0x06), /* FFEDDM2DATALKRATIO3 */ 5599 DRXJ_16TO8(0x0c), /* FFEDDM2DATALKRATIO4 */ 5600 DRXJ_16TO8(0x0c), /* FFEDDM2DATALKRATIO5 */ 5601 DRXJ_16TO8(0x0c), /* FFEDDM2DATALKRATIO6 */ 5602 DRXJ_16TO8(0x0c), /* FFEDDM2DATALKRATIO7 */ 5603 DRXJ_16TO8(0x0c), /* FFEDDM2DATALKRATIO8 */ 5604 DRXJ_16TO8(0x0c), /* FFEDDM2DATALKRATIO9 */ 5605 DRXJ_16TO8(0x06), /* FFEDDM2DATALKRATIO10 */ 5606 DRXJ_16TO8(0x06), /* FFEDDM2DATALKRATIO11 */ 5607 DRXJ_16TO8(0x06), /* FFEDDM2DATALKRATIO12 */ 5608 DRXJ_16TO8(0x2020), /* FIRTRAINGAIN1 */ 5609 DRXJ_16TO8(0x2020), /* FIRTRAINGAIN2 */ 5610 DRXJ_16TO8(0x2020), /* FIRTRAINGAIN3 */ 5611 DRXJ_16TO8(0x4040), /* FIRTRAINGAIN4 */ 5612 DRXJ_16TO8(0x4040), /* FIRTRAINGAIN5 */ 5613 DRXJ_16TO8(0x4040), /* FIRTRAINGAIN6 */ 5614 DRXJ_16TO8(0x4040), /* FIRTRAINGAIN7 */ 5615 DRXJ_16TO8(0x4040), /* FIRTRAINGAIN8 */ 5616 DRXJ_16TO8(0x4040), /* FIRTRAINGAIN9 */ 5617 DRXJ_16TO8(0x2020), /* FIRTRAINGAIN10 */ 5618 DRXJ_16TO8(0x2020), /* FIRTRAINGAIN11 */ 5619 DRXJ_16TO8(0x2020), /* FIRTRAINGAIN12 */ 5620 DRXJ_16TO8(0x0808), /* FIRRCA1GAIN1 */ 5621 DRXJ_16TO8(0x0808), /* FIRRCA1GAIN2 */ 5622 DRXJ_16TO8(0x0808), /* FIRRCA1GAIN3 */ 5623 DRXJ_16TO8(0x1010), /* FIRRCA1GAIN4 */ 5624 DRXJ_16TO8(0x1010), /* FIRRCA1GAIN5 */ 5625 DRXJ_16TO8(0x1010), /* FIRRCA1GAIN6 */ 5626 DRXJ_16TO8(0x1010), /* FIRRCA1GAIN7 */ 5627 DRXJ_16TO8(0x1010) /* FIRRCA1GAIN8 */ 5628 }; 5629 5630 static const u8 vsb_ffe_leak_gain_ram1[] = { 5631 DRXJ_16TO8(0x1010), /* FIRRCA1GAIN9 */ 5632 DRXJ_16TO8(0x0808), /* FIRRCA1GAIN10 */ 5633 DRXJ_16TO8(0x0808), /* FIRRCA1GAIN11 */ 5634 DRXJ_16TO8(0x0808), /* FIRRCA1GAIN12 */ 5635 DRXJ_16TO8(0x0808), /* FIRRCA2GAIN1 */ 5636 DRXJ_16TO8(0x0808), /* FIRRCA2GAIN2 */ 5637 DRXJ_16TO8(0x0808), /* FIRRCA2GAIN3 */ 5638 DRXJ_16TO8(0x1010), /* FIRRCA2GAIN4 */ 5639 DRXJ_16TO8(0x1010), /* FIRRCA2GAIN5 */ 5640 DRXJ_16TO8(0x1010), /* FIRRCA2GAIN6 */ 5641 DRXJ_16TO8(0x1010), /* FIRRCA2GAIN7 */ 5642 DRXJ_16TO8(0x1010), /* FIRRCA2GAIN8 */ 5643 DRXJ_16TO8(0x1010), /* FIRRCA2GAIN9 */ 5644 DRXJ_16TO8(0x0808), /* FIRRCA2GAIN10 */ 5645 DRXJ_16TO8(0x0808), /* FIRRCA2GAIN11 */ 5646 DRXJ_16TO8(0x0808), /* FIRRCA2GAIN12 */ 5647 DRXJ_16TO8(0x0303), /* FIRDDM1GAIN1 */ 5648 DRXJ_16TO8(0x0303), /* FIRDDM1GAIN2 */ 5649 DRXJ_16TO8(0x0303), /* FIRDDM1GAIN3 */ 5650 DRXJ_16TO8(0x0606), /* FIRDDM1GAIN4 */ 5651 DRXJ_16TO8(0x0606), /* FIRDDM1GAIN5 */ 5652 DRXJ_16TO8(0x0606), /* FIRDDM1GAIN6 */ 5653 DRXJ_16TO8(0x0606), /* FIRDDM1GAIN7 */ 5654 DRXJ_16TO8(0x0606), /* FIRDDM1GAIN8 */ 5655 DRXJ_16TO8(0x0606), /* FIRDDM1GAIN9 */ 5656 DRXJ_16TO8(0x0303), /* FIRDDM1GAIN10 */ 5657 DRXJ_16TO8(0x0303), /* FIRDDM1GAIN11 */ 5658 DRXJ_16TO8(0x0303), /* FIRDDM1GAIN12 */ 5659 DRXJ_16TO8(0x0303), /* FIRDDM2GAIN1 */ 5660 DRXJ_16TO8(0x0303), /* FIRDDM2GAIN2 */ 5661 DRXJ_16TO8(0x0303), /* FIRDDM2GAIN3 */ 5662 DRXJ_16TO8(0x0505), /* FIRDDM2GAIN4 */ 5663 DRXJ_16TO8(0x0505), /* FIRDDM2GAIN5 */ 5664 DRXJ_16TO8(0x0505), /* FIRDDM2GAIN6 */ 5665 DRXJ_16TO8(0x0505), /* FIRDDM2GAIN7 */ 5666 DRXJ_16TO8(0x0505), /* FIRDDM2GAIN8 */ 5667 DRXJ_16TO8(0x0505), /* FIRDDM2GAIN9 */ 5668 DRXJ_16TO8(0x0303), /* FIRDDM2GAIN10 */ 5669 DRXJ_16TO8(0x0303), /* FIRDDM2GAIN11 */ 5670 DRXJ_16TO8(0x0303), /* FIRDDM2GAIN12 */ 5671 DRXJ_16TO8(0x001f), /* DFETRAINLKRATIO */ 5672 DRXJ_16TO8(0x01ff), /* DFERCA1TRAINLKRATIO */ 5673 DRXJ_16TO8(0x01ff), /* DFERCA1DATALKRATIO */ 5674 DRXJ_16TO8(0x004f), /* DFERCA2TRAINLKRATIO */ 5675 DRXJ_16TO8(0x004f), /* DFERCA2DATALKRATIO */ 5676 DRXJ_16TO8(0x01ff), /* DFEDDM1TRAINLKRATIO */ 5677 DRXJ_16TO8(0x01ff), /* DFEDDM1DATALKRATIO */ 5678 DRXJ_16TO8(0x0352), /* DFEDDM2TRAINLKRATIO */ 5679 DRXJ_16TO8(0x0352), /* DFEDDM2DATALKRATIO */ 5680 DRXJ_16TO8(0x0000), /* DFETRAINGAIN */ 5681 DRXJ_16TO8(0x2020), /* DFERCA1GAIN */ 5682 DRXJ_16TO8(0x1010), /* DFERCA2GAIN */ 5683 DRXJ_16TO8(0x1818), /* DFEDDM1GAIN */ 5684 DRXJ_16TO8(0x1212) /* DFEDDM2GAIN */ 5685 }; 5686 5687 dev_addr = demod->my_i2c_dev_addr; 5688 rc = drxdap_fasi_write_block(dev_addr, VSB_SYSCTRL_RAM0_FFETRAINLKRATIO1__A, sizeof(vsb_ffe_leak_gain_ram0), ((u8 *)vsb_ffe_leak_gain_ram0), 0); 5689 if (rc != 0) { 5690 pr_err("error %d\n", rc); 5691 goto rw_error; 5692 } 5693 rc = drxdap_fasi_write_block(dev_addr, VSB_SYSCTRL_RAM1_FIRRCA1GAIN9__A, sizeof(vsb_ffe_leak_gain_ram1), ((u8 *)vsb_ffe_leak_gain_ram1), 0); 5694 if (rc != 0) { 5695 pr_err("error %d\n", rc); 5696 goto rw_error; 5697 } 5698 5699 return 0; 5700 rw_error: 5701 return rc; 5702 } 5703 5704 /* 5705 * \fn int set_vsb() 5706 * \brief Set 8VSB demod. 5707 * \param demod instance of demodulator. 5708 * \return int. 5709 * 5710 */ 5711 static int set_vsb(struct drx_demod_instance *demod) 5712 { 5713 struct i2c_device_addr *dev_addr = NULL; 5714 int rc; 5715 struct drx_common_attr *common_attr = NULL; 5716 struct drxjscu_cmd cmd_scu; 5717 struct drxj_data *ext_attr = NULL; 5718 u16 cmd_result = 0; 5719 u16 cmd_param = 0; 5720 static const u8 vsb_taps_re[] = { 5721 DRXJ_16TO8(-2), /* re0 */ 5722 DRXJ_16TO8(4), /* re1 */ 5723 DRXJ_16TO8(1), /* re2 */ 5724 DRXJ_16TO8(-4), /* re3 */ 5725 DRXJ_16TO8(1), /* re4 */ 5726 DRXJ_16TO8(4), /* re5 */ 5727 DRXJ_16TO8(-3), /* re6 */ 5728 DRXJ_16TO8(-3), /* re7 */ 5729 DRXJ_16TO8(6), /* re8 */ 5730 DRXJ_16TO8(1), /* re9 */ 5731 DRXJ_16TO8(-9), /* re10 */ 5732 DRXJ_16TO8(3), /* re11 */ 5733 DRXJ_16TO8(12), /* re12 */ 5734 DRXJ_16TO8(-9), /* re13 */ 5735 DRXJ_16TO8(-15), /* re14 */ 5736 DRXJ_16TO8(17), /* re15 */ 5737 DRXJ_16TO8(19), /* re16 */ 5738 DRXJ_16TO8(-29), /* re17 */ 5739 DRXJ_16TO8(-22), /* re18 */ 5740 DRXJ_16TO8(45), /* re19 */ 5741 DRXJ_16TO8(25), /* re20 */ 5742 DRXJ_16TO8(-70), /* re21 */ 5743 DRXJ_16TO8(-28), /* re22 */ 5744 DRXJ_16TO8(111), /* re23 */ 5745 DRXJ_16TO8(30), /* re24 */ 5746 DRXJ_16TO8(-201), /* re25 */ 5747 DRXJ_16TO8(-31), /* re26 */ 5748 DRXJ_16TO8(629) /* re27 */ 5749 }; 5750 5751 dev_addr = demod->my_i2c_dev_addr; 5752 common_attr = (struct drx_common_attr *) demod->my_common_attr; 5753 ext_attr = (struct drxj_data *) demod->my_ext_attr; 5754 5755 /* stop all comm_exec */ 5756 rc = drxj_dap_write_reg16(dev_addr, FEC_COMM_EXEC__A, FEC_COMM_EXEC_STOP, 0); 5757 if (rc != 0) { 5758 pr_err("error %d\n", rc); 5759 goto rw_error; 5760 } 5761 rc = drxj_dap_write_reg16(dev_addr, VSB_COMM_EXEC__A, VSB_COMM_EXEC_STOP, 0); 5762 if (rc != 0) { 5763 pr_err("error %d\n", rc); 5764 goto rw_error; 5765 } 5766 rc = drxj_dap_write_reg16(dev_addr, IQM_FS_COMM_EXEC__A, IQM_FS_COMM_EXEC_STOP, 0); 5767 if (rc != 0) { 5768 pr_err("error %d\n", rc); 5769 goto rw_error; 5770 } 5771 rc = drxj_dap_write_reg16(dev_addr, IQM_FD_COMM_EXEC__A, IQM_FD_COMM_EXEC_STOP, 0); 5772 if (rc != 0) { 5773 pr_err("error %d\n", rc); 5774 goto rw_error; 5775 } 5776 rc = drxj_dap_write_reg16(dev_addr, IQM_RC_COMM_EXEC__A, IQM_RC_COMM_EXEC_STOP, 0); 5777 if (rc != 0) { 5778 pr_err("error %d\n", rc); 5779 goto rw_error; 5780 } 5781 rc = drxj_dap_write_reg16(dev_addr, IQM_RT_COMM_EXEC__A, IQM_RT_COMM_EXEC_STOP, 0); 5782 if (rc != 0) { 5783 pr_err("error %d\n", rc); 5784 goto rw_error; 5785 } 5786 rc = drxj_dap_write_reg16(dev_addr, IQM_CF_COMM_EXEC__A, IQM_CF_COMM_EXEC_STOP, 0); 5787 if (rc != 0) { 5788 pr_err("error %d\n", rc); 5789 goto rw_error; 5790 } 5791 5792 /* reset demodulator */ 5793 cmd_scu.command = SCU_RAM_COMMAND_STANDARD_VSB 5794 | SCU_RAM_COMMAND_CMD_DEMOD_RESET; 5795 cmd_scu.parameter_len = 0; 5796 cmd_scu.result_len = 1; 5797 cmd_scu.parameter = NULL; 5798 cmd_scu.result = &cmd_result; 5799 rc = scu_command(dev_addr, &cmd_scu); 5800 if (rc != 0) { 5801 pr_err("error %d\n", rc); 5802 goto rw_error; 5803 } 5804 5805 rc = drxj_dap_write_reg16(dev_addr, IQM_AF_DCF_BYPASS__A, 1, 0); 5806 if (rc != 0) { 5807 pr_err("error %d\n", rc); 5808 goto rw_error; 5809 } 5810 rc = drxj_dap_write_reg16(dev_addr, IQM_FS_ADJ_SEL__A, IQM_FS_ADJ_SEL_B_VSB, 0); 5811 if (rc != 0) { 5812 pr_err("error %d\n", rc); 5813 goto rw_error; 5814 } 5815 rc = drxj_dap_write_reg16(dev_addr, IQM_RC_ADJ_SEL__A, IQM_RC_ADJ_SEL_B_VSB, 0); 5816 if (rc != 0) { 5817 pr_err("error %d\n", rc); 5818 goto rw_error; 5819 } 5820 ext_attr->iqm_rc_rate_ofs = 0x00AD0D79; 5821 rc = drxdap_fasi_write_reg32(dev_addr, IQM_RC_RATE_OFS_LO__A, ext_attr->iqm_rc_rate_ofs, 0); 5822 if (rc != 0) { 5823 pr_err("error %d\n", rc); 5824 goto rw_error; 5825 } 5826 rc = drxj_dap_write_reg16(dev_addr, VSB_TOP_CFAGC_GAINSHIFT__A, 4, 0); 5827 if (rc != 0) { 5828 pr_err("error %d\n", rc); 5829 goto rw_error; 5830 } 5831 rc = drxj_dap_write_reg16(dev_addr, VSB_TOP_CYGN1TRK__A, 1, 0); 5832 if (rc != 0) { 5833 pr_err("error %d\n", rc); 5834 goto rw_error; 5835 } 5836 5837 rc = drxj_dap_write_reg16(dev_addr, IQM_RC_CROUT_ENA__A, 1, 0); 5838 if (rc != 0) { 5839 pr_err("error %d\n", rc); 5840 goto rw_error; 5841 } 5842 rc = drxj_dap_write_reg16(dev_addr, IQM_RC_STRETCH__A, 28, 0); 5843 if (rc != 0) { 5844 pr_err("error %d\n", rc); 5845 goto rw_error; 5846 } 5847 rc = drxj_dap_write_reg16(dev_addr, IQM_RT_ACTIVE__A, 0, 0); 5848 if (rc != 0) { 5849 pr_err("error %d\n", rc); 5850 goto rw_error; 5851 } 5852 rc = drxj_dap_write_reg16(dev_addr, IQM_CF_SYMMETRIC__A, 0, 0); 5853 if (rc != 0) { 5854 pr_err("error %d\n", rc); 5855 goto rw_error; 5856 } 5857 rc = drxj_dap_write_reg16(dev_addr, IQM_CF_MIDTAP__A, 3, 0); 5858 if (rc != 0) { 5859 pr_err("error %d\n", rc); 5860 goto rw_error; 5861 } 5862 rc = drxj_dap_write_reg16(dev_addr, IQM_CF_OUT_ENA__A, IQM_CF_OUT_ENA_VSB__M, 0); 5863 if (rc != 0) { 5864 pr_err("error %d\n", rc); 5865 goto rw_error; 5866 } 5867 rc = drxj_dap_write_reg16(dev_addr, IQM_CF_SCALE__A, 1393, 0); 5868 if (rc != 0) { 5869 pr_err("error %d\n", rc); 5870 goto rw_error; 5871 } 5872 rc = drxj_dap_write_reg16(dev_addr, IQM_CF_SCALE_SH__A, 0, 0); 5873 if (rc != 0) { 5874 pr_err("error %d\n", rc); 5875 goto rw_error; 5876 } 5877 rc = drxj_dap_write_reg16(dev_addr, IQM_CF_POW_MEAS_LEN__A, 1, 0); 5878 if (rc != 0) { 5879 pr_err("error %d\n", rc); 5880 goto rw_error; 5881 } 5882 5883 rc = drxdap_fasi_write_block(dev_addr, IQM_CF_TAP_RE0__A, sizeof(vsb_taps_re), ((u8 *)vsb_taps_re), 0); 5884 if (rc != 0) { 5885 pr_err("error %d\n", rc); 5886 goto rw_error; 5887 } 5888 rc = drxdap_fasi_write_block(dev_addr, IQM_CF_TAP_IM0__A, sizeof(vsb_taps_re), ((u8 *)vsb_taps_re), 0); 5889 if (rc != 0) { 5890 pr_err("error %d\n", rc); 5891 goto rw_error; 5892 } 5893 5894 rc = drxj_dap_write_reg16(dev_addr, VSB_TOP_BNTHRESH__A, 330, 0); 5895 if (rc != 0) { 5896 pr_err("error %d\n", rc); 5897 goto rw_error; 5898 } /* set higher threshold */ 5899 rc = drxj_dap_write_reg16(dev_addr, VSB_TOP_CLPLASTNUM__A, 90, 0); 5900 if (rc != 0) { 5901 pr_err("error %d\n", rc); 5902 goto rw_error; 5903 } /* burst detection on */ 5904 rc = drxj_dap_write_reg16(dev_addr, VSB_TOP_SNRTH_RCA1__A, 0x0042, 0); 5905 if (rc != 0) { 5906 pr_err("error %d\n", rc); 5907 goto rw_error; 5908 } /* drop thresholds by 1 dB */ 5909 rc = drxj_dap_write_reg16(dev_addr, VSB_TOP_SNRTH_RCA2__A, 0x0053, 0); 5910 if (rc != 0) { 5911 pr_err("error %d\n", rc); 5912 goto rw_error; 5913 } /* drop thresholds by 2 dB */ 5914 rc = drxj_dap_write_reg16(dev_addr, VSB_TOP_EQCTRL__A, 0x1, 0); 5915 if (rc != 0) { 5916 pr_err("error %d\n", rc); 5917 goto rw_error; 5918 } /* cma on */ 5919 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_GPIO__A, 0, 0); 5920 if (rc != 0) { 5921 pr_err("error %d\n", rc); 5922 goto rw_error; 5923 } /* GPIO */ 5924 5925 /* Initialize the FEC Subsystem */ 5926 rc = drxj_dap_write_reg16(dev_addr, FEC_TOP_ANNEX__A, FEC_TOP_ANNEX_D, 0); 5927 if (rc != 0) { 5928 pr_err("error %d\n", rc); 5929 goto rw_error; 5930 } 5931 { 5932 u16 fec_oc_snc_mode = 0; 5933 rc = drxj_dap_read_reg16(dev_addr, FEC_OC_SNC_MODE__A, &fec_oc_snc_mode, 0); 5934 if (rc != 0) { 5935 pr_err("error %d\n", rc); 5936 goto rw_error; 5937 } 5938 /* output data even when not locked */ 5939 rc = drxj_dap_write_reg16(dev_addr, FEC_OC_SNC_MODE__A, fec_oc_snc_mode | FEC_OC_SNC_MODE_UNLOCK_ENABLE__M, 0); 5940 if (rc != 0) { 5941 pr_err("error %d\n", rc); 5942 goto rw_error; 5943 } 5944 } 5945 5946 /* set clip */ 5947 rc = drxj_dap_write_reg16(dev_addr, IQM_AF_CLP_LEN__A, 0, 0); 5948 if (rc != 0) { 5949 pr_err("error %d\n", rc); 5950 goto rw_error; 5951 } 5952 rc = drxj_dap_write_reg16(dev_addr, IQM_AF_CLP_TH__A, 470, 0); 5953 if (rc != 0) { 5954 pr_err("error %d\n", rc); 5955 goto rw_error; 5956 } 5957 rc = drxj_dap_write_reg16(dev_addr, IQM_AF_SNS_LEN__A, 0, 0); 5958 if (rc != 0) { 5959 pr_err("error %d\n", rc); 5960 goto rw_error; 5961 } 5962 rc = drxj_dap_write_reg16(dev_addr, VSB_TOP_SNRTH_PT__A, 0xD4, 0); 5963 if (rc != 0) { 5964 pr_err("error %d\n", rc); 5965 goto rw_error; 5966 } 5967 /* no transparent, no A&C framing; parity is set in mpegoutput */ 5968 { 5969 u16 fec_oc_reg_mode = 0; 5970 rc = drxj_dap_read_reg16(dev_addr, FEC_OC_MODE__A, &fec_oc_reg_mode, 0); 5971 if (rc != 0) { 5972 pr_err("error %d\n", rc); 5973 goto rw_error; 5974 } 5975 rc = drxj_dap_write_reg16(dev_addr, FEC_OC_MODE__A, fec_oc_reg_mode & (~(FEC_OC_MODE_TRANSPARENT__M | FEC_OC_MODE_CLEAR__M | FEC_OC_MODE_RETAIN_FRAMING__M)), 0); 5976 if (rc != 0) { 5977 pr_err("error %d\n", rc); 5978 goto rw_error; 5979 } 5980 } 5981 5982 rc = drxj_dap_write_reg16(dev_addr, FEC_DI_TIMEOUT_LO__A, 0, 0); 5983 if (rc != 0) { 5984 pr_err("error %d\n", rc); 5985 goto rw_error; 5986 } /* timeout counter for restarting */ 5987 rc = drxj_dap_write_reg16(dev_addr, FEC_DI_TIMEOUT_HI__A, 3, 0); 5988 if (rc != 0) { 5989 pr_err("error %d\n", rc); 5990 goto rw_error; 5991 } 5992 rc = drxj_dap_write_reg16(dev_addr, FEC_RS_MODE__A, 0, 0); 5993 if (rc != 0) { 5994 pr_err("error %d\n", rc); 5995 goto rw_error; 5996 } /* bypass disabled */ 5997 /* initialize RS packet error measurement parameters */ 5998 rc = drxj_dap_write_reg16(dev_addr, FEC_RS_MEASUREMENT_PERIOD__A, FEC_RS_MEASUREMENT_PERIOD, 0); 5999 if (rc != 0) { 6000 pr_err("error %d\n", rc); 6001 goto rw_error; 6002 } 6003 rc = drxj_dap_write_reg16(dev_addr, FEC_RS_MEASUREMENT_PRESCALE__A, FEC_RS_MEASUREMENT_PRESCALE, 0); 6004 if (rc != 0) { 6005 pr_err("error %d\n", rc); 6006 goto rw_error; 6007 } 6008 6009 /* init measurement period of MER/SER */ 6010 rc = drxj_dap_write_reg16(dev_addr, VSB_TOP_MEASUREMENT_PERIOD__A, VSB_TOP_MEASUREMENT_PERIOD, 0); 6011 if (rc != 0) { 6012 pr_err("error %d\n", rc); 6013 goto rw_error; 6014 } 6015 rc = drxdap_fasi_write_reg32(dev_addr, SCU_RAM_FEC_ACCUM_CW_CORRECTED_LO__A, 0, 0); 6016 if (rc != 0) { 6017 pr_err("error %d\n", rc); 6018 goto rw_error; 6019 } 6020 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_FEC_MEAS_COUNT__A, 0, 0); 6021 if (rc != 0) { 6022 pr_err("error %d\n", rc); 6023 goto rw_error; 6024 } 6025 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_FEC_ACCUM_PKT_FAILURES__A, 0, 0); 6026 if (rc != 0) { 6027 pr_err("error %d\n", rc); 6028 goto rw_error; 6029 } 6030 6031 rc = drxj_dap_write_reg16(dev_addr, VSB_TOP_CKGN1TRK__A, 128, 0); 6032 if (rc != 0) { 6033 pr_err("error %d\n", rc); 6034 goto rw_error; 6035 } 6036 /* B-Input to ADC, PGA+filter in standby */ 6037 if (!ext_attr->has_lna) { 6038 rc = drxj_dap_write_reg16(dev_addr, IQM_AF_AMUX__A, 0x02, 0); 6039 if (rc != 0) { 6040 pr_err("error %d\n", rc); 6041 goto rw_error; 6042 } 6043 } 6044 6045 /* turn on IQMAF. It has to be in front of setAgc**() */ 6046 rc = set_iqm_af(demod, true); 6047 if (rc != 0) { 6048 pr_err("error %d\n", rc); 6049 goto rw_error; 6050 } 6051 rc = adc_synchronization(demod); 6052 if (rc != 0) { 6053 pr_err("error %d\n", rc); 6054 goto rw_error; 6055 } 6056 6057 rc = init_agc(demod); 6058 if (rc != 0) { 6059 pr_err("error %d\n", rc); 6060 goto rw_error; 6061 } 6062 rc = set_agc_if(demod, &(ext_attr->vsb_if_agc_cfg), false); 6063 if (rc != 0) { 6064 pr_err("error %d\n", rc); 6065 goto rw_error; 6066 } 6067 rc = set_agc_rf(demod, &(ext_attr->vsb_rf_agc_cfg), false); 6068 if (rc != 0) { 6069 pr_err("error %d\n", rc); 6070 goto rw_error; 6071 } 6072 { 6073 /* TODO fix this, store a struct drxj_cfg_afe_gain structure in struct drxj_data instead 6074 of only the gain */ 6075 struct drxj_cfg_afe_gain vsb_pga_cfg = { DRX_STANDARD_8VSB, 0 }; 6076 6077 vsb_pga_cfg.gain = ext_attr->vsb_pga_cfg; 6078 rc = ctrl_set_cfg_afe_gain(demod, &vsb_pga_cfg); 6079 if (rc != 0) { 6080 pr_err("error %d\n", rc); 6081 goto rw_error; 6082 } 6083 } 6084 rc = ctrl_set_cfg_pre_saw(demod, &(ext_attr->vsb_pre_saw_cfg)); 6085 if (rc != 0) { 6086 pr_err("error %d\n", rc); 6087 goto rw_error; 6088 } 6089 6090 /* Mpeg output has to be in front of FEC active */ 6091 rc = set_mpegtei_handling(demod); 6092 if (rc != 0) { 6093 pr_err("error %d\n", rc); 6094 goto rw_error; 6095 } 6096 rc = bit_reverse_mpeg_output(demod); 6097 if (rc != 0) { 6098 pr_err("error %d\n", rc); 6099 goto rw_error; 6100 } 6101 rc = set_mpeg_start_width(demod); 6102 if (rc != 0) { 6103 pr_err("error %d\n", rc); 6104 goto rw_error; 6105 } 6106 { 6107 /* TODO: move to set_standard after hardware reset value problem is solved */ 6108 /* Configure initial MPEG output */ 6109 struct drx_cfg_mpeg_output cfg_mpeg_output; 6110 6111 memcpy(&cfg_mpeg_output, &common_attr->mpeg_cfg, sizeof(cfg_mpeg_output)); 6112 cfg_mpeg_output.enable_mpeg_output = true; 6113 6114 rc = ctrl_set_cfg_mpeg_output(demod, &cfg_mpeg_output); 6115 if (rc != 0) { 6116 pr_err("error %d\n", rc); 6117 goto rw_error; 6118 } 6119 } 6120 6121 /* TBD: what parameters should be set */ 6122 cmd_param = 0x00; /* Default mode AGC on, etc */ 6123 cmd_scu.command = SCU_RAM_COMMAND_STANDARD_VSB 6124 | SCU_RAM_COMMAND_CMD_DEMOD_SET_PARAM; 6125 cmd_scu.parameter_len = 1; 6126 cmd_scu.result_len = 1; 6127 cmd_scu.parameter = &cmd_param; 6128 cmd_scu.result = &cmd_result; 6129 rc = scu_command(dev_addr, &cmd_scu); 6130 if (rc != 0) { 6131 pr_err("error %d\n", rc); 6132 goto rw_error; 6133 } 6134 6135 rc = drxj_dap_write_reg16(dev_addr, VSB_TOP_BEAGC_GAINSHIFT__A, 0x0004, 0); 6136 if (rc != 0) { 6137 pr_err("error %d\n", rc); 6138 goto rw_error; 6139 } 6140 rc = drxj_dap_write_reg16(dev_addr, VSB_TOP_SNRTH_PT__A, 0x00D2, 0); 6141 if (rc != 0) { 6142 pr_err("error %d\n", rc); 6143 goto rw_error; 6144 } 6145 rc = drxj_dap_write_reg16(dev_addr, VSB_TOP_SYSSMTRNCTRL__A, VSB_TOP_SYSSMTRNCTRL__PRE | VSB_TOP_SYSSMTRNCTRL_NCOTIMEOUTCNTEN__M, 0); 6146 if (rc != 0) { 6147 pr_err("error %d\n", rc); 6148 goto rw_error; 6149 } 6150 rc = drxj_dap_write_reg16(dev_addr, VSB_TOP_BEDETCTRL__A, 0x142, 0); 6151 if (rc != 0) { 6152 pr_err("error %d\n", rc); 6153 goto rw_error; 6154 } 6155 rc = drxj_dap_write_reg16(dev_addr, VSB_TOP_LBAGCREFLVL__A, 640, 0); 6156 if (rc != 0) { 6157 pr_err("error %d\n", rc); 6158 goto rw_error; 6159 } 6160 rc = drxj_dap_write_reg16(dev_addr, VSB_TOP_CYGN1ACQ__A, 4, 0); 6161 if (rc != 0) { 6162 pr_err("error %d\n", rc); 6163 goto rw_error; 6164 } 6165 rc = drxj_dap_write_reg16(dev_addr, VSB_TOP_CYGN1TRK__A, 2, 0); 6166 if (rc != 0) { 6167 pr_err("error %d\n", rc); 6168 goto rw_error; 6169 } 6170 rc = drxj_dap_write_reg16(dev_addr, VSB_TOP_CYGN2TRK__A, 3, 0); 6171 if (rc != 0) { 6172 pr_err("error %d\n", rc); 6173 goto rw_error; 6174 } 6175 6176 /* start demodulator */ 6177 cmd_scu.command = SCU_RAM_COMMAND_STANDARD_VSB 6178 | SCU_RAM_COMMAND_CMD_DEMOD_START; 6179 cmd_scu.parameter_len = 0; 6180 cmd_scu.result_len = 1; 6181 cmd_scu.parameter = NULL; 6182 cmd_scu.result = &cmd_result; 6183 rc = scu_command(dev_addr, &cmd_scu); 6184 if (rc != 0) { 6185 pr_err("error %d\n", rc); 6186 goto rw_error; 6187 } 6188 6189 rc = drxj_dap_write_reg16(dev_addr, IQM_COMM_EXEC__A, IQM_COMM_EXEC_ACTIVE, 0); 6190 if (rc != 0) { 6191 pr_err("error %d\n", rc); 6192 goto rw_error; 6193 } 6194 rc = drxj_dap_write_reg16(dev_addr, VSB_COMM_EXEC__A, VSB_COMM_EXEC_ACTIVE, 0); 6195 if (rc != 0) { 6196 pr_err("error %d\n", rc); 6197 goto rw_error; 6198 } 6199 rc = drxj_dap_write_reg16(dev_addr, FEC_COMM_EXEC__A, FEC_COMM_EXEC_ACTIVE, 0); 6200 if (rc != 0) { 6201 pr_err("error %d\n", rc); 6202 goto rw_error; 6203 } 6204 6205 return 0; 6206 rw_error: 6207 return rc; 6208 } 6209 6210 /* 6211 * \fn static short get_vsb_post_rs_pck_err(struct i2c_device_addr *dev_addr, u16 *PckErrs) 6212 * \brief Get the values of packet error in 8VSB mode 6213 * \return Error code 6214 */ 6215 static int get_vsb_post_rs_pck_err(struct i2c_device_addr *dev_addr, 6216 u32 *pck_errs, u32 *pck_count) 6217 { 6218 int rc; 6219 u16 data = 0; 6220 u16 period = 0; 6221 u16 prescale = 0; 6222 u16 packet_errors_mant = 0; 6223 u16 packet_errors_exp = 0; 6224 6225 rc = drxj_dap_read_reg16(dev_addr, FEC_RS_NR_FAILURES__A, &data, 0); 6226 if (rc != 0) { 6227 pr_err("error %d\n", rc); 6228 goto rw_error; 6229 } 6230 packet_errors_mant = data & FEC_RS_NR_FAILURES_FIXED_MANT__M; 6231 packet_errors_exp = (data & FEC_RS_NR_FAILURES_EXP__M) 6232 >> FEC_RS_NR_FAILURES_EXP__B; 6233 period = FEC_RS_MEASUREMENT_PERIOD; 6234 prescale = FEC_RS_MEASUREMENT_PRESCALE; 6235 /* packet error rate = (error packet number) per second */ 6236 /* 77.3 us is time for per packet */ 6237 if (period * prescale == 0) { 6238 pr_err("error: period and/or prescale is zero!\n"); 6239 return -EIO; 6240 } 6241 *pck_errs = packet_errors_mant * (1 << packet_errors_exp); 6242 *pck_count = period * prescale * 77; 6243 6244 return 0; 6245 rw_error: 6246 return rc; 6247 } 6248 6249 /* 6250 * \fn static short GetVSBBer(struct i2c_device_addr *dev_addr, u32 *ber) 6251 * \brief Get the values of ber in VSB mode 6252 * \return Error code 6253 */ 6254 static int get_vs_bpost_viterbi_ber(struct i2c_device_addr *dev_addr, 6255 u32 *ber, u32 *cnt) 6256 { 6257 int rc; 6258 u16 data = 0; 6259 u16 period = 0; 6260 u16 prescale = 0; 6261 u16 bit_errors_mant = 0; 6262 u16 bit_errors_exp = 0; 6263 6264 rc = drxj_dap_read_reg16(dev_addr, FEC_RS_NR_BIT_ERRORS__A, &data, 0); 6265 if (rc != 0) { 6266 pr_err("error %d\n", rc); 6267 goto rw_error; 6268 } 6269 period = FEC_RS_MEASUREMENT_PERIOD; 6270 prescale = FEC_RS_MEASUREMENT_PRESCALE; 6271 6272 bit_errors_mant = data & FEC_RS_NR_BIT_ERRORS_FIXED_MANT__M; 6273 bit_errors_exp = (data & FEC_RS_NR_BIT_ERRORS_EXP__M) 6274 >> FEC_RS_NR_BIT_ERRORS_EXP__B; 6275 6276 *cnt = period * prescale * 207 * ((bit_errors_exp > 2) ? 1 : 8); 6277 6278 if (((bit_errors_mant << bit_errors_exp) >> 3) > 68700) 6279 *ber = (*cnt) * 26570; 6280 else { 6281 if (period * prescale == 0) { 6282 pr_err("error: period and/or prescale is zero!\n"); 6283 return -EIO; 6284 } 6285 *ber = bit_errors_mant << ((bit_errors_exp > 2) ? 6286 (bit_errors_exp - 3) : bit_errors_exp); 6287 } 6288 6289 return 0; 6290 rw_error: 6291 return rc; 6292 } 6293 6294 /* 6295 * \fn static short get_vs_bpre_viterbi_ber(struct i2c_device_addr *dev_addr, u32 *ber) 6296 * \brief Get the values of ber in VSB mode 6297 * \return Error code 6298 */ 6299 static int get_vs_bpre_viterbi_ber(struct i2c_device_addr *dev_addr, 6300 u32 *ber, u32 *cnt) 6301 { 6302 u16 data = 0; 6303 int rc; 6304 6305 rc = drxj_dap_read_reg16(dev_addr, VSB_TOP_NR_SYM_ERRS__A, &data, 0); 6306 if (rc != 0) { 6307 pr_err("error %d\n", rc); 6308 return -EIO; 6309 } 6310 *ber = data; 6311 *cnt = VSB_TOP_MEASUREMENT_PERIOD * SYMBOLS_PER_SEGMENT; 6312 6313 return 0; 6314 } 6315 6316 /* 6317 * \fn static int get_vsbmer(struct i2c_device_addr *dev_addr, u16 *mer) 6318 * \brief Get the values of MER 6319 * \return Error code 6320 */ 6321 static int get_vsbmer(struct i2c_device_addr *dev_addr, u16 *mer) 6322 { 6323 int rc; 6324 u16 data_hi = 0; 6325 6326 rc = drxj_dap_read_reg16(dev_addr, VSB_TOP_ERR_ENERGY_H__A, &data_hi, 0); 6327 if (rc != 0) { 6328 pr_err("error %d\n", rc); 6329 goto rw_error; 6330 } 6331 *mer = 6332 (u16) (log1_times100(21504) - log1_times100((data_hi << 6) / 52)); 6333 6334 return 0; 6335 rw_error: 6336 return rc; 6337 } 6338 6339 6340 /*============================================================================*/ 6341 /*== END 8VSB DATAPATH FUNCTIONS ==*/ 6342 /*============================================================================*/ 6343 6344 /*============================================================================*/ 6345 /*============================================================================*/ 6346 /*== QAM DATAPATH FUNCTIONS ==*/ 6347 /*============================================================================*/ 6348 /*============================================================================*/ 6349 6350 /* 6351 * \fn int power_down_qam () 6352 * \brief Powr down QAM related blocks. 6353 * \param demod instance of demodulator. 6354 * \param channel pointer to channel data. 6355 * \return int. 6356 */ 6357 static int power_down_qam(struct drx_demod_instance *demod, bool primary) 6358 { 6359 struct drxjscu_cmd cmd_scu = { /* command */ 0, 6360 /* parameter_len */ 0, 6361 /* result_len */ 0, 6362 /* *parameter */ NULL, 6363 /* *result */ NULL 6364 }; 6365 int rc; 6366 struct i2c_device_addr *dev_addr = demod->my_i2c_dev_addr; 6367 struct drx_cfg_mpeg_output cfg_mpeg_output; 6368 struct drx_common_attr *common_attr = demod->my_common_attr; 6369 u16 cmd_result = 0; 6370 6371 /* 6372 STOP demodulator 6373 resets IQM, QAM and FEC HW blocks 6374 */ 6375 /* stop all comm_exec */ 6376 rc = drxj_dap_write_reg16(dev_addr, FEC_COMM_EXEC__A, FEC_COMM_EXEC_STOP, 0); 6377 if (rc != 0) { 6378 pr_err("error %d\n", rc); 6379 goto rw_error; 6380 } 6381 rc = drxj_dap_write_reg16(dev_addr, QAM_COMM_EXEC__A, QAM_COMM_EXEC_STOP, 0); 6382 if (rc != 0) { 6383 pr_err("error %d\n", rc); 6384 goto rw_error; 6385 } 6386 6387 cmd_scu.command = SCU_RAM_COMMAND_STANDARD_QAM | 6388 SCU_RAM_COMMAND_CMD_DEMOD_STOP; 6389 cmd_scu.parameter_len = 0; 6390 cmd_scu.result_len = 1; 6391 cmd_scu.parameter = NULL; 6392 cmd_scu.result = &cmd_result; 6393 rc = scu_command(dev_addr, &cmd_scu); 6394 if (rc != 0) { 6395 pr_err("error %d\n", rc); 6396 goto rw_error; 6397 } 6398 6399 if (primary) { 6400 rc = drxj_dap_write_reg16(dev_addr, IQM_COMM_EXEC__A, IQM_COMM_EXEC_STOP, 0); 6401 if (rc != 0) { 6402 pr_err("error %d\n", rc); 6403 goto rw_error; 6404 } 6405 rc = set_iqm_af(demod, false); 6406 if (rc != 0) { 6407 pr_err("error %d\n", rc); 6408 goto rw_error; 6409 } 6410 } else { 6411 rc = drxj_dap_write_reg16(dev_addr, IQM_FS_COMM_EXEC__A, IQM_FS_COMM_EXEC_STOP, 0); 6412 if (rc != 0) { 6413 pr_err("error %d\n", rc); 6414 goto rw_error; 6415 } 6416 rc = drxj_dap_write_reg16(dev_addr, IQM_FD_COMM_EXEC__A, IQM_FD_COMM_EXEC_STOP, 0); 6417 if (rc != 0) { 6418 pr_err("error %d\n", rc); 6419 goto rw_error; 6420 } 6421 rc = drxj_dap_write_reg16(dev_addr, IQM_RC_COMM_EXEC__A, IQM_RC_COMM_EXEC_STOP, 0); 6422 if (rc != 0) { 6423 pr_err("error %d\n", rc); 6424 goto rw_error; 6425 } 6426 rc = drxj_dap_write_reg16(dev_addr, IQM_RT_COMM_EXEC__A, IQM_RT_COMM_EXEC_STOP, 0); 6427 if (rc != 0) { 6428 pr_err("error %d\n", rc); 6429 goto rw_error; 6430 } 6431 rc = drxj_dap_write_reg16(dev_addr, IQM_CF_COMM_EXEC__A, IQM_CF_COMM_EXEC_STOP, 0); 6432 if (rc != 0) { 6433 pr_err("error %d\n", rc); 6434 goto rw_error; 6435 } 6436 } 6437 6438 memcpy(&cfg_mpeg_output, &common_attr->mpeg_cfg, sizeof(cfg_mpeg_output)); 6439 cfg_mpeg_output.enable_mpeg_output = false; 6440 6441 rc = ctrl_set_cfg_mpeg_output(demod, &cfg_mpeg_output); 6442 if (rc != 0) { 6443 pr_err("error %d\n", rc); 6444 goto rw_error; 6445 } 6446 6447 return 0; 6448 rw_error: 6449 return rc; 6450 } 6451 6452 /*============================================================================*/ 6453 6454 /* 6455 * \fn int set_qam_measurement () 6456 * \brief Setup of the QAM Measuremnt intervals for signal quality 6457 * \param demod instance of demod. 6458 * \param constellation current constellation. 6459 * \return int. 6460 * 6461 * NOTE: 6462 * Take into account that for certain settings the errorcounters can overflow. 6463 * The implementation does not check this. 6464 * 6465 * TODO: overriding the ext_attr->fec_bits_desired by constellation dependent 6466 * constants to get a measurement period of approx. 1 sec. Remove fec_bits_desired 6467 * field ? 6468 * 6469 */ 6470 #ifndef DRXJ_VSB_ONLY 6471 static int 6472 set_qam_measurement(struct drx_demod_instance *demod, 6473 enum drx_modulation constellation, u32 symbol_rate) 6474 { 6475 struct i2c_device_addr *dev_addr = NULL; /* device address for I2C writes */ 6476 struct drxj_data *ext_attr = NULL; /* Global data container for DRXJ specific data */ 6477 int rc; 6478 u32 fec_bits_desired = 0; /* BER accounting period */ 6479 u16 fec_rs_plen = 0; /* defines RS BER measurement period */ 6480 u16 fec_rs_prescale = 0; /* ReedSolomon Measurement Prescale */ 6481 u32 fec_rs_period = 0; /* Value for corresponding I2C register */ 6482 u32 fec_rs_bit_cnt = 0; /* Actual precise amount of bits */ 6483 u32 fec_oc_snc_fail_period = 0; /* Value for corresponding I2C register */ 6484 u32 qam_vd_period = 0; /* Value for corresponding I2C register */ 6485 u32 qam_vd_bit_cnt = 0; /* Actual precise amount of bits */ 6486 u16 fec_vd_plen = 0; /* no of trellis symbols: VD SER measur period */ 6487 u16 qam_vd_prescale = 0; /* Viterbi Measurement Prescale */ 6488 6489 dev_addr = demod->my_i2c_dev_addr; 6490 ext_attr = (struct drxj_data *) demod->my_ext_attr; 6491 6492 fec_bits_desired = ext_attr->fec_bits_desired; 6493 fec_rs_prescale = ext_attr->fec_rs_prescale; 6494 6495 switch (constellation) { 6496 case DRX_CONSTELLATION_QAM16: 6497 fec_bits_desired = 4 * symbol_rate; 6498 break; 6499 case DRX_CONSTELLATION_QAM32: 6500 fec_bits_desired = 5 * symbol_rate; 6501 break; 6502 case DRX_CONSTELLATION_QAM64: 6503 fec_bits_desired = 6 * symbol_rate; 6504 break; 6505 case DRX_CONSTELLATION_QAM128: 6506 fec_bits_desired = 7 * symbol_rate; 6507 break; 6508 case DRX_CONSTELLATION_QAM256: 6509 fec_bits_desired = 8 * symbol_rate; 6510 break; 6511 default: 6512 return -EINVAL; 6513 } 6514 6515 /* Parameters for Reed-Solomon Decoder */ 6516 /* fecrs_period = (int)ceil(FEC_BITS_DESIRED/(fecrs_prescale*plen)) */ 6517 /* rs_bit_cnt = fecrs_period*fecrs_prescale*plen */ 6518 /* result is within 32 bit arithmetic -> */ 6519 /* no need for mult or frac functions */ 6520 6521 /* TODO: use constant instead of calculation and remove the fec_rs_plen in ext_attr */ 6522 switch (ext_attr->standard) { 6523 case DRX_STANDARD_ITU_A: 6524 case DRX_STANDARD_ITU_C: 6525 fec_rs_plen = 204 * 8; 6526 break; 6527 case DRX_STANDARD_ITU_B: 6528 fec_rs_plen = 128 * 7; 6529 break; 6530 default: 6531 return -EINVAL; 6532 } 6533 6534 ext_attr->fec_rs_plen = fec_rs_plen; /* for getSigQual */ 6535 fec_rs_bit_cnt = fec_rs_prescale * fec_rs_plen; /* temp storage */ 6536 if (fec_rs_bit_cnt == 0) { 6537 pr_err("error: fec_rs_bit_cnt is zero!\n"); 6538 return -EIO; 6539 } 6540 fec_rs_period = fec_bits_desired / fec_rs_bit_cnt + 1; /* ceil */ 6541 if (ext_attr->standard != DRX_STANDARD_ITU_B) 6542 fec_oc_snc_fail_period = fec_rs_period; 6543 6544 /* limit to max 16 bit value (I2C register width) if needed */ 6545 if (fec_rs_period > 0xFFFF) 6546 fec_rs_period = 0xFFFF; 6547 6548 /* write corresponding registers */ 6549 switch (ext_attr->standard) { 6550 case DRX_STANDARD_ITU_A: 6551 case DRX_STANDARD_ITU_C: 6552 break; 6553 case DRX_STANDARD_ITU_B: 6554 switch (constellation) { 6555 case DRX_CONSTELLATION_QAM64: 6556 fec_rs_period = 31581; 6557 fec_oc_snc_fail_period = 17932; 6558 break; 6559 case DRX_CONSTELLATION_QAM256: 6560 fec_rs_period = 45446; 6561 fec_oc_snc_fail_period = 25805; 6562 break; 6563 default: 6564 return -EINVAL; 6565 } 6566 break; 6567 default: 6568 return -EINVAL; 6569 } 6570 6571 rc = drxj_dap_write_reg16(dev_addr, FEC_OC_SNC_FAIL_PERIOD__A, (u16)fec_oc_snc_fail_period, 0); 6572 if (rc != 0) { 6573 pr_err("error %d\n", rc); 6574 goto rw_error; 6575 } 6576 rc = drxj_dap_write_reg16(dev_addr, FEC_RS_MEASUREMENT_PERIOD__A, (u16)fec_rs_period, 0); 6577 if (rc != 0) { 6578 pr_err("error %d\n", rc); 6579 goto rw_error; 6580 } 6581 rc = drxj_dap_write_reg16(dev_addr, FEC_RS_MEASUREMENT_PRESCALE__A, fec_rs_prescale, 0); 6582 if (rc != 0) { 6583 pr_err("error %d\n", rc); 6584 goto rw_error; 6585 } 6586 ext_attr->fec_rs_period = (u16) fec_rs_period; 6587 ext_attr->fec_rs_prescale = fec_rs_prescale; 6588 rc = drxdap_fasi_write_reg32(dev_addr, SCU_RAM_FEC_ACCUM_CW_CORRECTED_LO__A, 0, 0); 6589 if (rc != 0) { 6590 pr_err("error %d\n", rc); 6591 goto rw_error; 6592 } 6593 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_FEC_MEAS_COUNT__A, 0, 0); 6594 if (rc != 0) { 6595 pr_err("error %d\n", rc); 6596 goto rw_error; 6597 } 6598 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_FEC_ACCUM_PKT_FAILURES__A, 0, 0); 6599 if (rc != 0) { 6600 pr_err("error %d\n", rc); 6601 goto rw_error; 6602 } 6603 6604 if (ext_attr->standard == DRX_STANDARD_ITU_B) { 6605 /* Parameters for Viterbi Decoder */ 6606 /* qamvd_period = (int)ceil(FEC_BITS_DESIRED/ */ 6607 /* (qamvd_prescale*plen*(qam_constellation+1))) */ 6608 /* vd_bit_cnt = qamvd_period*qamvd_prescale*plen */ 6609 /* result is within 32 bit arithmetic -> */ 6610 /* no need for mult or frac functions */ 6611 6612 /* a(8 bit) * b(8 bit) = 16 bit result => mult32 not needed */ 6613 fec_vd_plen = ext_attr->fec_vd_plen; 6614 qam_vd_prescale = ext_attr->qam_vd_prescale; 6615 qam_vd_bit_cnt = qam_vd_prescale * fec_vd_plen; /* temp storage */ 6616 6617 switch (constellation) { 6618 case DRX_CONSTELLATION_QAM64: 6619 /* a(16 bit) * b(4 bit) = 20 bit result => mult32 not needed */ 6620 qam_vd_period = 6621 qam_vd_bit_cnt * (QAM_TOP_CONSTELLATION_QAM64 + 1) 6622 * (QAM_TOP_CONSTELLATION_QAM64 + 1); 6623 break; 6624 case DRX_CONSTELLATION_QAM256: 6625 /* a(16 bit) * b(5 bit) = 21 bit result => mult32 not needed */ 6626 qam_vd_period = 6627 qam_vd_bit_cnt * (QAM_TOP_CONSTELLATION_QAM256 + 1) 6628 * (QAM_TOP_CONSTELLATION_QAM256 + 1); 6629 break; 6630 default: 6631 return -EINVAL; 6632 } 6633 if (qam_vd_period == 0) { 6634 pr_err("error: qam_vd_period is zero!\n"); 6635 return -EIO; 6636 } 6637 qam_vd_period = fec_bits_desired / qam_vd_period; 6638 /* limit to max 16 bit value (I2C register width) if needed */ 6639 if (qam_vd_period > 0xFFFF) 6640 qam_vd_period = 0xFFFF; 6641 6642 /* a(16 bit) * b(16 bit) = 32 bit result => mult32 not needed */ 6643 qam_vd_bit_cnt *= qam_vd_period; 6644 6645 rc = drxj_dap_write_reg16(dev_addr, QAM_VD_MEASUREMENT_PERIOD__A, (u16)qam_vd_period, 0); 6646 if (rc != 0) { 6647 pr_err("error %d\n", rc); 6648 goto rw_error; 6649 } 6650 rc = drxj_dap_write_reg16(dev_addr, QAM_VD_MEASUREMENT_PRESCALE__A, qam_vd_prescale, 0); 6651 if (rc != 0) { 6652 pr_err("error %d\n", rc); 6653 goto rw_error; 6654 } 6655 ext_attr->qam_vd_period = (u16) qam_vd_period; 6656 ext_attr->qam_vd_prescale = qam_vd_prescale; 6657 } 6658 6659 return 0; 6660 rw_error: 6661 return rc; 6662 } 6663 6664 /*============================================================================*/ 6665 6666 /* 6667 * \fn int set_qam16 () 6668 * \brief QAM16 specific setup 6669 * \param demod instance of demod. 6670 * \return int. 6671 */ 6672 static int set_qam16(struct drx_demod_instance *demod) 6673 { 6674 struct i2c_device_addr *dev_addr = demod->my_i2c_dev_addr; 6675 int rc; 6676 static const u8 qam_dq_qual_fun[] = { 6677 DRXJ_16TO8(2), /* fun0 */ 6678 DRXJ_16TO8(2), /* fun1 */ 6679 DRXJ_16TO8(2), /* fun2 */ 6680 DRXJ_16TO8(2), /* fun3 */ 6681 DRXJ_16TO8(3), /* fun4 */ 6682 DRXJ_16TO8(3), /* fun5 */ 6683 }; 6684 static const u8 qam_eq_cma_rad[] = { 6685 DRXJ_16TO8(13517), /* RAD0 */ 6686 DRXJ_16TO8(13517), /* RAD1 */ 6687 DRXJ_16TO8(13517), /* RAD2 */ 6688 DRXJ_16TO8(13517), /* RAD3 */ 6689 DRXJ_16TO8(13517), /* RAD4 */ 6690 DRXJ_16TO8(13517), /* RAD5 */ 6691 }; 6692 6693 rc = drxdap_fasi_write_block(dev_addr, QAM_DQ_QUAL_FUN0__A, sizeof(qam_dq_qual_fun), ((u8 *)qam_dq_qual_fun), 0); 6694 if (rc != 0) { 6695 pr_err("error %d\n", rc); 6696 goto rw_error; 6697 } 6698 rc = drxdap_fasi_write_block(dev_addr, SCU_RAM_QAM_EQ_CMA_RAD0__A, sizeof(qam_eq_cma_rad), ((u8 *)qam_eq_cma_rad), 0); 6699 if (rc != 0) { 6700 pr_err("error %d\n", rc); 6701 goto rw_error; 6702 } 6703 6704 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_RTH__A, 140, 0); 6705 if (rc != 0) { 6706 pr_err("error %d\n", rc); 6707 goto rw_error; 6708 } 6709 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_FTH__A, 50, 0); 6710 if (rc != 0) { 6711 pr_err("error %d\n", rc); 6712 goto rw_error; 6713 } 6714 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_PTH__A, 120, 0); 6715 if (rc != 0) { 6716 pr_err("error %d\n", rc); 6717 goto rw_error; 6718 } 6719 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_QTH__A, 230, 0); 6720 if (rc != 0) { 6721 pr_err("error %d\n", rc); 6722 goto rw_error; 6723 } 6724 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_CTH__A, 95, 0); 6725 if (rc != 0) { 6726 pr_err("error %d\n", rc); 6727 goto rw_error; 6728 } 6729 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_MTH__A, 105, 0); 6730 if (rc != 0) { 6731 pr_err("error %d\n", rc); 6732 goto rw_error; 6733 } 6734 6735 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_RATE_LIM__A, 40, 0); 6736 if (rc != 0) { 6737 pr_err("error %d\n", rc); 6738 goto rw_error; 6739 } 6740 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_FREQ_LIM__A, 56, 0); 6741 if (rc != 0) { 6742 pr_err("error %d\n", rc); 6743 goto rw_error; 6744 } 6745 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_COUNT_LIM__A, 3, 0); 6746 if (rc != 0) { 6747 pr_err("error %d\n", rc); 6748 goto rw_error; 6749 } 6750 6751 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__A, 16, 0); 6752 if (rc != 0) { 6753 pr_err("error %d\n", rc); 6754 goto rw_error; 6755 } 6756 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__A, 220, 0); 6757 if (rc != 0) { 6758 pr_err("error %d\n", rc); 6759 goto rw_error; 6760 } 6761 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET1__A, 25, 0); 6762 if (rc != 0) { 6763 pr_err("error %d\n", rc); 6764 goto rw_error; 6765 } 6766 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET2__A, 6, 0); 6767 if (rc != 0) { 6768 pr_err("error %d\n", rc); 6769 goto rw_error; 6770 } 6771 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET3__A, (u16)(-24), 0); 6772 if (rc != 0) { 6773 pr_err("error %d\n", rc); 6774 goto rw_error; 6775 } 6776 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET4__A, (u16)(-65), 0); 6777 if (rc != 0) { 6778 pr_err("error %d\n", rc); 6779 goto rw_error; 6780 } 6781 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A, (u16)(-127), 0); 6782 if (rc != 0) { 6783 pr_err("error %d\n", rc); 6784 goto rw_error; 6785 } 6786 6787 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CA_FINE__A, 15, 0); 6788 if (rc != 0) { 6789 pr_err("error %d\n", rc); 6790 goto rw_error; 6791 } 6792 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CA_COARSE__A, 40, 0); 6793 if (rc != 0) { 6794 pr_err("error %d\n", rc); 6795 goto rw_error; 6796 } 6797 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CP_FINE__A, 2, 0); 6798 if (rc != 0) { 6799 pr_err("error %d\n", rc); 6800 goto rw_error; 6801 } 6802 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CP_MEDIUM__A, 20, 0); 6803 if (rc != 0) { 6804 pr_err("error %d\n", rc); 6805 goto rw_error; 6806 } 6807 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CP_COARSE__A, 255, 0); 6808 if (rc != 0) { 6809 pr_err("error %d\n", rc); 6810 goto rw_error; 6811 } 6812 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CI_FINE__A, 2, 0); 6813 if (rc != 0) { 6814 pr_err("error %d\n", rc); 6815 goto rw_error; 6816 } 6817 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CI_MEDIUM__A, 10, 0); 6818 if (rc != 0) { 6819 pr_err("error %d\n", rc); 6820 goto rw_error; 6821 } 6822 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CI_COARSE__A, 50, 0); 6823 if (rc != 0) { 6824 pr_err("error %d\n", rc); 6825 goto rw_error; 6826 } 6827 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EP_FINE__A, 12, 0); 6828 if (rc != 0) { 6829 pr_err("error %d\n", rc); 6830 goto rw_error; 6831 } 6832 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EP_MEDIUM__A, 24, 0); 6833 if (rc != 0) { 6834 pr_err("error %d\n", rc); 6835 goto rw_error; 6836 } 6837 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EP_COARSE__A, 24, 0); 6838 if (rc != 0) { 6839 pr_err("error %d\n", rc); 6840 goto rw_error; 6841 } 6842 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EI_FINE__A, 12, 0); 6843 if (rc != 0) { 6844 pr_err("error %d\n", rc); 6845 goto rw_error; 6846 } 6847 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EI_MEDIUM__A, 16, 0); 6848 if (rc != 0) { 6849 pr_err("error %d\n", rc); 6850 goto rw_error; 6851 } 6852 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EI_COARSE__A, 16, 0); 6853 if (rc != 0) { 6854 pr_err("error %d\n", rc); 6855 goto rw_error; 6856 } 6857 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF_FINE__A, 16, 0); 6858 if (rc != 0) { 6859 pr_err("error %d\n", rc); 6860 goto rw_error; 6861 } 6862 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF_MEDIUM__A, 32, 0); 6863 if (rc != 0) { 6864 pr_err("error %d\n", rc); 6865 goto rw_error; 6866 } 6867 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF_COARSE__A, 240, 0); 6868 if (rc != 0) { 6869 pr_err("error %d\n", rc); 6870 goto rw_error; 6871 } 6872 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF1_FINE__A, 5, 0); 6873 if (rc != 0) { 6874 pr_err("error %d\n", rc); 6875 goto rw_error; 6876 } 6877 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF1_MEDIUM__A, 15, 0); 6878 if (rc != 0) { 6879 pr_err("error %d\n", rc); 6880 goto rw_error; 6881 } 6882 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF1_COARSE__A, 32, 0); 6883 if (rc != 0) { 6884 pr_err("error %d\n", rc); 6885 goto rw_error; 6886 } 6887 6888 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_SL_SIG_POWER__A, 40960, 0); 6889 if (rc != 0) { 6890 pr_err("error %d\n", rc); 6891 goto rw_error; 6892 } 6893 6894 return 0; 6895 rw_error: 6896 return rc; 6897 } 6898 6899 /*============================================================================*/ 6900 6901 /* 6902 * \fn int set_qam32 () 6903 * \brief QAM32 specific setup 6904 * \param demod instance of demod. 6905 * \return int. 6906 */ 6907 static int set_qam32(struct drx_demod_instance *demod) 6908 { 6909 struct i2c_device_addr *dev_addr = demod->my_i2c_dev_addr; 6910 int rc; 6911 static const u8 qam_dq_qual_fun[] = { 6912 DRXJ_16TO8(3), /* fun0 */ 6913 DRXJ_16TO8(3), /* fun1 */ 6914 DRXJ_16TO8(3), /* fun2 */ 6915 DRXJ_16TO8(3), /* fun3 */ 6916 DRXJ_16TO8(4), /* fun4 */ 6917 DRXJ_16TO8(4), /* fun5 */ 6918 }; 6919 static const u8 qam_eq_cma_rad[] = { 6920 DRXJ_16TO8(6707), /* RAD0 */ 6921 DRXJ_16TO8(6707), /* RAD1 */ 6922 DRXJ_16TO8(6707), /* RAD2 */ 6923 DRXJ_16TO8(6707), /* RAD3 */ 6924 DRXJ_16TO8(6707), /* RAD4 */ 6925 DRXJ_16TO8(6707), /* RAD5 */ 6926 }; 6927 6928 rc = drxdap_fasi_write_block(dev_addr, QAM_DQ_QUAL_FUN0__A, sizeof(qam_dq_qual_fun), ((u8 *)qam_dq_qual_fun), 0); 6929 if (rc != 0) { 6930 pr_err("error %d\n", rc); 6931 goto rw_error; 6932 } 6933 rc = drxdap_fasi_write_block(dev_addr, SCU_RAM_QAM_EQ_CMA_RAD0__A, sizeof(qam_eq_cma_rad), ((u8 *)qam_eq_cma_rad), 0); 6934 if (rc != 0) { 6935 pr_err("error %d\n", rc); 6936 goto rw_error; 6937 } 6938 6939 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_RTH__A, 90, 0); 6940 if (rc != 0) { 6941 pr_err("error %d\n", rc); 6942 goto rw_error; 6943 } 6944 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_FTH__A, 50, 0); 6945 if (rc != 0) { 6946 pr_err("error %d\n", rc); 6947 goto rw_error; 6948 } 6949 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_PTH__A, 100, 0); 6950 if (rc != 0) { 6951 pr_err("error %d\n", rc); 6952 goto rw_error; 6953 } 6954 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_QTH__A, 170, 0); 6955 if (rc != 0) { 6956 pr_err("error %d\n", rc); 6957 goto rw_error; 6958 } 6959 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_CTH__A, 80, 0); 6960 if (rc != 0) { 6961 pr_err("error %d\n", rc); 6962 goto rw_error; 6963 } 6964 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_MTH__A, 100, 0); 6965 if (rc != 0) { 6966 pr_err("error %d\n", rc); 6967 goto rw_error; 6968 } 6969 6970 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_RATE_LIM__A, 40, 0); 6971 if (rc != 0) { 6972 pr_err("error %d\n", rc); 6973 goto rw_error; 6974 } 6975 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_FREQ_LIM__A, 56, 0); 6976 if (rc != 0) { 6977 pr_err("error %d\n", rc); 6978 goto rw_error; 6979 } 6980 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_COUNT_LIM__A, 3, 0); 6981 if (rc != 0) { 6982 pr_err("error %d\n", rc); 6983 goto rw_error; 6984 } 6985 6986 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__A, 12, 0); 6987 if (rc != 0) { 6988 pr_err("error %d\n", rc); 6989 goto rw_error; 6990 } 6991 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__A, 140, 0); 6992 if (rc != 0) { 6993 pr_err("error %d\n", rc); 6994 goto rw_error; 6995 } 6996 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET1__A, (u16)(-8), 0); 6997 if (rc != 0) { 6998 pr_err("error %d\n", rc); 6999 goto rw_error; 7000 } 7001 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET2__A, (u16)(-16), 0); 7002 if (rc != 0) { 7003 pr_err("error %d\n", rc); 7004 goto rw_error; 7005 } 7006 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET3__A, (u16)(-26), 0); 7007 if (rc != 0) { 7008 pr_err("error %d\n", rc); 7009 goto rw_error; 7010 } 7011 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET4__A, (u16)(-56), 0); 7012 if (rc != 0) { 7013 pr_err("error %d\n", rc); 7014 goto rw_error; 7015 } 7016 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A, (u16)(-86), 0); 7017 if (rc != 0) { 7018 pr_err("error %d\n", rc); 7019 goto rw_error; 7020 } 7021 7022 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CA_FINE__A, 15, 0); 7023 if (rc != 0) { 7024 pr_err("error %d\n", rc); 7025 goto rw_error; 7026 } 7027 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CA_COARSE__A, 40, 0); 7028 if (rc != 0) { 7029 pr_err("error %d\n", rc); 7030 goto rw_error; 7031 } 7032 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CP_FINE__A, 2, 0); 7033 if (rc != 0) { 7034 pr_err("error %d\n", rc); 7035 goto rw_error; 7036 } 7037 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CP_MEDIUM__A, 20, 0); 7038 if (rc != 0) { 7039 pr_err("error %d\n", rc); 7040 goto rw_error; 7041 } 7042 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CP_COARSE__A, 255, 0); 7043 if (rc != 0) { 7044 pr_err("error %d\n", rc); 7045 goto rw_error; 7046 } 7047 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CI_FINE__A, 2, 0); 7048 if (rc != 0) { 7049 pr_err("error %d\n", rc); 7050 goto rw_error; 7051 } 7052 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CI_MEDIUM__A, 10, 0); 7053 if (rc != 0) { 7054 pr_err("error %d\n", rc); 7055 goto rw_error; 7056 } 7057 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CI_COARSE__A, 50, 0); 7058 if (rc != 0) { 7059 pr_err("error %d\n", rc); 7060 goto rw_error; 7061 } 7062 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EP_FINE__A, 12, 0); 7063 if (rc != 0) { 7064 pr_err("error %d\n", rc); 7065 goto rw_error; 7066 } 7067 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EP_MEDIUM__A, 24, 0); 7068 if (rc != 0) { 7069 pr_err("error %d\n", rc); 7070 goto rw_error; 7071 } 7072 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EP_COARSE__A, 24, 0); 7073 if (rc != 0) { 7074 pr_err("error %d\n", rc); 7075 goto rw_error; 7076 } 7077 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EI_FINE__A, 12, 0); 7078 if (rc != 0) { 7079 pr_err("error %d\n", rc); 7080 goto rw_error; 7081 } 7082 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EI_MEDIUM__A, 16, 0); 7083 if (rc != 0) { 7084 pr_err("error %d\n", rc); 7085 goto rw_error; 7086 } 7087 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EI_COARSE__A, 16, 0); 7088 if (rc != 0) { 7089 pr_err("error %d\n", rc); 7090 goto rw_error; 7091 } 7092 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF_FINE__A, 16, 0); 7093 if (rc != 0) { 7094 pr_err("error %d\n", rc); 7095 goto rw_error; 7096 } 7097 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF_MEDIUM__A, 32, 0); 7098 if (rc != 0) { 7099 pr_err("error %d\n", rc); 7100 goto rw_error; 7101 } 7102 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF_COARSE__A, 176, 0); 7103 if (rc != 0) { 7104 pr_err("error %d\n", rc); 7105 goto rw_error; 7106 } 7107 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF1_FINE__A, 5, 0); 7108 if (rc != 0) { 7109 pr_err("error %d\n", rc); 7110 goto rw_error; 7111 } 7112 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF1_MEDIUM__A, 15, 0); 7113 if (rc != 0) { 7114 pr_err("error %d\n", rc); 7115 goto rw_error; 7116 } 7117 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF1_COARSE__A, 8, 0); 7118 if (rc != 0) { 7119 pr_err("error %d\n", rc); 7120 goto rw_error; 7121 } 7122 7123 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_SL_SIG_POWER__A, 20480, 0); 7124 if (rc != 0) { 7125 pr_err("error %d\n", rc); 7126 goto rw_error; 7127 } 7128 7129 return 0; 7130 rw_error: 7131 return rc; 7132 } 7133 7134 /*============================================================================*/ 7135 7136 /* 7137 * \fn int set_qam64 () 7138 * \brief QAM64 specific setup 7139 * \param demod instance of demod. 7140 * \return int. 7141 */ 7142 static int set_qam64(struct drx_demod_instance *demod) 7143 { 7144 struct i2c_device_addr *dev_addr = demod->my_i2c_dev_addr; 7145 int rc; 7146 static const u8 qam_dq_qual_fun[] = { 7147 /* this is hw reset value. no necessary to re-write */ 7148 DRXJ_16TO8(4), /* fun0 */ 7149 DRXJ_16TO8(4), /* fun1 */ 7150 DRXJ_16TO8(4), /* fun2 */ 7151 DRXJ_16TO8(4), /* fun3 */ 7152 DRXJ_16TO8(6), /* fun4 */ 7153 DRXJ_16TO8(6), /* fun5 */ 7154 }; 7155 static const u8 qam_eq_cma_rad[] = { 7156 DRXJ_16TO8(13336), /* RAD0 */ 7157 DRXJ_16TO8(12618), /* RAD1 */ 7158 DRXJ_16TO8(11988), /* RAD2 */ 7159 DRXJ_16TO8(13809), /* RAD3 */ 7160 DRXJ_16TO8(13809), /* RAD4 */ 7161 DRXJ_16TO8(15609), /* RAD5 */ 7162 }; 7163 7164 rc = drxdap_fasi_write_block(dev_addr, QAM_DQ_QUAL_FUN0__A, sizeof(qam_dq_qual_fun), ((u8 *)qam_dq_qual_fun), 0); 7165 if (rc != 0) { 7166 pr_err("error %d\n", rc); 7167 goto rw_error; 7168 } 7169 rc = drxdap_fasi_write_block(dev_addr, SCU_RAM_QAM_EQ_CMA_RAD0__A, sizeof(qam_eq_cma_rad), ((u8 *)qam_eq_cma_rad), 0); 7170 if (rc != 0) { 7171 pr_err("error %d\n", rc); 7172 goto rw_error; 7173 } 7174 7175 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_RTH__A, 105, 0); 7176 if (rc != 0) { 7177 pr_err("error %d\n", rc); 7178 goto rw_error; 7179 } 7180 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_FTH__A, 60, 0); 7181 if (rc != 0) { 7182 pr_err("error %d\n", rc); 7183 goto rw_error; 7184 } 7185 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_PTH__A, 100, 0); 7186 if (rc != 0) { 7187 pr_err("error %d\n", rc); 7188 goto rw_error; 7189 } 7190 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_QTH__A, 195, 0); 7191 if (rc != 0) { 7192 pr_err("error %d\n", rc); 7193 goto rw_error; 7194 } 7195 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_CTH__A, 80, 0); 7196 if (rc != 0) { 7197 pr_err("error %d\n", rc); 7198 goto rw_error; 7199 } 7200 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_MTH__A, 84, 0); 7201 if (rc != 0) { 7202 pr_err("error %d\n", rc); 7203 goto rw_error; 7204 } 7205 7206 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_RATE_LIM__A, 40, 0); 7207 if (rc != 0) { 7208 pr_err("error %d\n", rc); 7209 goto rw_error; 7210 } 7211 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_FREQ_LIM__A, 32, 0); 7212 if (rc != 0) { 7213 pr_err("error %d\n", rc); 7214 goto rw_error; 7215 } 7216 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_COUNT_LIM__A, 3, 0); 7217 if (rc != 0) { 7218 pr_err("error %d\n", rc); 7219 goto rw_error; 7220 } 7221 7222 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__A, 12, 0); 7223 if (rc != 0) { 7224 pr_err("error %d\n", rc); 7225 goto rw_error; 7226 } 7227 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__A, 141, 0); 7228 if (rc != 0) { 7229 pr_err("error %d\n", rc); 7230 goto rw_error; 7231 } 7232 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET1__A, 7, 0); 7233 if (rc != 0) { 7234 pr_err("error %d\n", rc); 7235 goto rw_error; 7236 } 7237 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET2__A, 0, 0); 7238 if (rc != 0) { 7239 pr_err("error %d\n", rc); 7240 goto rw_error; 7241 } 7242 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET3__A, (u16)(-15), 0); 7243 if (rc != 0) { 7244 pr_err("error %d\n", rc); 7245 goto rw_error; 7246 } 7247 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET4__A, (u16)(-45), 0); 7248 if (rc != 0) { 7249 pr_err("error %d\n", rc); 7250 goto rw_error; 7251 } 7252 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A, (u16)(-80), 0); 7253 if (rc != 0) { 7254 pr_err("error %d\n", rc); 7255 goto rw_error; 7256 } 7257 7258 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CA_FINE__A, 15, 0); 7259 if (rc != 0) { 7260 pr_err("error %d\n", rc); 7261 goto rw_error; 7262 } 7263 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CA_COARSE__A, 40, 0); 7264 if (rc != 0) { 7265 pr_err("error %d\n", rc); 7266 goto rw_error; 7267 } 7268 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CP_FINE__A, 2, 0); 7269 if (rc != 0) { 7270 pr_err("error %d\n", rc); 7271 goto rw_error; 7272 } 7273 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CP_MEDIUM__A, 30, 0); 7274 if (rc != 0) { 7275 pr_err("error %d\n", rc); 7276 goto rw_error; 7277 } 7278 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CP_COARSE__A, 255, 0); 7279 if (rc != 0) { 7280 pr_err("error %d\n", rc); 7281 goto rw_error; 7282 } 7283 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CI_FINE__A, 2, 0); 7284 if (rc != 0) { 7285 pr_err("error %d\n", rc); 7286 goto rw_error; 7287 } 7288 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CI_MEDIUM__A, 15, 0); 7289 if (rc != 0) { 7290 pr_err("error %d\n", rc); 7291 goto rw_error; 7292 } 7293 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CI_COARSE__A, 80, 0); 7294 if (rc != 0) { 7295 pr_err("error %d\n", rc); 7296 goto rw_error; 7297 } 7298 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EP_FINE__A, 12, 0); 7299 if (rc != 0) { 7300 pr_err("error %d\n", rc); 7301 goto rw_error; 7302 } 7303 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EP_MEDIUM__A, 24, 0); 7304 if (rc != 0) { 7305 pr_err("error %d\n", rc); 7306 goto rw_error; 7307 } 7308 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EP_COARSE__A, 24, 0); 7309 if (rc != 0) { 7310 pr_err("error %d\n", rc); 7311 goto rw_error; 7312 } 7313 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EI_FINE__A, 12, 0); 7314 if (rc != 0) { 7315 pr_err("error %d\n", rc); 7316 goto rw_error; 7317 } 7318 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EI_MEDIUM__A, 16, 0); 7319 if (rc != 0) { 7320 pr_err("error %d\n", rc); 7321 goto rw_error; 7322 } 7323 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EI_COARSE__A, 16, 0); 7324 if (rc != 0) { 7325 pr_err("error %d\n", rc); 7326 goto rw_error; 7327 } 7328 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF_FINE__A, 16, 0); 7329 if (rc != 0) { 7330 pr_err("error %d\n", rc); 7331 goto rw_error; 7332 } 7333 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF_MEDIUM__A, 48, 0); 7334 if (rc != 0) { 7335 pr_err("error %d\n", rc); 7336 goto rw_error; 7337 } 7338 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF_COARSE__A, 160, 0); 7339 if (rc != 0) { 7340 pr_err("error %d\n", rc); 7341 goto rw_error; 7342 } 7343 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF1_FINE__A, 5, 0); 7344 if (rc != 0) { 7345 pr_err("error %d\n", rc); 7346 goto rw_error; 7347 } 7348 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF1_MEDIUM__A, 15, 0); 7349 if (rc != 0) { 7350 pr_err("error %d\n", rc); 7351 goto rw_error; 7352 } 7353 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF1_COARSE__A, 32, 0); 7354 if (rc != 0) { 7355 pr_err("error %d\n", rc); 7356 goto rw_error; 7357 } 7358 7359 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_SL_SIG_POWER__A, 43008, 0); 7360 if (rc != 0) { 7361 pr_err("error %d\n", rc); 7362 goto rw_error; 7363 } 7364 7365 return 0; 7366 rw_error: 7367 return rc; 7368 } 7369 7370 /*============================================================================*/ 7371 7372 /* 7373 * \fn int set_qam128 () 7374 * \brief QAM128 specific setup 7375 * \param demod: instance of demod. 7376 * \return int. 7377 */ 7378 static int set_qam128(struct drx_demod_instance *demod) 7379 { 7380 struct i2c_device_addr *dev_addr = demod->my_i2c_dev_addr; 7381 int rc; 7382 static const u8 qam_dq_qual_fun[] = { 7383 DRXJ_16TO8(6), /* fun0 */ 7384 DRXJ_16TO8(6), /* fun1 */ 7385 DRXJ_16TO8(6), /* fun2 */ 7386 DRXJ_16TO8(6), /* fun3 */ 7387 DRXJ_16TO8(9), /* fun4 */ 7388 DRXJ_16TO8(9), /* fun5 */ 7389 }; 7390 static const u8 qam_eq_cma_rad[] = { 7391 DRXJ_16TO8(6164), /* RAD0 */ 7392 DRXJ_16TO8(6598), /* RAD1 */ 7393 DRXJ_16TO8(6394), /* RAD2 */ 7394 DRXJ_16TO8(6409), /* RAD3 */ 7395 DRXJ_16TO8(6656), /* RAD4 */ 7396 DRXJ_16TO8(7238), /* RAD5 */ 7397 }; 7398 7399 rc = drxdap_fasi_write_block(dev_addr, QAM_DQ_QUAL_FUN0__A, sizeof(qam_dq_qual_fun), ((u8 *)qam_dq_qual_fun), 0); 7400 if (rc != 0) { 7401 pr_err("error %d\n", rc); 7402 goto rw_error; 7403 } 7404 rc = drxdap_fasi_write_block(dev_addr, SCU_RAM_QAM_EQ_CMA_RAD0__A, sizeof(qam_eq_cma_rad), ((u8 *)qam_eq_cma_rad), 0); 7405 if (rc != 0) { 7406 pr_err("error %d\n", rc); 7407 goto rw_error; 7408 } 7409 7410 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_RTH__A, 50, 0); 7411 if (rc != 0) { 7412 pr_err("error %d\n", rc); 7413 goto rw_error; 7414 } 7415 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_FTH__A, 60, 0); 7416 if (rc != 0) { 7417 pr_err("error %d\n", rc); 7418 goto rw_error; 7419 } 7420 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_PTH__A, 100, 0); 7421 if (rc != 0) { 7422 pr_err("error %d\n", rc); 7423 goto rw_error; 7424 } 7425 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_QTH__A, 140, 0); 7426 if (rc != 0) { 7427 pr_err("error %d\n", rc); 7428 goto rw_error; 7429 } 7430 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_CTH__A, 80, 0); 7431 if (rc != 0) { 7432 pr_err("error %d\n", rc); 7433 goto rw_error; 7434 } 7435 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_MTH__A, 100, 0); 7436 if (rc != 0) { 7437 pr_err("error %d\n", rc); 7438 goto rw_error; 7439 } 7440 7441 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_RATE_LIM__A, 40, 0); 7442 if (rc != 0) { 7443 pr_err("error %d\n", rc); 7444 goto rw_error; 7445 } 7446 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_FREQ_LIM__A, 32, 0); 7447 if (rc != 0) { 7448 pr_err("error %d\n", rc); 7449 goto rw_error; 7450 } 7451 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_COUNT_LIM__A, 3, 0); 7452 if (rc != 0) { 7453 pr_err("error %d\n", rc); 7454 goto rw_error; 7455 } 7456 7457 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__A, 8, 0); 7458 if (rc != 0) { 7459 pr_err("error %d\n", rc); 7460 goto rw_error; 7461 } 7462 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__A, 65, 0); 7463 if (rc != 0) { 7464 pr_err("error %d\n", rc); 7465 goto rw_error; 7466 } 7467 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET1__A, 5, 0); 7468 if (rc != 0) { 7469 pr_err("error %d\n", rc); 7470 goto rw_error; 7471 } 7472 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET2__A, 3, 0); 7473 if (rc != 0) { 7474 pr_err("error %d\n", rc); 7475 goto rw_error; 7476 } 7477 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET3__A, (u16)(-1), 0); 7478 if (rc != 0) { 7479 pr_err("error %d\n", rc); 7480 goto rw_error; 7481 } 7482 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET4__A, 12, 0); 7483 if (rc != 0) { 7484 pr_err("error %d\n", rc); 7485 goto rw_error; 7486 } 7487 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A, (u16)(-23), 0); 7488 if (rc != 0) { 7489 pr_err("error %d\n", rc); 7490 goto rw_error; 7491 } 7492 7493 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CA_FINE__A, 15, 0); 7494 if (rc != 0) { 7495 pr_err("error %d\n", rc); 7496 goto rw_error; 7497 } 7498 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CA_COARSE__A, 40, 0); 7499 if (rc != 0) { 7500 pr_err("error %d\n", rc); 7501 goto rw_error; 7502 } 7503 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CP_FINE__A, 2, 0); 7504 if (rc != 0) { 7505 pr_err("error %d\n", rc); 7506 goto rw_error; 7507 } 7508 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CP_MEDIUM__A, 40, 0); 7509 if (rc != 0) { 7510 pr_err("error %d\n", rc); 7511 goto rw_error; 7512 } 7513 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CP_COARSE__A, 255, 0); 7514 if (rc != 0) { 7515 pr_err("error %d\n", rc); 7516 goto rw_error; 7517 } 7518 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CI_FINE__A, 2, 0); 7519 if (rc != 0) { 7520 pr_err("error %d\n", rc); 7521 goto rw_error; 7522 } 7523 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CI_MEDIUM__A, 20, 0); 7524 if (rc != 0) { 7525 pr_err("error %d\n", rc); 7526 goto rw_error; 7527 } 7528 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CI_COARSE__A, 80, 0); 7529 if (rc != 0) { 7530 pr_err("error %d\n", rc); 7531 goto rw_error; 7532 } 7533 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EP_FINE__A, 12, 0); 7534 if (rc != 0) { 7535 pr_err("error %d\n", rc); 7536 goto rw_error; 7537 } 7538 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EP_MEDIUM__A, 24, 0); 7539 if (rc != 0) { 7540 pr_err("error %d\n", rc); 7541 goto rw_error; 7542 } 7543 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EP_COARSE__A, 24, 0); 7544 if (rc != 0) { 7545 pr_err("error %d\n", rc); 7546 goto rw_error; 7547 } 7548 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EI_FINE__A, 12, 0); 7549 if (rc != 0) { 7550 pr_err("error %d\n", rc); 7551 goto rw_error; 7552 } 7553 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EI_MEDIUM__A, 16, 0); 7554 if (rc != 0) { 7555 pr_err("error %d\n", rc); 7556 goto rw_error; 7557 } 7558 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EI_COARSE__A, 16, 0); 7559 if (rc != 0) { 7560 pr_err("error %d\n", rc); 7561 goto rw_error; 7562 } 7563 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF_FINE__A, 16, 0); 7564 if (rc != 0) { 7565 pr_err("error %d\n", rc); 7566 goto rw_error; 7567 } 7568 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF_MEDIUM__A, 32, 0); 7569 if (rc != 0) { 7570 pr_err("error %d\n", rc); 7571 goto rw_error; 7572 } 7573 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF_COARSE__A, 144, 0); 7574 if (rc != 0) { 7575 pr_err("error %d\n", rc); 7576 goto rw_error; 7577 } 7578 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF1_FINE__A, 5, 0); 7579 if (rc != 0) { 7580 pr_err("error %d\n", rc); 7581 goto rw_error; 7582 } 7583 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF1_MEDIUM__A, 15, 0); 7584 if (rc != 0) { 7585 pr_err("error %d\n", rc); 7586 goto rw_error; 7587 } 7588 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF1_COARSE__A, 16, 0); 7589 if (rc != 0) { 7590 pr_err("error %d\n", rc); 7591 goto rw_error; 7592 } 7593 7594 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_SL_SIG_POWER__A, 20992, 0); 7595 if (rc != 0) { 7596 pr_err("error %d\n", rc); 7597 goto rw_error; 7598 } 7599 7600 return 0; 7601 rw_error: 7602 return rc; 7603 } 7604 7605 /*============================================================================*/ 7606 7607 /* 7608 * \fn int set_qam256 () 7609 * \brief QAM256 specific setup 7610 * \param demod: instance of demod. 7611 * \return int. 7612 */ 7613 static int set_qam256(struct drx_demod_instance *demod) 7614 { 7615 struct i2c_device_addr *dev_addr = demod->my_i2c_dev_addr; 7616 int rc; 7617 static const u8 qam_dq_qual_fun[] = { 7618 DRXJ_16TO8(8), /* fun0 */ 7619 DRXJ_16TO8(8), /* fun1 */ 7620 DRXJ_16TO8(8), /* fun2 */ 7621 DRXJ_16TO8(8), /* fun3 */ 7622 DRXJ_16TO8(12), /* fun4 */ 7623 DRXJ_16TO8(12), /* fun5 */ 7624 }; 7625 static const u8 qam_eq_cma_rad[] = { 7626 DRXJ_16TO8(12345), /* RAD0 */ 7627 DRXJ_16TO8(12345), /* RAD1 */ 7628 DRXJ_16TO8(13626), /* RAD2 */ 7629 DRXJ_16TO8(12931), /* RAD3 */ 7630 DRXJ_16TO8(14719), /* RAD4 */ 7631 DRXJ_16TO8(15356), /* RAD5 */ 7632 }; 7633 7634 rc = drxdap_fasi_write_block(dev_addr, QAM_DQ_QUAL_FUN0__A, sizeof(qam_dq_qual_fun), ((u8 *)qam_dq_qual_fun), 0); 7635 if (rc != 0) { 7636 pr_err("error %d\n", rc); 7637 goto rw_error; 7638 } 7639 rc = drxdap_fasi_write_block(dev_addr, SCU_RAM_QAM_EQ_CMA_RAD0__A, sizeof(qam_eq_cma_rad), ((u8 *)qam_eq_cma_rad), 0); 7640 if (rc != 0) { 7641 pr_err("error %d\n", rc); 7642 goto rw_error; 7643 } 7644 7645 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_RTH__A, 50, 0); 7646 if (rc != 0) { 7647 pr_err("error %d\n", rc); 7648 goto rw_error; 7649 } 7650 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_FTH__A, 60, 0); 7651 if (rc != 0) { 7652 pr_err("error %d\n", rc); 7653 goto rw_error; 7654 } 7655 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_PTH__A, 100, 0); 7656 if (rc != 0) { 7657 pr_err("error %d\n", rc); 7658 goto rw_error; 7659 } 7660 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_QTH__A, 150, 0); 7661 if (rc != 0) { 7662 pr_err("error %d\n", rc); 7663 goto rw_error; 7664 } 7665 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_CTH__A, 80, 0); 7666 if (rc != 0) { 7667 pr_err("error %d\n", rc); 7668 goto rw_error; 7669 } 7670 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_MTH__A, 110, 0); 7671 if (rc != 0) { 7672 pr_err("error %d\n", rc); 7673 goto rw_error; 7674 } 7675 7676 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_RATE_LIM__A, 40, 0); 7677 if (rc != 0) { 7678 pr_err("error %d\n", rc); 7679 goto rw_error; 7680 } 7681 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_FREQ_LIM__A, 16, 0); 7682 if (rc != 0) { 7683 pr_err("error %d\n", rc); 7684 goto rw_error; 7685 } 7686 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_COUNT_LIM__A, 3, 0); 7687 if (rc != 0) { 7688 pr_err("error %d\n", rc); 7689 goto rw_error; 7690 } 7691 7692 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__A, 8, 0); 7693 if (rc != 0) { 7694 pr_err("error %d\n", rc); 7695 goto rw_error; 7696 } 7697 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__A, 74, 0); 7698 if (rc != 0) { 7699 pr_err("error %d\n", rc); 7700 goto rw_error; 7701 } 7702 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET1__A, 18, 0); 7703 if (rc != 0) { 7704 pr_err("error %d\n", rc); 7705 goto rw_error; 7706 } 7707 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET2__A, 13, 0); 7708 if (rc != 0) { 7709 pr_err("error %d\n", rc); 7710 goto rw_error; 7711 } 7712 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET3__A, 7, 0); 7713 if (rc != 0) { 7714 pr_err("error %d\n", rc); 7715 goto rw_error; 7716 } 7717 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET4__A, 0, 0); 7718 if (rc != 0) { 7719 pr_err("error %d\n", rc); 7720 goto rw_error; 7721 } 7722 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A, (u16)(-8), 0); 7723 if (rc != 0) { 7724 pr_err("error %d\n", rc); 7725 goto rw_error; 7726 } 7727 7728 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CA_FINE__A, 15, 0); 7729 if (rc != 0) { 7730 pr_err("error %d\n", rc); 7731 goto rw_error; 7732 } 7733 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CA_COARSE__A, 40, 0); 7734 if (rc != 0) { 7735 pr_err("error %d\n", rc); 7736 goto rw_error; 7737 } 7738 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CP_FINE__A, 2, 0); 7739 if (rc != 0) { 7740 pr_err("error %d\n", rc); 7741 goto rw_error; 7742 } 7743 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CP_MEDIUM__A, 50, 0); 7744 if (rc != 0) { 7745 pr_err("error %d\n", rc); 7746 goto rw_error; 7747 } 7748 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CP_COARSE__A, 255, 0); 7749 if (rc != 0) { 7750 pr_err("error %d\n", rc); 7751 goto rw_error; 7752 } 7753 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CI_FINE__A, 2, 0); 7754 if (rc != 0) { 7755 pr_err("error %d\n", rc); 7756 goto rw_error; 7757 } 7758 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CI_MEDIUM__A, 25, 0); 7759 if (rc != 0) { 7760 pr_err("error %d\n", rc); 7761 goto rw_error; 7762 } 7763 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CI_COARSE__A, 80, 0); 7764 if (rc != 0) { 7765 pr_err("error %d\n", rc); 7766 goto rw_error; 7767 } 7768 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EP_FINE__A, 12, 0); 7769 if (rc != 0) { 7770 pr_err("error %d\n", rc); 7771 goto rw_error; 7772 } 7773 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EP_MEDIUM__A, 24, 0); 7774 if (rc != 0) { 7775 pr_err("error %d\n", rc); 7776 goto rw_error; 7777 } 7778 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EP_COARSE__A, 24, 0); 7779 if (rc != 0) { 7780 pr_err("error %d\n", rc); 7781 goto rw_error; 7782 } 7783 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EI_FINE__A, 12, 0); 7784 if (rc != 0) { 7785 pr_err("error %d\n", rc); 7786 goto rw_error; 7787 } 7788 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EI_MEDIUM__A, 16, 0); 7789 if (rc != 0) { 7790 pr_err("error %d\n", rc); 7791 goto rw_error; 7792 } 7793 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EI_COARSE__A, 16, 0); 7794 if (rc != 0) { 7795 pr_err("error %d\n", rc); 7796 goto rw_error; 7797 } 7798 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF_FINE__A, 16, 0); 7799 if (rc != 0) { 7800 pr_err("error %d\n", rc); 7801 goto rw_error; 7802 } 7803 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF_MEDIUM__A, 48, 0); 7804 if (rc != 0) { 7805 pr_err("error %d\n", rc); 7806 goto rw_error; 7807 } 7808 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF_COARSE__A, 80, 0); 7809 if (rc != 0) { 7810 pr_err("error %d\n", rc); 7811 goto rw_error; 7812 } 7813 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF1_FINE__A, 5, 0); 7814 if (rc != 0) { 7815 pr_err("error %d\n", rc); 7816 goto rw_error; 7817 } 7818 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF1_MEDIUM__A, 15, 0); 7819 if (rc != 0) { 7820 pr_err("error %d\n", rc); 7821 goto rw_error; 7822 } 7823 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF1_COARSE__A, 16, 0); 7824 if (rc != 0) { 7825 pr_err("error %d\n", rc); 7826 goto rw_error; 7827 } 7828 7829 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_SL_SIG_POWER__A, 43520, 0); 7830 if (rc != 0) { 7831 pr_err("error %d\n", rc); 7832 goto rw_error; 7833 } 7834 7835 return 0; 7836 rw_error: 7837 return rc; 7838 } 7839 7840 /*============================================================================*/ 7841 #define QAM_SET_OP_ALL 0x1 7842 #define QAM_SET_OP_CONSTELLATION 0x2 7843 #define QAM_SET_OP_SPECTRUM 0X4 7844 7845 /* 7846 * \fn int set_qam () 7847 * \brief Set QAM demod. 7848 * \param demod: instance of demod. 7849 * \param channel: pointer to channel data. 7850 * \return int. 7851 */ 7852 static int 7853 set_qam(struct drx_demod_instance *demod, 7854 struct drx_channel *channel, s32 tuner_freq_offset, u32 op) 7855 { 7856 struct i2c_device_addr *dev_addr = NULL; 7857 struct drxj_data *ext_attr = NULL; 7858 struct drx_common_attr *common_attr = NULL; 7859 int rc; 7860 u32 adc_frequency = 0; 7861 u32 iqm_rc_rate = 0; 7862 u16 cmd_result = 0; 7863 u16 lc_symbol_freq = 0; 7864 u16 iqm_rc_stretch = 0; 7865 u16 set_env_parameters = 0; 7866 u16 set_param_parameters[2] = { 0 }; 7867 struct drxjscu_cmd cmd_scu = { /* command */ 0, 7868 /* parameter_len */ 0, 7869 /* result_len */ 0, 7870 /* parameter */ NULL, 7871 /* result */ NULL 7872 }; 7873 static const u8 qam_a_taps[] = { 7874 DRXJ_16TO8(-1), /* re0 */ 7875 DRXJ_16TO8(1), /* re1 */ 7876 DRXJ_16TO8(1), /* re2 */ 7877 DRXJ_16TO8(-1), /* re3 */ 7878 DRXJ_16TO8(-1), /* re4 */ 7879 DRXJ_16TO8(2), /* re5 */ 7880 DRXJ_16TO8(1), /* re6 */ 7881 DRXJ_16TO8(-2), /* re7 */ 7882 DRXJ_16TO8(0), /* re8 */ 7883 DRXJ_16TO8(3), /* re9 */ 7884 DRXJ_16TO8(-1), /* re10 */ 7885 DRXJ_16TO8(-3), /* re11 */ 7886 DRXJ_16TO8(4), /* re12 */ 7887 DRXJ_16TO8(1), /* re13 */ 7888 DRXJ_16TO8(-8), /* re14 */ 7889 DRXJ_16TO8(4), /* re15 */ 7890 DRXJ_16TO8(13), /* re16 */ 7891 DRXJ_16TO8(-13), /* re17 */ 7892 DRXJ_16TO8(-19), /* re18 */ 7893 DRXJ_16TO8(28), /* re19 */ 7894 DRXJ_16TO8(25), /* re20 */ 7895 DRXJ_16TO8(-53), /* re21 */ 7896 DRXJ_16TO8(-31), /* re22 */ 7897 DRXJ_16TO8(96), /* re23 */ 7898 DRXJ_16TO8(37), /* re24 */ 7899 DRXJ_16TO8(-190), /* re25 */ 7900 DRXJ_16TO8(-40), /* re26 */ 7901 DRXJ_16TO8(619) /* re27 */ 7902 }; 7903 static const u8 qam_b64_taps[] = { 7904 DRXJ_16TO8(0), /* re0 */ 7905 DRXJ_16TO8(-2), /* re1 */ 7906 DRXJ_16TO8(1), /* re2 */ 7907 DRXJ_16TO8(2), /* re3 */ 7908 DRXJ_16TO8(-2), /* re4 */ 7909 DRXJ_16TO8(0), /* re5 */ 7910 DRXJ_16TO8(4), /* re6 */ 7911 DRXJ_16TO8(-2), /* re7 */ 7912 DRXJ_16TO8(-4), /* re8 */ 7913 DRXJ_16TO8(4), /* re9 */ 7914 DRXJ_16TO8(3), /* re10 */ 7915 DRXJ_16TO8(-6), /* re11 */ 7916 DRXJ_16TO8(0), /* re12 */ 7917 DRXJ_16TO8(6), /* re13 */ 7918 DRXJ_16TO8(-5), /* re14 */ 7919 DRXJ_16TO8(-3), /* re15 */ 7920 DRXJ_16TO8(11), /* re16 */ 7921 DRXJ_16TO8(-4), /* re17 */ 7922 DRXJ_16TO8(-19), /* re18 */ 7923 DRXJ_16TO8(19), /* re19 */ 7924 DRXJ_16TO8(28), /* re20 */ 7925 DRXJ_16TO8(-45), /* re21 */ 7926 DRXJ_16TO8(-36), /* re22 */ 7927 DRXJ_16TO8(90), /* re23 */ 7928 DRXJ_16TO8(42), /* re24 */ 7929 DRXJ_16TO8(-185), /* re25 */ 7930 DRXJ_16TO8(-46), /* re26 */ 7931 DRXJ_16TO8(614) /* re27 */ 7932 }; 7933 static const u8 qam_b256_taps[] = { 7934 DRXJ_16TO8(-2), /* re0 */ 7935 DRXJ_16TO8(4), /* re1 */ 7936 DRXJ_16TO8(1), /* re2 */ 7937 DRXJ_16TO8(-4), /* re3 */ 7938 DRXJ_16TO8(0), /* re4 */ 7939 DRXJ_16TO8(4), /* re5 */ 7940 DRXJ_16TO8(-2), /* re6 */ 7941 DRXJ_16TO8(-4), /* re7 */ 7942 DRXJ_16TO8(5), /* re8 */ 7943 DRXJ_16TO8(2), /* re9 */ 7944 DRXJ_16TO8(-8), /* re10 */ 7945 DRXJ_16TO8(2), /* re11 */ 7946 DRXJ_16TO8(11), /* re12 */ 7947 DRXJ_16TO8(-8), /* re13 */ 7948 DRXJ_16TO8(-15), /* re14 */ 7949 DRXJ_16TO8(16), /* re15 */ 7950 DRXJ_16TO8(19), /* re16 */ 7951 DRXJ_16TO8(-27), /* re17 */ 7952 DRXJ_16TO8(-22), /* re18 */ 7953 DRXJ_16TO8(44), /* re19 */ 7954 DRXJ_16TO8(26), /* re20 */ 7955 DRXJ_16TO8(-69), /* re21 */ 7956 DRXJ_16TO8(-28), /* re22 */ 7957 DRXJ_16TO8(110), /* re23 */ 7958 DRXJ_16TO8(31), /* re24 */ 7959 DRXJ_16TO8(-201), /* re25 */ 7960 DRXJ_16TO8(-32), /* re26 */ 7961 DRXJ_16TO8(628) /* re27 */ 7962 }; 7963 static const u8 qam_c_taps[] = { 7964 DRXJ_16TO8(-3), /* re0 */ 7965 DRXJ_16TO8(3), /* re1 */ 7966 DRXJ_16TO8(2), /* re2 */ 7967 DRXJ_16TO8(-4), /* re3 */ 7968 DRXJ_16TO8(0), /* re4 */ 7969 DRXJ_16TO8(4), /* re5 */ 7970 DRXJ_16TO8(-1), /* re6 */ 7971 DRXJ_16TO8(-4), /* re7 */ 7972 DRXJ_16TO8(3), /* re8 */ 7973 DRXJ_16TO8(3), /* re9 */ 7974 DRXJ_16TO8(-5), /* re10 */ 7975 DRXJ_16TO8(0), /* re11 */ 7976 DRXJ_16TO8(9), /* re12 */ 7977 DRXJ_16TO8(-4), /* re13 */ 7978 DRXJ_16TO8(-12), /* re14 */ 7979 DRXJ_16TO8(10), /* re15 */ 7980 DRXJ_16TO8(16), /* re16 */ 7981 DRXJ_16TO8(-21), /* re17 */ 7982 DRXJ_16TO8(-20), /* re18 */ 7983 DRXJ_16TO8(37), /* re19 */ 7984 DRXJ_16TO8(25), /* re20 */ 7985 DRXJ_16TO8(-62), /* re21 */ 7986 DRXJ_16TO8(-28), /* re22 */ 7987 DRXJ_16TO8(105), /* re23 */ 7988 DRXJ_16TO8(31), /* re24 */ 7989 DRXJ_16TO8(-197), /* re25 */ 7990 DRXJ_16TO8(-33), /* re26 */ 7991 DRXJ_16TO8(626) /* re27 */ 7992 }; 7993 7994 dev_addr = demod->my_i2c_dev_addr; 7995 ext_attr = (struct drxj_data *) demod->my_ext_attr; 7996 common_attr = (struct drx_common_attr *) demod->my_common_attr; 7997 7998 if ((op & QAM_SET_OP_ALL) || (op & QAM_SET_OP_CONSTELLATION)) { 7999 if (ext_attr->standard == DRX_STANDARD_ITU_B) { 8000 switch (channel->constellation) { 8001 case DRX_CONSTELLATION_QAM256: 8002 iqm_rc_rate = 0x00AE3562; 8003 lc_symbol_freq = 8004 QAM_LC_SYMBOL_FREQ_FREQ_QAM_B_256; 8005 channel->symbolrate = 5360537; 8006 iqm_rc_stretch = IQM_RC_STRETCH_QAM_B_256; 8007 break; 8008 case DRX_CONSTELLATION_QAM64: 8009 iqm_rc_rate = 0x00C05A0E; 8010 lc_symbol_freq = 409; 8011 channel->symbolrate = 5056941; 8012 iqm_rc_stretch = IQM_RC_STRETCH_QAM_B_64; 8013 break; 8014 default: 8015 return -EINVAL; 8016 } 8017 } else { 8018 adc_frequency = (common_attr->sys_clock_freq * 1000) / 3; 8019 if (channel->symbolrate == 0) { 8020 pr_err("error: channel symbolrate is zero!\n"); 8021 return -EIO; 8022 } 8023 iqm_rc_rate = 8024 (adc_frequency / channel->symbolrate) * (1 << 21) + 8025 (frac28 8026 ((adc_frequency % channel->symbolrate), 8027 channel->symbolrate) >> 7) - (1 << 23); 8028 lc_symbol_freq = 8029 (u16) (frac28 8030 (channel->symbolrate + 8031 (adc_frequency >> 13), 8032 adc_frequency) >> 16); 8033 if (lc_symbol_freq > 511) 8034 lc_symbol_freq = 511; 8035 8036 iqm_rc_stretch = 21; 8037 } 8038 8039 if (ext_attr->standard == DRX_STANDARD_ITU_A) { 8040 set_env_parameters = QAM_TOP_ANNEX_A; /* annex */ 8041 set_param_parameters[0] = channel->constellation; /* constellation */ 8042 set_param_parameters[1] = DRX_INTERLEAVEMODE_I12_J17; /* interleave mode */ 8043 } else if (ext_attr->standard == DRX_STANDARD_ITU_B) { 8044 set_env_parameters = QAM_TOP_ANNEX_B; /* annex */ 8045 set_param_parameters[0] = channel->constellation; /* constellation */ 8046 set_param_parameters[1] = channel->interleavemode; /* interleave mode */ 8047 } else if (ext_attr->standard == DRX_STANDARD_ITU_C) { 8048 set_env_parameters = QAM_TOP_ANNEX_C; /* annex */ 8049 set_param_parameters[0] = channel->constellation; /* constellation */ 8050 set_param_parameters[1] = DRX_INTERLEAVEMODE_I12_J17; /* interleave mode */ 8051 } else { 8052 return -EINVAL; 8053 } 8054 } 8055 8056 if (op & QAM_SET_OP_ALL) { 8057 /* 8058 STEP 1: reset demodulator 8059 resets IQM, QAM and FEC HW blocks 8060 resets SCU variables 8061 */ 8062 /* stop all comm_exec */ 8063 rc = drxj_dap_write_reg16(dev_addr, FEC_COMM_EXEC__A, FEC_COMM_EXEC_STOP, 0); 8064 if (rc != 0) { 8065 pr_err("error %d\n", rc); 8066 goto rw_error; 8067 } 8068 rc = drxj_dap_write_reg16(dev_addr, QAM_COMM_EXEC__A, QAM_COMM_EXEC_STOP, 0); 8069 if (rc != 0) { 8070 pr_err("error %d\n", rc); 8071 goto rw_error; 8072 } 8073 rc = drxj_dap_write_reg16(dev_addr, IQM_FS_COMM_EXEC__A, IQM_FS_COMM_EXEC_STOP, 0); 8074 if (rc != 0) { 8075 pr_err("error %d\n", rc); 8076 goto rw_error; 8077 } 8078 rc = drxj_dap_write_reg16(dev_addr, IQM_FD_COMM_EXEC__A, IQM_FD_COMM_EXEC_STOP, 0); 8079 if (rc != 0) { 8080 pr_err("error %d\n", rc); 8081 goto rw_error; 8082 } 8083 rc = drxj_dap_write_reg16(dev_addr, IQM_RC_COMM_EXEC__A, IQM_RC_COMM_EXEC_STOP, 0); 8084 if (rc != 0) { 8085 pr_err("error %d\n", rc); 8086 goto rw_error; 8087 } 8088 rc = drxj_dap_write_reg16(dev_addr, IQM_RT_COMM_EXEC__A, IQM_RT_COMM_EXEC_STOP, 0); 8089 if (rc != 0) { 8090 pr_err("error %d\n", rc); 8091 goto rw_error; 8092 } 8093 rc = drxj_dap_write_reg16(dev_addr, IQM_CF_COMM_EXEC__A, IQM_CF_COMM_EXEC_STOP, 0); 8094 if (rc != 0) { 8095 pr_err("error %d\n", rc); 8096 goto rw_error; 8097 } 8098 8099 cmd_scu.command = SCU_RAM_COMMAND_STANDARD_QAM | 8100 SCU_RAM_COMMAND_CMD_DEMOD_RESET; 8101 cmd_scu.parameter_len = 0; 8102 cmd_scu.result_len = 1; 8103 cmd_scu.parameter = NULL; 8104 cmd_scu.result = &cmd_result; 8105 rc = scu_command(dev_addr, &cmd_scu); 8106 if (rc != 0) { 8107 pr_err("error %d\n", rc); 8108 goto rw_error; 8109 } 8110 } 8111 8112 if ((op & QAM_SET_OP_ALL) || (op & QAM_SET_OP_CONSTELLATION)) { 8113 /* 8114 STEP 2: configure demodulator 8115 -set env 8116 -set params (resets IQM,QAM,FEC HW; initializes some SCU variables ) 8117 */ 8118 cmd_scu.command = SCU_RAM_COMMAND_STANDARD_QAM | 8119 SCU_RAM_COMMAND_CMD_DEMOD_SET_ENV; 8120 cmd_scu.parameter_len = 1; 8121 cmd_scu.result_len = 1; 8122 cmd_scu.parameter = &set_env_parameters; 8123 cmd_scu.result = &cmd_result; 8124 rc = scu_command(dev_addr, &cmd_scu); 8125 if (rc != 0) { 8126 pr_err("error %d\n", rc); 8127 goto rw_error; 8128 } 8129 8130 cmd_scu.command = SCU_RAM_COMMAND_STANDARD_QAM | 8131 SCU_RAM_COMMAND_CMD_DEMOD_SET_PARAM; 8132 cmd_scu.parameter_len = 2; 8133 cmd_scu.result_len = 1; 8134 cmd_scu.parameter = set_param_parameters; 8135 cmd_scu.result = &cmd_result; 8136 rc = scu_command(dev_addr, &cmd_scu); 8137 if (rc != 0) { 8138 pr_err("error %d\n", rc); 8139 goto rw_error; 8140 } 8141 /* set symbol rate */ 8142 rc = drxdap_fasi_write_reg32(dev_addr, IQM_RC_RATE_OFS_LO__A, iqm_rc_rate, 0); 8143 if (rc != 0) { 8144 pr_err("error %d\n", rc); 8145 goto rw_error; 8146 } 8147 ext_attr->iqm_rc_rate_ofs = iqm_rc_rate; 8148 rc = set_qam_measurement(demod, channel->constellation, channel->symbolrate); 8149 if (rc != 0) { 8150 pr_err("error %d\n", rc); 8151 goto rw_error; 8152 } 8153 } 8154 /* STEP 3: enable the system in a mode where the ADC provides valid signal 8155 setup constellation independent registers */ 8156 /* from qam_cmd.py script (qam_driver_b) */ 8157 /* TODO: remove re-writes of HW reset values */ 8158 if ((op & QAM_SET_OP_ALL) || (op & QAM_SET_OP_SPECTRUM)) { 8159 rc = set_frequency(demod, channel, tuner_freq_offset); 8160 if (rc != 0) { 8161 pr_err("error %d\n", rc); 8162 goto rw_error; 8163 } 8164 } 8165 8166 if ((op & QAM_SET_OP_ALL) || (op & QAM_SET_OP_CONSTELLATION)) { 8167 8168 rc = drxj_dap_write_reg16(dev_addr, QAM_LC_SYMBOL_FREQ__A, lc_symbol_freq, 0); 8169 if (rc != 0) { 8170 pr_err("error %d\n", rc); 8171 goto rw_error; 8172 } 8173 rc = drxj_dap_write_reg16(dev_addr, IQM_RC_STRETCH__A, iqm_rc_stretch, 0); 8174 if (rc != 0) { 8175 pr_err("error %d\n", rc); 8176 goto rw_error; 8177 } 8178 } 8179 8180 if (op & QAM_SET_OP_ALL) { 8181 if (!ext_attr->has_lna) { 8182 rc = drxj_dap_write_reg16(dev_addr, IQM_AF_AMUX__A, 0x02, 0); 8183 if (rc != 0) { 8184 pr_err("error %d\n", rc); 8185 goto rw_error; 8186 } 8187 } 8188 rc = drxj_dap_write_reg16(dev_addr, IQM_CF_SYMMETRIC__A, 0, 0); 8189 if (rc != 0) { 8190 pr_err("error %d\n", rc); 8191 goto rw_error; 8192 } 8193 rc = drxj_dap_write_reg16(dev_addr, IQM_CF_MIDTAP__A, 3, 0); 8194 if (rc != 0) { 8195 pr_err("error %d\n", rc); 8196 goto rw_error; 8197 } 8198 rc = drxj_dap_write_reg16(dev_addr, IQM_CF_OUT_ENA__A, IQM_CF_OUT_ENA_QAM__M, 0); 8199 if (rc != 0) { 8200 pr_err("error %d\n", rc); 8201 goto rw_error; 8202 } 8203 8204 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_WR_RSV_0__A, 0x5f, 0); 8205 if (rc != 0) { 8206 pr_err("error %d\n", rc); 8207 goto rw_error; 8208 } /* scu temporary shut down agc */ 8209 8210 rc = drxj_dap_write_reg16(dev_addr, IQM_AF_SYNC_SEL__A, 3, 0); 8211 if (rc != 0) { 8212 pr_err("error %d\n", rc); 8213 goto rw_error; 8214 } 8215 rc = drxj_dap_write_reg16(dev_addr, IQM_AF_CLP_LEN__A, 0, 0); 8216 if (rc != 0) { 8217 pr_err("error %d\n", rc); 8218 goto rw_error; 8219 } 8220 rc = drxj_dap_write_reg16(dev_addr, IQM_AF_CLP_TH__A, 448, 0); 8221 if (rc != 0) { 8222 pr_err("error %d\n", rc); 8223 goto rw_error; 8224 } 8225 rc = drxj_dap_write_reg16(dev_addr, IQM_AF_SNS_LEN__A, 0, 0); 8226 if (rc != 0) { 8227 pr_err("error %d\n", rc); 8228 goto rw_error; 8229 } 8230 rc = drxj_dap_write_reg16(dev_addr, IQM_AF_PDREF__A, 4, 0); 8231 if (rc != 0) { 8232 pr_err("error %d\n", rc); 8233 goto rw_error; 8234 } 8235 rc = drxj_dap_write_reg16(dev_addr, IQM_AF_STDBY__A, 0x10, 0); 8236 if (rc != 0) { 8237 pr_err("error %d\n", rc); 8238 goto rw_error; 8239 } 8240 rc = drxj_dap_write_reg16(dev_addr, IQM_AF_PGA_GAIN__A, 11, 0); 8241 if (rc != 0) { 8242 pr_err("error %d\n", rc); 8243 goto rw_error; 8244 } 8245 8246 rc = drxj_dap_write_reg16(dev_addr, IQM_CF_POW_MEAS_LEN__A, 1, 0); 8247 if (rc != 0) { 8248 pr_err("error %d\n", rc); 8249 goto rw_error; 8250 } 8251 rc = drxj_dap_write_reg16(dev_addr, IQM_CF_SCALE_SH__A, IQM_CF_SCALE_SH__PRE, 0); 8252 if (rc != 0) { 8253 pr_err("error %d\n", rc); 8254 goto rw_error; 8255 } /*! reset default val ! */ 8256 8257 rc = drxj_dap_write_reg16(dev_addr, QAM_SY_TIMEOUT__A, QAM_SY_TIMEOUT__PRE, 0); 8258 if (rc != 0) { 8259 pr_err("error %d\n", rc); 8260 goto rw_error; 8261 } /*! reset default val ! */ 8262 if (ext_attr->standard == DRX_STANDARD_ITU_B) { 8263 rc = drxj_dap_write_reg16(dev_addr, QAM_SY_SYNC_LWM__A, QAM_SY_SYNC_LWM__PRE, 0); 8264 if (rc != 0) { 8265 pr_err("error %d\n", rc); 8266 goto rw_error; 8267 } /*! reset default val ! */ 8268 rc = drxj_dap_write_reg16(dev_addr, QAM_SY_SYNC_AWM__A, QAM_SY_SYNC_AWM__PRE, 0); 8269 if (rc != 0) { 8270 pr_err("error %d\n", rc); 8271 goto rw_error; 8272 } /*! reset default val ! */ 8273 rc = drxj_dap_write_reg16(dev_addr, QAM_SY_SYNC_HWM__A, QAM_SY_SYNC_HWM__PRE, 0); 8274 if (rc != 0) { 8275 pr_err("error %d\n", rc); 8276 goto rw_error; 8277 } /*! reset default val ! */ 8278 } else { 8279 switch (channel->constellation) { 8280 case DRX_CONSTELLATION_QAM16: 8281 case DRX_CONSTELLATION_QAM64: 8282 case DRX_CONSTELLATION_QAM256: 8283 rc = drxj_dap_write_reg16(dev_addr, QAM_SY_SYNC_LWM__A, 0x03, 0); 8284 if (rc != 0) { 8285 pr_err("error %d\n", rc); 8286 goto rw_error; 8287 } 8288 rc = drxj_dap_write_reg16(dev_addr, QAM_SY_SYNC_AWM__A, 0x04, 0); 8289 if (rc != 0) { 8290 pr_err("error %d\n", rc); 8291 goto rw_error; 8292 } 8293 rc = drxj_dap_write_reg16(dev_addr, QAM_SY_SYNC_HWM__A, QAM_SY_SYNC_HWM__PRE, 0); 8294 if (rc != 0) { 8295 pr_err("error %d\n", rc); 8296 goto rw_error; 8297 } /*! reset default val ! */ 8298 break; 8299 case DRX_CONSTELLATION_QAM32: 8300 case DRX_CONSTELLATION_QAM128: 8301 rc = drxj_dap_write_reg16(dev_addr, QAM_SY_SYNC_LWM__A, 0x03, 0); 8302 if (rc != 0) { 8303 pr_err("error %d\n", rc); 8304 goto rw_error; 8305 } 8306 rc = drxj_dap_write_reg16(dev_addr, QAM_SY_SYNC_AWM__A, 0x05, 0); 8307 if (rc != 0) { 8308 pr_err("error %d\n", rc); 8309 goto rw_error; 8310 } 8311 rc = drxj_dap_write_reg16(dev_addr, QAM_SY_SYNC_HWM__A, 0x06, 0); 8312 if (rc != 0) { 8313 pr_err("error %d\n", rc); 8314 goto rw_error; 8315 } 8316 break; 8317 default: 8318 return -EIO; 8319 } /* switch */ 8320 } 8321 8322 rc = drxj_dap_write_reg16(dev_addr, QAM_LC_MODE__A, QAM_LC_MODE__PRE, 0); 8323 if (rc != 0) { 8324 pr_err("error %d\n", rc); 8325 goto rw_error; 8326 } /*! reset default val ! */ 8327 rc = drxj_dap_write_reg16(dev_addr, QAM_LC_RATE_LIMIT__A, 3, 0); 8328 if (rc != 0) { 8329 pr_err("error %d\n", rc); 8330 goto rw_error; 8331 } 8332 rc = drxj_dap_write_reg16(dev_addr, QAM_LC_LPF_FACTORP__A, 4, 0); 8333 if (rc != 0) { 8334 pr_err("error %d\n", rc); 8335 goto rw_error; 8336 } 8337 rc = drxj_dap_write_reg16(dev_addr, QAM_LC_LPF_FACTORI__A, 4, 0); 8338 if (rc != 0) { 8339 pr_err("error %d\n", rc); 8340 goto rw_error; 8341 } 8342 rc = drxj_dap_write_reg16(dev_addr, QAM_LC_MODE__A, 7, 0); 8343 if (rc != 0) { 8344 pr_err("error %d\n", rc); 8345 goto rw_error; 8346 } 8347 rc = drxj_dap_write_reg16(dev_addr, QAM_LC_QUAL_TAB0__A, 1, 0); 8348 if (rc != 0) { 8349 pr_err("error %d\n", rc); 8350 goto rw_error; 8351 } 8352 rc = drxj_dap_write_reg16(dev_addr, QAM_LC_QUAL_TAB1__A, 1, 0); 8353 if (rc != 0) { 8354 pr_err("error %d\n", rc); 8355 goto rw_error; 8356 } 8357 rc = drxj_dap_write_reg16(dev_addr, QAM_LC_QUAL_TAB2__A, 1, 0); 8358 if (rc != 0) { 8359 pr_err("error %d\n", rc); 8360 goto rw_error; 8361 } 8362 rc = drxj_dap_write_reg16(dev_addr, QAM_LC_QUAL_TAB3__A, 1, 0); 8363 if (rc != 0) { 8364 pr_err("error %d\n", rc); 8365 goto rw_error; 8366 } 8367 rc = drxj_dap_write_reg16(dev_addr, QAM_LC_QUAL_TAB4__A, 2, 0); 8368 if (rc != 0) { 8369 pr_err("error %d\n", rc); 8370 goto rw_error; 8371 } 8372 rc = drxj_dap_write_reg16(dev_addr, QAM_LC_QUAL_TAB5__A, 2, 0); 8373 if (rc != 0) { 8374 pr_err("error %d\n", rc); 8375 goto rw_error; 8376 } 8377 rc = drxj_dap_write_reg16(dev_addr, QAM_LC_QUAL_TAB6__A, 2, 0); 8378 if (rc != 0) { 8379 pr_err("error %d\n", rc); 8380 goto rw_error; 8381 } 8382 rc = drxj_dap_write_reg16(dev_addr, QAM_LC_QUAL_TAB8__A, 2, 0); 8383 if (rc != 0) { 8384 pr_err("error %d\n", rc); 8385 goto rw_error; 8386 } 8387 rc = drxj_dap_write_reg16(dev_addr, QAM_LC_QUAL_TAB9__A, 2, 0); 8388 if (rc != 0) { 8389 pr_err("error %d\n", rc); 8390 goto rw_error; 8391 } 8392 rc = drxj_dap_write_reg16(dev_addr, QAM_LC_QUAL_TAB10__A, 2, 0); 8393 if (rc != 0) { 8394 pr_err("error %d\n", rc); 8395 goto rw_error; 8396 } 8397 rc = drxj_dap_write_reg16(dev_addr, QAM_LC_QUAL_TAB12__A, 2, 0); 8398 if (rc != 0) { 8399 pr_err("error %d\n", rc); 8400 goto rw_error; 8401 } 8402 rc = drxj_dap_write_reg16(dev_addr, QAM_LC_QUAL_TAB15__A, 3, 0); 8403 if (rc != 0) { 8404 pr_err("error %d\n", rc); 8405 goto rw_error; 8406 } 8407 rc = drxj_dap_write_reg16(dev_addr, QAM_LC_QUAL_TAB16__A, 3, 0); 8408 if (rc != 0) { 8409 pr_err("error %d\n", rc); 8410 goto rw_error; 8411 } 8412 rc = drxj_dap_write_reg16(dev_addr, QAM_LC_QUAL_TAB20__A, 4, 0); 8413 if (rc != 0) { 8414 pr_err("error %d\n", rc); 8415 goto rw_error; 8416 } 8417 rc = drxj_dap_write_reg16(dev_addr, QAM_LC_QUAL_TAB25__A, 4, 0); 8418 if (rc != 0) { 8419 pr_err("error %d\n", rc); 8420 goto rw_error; 8421 } 8422 8423 rc = drxj_dap_write_reg16(dev_addr, IQM_FS_ADJ_SEL__A, 1, 0); 8424 if (rc != 0) { 8425 pr_err("error %d\n", rc); 8426 goto rw_error; 8427 } 8428 rc = drxj_dap_write_reg16(dev_addr, IQM_RC_ADJ_SEL__A, 1, 0); 8429 if (rc != 0) { 8430 pr_err("error %d\n", rc); 8431 goto rw_error; 8432 } 8433 rc = drxj_dap_write_reg16(dev_addr, IQM_CF_ADJ_SEL__A, 1, 0); 8434 if (rc != 0) { 8435 pr_err("error %d\n", rc); 8436 goto rw_error; 8437 } 8438 rc = drxj_dap_write_reg16(dev_addr, IQM_CF_POW_MEAS_LEN__A, 0, 0); 8439 if (rc != 0) { 8440 pr_err("error %d\n", rc); 8441 goto rw_error; 8442 } 8443 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_GPIO__A, 0, 0); 8444 if (rc != 0) { 8445 pr_err("error %d\n", rc); 8446 goto rw_error; 8447 } 8448 8449 /* No more resets of the IQM, current standard correctly set => 8450 now AGCs can be configured. */ 8451 /* turn on IQMAF. It has to be in front of setAgc**() */ 8452 rc = set_iqm_af(demod, true); 8453 if (rc != 0) { 8454 pr_err("error %d\n", rc); 8455 goto rw_error; 8456 } 8457 rc = adc_synchronization(demod); 8458 if (rc != 0) { 8459 pr_err("error %d\n", rc); 8460 goto rw_error; 8461 } 8462 8463 rc = init_agc(demod); 8464 if (rc != 0) { 8465 pr_err("error %d\n", rc); 8466 goto rw_error; 8467 } 8468 rc = set_agc_if(demod, &(ext_attr->qam_if_agc_cfg), false); 8469 if (rc != 0) { 8470 pr_err("error %d\n", rc); 8471 goto rw_error; 8472 } 8473 rc = set_agc_rf(demod, &(ext_attr->qam_rf_agc_cfg), false); 8474 if (rc != 0) { 8475 pr_err("error %d\n", rc); 8476 goto rw_error; 8477 } 8478 { 8479 /* TODO fix this, store a struct drxj_cfg_afe_gain structure in struct drxj_data instead 8480 of only the gain */ 8481 struct drxj_cfg_afe_gain qam_pga_cfg = { DRX_STANDARD_ITU_B, 0 }; 8482 8483 qam_pga_cfg.gain = ext_attr->qam_pga_cfg; 8484 rc = ctrl_set_cfg_afe_gain(demod, &qam_pga_cfg); 8485 if (rc != 0) { 8486 pr_err("error %d\n", rc); 8487 goto rw_error; 8488 } 8489 } 8490 rc = ctrl_set_cfg_pre_saw(demod, &(ext_attr->qam_pre_saw_cfg)); 8491 if (rc != 0) { 8492 pr_err("error %d\n", rc); 8493 goto rw_error; 8494 } 8495 } 8496 8497 if ((op & QAM_SET_OP_ALL) || (op & QAM_SET_OP_CONSTELLATION)) { 8498 if (ext_attr->standard == DRX_STANDARD_ITU_A) { 8499 rc = drxdap_fasi_write_block(dev_addr, IQM_CF_TAP_RE0__A, sizeof(qam_a_taps), ((u8 *)qam_a_taps), 0); 8500 if (rc != 0) { 8501 pr_err("error %d\n", rc); 8502 goto rw_error; 8503 } 8504 rc = drxdap_fasi_write_block(dev_addr, IQM_CF_TAP_IM0__A, sizeof(qam_a_taps), ((u8 *)qam_a_taps), 0); 8505 if (rc != 0) { 8506 pr_err("error %d\n", rc); 8507 goto rw_error; 8508 } 8509 } else if (ext_attr->standard == DRX_STANDARD_ITU_B) { 8510 switch (channel->constellation) { 8511 case DRX_CONSTELLATION_QAM64: 8512 rc = drxdap_fasi_write_block(dev_addr, IQM_CF_TAP_RE0__A, sizeof(qam_b64_taps), ((u8 *)qam_b64_taps), 0); 8513 if (rc != 0) { 8514 pr_err("error %d\n", rc); 8515 goto rw_error; 8516 } 8517 rc = drxdap_fasi_write_block(dev_addr, IQM_CF_TAP_IM0__A, sizeof(qam_b64_taps), ((u8 *)qam_b64_taps), 0); 8518 if (rc != 0) { 8519 pr_err("error %d\n", rc); 8520 goto rw_error; 8521 } 8522 break; 8523 case DRX_CONSTELLATION_QAM256: 8524 rc = drxdap_fasi_write_block(dev_addr, IQM_CF_TAP_RE0__A, sizeof(qam_b256_taps), ((u8 *)qam_b256_taps), 0); 8525 if (rc != 0) { 8526 pr_err("error %d\n", rc); 8527 goto rw_error; 8528 } 8529 rc = drxdap_fasi_write_block(dev_addr, IQM_CF_TAP_IM0__A, sizeof(qam_b256_taps), ((u8 *)qam_b256_taps), 0); 8530 if (rc != 0) { 8531 pr_err("error %d\n", rc); 8532 goto rw_error; 8533 } 8534 break; 8535 default: 8536 return -EIO; 8537 } 8538 } else if (ext_attr->standard == DRX_STANDARD_ITU_C) { 8539 rc = drxdap_fasi_write_block(dev_addr, IQM_CF_TAP_RE0__A, sizeof(qam_c_taps), ((u8 *)qam_c_taps), 0); 8540 if (rc != 0) { 8541 pr_err("error %d\n", rc); 8542 goto rw_error; 8543 } 8544 rc = drxdap_fasi_write_block(dev_addr, IQM_CF_TAP_IM0__A, sizeof(qam_c_taps), ((u8 *)qam_c_taps), 0); 8545 if (rc != 0) { 8546 pr_err("error %d\n", rc); 8547 goto rw_error; 8548 } 8549 } 8550 8551 /* SETP 4: constellation specific setup */ 8552 switch (channel->constellation) { 8553 case DRX_CONSTELLATION_QAM16: 8554 rc = set_qam16(demod); 8555 if (rc != 0) { 8556 pr_err("error %d\n", rc); 8557 goto rw_error; 8558 } 8559 break; 8560 case DRX_CONSTELLATION_QAM32: 8561 rc = set_qam32(demod); 8562 if (rc != 0) { 8563 pr_err("error %d\n", rc); 8564 goto rw_error; 8565 } 8566 break; 8567 case DRX_CONSTELLATION_QAM64: 8568 rc = set_qam64(demod); 8569 if (rc != 0) { 8570 pr_err("error %d\n", rc); 8571 goto rw_error; 8572 } 8573 break; 8574 case DRX_CONSTELLATION_QAM128: 8575 rc = set_qam128(demod); 8576 if (rc != 0) { 8577 pr_err("error %d\n", rc); 8578 goto rw_error; 8579 } 8580 break; 8581 case DRX_CONSTELLATION_QAM256: 8582 rc = set_qam256(demod); 8583 if (rc != 0) { 8584 pr_err("error %d\n", rc); 8585 goto rw_error; 8586 } 8587 break; 8588 default: 8589 return -EIO; 8590 } /* switch */ 8591 } 8592 8593 if ((op & QAM_SET_OP_ALL)) { 8594 rc = drxj_dap_write_reg16(dev_addr, IQM_CF_SCALE_SH__A, 0, 0); 8595 if (rc != 0) { 8596 pr_err("error %d\n", rc); 8597 goto rw_error; 8598 } 8599 8600 /* Mpeg output has to be in front of FEC active */ 8601 rc = set_mpegtei_handling(demod); 8602 if (rc != 0) { 8603 pr_err("error %d\n", rc); 8604 goto rw_error; 8605 } 8606 rc = bit_reverse_mpeg_output(demod); 8607 if (rc != 0) { 8608 pr_err("error %d\n", rc); 8609 goto rw_error; 8610 } 8611 rc = set_mpeg_start_width(demod); 8612 if (rc != 0) { 8613 pr_err("error %d\n", rc); 8614 goto rw_error; 8615 } 8616 { 8617 /* TODO: move to set_standard after hardware reset value problem is solved */ 8618 /* Configure initial MPEG output */ 8619 struct drx_cfg_mpeg_output cfg_mpeg_output; 8620 8621 memcpy(&cfg_mpeg_output, &common_attr->mpeg_cfg, sizeof(cfg_mpeg_output)); 8622 cfg_mpeg_output.enable_mpeg_output = true; 8623 8624 rc = ctrl_set_cfg_mpeg_output(demod, &cfg_mpeg_output); 8625 if (rc != 0) { 8626 pr_err("error %d\n", rc); 8627 goto rw_error; 8628 } 8629 } 8630 } 8631 8632 if ((op & QAM_SET_OP_ALL) || (op & QAM_SET_OP_CONSTELLATION)) { 8633 8634 /* STEP 5: start QAM demodulator (starts FEC, QAM and IQM HW) */ 8635 cmd_scu.command = SCU_RAM_COMMAND_STANDARD_QAM | 8636 SCU_RAM_COMMAND_CMD_DEMOD_START; 8637 cmd_scu.parameter_len = 0; 8638 cmd_scu.result_len = 1; 8639 cmd_scu.parameter = NULL; 8640 cmd_scu.result = &cmd_result; 8641 rc = scu_command(dev_addr, &cmd_scu); 8642 if (rc != 0) { 8643 pr_err("error %d\n", rc); 8644 goto rw_error; 8645 } 8646 } 8647 8648 rc = drxj_dap_write_reg16(dev_addr, IQM_COMM_EXEC__A, IQM_COMM_EXEC_ACTIVE, 0); 8649 if (rc != 0) { 8650 pr_err("error %d\n", rc); 8651 goto rw_error; 8652 } 8653 rc = drxj_dap_write_reg16(dev_addr, QAM_COMM_EXEC__A, QAM_COMM_EXEC_ACTIVE, 0); 8654 if (rc != 0) { 8655 pr_err("error %d\n", rc); 8656 goto rw_error; 8657 } 8658 rc = drxj_dap_write_reg16(dev_addr, FEC_COMM_EXEC__A, FEC_COMM_EXEC_ACTIVE, 0); 8659 if (rc != 0) { 8660 pr_err("error %d\n", rc); 8661 goto rw_error; 8662 } 8663 8664 return 0; 8665 rw_error: 8666 return rc; 8667 } 8668 8669 /*============================================================================*/ 8670 static int ctrl_get_qam_sig_quality(struct drx_demod_instance *demod); 8671 8672 static int qam_flip_spec(struct drx_demod_instance *demod, struct drx_channel *channel) 8673 { 8674 struct i2c_device_addr *dev_addr = demod->my_i2c_dev_addr; 8675 struct drxj_data *ext_attr = demod->my_ext_attr; 8676 int rc; 8677 u32 iqm_fs_rate_ofs = 0; 8678 u32 iqm_fs_rate_lo = 0; 8679 u16 qam_ctl_ena = 0; 8680 u16 data = 0; 8681 u16 equ_mode = 0; 8682 u16 fsm_state = 0; 8683 int i = 0; 8684 int ofsofs = 0; 8685 8686 /* Silence the controlling of lc, equ, and the acquisition state machine */ 8687 rc = drxj_dap_read_reg16(dev_addr, SCU_RAM_QAM_CTL_ENA__A, &qam_ctl_ena, 0); 8688 if (rc != 0) { 8689 pr_err("error %d\n", rc); 8690 goto rw_error; 8691 } 8692 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_CTL_ENA__A, qam_ctl_ena & ~(SCU_RAM_QAM_CTL_ENA_ACQ__M | SCU_RAM_QAM_CTL_ENA_EQU__M | SCU_RAM_QAM_CTL_ENA_LC__M), 0); 8693 if (rc != 0) { 8694 pr_err("error %d\n", rc); 8695 goto rw_error; 8696 } 8697 8698 /* freeze the frequency control loop */ 8699 rc = drxj_dap_write_reg16(dev_addr, QAM_LC_CF__A, 0, 0); 8700 if (rc != 0) { 8701 pr_err("error %d\n", rc); 8702 goto rw_error; 8703 } 8704 rc = drxj_dap_write_reg16(dev_addr, QAM_LC_CF1__A, 0, 0); 8705 if (rc != 0) { 8706 pr_err("error %d\n", rc); 8707 goto rw_error; 8708 } 8709 8710 rc = drxj_dap_atomic_read_reg32(dev_addr, IQM_FS_RATE_OFS_LO__A, &iqm_fs_rate_ofs, 0); 8711 if (rc != 0) { 8712 pr_err("error %d\n", rc); 8713 goto rw_error; 8714 } 8715 rc = drxj_dap_atomic_read_reg32(dev_addr, IQM_FS_RATE_LO__A, &iqm_fs_rate_lo, 0); 8716 if (rc != 0) { 8717 pr_err("error %d\n", rc); 8718 goto rw_error; 8719 } 8720 ofsofs = iqm_fs_rate_lo - iqm_fs_rate_ofs; 8721 iqm_fs_rate_ofs = ~iqm_fs_rate_ofs + 1; 8722 iqm_fs_rate_ofs -= 2 * ofsofs; 8723 8724 /* freeze dq/fq updating */ 8725 rc = drxj_dap_read_reg16(dev_addr, QAM_DQ_MODE__A, &data, 0); 8726 if (rc != 0) { 8727 pr_err("error %d\n", rc); 8728 goto rw_error; 8729 } 8730 data = (data & 0xfff9); 8731 rc = drxj_dap_write_reg16(dev_addr, QAM_DQ_MODE__A, data, 0); 8732 if (rc != 0) { 8733 pr_err("error %d\n", rc); 8734 goto rw_error; 8735 } 8736 rc = drxj_dap_write_reg16(dev_addr, QAM_FQ_MODE__A, data, 0); 8737 if (rc != 0) { 8738 pr_err("error %d\n", rc); 8739 goto rw_error; 8740 } 8741 8742 /* lc_cp / _ci / _ca */ 8743 rc = drxj_dap_write_reg16(dev_addr, QAM_LC_CI__A, 0, 0); 8744 if (rc != 0) { 8745 pr_err("error %d\n", rc); 8746 goto rw_error; 8747 } 8748 rc = drxj_dap_write_reg16(dev_addr, QAM_LC_EP__A, 0, 0); 8749 if (rc != 0) { 8750 pr_err("error %d\n", rc); 8751 goto rw_error; 8752 } 8753 rc = drxj_dap_write_reg16(dev_addr, QAM_FQ_LA_FACTOR__A, 0, 0); 8754 if (rc != 0) { 8755 pr_err("error %d\n", rc); 8756 goto rw_error; 8757 } 8758 8759 /* flip the spec */ 8760 rc = drxdap_fasi_write_reg32(dev_addr, IQM_FS_RATE_OFS_LO__A, iqm_fs_rate_ofs, 0); 8761 if (rc != 0) { 8762 pr_err("error %d\n", rc); 8763 goto rw_error; 8764 } 8765 ext_attr->iqm_fs_rate_ofs = iqm_fs_rate_ofs; 8766 ext_attr->pos_image = !ext_attr->pos_image; 8767 8768 /* freeze dq/fq updating */ 8769 rc = drxj_dap_read_reg16(dev_addr, QAM_DQ_MODE__A, &data, 0); 8770 if (rc != 0) { 8771 pr_err("error %d\n", rc); 8772 goto rw_error; 8773 } 8774 equ_mode = data; 8775 data = (data & 0xfff9); 8776 rc = drxj_dap_write_reg16(dev_addr, QAM_DQ_MODE__A, data, 0); 8777 if (rc != 0) { 8778 pr_err("error %d\n", rc); 8779 goto rw_error; 8780 } 8781 rc = drxj_dap_write_reg16(dev_addr, QAM_FQ_MODE__A, data, 0); 8782 if (rc != 0) { 8783 pr_err("error %d\n", rc); 8784 goto rw_error; 8785 } 8786 8787 for (i = 0; i < 28; i++) { 8788 rc = drxj_dap_read_reg16(dev_addr, QAM_DQ_TAP_IM_EL0__A + (2 * i), &data, 0); 8789 if (rc != 0) { 8790 pr_err("error %d\n", rc); 8791 goto rw_error; 8792 } 8793 rc = drxj_dap_write_reg16(dev_addr, QAM_DQ_TAP_IM_EL0__A + (2 * i), -data, 0); 8794 if (rc != 0) { 8795 pr_err("error %d\n", rc); 8796 goto rw_error; 8797 } 8798 } 8799 8800 for (i = 0; i < 24; i++) { 8801 rc = drxj_dap_read_reg16(dev_addr, QAM_FQ_TAP_IM_EL0__A + (2 * i), &data, 0); 8802 if (rc != 0) { 8803 pr_err("error %d\n", rc); 8804 goto rw_error; 8805 } 8806 rc = drxj_dap_write_reg16(dev_addr, QAM_FQ_TAP_IM_EL0__A + (2 * i), -data, 0); 8807 if (rc != 0) { 8808 pr_err("error %d\n", rc); 8809 goto rw_error; 8810 } 8811 } 8812 8813 data = equ_mode; 8814 rc = drxj_dap_write_reg16(dev_addr, QAM_DQ_MODE__A, data, 0); 8815 if (rc != 0) { 8816 pr_err("error %d\n", rc); 8817 goto rw_error; 8818 } 8819 rc = drxj_dap_write_reg16(dev_addr, QAM_FQ_MODE__A, data, 0); 8820 if (rc != 0) { 8821 pr_err("error %d\n", rc); 8822 goto rw_error; 8823 } 8824 8825 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_STATE_TGT__A, 4, 0); 8826 if (rc != 0) { 8827 pr_err("error %d\n", rc); 8828 goto rw_error; 8829 } 8830 8831 i = 0; 8832 while ((fsm_state != 4) && (i++ < 100)) { 8833 rc = drxj_dap_read_reg16(dev_addr, SCU_RAM_QAM_FSM_STATE__A, &fsm_state, 0); 8834 if (rc != 0) { 8835 pr_err("error %d\n", rc); 8836 goto rw_error; 8837 } 8838 } 8839 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_CTL_ENA__A, (qam_ctl_ena | 0x0016), 0); 8840 if (rc != 0) { 8841 pr_err("error %d\n", rc); 8842 goto rw_error; 8843 } 8844 8845 return 0; 8846 rw_error: 8847 return rc; 8848 8849 } 8850 8851 #define NO_LOCK 0x0 8852 #define DEMOD_LOCKED 0x1 8853 #define SYNC_FLIPPED 0x2 8854 #define SPEC_MIRRORED 0x4 8855 /* 8856 * \fn int qam64auto () 8857 * \brief auto do sync pattern switching and mirroring. 8858 * \param demod: instance of demod. 8859 * \param channel: pointer to channel data. 8860 * \param tuner_freq_offset: tuner frequency offset. 8861 * \param lock_status: pointer to lock status. 8862 * \return int. 8863 */ 8864 static int 8865 qam64auto(struct drx_demod_instance *demod, 8866 struct drx_channel *channel, 8867 s32 tuner_freq_offset, enum drx_lock_status *lock_status) 8868 { 8869 struct drxj_data *ext_attr = demod->my_ext_attr; 8870 struct i2c_device_addr *dev_addr = demod->my_i2c_dev_addr; 8871 struct drx39xxj_state *state = dev_addr->user_data; 8872 struct dtv_frontend_properties *p = &state->frontend.dtv_property_cache; 8873 int rc; 8874 u32 lck_state = NO_LOCK; 8875 u32 start_time = 0; 8876 u32 d_locked_time = 0; 8877 u32 timeout_ofs = 0; 8878 u16 data = 0; 8879 8880 /* external attributes for storing acquired channel constellation */ 8881 *lock_status = DRX_NOT_LOCKED; 8882 start_time = jiffies_to_msecs(jiffies); 8883 lck_state = NO_LOCK; 8884 do { 8885 rc = ctrl_lock_status(demod, lock_status); 8886 if (rc != 0) { 8887 pr_err("error %d\n", rc); 8888 goto rw_error; 8889 } 8890 8891 switch (lck_state) { 8892 case NO_LOCK: 8893 if (*lock_status == DRXJ_DEMOD_LOCK) { 8894 rc = ctrl_get_qam_sig_quality(demod); 8895 if (rc != 0) { 8896 pr_err("error %d\n", rc); 8897 goto rw_error; 8898 } 8899 if (p->cnr.stat[0].svalue > 20800) { 8900 lck_state = DEMOD_LOCKED; 8901 /* some delay to see if fec_lock possible TODO find the right value */ 8902 timeout_ofs += DRXJ_QAM_DEMOD_LOCK_EXT_WAITTIME; /* see something, waiting longer */ 8903 d_locked_time = jiffies_to_msecs(jiffies); 8904 } 8905 } 8906 break; 8907 case DEMOD_LOCKED: 8908 if ((*lock_status == DRXJ_DEMOD_LOCK) && /* still demod_lock in 150ms */ 8909 ((jiffies_to_msecs(jiffies) - d_locked_time) > 8910 DRXJ_QAM_FEC_LOCK_WAITTIME)) { 8911 rc = drxj_dap_read_reg16(demod->my_i2c_dev_addr, QAM_SY_TIMEOUT__A, &data, 0); 8912 if (rc != 0) { 8913 pr_err("error %d\n", rc); 8914 goto rw_error; 8915 } 8916 rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, QAM_SY_TIMEOUT__A, data | 0x1, 0); 8917 if (rc != 0) { 8918 pr_err("error %d\n", rc); 8919 goto rw_error; 8920 } 8921 lck_state = SYNC_FLIPPED; 8922 msleep(10); 8923 } 8924 break; 8925 case SYNC_FLIPPED: 8926 if (*lock_status == DRXJ_DEMOD_LOCK) { 8927 if (channel->mirror == DRX_MIRROR_AUTO) { 8928 /* flip sync pattern back */ 8929 rc = drxj_dap_read_reg16(demod->my_i2c_dev_addr, QAM_SY_TIMEOUT__A, &data, 0); 8930 if (rc != 0) { 8931 pr_err("error %d\n", rc); 8932 goto rw_error; 8933 } 8934 rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, QAM_SY_TIMEOUT__A, data & 0xFFFE, 0); 8935 if (rc != 0) { 8936 pr_err("error %d\n", rc); 8937 goto rw_error; 8938 } 8939 /* flip spectrum */ 8940 ext_attr->mirror = DRX_MIRROR_YES; 8941 rc = qam_flip_spec(demod, channel); 8942 if (rc != 0) { 8943 pr_err("error %d\n", rc); 8944 goto rw_error; 8945 } 8946 lck_state = SPEC_MIRRORED; 8947 /* reset timer TODO: still need 500ms? */ 8948 start_time = d_locked_time = 8949 jiffies_to_msecs(jiffies); 8950 timeout_ofs = 0; 8951 } else { /* no need to wait lock */ 8952 8953 start_time = 8954 jiffies_to_msecs(jiffies) - 8955 DRXJ_QAM_MAX_WAITTIME - timeout_ofs; 8956 } 8957 } 8958 break; 8959 case SPEC_MIRRORED: 8960 if ((*lock_status == DRXJ_DEMOD_LOCK) && /* still demod_lock in 150ms */ 8961 ((jiffies_to_msecs(jiffies) - d_locked_time) > 8962 DRXJ_QAM_FEC_LOCK_WAITTIME)) { 8963 rc = ctrl_get_qam_sig_quality(demod); 8964 if (rc != 0) { 8965 pr_err("error %d\n", rc); 8966 goto rw_error; 8967 } 8968 if (p->cnr.stat[0].svalue > 20800) { 8969 rc = drxj_dap_read_reg16(demod->my_i2c_dev_addr, QAM_SY_TIMEOUT__A, &data, 0); 8970 if (rc != 0) { 8971 pr_err("error %d\n", rc); 8972 goto rw_error; 8973 } 8974 rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, QAM_SY_TIMEOUT__A, data | 0x1, 0); 8975 if (rc != 0) { 8976 pr_err("error %d\n", rc); 8977 goto rw_error; 8978 } 8979 /* no need to wait lock */ 8980 start_time = 8981 jiffies_to_msecs(jiffies) - 8982 DRXJ_QAM_MAX_WAITTIME - timeout_ofs; 8983 } 8984 } 8985 break; 8986 default: 8987 break; 8988 } 8989 msleep(10); 8990 } while 8991 ((*lock_status != DRX_LOCKED) && 8992 (*lock_status != DRX_NEVER_LOCK) && 8993 ((jiffies_to_msecs(jiffies) - start_time) < 8994 (DRXJ_QAM_MAX_WAITTIME + timeout_ofs)) 8995 ); 8996 /* Returning control to application ... */ 8997 8998 return 0; 8999 rw_error: 9000 return rc; 9001 } 9002 9003 /* 9004 * \fn int qam256auto () 9005 * \brief auto do sync pattern switching and mirroring. 9006 * \param demod: instance of demod. 9007 * \param channel: pointer to channel data. 9008 * \param tuner_freq_offset: tuner frequency offset. 9009 * \param lock_status: pointer to lock status. 9010 * \return int. 9011 */ 9012 static int 9013 qam256auto(struct drx_demod_instance *demod, 9014 struct drx_channel *channel, 9015 s32 tuner_freq_offset, enum drx_lock_status *lock_status) 9016 { 9017 struct drxj_data *ext_attr = demod->my_ext_attr; 9018 struct i2c_device_addr *dev_addr = demod->my_i2c_dev_addr; 9019 struct drx39xxj_state *state = dev_addr->user_data; 9020 struct dtv_frontend_properties *p = &state->frontend.dtv_property_cache; 9021 int rc; 9022 u32 lck_state = NO_LOCK; 9023 u32 start_time = 0; 9024 u32 d_locked_time = 0; 9025 u32 timeout_ofs = DRXJ_QAM_DEMOD_LOCK_EXT_WAITTIME; 9026 9027 /* external attributes for storing acquired channel constellation */ 9028 *lock_status = DRX_NOT_LOCKED; 9029 start_time = jiffies_to_msecs(jiffies); 9030 lck_state = NO_LOCK; 9031 do { 9032 rc = ctrl_lock_status(demod, lock_status); 9033 if (rc != 0) { 9034 pr_err("error %d\n", rc); 9035 goto rw_error; 9036 } 9037 switch (lck_state) { 9038 case NO_LOCK: 9039 if (*lock_status == DRXJ_DEMOD_LOCK) { 9040 rc = ctrl_get_qam_sig_quality(demod); 9041 if (rc != 0) { 9042 pr_err("error %d\n", rc); 9043 goto rw_error; 9044 } 9045 if (p->cnr.stat[0].svalue > 26800) { 9046 lck_state = DEMOD_LOCKED; 9047 timeout_ofs += DRXJ_QAM_DEMOD_LOCK_EXT_WAITTIME; /* see something, wait longer */ 9048 d_locked_time = jiffies_to_msecs(jiffies); 9049 } 9050 } 9051 break; 9052 case DEMOD_LOCKED: 9053 if (*lock_status == DRXJ_DEMOD_LOCK) { 9054 if ((channel->mirror == DRX_MIRROR_AUTO) && 9055 ((jiffies_to_msecs(jiffies) - d_locked_time) > 9056 DRXJ_QAM_FEC_LOCK_WAITTIME)) { 9057 ext_attr->mirror = DRX_MIRROR_YES; 9058 rc = qam_flip_spec(demod, channel); 9059 if (rc != 0) { 9060 pr_err("error %d\n", rc); 9061 goto rw_error; 9062 } 9063 lck_state = SPEC_MIRRORED; 9064 /* reset timer TODO: still need 300ms? */ 9065 start_time = jiffies_to_msecs(jiffies); 9066 timeout_ofs = -DRXJ_QAM_MAX_WAITTIME / 2; 9067 } 9068 } 9069 break; 9070 case SPEC_MIRRORED: 9071 break; 9072 default: 9073 break; 9074 } 9075 msleep(10); 9076 } while 9077 ((*lock_status < DRX_LOCKED) && 9078 (*lock_status != DRX_NEVER_LOCK) && 9079 ((jiffies_to_msecs(jiffies) - start_time) < 9080 (DRXJ_QAM_MAX_WAITTIME + timeout_ofs))); 9081 9082 return 0; 9083 rw_error: 9084 return rc; 9085 } 9086 9087 /* 9088 * \fn int set_qam_channel () 9089 * \brief Set QAM channel according to the requested constellation. 9090 * \param demod: instance of demod. 9091 * \param channel: pointer to channel data. 9092 * \return int. 9093 */ 9094 static int 9095 set_qam_channel(struct drx_demod_instance *demod, 9096 struct drx_channel *channel, s32 tuner_freq_offset) 9097 { 9098 struct drxj_data *ext_attr = NULL; 9099 int rc; 9100 enum drx_lock_status lock_status = DRX_NOT_LOCKED; 9101 bool auto_flag = false; 9102 9103 /* external attributes for storing acquired channel constellation */ 9104 ext_attr = (struct drxj_data *) demod->my_ext_attr; 9105 9106 /* set QAM channel constellation */ 9107 switch (channel->constellation) { 9108 case DRX_CONSTELLATION_QAM16: 9109 case DRX_CONSTELLATION_QAM32: 9110 case DRX_CONSTELLATION_QAM128: 9111 return -EINVAL; 9112 case DRX_CONSTELLATION_QAM64: 9113 case DRX_CONSTELLATION_QAM256: 9114 if (ext_attr->standard != DRX_STANDARD_ITU_B) 9115 return -EINVAL; 9116 9117 ext_attr->constellation = channel->constellation; 9118 if (channel->mirror == DRX_MIRROR_AUTO) 9119 ext_attr->mirror = DRX_MIRROR_NO; 9120 else 9121 ext_attr->mirror = channel->mirror; 9122 9123 rc = set_qam(demod, channel, tuner_freq_offset, QAM_SET_OP_ALL); 9124 if (rc != 0) { 9125 pr_err("error %d\n", rc); 9126 goto rw_error; 9127 } 9128 9129 if (channel->constellation == DRX_CONSTELLATION_QAM64) 9130 rc = qam64auto(demod, channel, tuner_freq_offset, 9131 &lock_status); 9132 else 9133 rc = qam256auto(demod, channel, tuner_freq_offset, 9134 &lock_status); 9135 if (rc != 0) { 9136 pr_err("error %d\n", rc); 9137 goto rw_error; 9138 } 9139 break; 9140 case DRX_CONSTELLATION_AUTO: /* for channel scan */ 9141 if (ext_attr->standard == DRX_STANDARD_ITU_B) { 9142 u16 qam_ctl_ena = 0; 9143 9144 auto_flag = true; 9145 9146 /* try to lock default QAM constellation: QAM256 */ 9147 channel->constellation = DRX_CONSTELLATION_QAM256; 9148 ext_attr->constellation = DRX_CONSTELLATION_QAM256; 9149 if (channel->mirror == DRX_MIRROR_AUTO) 9150 ext_attr->mirror = DRX_MIRROR_NO; 9151 else 9152 ext_attr->mirror = channel->mirror; 9153 rc = set_qam(demod, channel, tuner_freq_offset, 9154 QAM_SET_OP_ALL); 9155 if (rc != 0) { 9156 pr_err("error %d\n", rc); 9157 goto rw_error; 9158 } 9159 rc = qam256auto(demod, channel, tuner_freq_offset, 9160 &lock_status); 9161 if (rc != 0) { 9162 pr_err("error %d\n", rc); 9163 goto rw_error; 9164 } 9165 9166 if (lock_status >= DRX_LOCKED) { 9167 channel->constellation = DRX_CONSTELLATION_AUTO; 9168 break; 9169 } 9170 9171 /* QAM254 not locked. Try QAM64 constellation */ 9172 channel->constellation = DRX_CONSTELLATION_QAM64; 9173 ext_attr->constellation = DRX_CONSTELLATION_QAM64; 9174 if (channel->mirror == DRX_MIRROR_AUTO) 9175 ext_attr->mirror = DRX_MIRROR_NO; 9176 else 9177 ext_attr->mirror = channel->mirror; 9178 9179 rc = drxj_dap_read_reg16(demod->my_i2c_dev_addr, 9180 SCU_RAM_QAM_CTL_ENA__A, 9181 &qam_ctl_ena, 0); 9182 if (rc != 0) { 9183 pr_err("error %d\n", rc); 9184 goto rw_error; 9185 } 9186 rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, 9187 SCU_RAM_QAM_CTL_ENA__A, 9188 qam_ctl_ena & ~SCU_RAM_QAM_CTL_ENA_ACQ__M, 0); 9189 if (rc != 0) { 9190 pr_err("error %d\n", rc); 9191 goto rw_error; 9192 } 9193 rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, 9194 SCU_RAM_QAM_FSM_STATE_TGT__A, 9195 0x2, 0); 9196 if (rc != 0) { 9197 pr_err("error %d\n", rc); 9198 goto rw_error; 9199 } /* force to rate hunting */ 9200 9201 rc = set_qam(demod, channel, tuner_freq_offset, 9202 QAM_SET_OP_CONSTELLATION); 9203 if (rc != 0) { 9204 pr_err("error %d\n", rc); 9205 goto rw_error; 9206 } 9207 rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, 9208 SCU_RAM_QAM_CTL_ENA__A, 9209 qam_ctl_ena, 0); 9210 if (rc != 0) { 9211 pr_err("error %d\n", rc); 9212 goto rw_error; 9213 } 9214 9215 rc = qam64auto(demod, channel, tuner_freq_offset, 9216 &lock_status); 9217 if (rc != 0) { 9218 pr_err("error %d\n", rc); 9219 goto rw_error; 9220 } 9221 9222 channel->constellation = DRX_CONSTELLATION_AUTO; 9223 } else if (ext_attr->standard == DRX_STANDARD_ITU_C) { 9224 u16 qam_ctl_ena = 0; 9225 9226 channel->constellation = DRX_CONSTELLATION_QAM64; 9227 ext_attr->constellation = DRX_CONSTELLATION_QAM64; 9228 auto_flag = true; 9229 9230 if (channel->mirror == DRX_MIRROR_AUTO) 9231 ext_attr->mirror = DRX_MIRROR_NO; 9232 else 9233 ext_attr->mirror = channel->mirror; 9234 rc = drxj_dap_read_reg16(demod->my_i2c_dev_addr, 9235 SCU_RAM_QAM_CTL_ENA__A, 9236 &qam_ctl_ena, 0); 9237 if (rc != 0) { 9238 pr_err("error %d\n", rc); 9239 goto rw_error; 9240 } 9241 rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, 9242 SCU_RAM_QAM_CTL_ENA__A, 9243 qam_ctl_ena & ~SCU_RAM_QAM_CTL_ENA_ACQ__M, 0); 9244 if (rc != 0) { 9245 pr_err("error %d\n", rc); 9246 goto rw_error; 9247 } 9248 rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, 9249 SCU_RAM_QAM_FSM_STATE_TGT__A, 9250 0x2, 0); 9251 if (rc != 0) { 9252 pr_err("error %d\n", rc); 9253 goto rw_error; 9254 } /* force to rate hunting */ 9255 9256 rc = set_qam(demod, channel, tuner_freq_offset, 9257 QAM_SET_OP_CONSTELLATION); 9258 if (rc != 0) { 9259 pr_err("error %d\n", rc); 9260 goto rw_error; 9261 } 9262 rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, 9263 SCU_RAM_QAM_CTL_ENA__A, 9264 qam_ctl_ena, 0); 9265 if (rc != 0) { 9266 pr_err("error %d\n", rc); 9267 goto rw_error; 9268 } 9269 rc = qam64auto(demod, channel, tuner_freq_offset, 9270 &lock_status); 9271 if (rc != 0) { 9272 pr_err("error %d\n", rc); 9273 goto rw_error; 9274 } 9275 channel->constellation = DRX_CONSTELLATION_AUTO; 9276 } else { 9277 return -EINVAL; 9278 } 9279 break; 9280 default: 9281 return -EINVAL; 9282 } 9283 9284 return 0; 9285 rw_error: 9286 /* restore starting value */ 9287 if (auto_flag) 9288 channel->constellation = DRX_CONSTELLATION_AUTO; 9289 return rc; 9290 } 9291 9292 /*============================================================================*/ 9293 9294 /* 9295 * \fn static short get_qamrs_err_count(struct i2c_device_addr *dev_addr) 9296 * \brief Get RS error count in QAM mode (used for post RS BER calculation) 9297 * \return Error code 9298 * 9299 * precondition: measurement period & measurement prescale must be set 9300 * 9301 */ 9302 static int 9303 get_qamrs_err_count(struct i2c_device_addr *dev_addr, 9304 struct drxjrs_errors *rs_errors) 9305 { 9306 int rc; 9307 u16 nr_bit_errors = 0, 9308 nr_symbol_errors = 0, 9309 nr_packet_errors = 0, nr_failures = 0, nr_snc_par_fail_count = 0; 9310 9311 /* check arguments */ 9312 if (dev_addr == NULL) 9313 return -EINVAL; 9314 9315 /* all reported errors are received in the */ 9316 /* most recently finished measurement period */ 9317 /* no of pre RS bit errors */ 9318 rc = drxj_dap_read_reg16(dev_addr, FEC_RS_NR_BIT_ERRORS__A, &nr_bit_errors, 0); 9319 if (rc != 0) { 9320 pr_err("error %d\n", rc); 9321 goto rw_error; 9322 } 9323 /* no of symbol errors */ 9324 rc = drxj_dap_read_reg16(dev_addr, FEC_RS_NR_SYMBOL_ERRORS__A, &nr_symbol_errors, 0); 9325 if (rc != 0) { 9326 pr_err("error %d\n", rc); 9327 goto rw_error; 9328 } 9329 /* no of packet errors */ 9330 rc = drxj_dap_read_reg16(dev_addr, FEC_RS_NR_PACKET_ERRORS__A, &nr_packet_errors, 0); 9331 if (rc != 0) { 9332 pr_err("error %d\n", rc); 9333 goto rw_error; 9334 } 9335 /* no of failures to decode */ 9336 rc = drxj_dap_read_reg16(dev_addr, FEC_RS_NR_FAILURES__A, &nr_failures, 0); 9337 if (rc != 0) { 9338 pr_err("error %d\n", rc); 9339 goto rw_error; 9340 } 9341 /* no of post RS bit erros */ 9342 rc = drxj_dap_read_reg16(dev_addr, FEC_OC_SNC_FAIL_COUNT__A, &nr_snc_par_fail_count, 0); 9343 if (rc != 0) { 9344 pr_err("error %d\n", rc); 9345 goto rw_error; 9346 } 9347 /* TODO: NOTE */ 9348 /* These register values are fetched in non-atomic fashion */ 9349 /* It is possible that the read values contain unrelated information */ 9350 9351 rs_errors->nr_bit_errors = nr_bit_errors & FEC_RS_NR_BIT_ERRORS__M; 9352 rs_errors->nr_symbol_errors = nr_symbol_errors & FEC_RS_NR_SYMBOL_ERRORS__M; 9353 rs_errors->nr_packet_errors = nr_packet_errors & FEC_RS_NR_PACKET_ERRORS__M; 9354 rs_errors->nr_failures = nr_failures & FEC_RS_NR_FAILURES__M; 9355 rs_errors->nr_snc_par_fail_count = 9356 nr_snc_par_fail_count & FEC_OC_SNC_FAIL_COUNT__M; 9357 9358 return 0; 9359 rw_error: 9360 return rc; 9361 } 9362 9363 /*============================================================================*/ 9364 9365 /* 9366 * \fn int get_sig_strength() 9367 * \brief Retrieve signal strength for VSB and QAM. 9368 * \param demod Pointer to demod instance 9369 * \param u16-t Pointer to signal strength data; range 0, .. , 100. 9370 * \return int. 9371 * \retval 0 sig_strength contains valid data. 9372 * \retval -EINVAL sig_strength is NULL. 9373 * \retval -EIO Erroneous data, sig_strength contains invalid data. 9374 */ 9375 #define DRXJ_AGC_TOP 0x2800 9376 #define DRXJ_AGC_SNS 0x1600 9377 #define DRXJ_RFAGC_MAX 0x3fff 9378 #define DRXJ_RFAGC_MIN 0x800 9379 9380 static int get_sig_strength(struct drx_demod_instance *demod, u16 *sig_strength) 9381 { 9382 struct i2c_device_addr *dev_addr = demod->my_i2c_dev_addr; 9383 int rc; 9384 u16 rf_gain = 0; 9385 u16 if_gain = 0; 9386 u16 if_agc_sns = 0; 9387 u16 if_agc_top = 0; 9388 u16 rf_agc_max = 0; 9389 u16 rf_agc_min = 0; 9390 9391 rc = drxj_dap_read_reg16(dev_addr, IQM_AF_AGC_IF__A, &if_gain, 0); 9392 if (rc != 0) { 9393 pr_err("error %d\n", rc); 9394 goto rw_error; 9395 } 9396 if_gain &= IQM_AF_AGC_IF__M; 9397 rc = drxj_dap_read_reg16(dev_addr, IQM_AF_AGC_RF__A, &rf_gain, 0); 9398 if (rc != 0) { 9399 pr_err("error %d\n", rc); 9400 goto rw_error; 9401 } 9402 rf_gain &= IQM_AF_AGC_RF__M; 9403 9404 if_agc_sns = DRXJ_AGC_SNS; 9405 if_agc_top = DRXJ_AGC_TOP; 9406 rf_agc_max = DRXJ_RFAGC_MAX; 9407 rf_agc_min = DRXJ_RFAGC_MIN; 9408 9409 if (if_gain > if_agc_top) { 9410 if (rf_gain > rf_agc_max) 9411 *sig_strength = 100; 9412 else if (rf_gain > rf_agc_min) { 9413 if (rf_agc_max == rf_agc_min) { 9414 pr_err("error: rf_agc_max == rf_agc_min\n"); 9415 return -EIO; 9416 } 9417 *sig_strength = 9418 75 + 25 * (rf_gain - rf_agc_min) / (rf_agc_max - 9419 rf_agc_min); 9420 } else 9421 *sig_strength = 75; 9422 } else if (if_gain > if_agc_sns) { 9423 if (if_agc_top == if_agc_sns) { 9424 pr_err("error: if_agc_top == if_agc_sns\n"); 9425 return -EIO; 9426 } 9427 *sig_strength = 9428 20 + 55 * (if_gain - if_agc_sns) / (if_agc_top - if_agc_sns); 9429 } else { 9430 if (!if_agc_sns) { 9431 pr_err("error: if_agc_sns is zero!\n"); 9432 return -EIO; 9433 } 9434 *sig_strength = (20 * if_gain / if_agc_sns); 9435 } 9436 9437 if (*sig_strength <= 7) 9438 *sig_strength = 0; 9439 9440 return 0; 9441 rw_error: 9442 return rc; 9443 } 9444 9445 /* 9446 * \fn int ctrl_get_qam_sig_quality() 9447 * \brief Retrieve QAM signal quality from device. 9448 * \param devmod Pointer to demodulator instance. 9449 * \param sig_quality Pointer to signal quality data. 9450 * \return int. 9451 * \retval 0 sig_quality contains valid data. 9452 * \retval -EINVAL sig_quality is NULL. 9453 * \retval -EIO Erroneous data, sig_quality contains invalid data. 9454 9455 * Pre-condition: Device must be started and in lock. 9456 */ 9457 static int 9458 ctrl_get_qam_sig_quality(struct drx_demod_instance *demod) 9459 { 9460 struct i2c_device_addr *dev_addr = demod->my_i2c_dev_addr; 9461 struct drxj_data *ext_attr = demod->my_ext_attr; 9462 struct drx39xxj_state *state = dev_addr->user_data; 9463 struct dtv_frontend_properties *p = &state->frontend.dtv_property_cache; 9464 struct drxjrs_errors measuredrs_errors = { 0, 0, 0, 0, 0 }; 9465 enum drx_modulation constellation = ext_attr->constellation; 9466 int rc; 9467 9468 u32 pre_bit_err_rs = 0; /* pre RedSolomon Bit Error Rate */ 9469 u32 post_bit_err_rs = 0; /* post RedSolomon Bit Error Rate */ 9470 u32 pkt_errs = 0; /* no of packet errors in RS */ 9471 u16 qam_sl_err_power = 0; /* accumulated error between raw and sliced symbols */ 9472 u16 qsym_err_vd = 0; /* quadrature symbol errors in QAM_VD */ 9473 u16 fec_oc_period = 0; /* SNC sync failure measurement period */ 9474 u16 fec_rs_prescale = 0; /* ReedSolomon Measurement Prescale */ 9475 u16 fec_rs_period = 0; /* Value for corresponding I2C register */ 9476 /* calculation constants */ 9477 u32 rs_bit_cnt = 0; /* RedSolomon Bit Count */ 9478 u32 qam_sl_sig_power = 0; /* used for MER, depends of QAM constellation */ 9479 /* intermediate results */ 9480 u32 e = 0; /* exponent value used for QAM BER/SER */ 9481 u32 m = 0; /* mantisa value used for QAM BER/SER */ 9482 u32 ber_cnt = 0; /* BER count */ 9483 /* signal quality info */ 9484 u32 qam_sl_mer = 0; /* QAM MER */ 9485 u32 qam_pre_rs_ber = 0; /* Pre RedSolomon BER */ 9486 u32 qam_post_rs_ber = 0; /* Post RedSolomon BER */ 9487 u32 qam_vd_ser = 0; /* ViterbiDecoder SER */ 9488 u16 qam_vd_prescale = 0; /* Viterbi Measurement Prescale */ 9489 u16 qam_vd_period = 0; /* Viterbi Measurement period */ 9490 u32 vd_bit_cnt = 0; /* ViterbiDecoder Bit Count */ 9491 9492 p->block_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE; 9493 9494 /* read the physical registers */ 9495 /* Get the RS error data */ 9496 rc = get_qamrs_err_count(dev_addr, &measuredrs_errors); 9497 if (rc != 0) { 9498 pr_err("error %d\n", rc); 9499 goto rw_error; 9500 } 9501 /* get the register value needed for MER */ 9502 rc = drxj_dap_read_reg16(dev_addr, QAM_SL_ERR_POWER__A, &qam_sl_err_power, 0); 9503 if (rc != 0) { 9504 pr_err("error %d\n", rc); 9505 goto rw_error; 9506 } 9507 /* get the register value needed for post RS BER */ 9508 rc = drxj_dap_read_reg16(dev_addr, FEC_OC_SNC_FAIL_PERIOD__A, &fec_oc_period, 0); 9509 if (rc != 0) { 9510 pr_err("error %d\n", rc); 9511 goto rw_error; 9512 } 9513 9514 /* get constants needed for signal quality calculation */ 9515 fec_rs_period = ext_attr->fec_rs_period; 9516 fec_rs_prescale = ext_attr->fec_rs_prescale; 9517 rs_bit_cnt = fec_rs_period * fec_rs_prescale * ext_attr->fec_rs_plen; 9518 qam_vd_period = ext_attr->qam_vd_period; 9519 qam_vd_prescale = ext_attr->qam_vd_prescale; 9520 vd_bit_cnt = qam_vd_period * qam_vd_prescale * ext_attr->fec_vd_plen; 9521 9522 /* DRXJ_QAM_SL_SIG_POWER_QAMxxx * 4 */ 9523 switch (constellation) { 9524 case DRX_CONSTELLATION_QAM16: 9525 qam_sl_sig_power = DRXJ_QAM_SL_SIG_POWER_QAM16 << 2; 9526 break; 9527 case DRX_CONSTELLATION_QAM32: 9528 qam_sl_sig_power = DRXJ_QAM_SL_SIG_POWER_QAM32 << 2; 9529 break; 9530 case DRX_CONSTELLATION_QAM64: 9531 qam_sl_sig_power = DRXJ_QAM_SL_SIG_POWER_QAM64 << 2; 9532 break; 9533 case DRX_CONSTELLATION_QAM128: 9534 qam_sl_sig_power = DRXJ_QAM_SL_SIG_POWER_QAM128 << 2; 9535 break; 9536 case DRX_CONSTELLATION_QAM256: 9537 qam_sl_sig_power = DRXJ_QAM_SL_SIG_POWER_QAM256 << 2; 9538 break; 9539 default: 9540 rc = -EIO; 9541 goto rw_error; 9542 } 9543 9544 /* ------------------------------ */ 9545 /* MER Calculation */ 9546 /* ------------------------------ */ 9547 /* MER is good if it is above 27.5 for QAM256 or 21.5 for QAM64 */ 9548 9549 /* 10.0*log10(qam_sl_sig_power * 4.0 / qam_sl_err_power); */ 9550 if (qam_sl_err_power == 0) 9551 qam_sl_mer = 0; 9552 else 9553 qam_sl_mer = log1_times100(qam_sl_sig_power) - log1_times100((u32)qam_sl_err_power); 9554 9555 /* ----------------------------------------- */ 9556 /* Pre Viterbi Symbol Error Rate Calculation */ 9557 /* ----------------------------------------- */ 9558 /* pre viterbi SER is good if it is below 0.025 */ 9559 9560 /* get the register value */ 9561 /* no of quadrature symbol errors */ 9562 rc = drxj_dap_read_reg16(dev_addr, QAM_VD_NR_QSYM_ERRORS__A, &qsym_err_vd, 0); 9563 if (rc != 0) { 9564 pr_err("error %d\n", rc); 9565 goto rw_error; 9566 } 9567 /* Extract the Exponent and the Mantisa */ 9568 /* of number of quadrature symbol errors */ 9569 e = (qsym_err_vd & QAM_VD_NR_QSYM_ERRORS_EXP__M) >> 9570 QAM_VD_NR_QSYM_ERRORS_EXP__B; 9571 m = (qsym_err_vd & QAM_VD_NR_SYMBOL_ERRORS_FIXED_MANT__M) >> 9572 QAM_VD_NR_SYMBOL_ERRORS_FIXED_MANT__B; 9573 9574 if ((m << e) >> 3 > 549752) 9575 qam_vd_ser = 500000 * vd_bit_cnt * ((e > 2) ? 1 : 8) / 8; 9576 else 9577 qam_vd_ser = m << ((e > 2) ? (e - 3) : e); 9578 9579 /* --------------------------------------- */ 9580 /* pre and post RedSolomon BER Calculation */ 9581 /* --------------------------------------- */ 9582 /* pre RS BER is good if it is below 3.5e-4 */ 9583 9584 /* get the register values */ 9585 pre_bit_err_rs = (u32) measuredrs_errors.nr_bit_errors; 9586 pkt_errs = post_bit_err_rs = (u32) measuredrs_errors.nr_snc_par_fail_count; 9587 9588 /* Extract the Exponent and the Mantisa of the */ 9589 /* pre Reed-Solomon bit error count */ 9590 e = (pre_bit_err_rs & FEC_RS_NR_BIT_ERRORS_EXP__M) >> 9591 FEC_RS_NR_BIT_ERRORS_EXP__B; 9592 m = (pre_bit_err_rs & FEC_RS_NR_BIT_ERRORS_FIXED_MANT__M) >> 9593 FEC_RS_NR_BIT_ERRORS_FIXED_MANT__B; 9594 9595 ber_cnt = m << e; 9596 9597 /*qam_pre_rs_ber = frac_times1e6( ber_cnt, rs_bit_cnt ); */ 9598 if (m > (rs_bit_cnt >> (e + 1)) || (rs_bit_cnt >> e) == 0) 9599 qam_pre_rs_ber = 500000 * rs_bit_cnt >> e; 9600 else 9601 qam_pre_rs_ber = ber_cnt; 9602 9603 /* post RS BER = 1000000* (11.17 * FEC_OC_SNC_FAIL_COUNT__A) / */ 9604 /* (1504.0 * FEC_OC_SNC_FAIL_PERIOD__A) */ 9605 /* 9606 => c = (1000000*100*11.17)/1504 = 9607 post RS BER = (( c* FEC_OC_SNC_FAIL_COUNT__A) / 9608 (100 * FEC_OC_SNC_FAIL_PERIOD__A) 9609 *100 and /100 is for more precision. 9610 => (20 bits * 12 bits) /(16 bits * 7 bits) => safe in 32 bits computation 9611 9612 Precision errors still possible. 9613 */ 9614 if (!fec_oc_period) { 9615 qam_post_rs_ber = 0xFFFFFFFF; 9616 } else { 9617 e = post_bit_err_rs * 742686; 9618 m = fec_oc_period * 100; 9619 qam_post_rs_ber = e / m; 9620 } 9621 9622 /* fill signal quality data structure */ 9623 p->pre_bit_count.stat[0].scale = FE_SCALE_COUNTER; 9624 p->post_bit_count.stat[0].scale = FE_SCALE_COUNTER; 9625 p->pre_bit_error.stat[0].scale = FE_SCALE_COUNTER; 9626 p->post_bit_error.stat[0].scale = FE_SCALE_COUNTER; 9627 p->block_error.stat[0].scale = FE_SCALE_COUNTER; 9628 p->cnr.stat[0].scale = FE_SCALE_DECIBEL; 9629 9630 p->cnr.stat[0].svalue = ((u16) qam_sl_mer) * 100; 9631 if (ext_attr->standard == DRX_STANDARD_ITU_B) { 9632 p->pre_bit_error.stat[0].uvalue += qam_vd_ser; 9633 p->pre_bit_count.stat[0].uvalue += vd_bit_cnt * ((e > 2) ? 1 : 8) / 8; 9634 } else { 9635 p->pre_bit_error.stat[0].uvalue += qam_pre_rs_ber; 9636 p->pre_bit_count.stat[0].uvalue += rs_bit_cnt >> e; 9637 } 9638 9639 p->post_bit_error.stat[0].uvalue += qam_post_rs_ber; 9640 p->post_bit_count.stat[0].uvalue += rs_bit_cnt >> e; 9641 9642 p->block_error.stat[0].uvalue += pkt_errs; 9643 9644 #ifdef DRXJ_SIGNAL_ACCUM_ERR 9645 rc = get_acc_pkt_err(demod, &sig_quality->packet_error); 9646 if (rc != 0) { 9647 pr_err("error %d\n", rc); 9648 goto rw_error; 9649 } 9650 #endif 9651 9652 return 0; 9653 rw_error: 9654 p->pre_bit_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE; 9655 p->post_bit_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE; 9656 p->pre_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE; 9657 p->post_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE; 9658 p->block_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE; 9659 p->cnr.stat[0].scale = FE_SCALE_NOT_AVAILABLE; 9660 9661 return rc; 9662 } 9663 9664 #endif /* #ifndef DRXJ_VSB_ONLY */ 9665 9666 /*============================================================================*/ 9667 /*== END QAM DATAPATH FUNCTIONS ==*/ 9668 /*============================================================================*/ 9669 9670 /*============================================================================*/ 9671 /*============================================================================*/ 9672 /*== ATV DATAPATH FUNCTIONS ==*/ 9673 /*============================================================================*/ 9674 /*============================================================================*/ 9675 9676 /* 9677 Implementation notes. 9678 9679 NTSC/FM AGCs 9680 9681 Four AGCs are used for NTSC: 9682 (1) RF (used to attenuate the input signal in case of to much power) 9683 (2) IF (used to attenuate the input signal in case of to much power) 9684 (3) Video AGC (used to amplify the output signal in case input to low) 9685 (4) SIF AGC (used to amplify the output signal in case input to low) 9686 9687 Video AGC is coupled to RF and IF. SIF AGC is not coupled. It is assumed 9688 that the coupling between Video AGC and the RF and IF AGCs also works in 9689 favor of the SIF AGC. 9690 9691 Three AGCs are used for FM: 9692 (1) RF (used to attenuate the input signal in case of to much power) 9693 (2) IF (used to attenuate the input signal in case of to much power) 9694 (3) SIF AGC (used to amplify the output signal in case input to low) 9695 9696 The SIF AGC is now coupled to the RF/IF AGCs. 9697 The SIF AGC is needed for both SIF output and the internal SIF signal to 9698 the AUD block. 9699 9700 RF and IF AGCs DACs are part of AFE, Video and SIF AGC DACs are part of 9701 the ATV block. The AGC control algorithms are all implemented in 9702 microcode. 9703 9704 ATV SETTINGS 9705 9706 (Shadow settings will not be used for now, they will be implemented 9707 later on because of the schedule) 9708 9709 Several HW/SCU "settings" can be used for ATV. The standard selection 9710 will reset most of these settings. To avoid that the end user application 9711 has to perform these settings each time the ATV or FM standards is 9712 selected the driver will shadow these settings. This enables the end user 9713 to perform the settings only once after a drx_open(). The driver must 9714 write the shadow settings to HW/SCU in case: 9715 ( setstandard FM/ATV) || 9716 ( settings have changed && FM/ATV standard is active) 9717 The shadow settings will be stored in the device specific data container. 9718 A set of flags will be defined to flag changes in shadow settings. 9719 A routine will be implemented to write all changed shadow settings to 9720 HW/SCU. 9721 9722 The "settings" will consist of: AGC settings, filter settings etc. 9723 9724 Disadvantage of use of shadow settings: 9725 Direct changes in HW/SCU registers will not be reflected in the 9726 shadow settings and these changes will be overwritten during a next 9727 update. This can happen during evaluation. This will not be a problem 9728 for normal customer usage. 9729 */ 9730 /* -------------------------------------------------------------------------- */ 9731 9732 /* 9733 * \fn int power_down_atv () 9734 * \brief Power down ATV. 9735 * \param demod instance of demodulator 9736 * \param standard either NTSC or FM (sub strandard for ATV ) 9737 * \return int. 9738 * 9739 * Stops and thus resets ATV and IQM block 9740 * SIF and CVBS ADC are powered down 9741 * Calls audio power down 9742 */ 9743 static int 9744 power_down_atv(struct drx_demod_instance *demod, enum drx_standard standard, bool primary) 9745 { 9746 struct i2c_device_addr *dev_addr = demod->my_i2c_dev_addr; 9747 struct drxjscu_cmd cmd_scu = { /* command */ 0, 9748 /* parameter_len */ 0, 9749 /* result_len */ 0, 9750 /* *parameter */ NULL, 9751 /* *result */ NULL 9752 }; 9753 int rc; 9754 u16 cmd_result = 0; 9755 9756 /* ATV NTSC */ 9757 9758 /* Stop ATV SCU (will reset ATV and IQM hardware */ 9759 cmd_scu.command = SCU_RAM_COMMAND_STANDARD_ATV | 9760 SCU_RAM_COMMAND_CMD_DEMOD_STOP; 9761 cmd_scu.parameter_len = 0; 9762 cmd_scu.result_len = 1; 9763 cmd_scu.parameter = NULL; 9764 cmd_scu.result = &cmd_result; 9765 rc = scu_command(dev_addr, &cmd_scu); 9766 if (rc != 0) { 9767 pr_err("error %d\n", rc); 9768 goto rw_error; 9769 } 9770 /* Disable ATV outputs (ATV reset enables CVBS, undo this) */ 9771 rc = drxj_dap_write_reg16(dev_addr, ATV_TOP_STDBY__A, (ATV_TOP_STDBY_SIF_STDBY_STANDBY & (~ATV_TOP_STDBY_CVBS_STDBY_A2_ACTIVE)), 0); 9772 if (rc != 0) { 9773 pr_err("error %d\n", rc); 9774 goto rw_error; 9775 } 9776 9777 rc = drxj_dap_write_reg16(dev_addr, ATV_COMM_EXEC__A, ATV_COMM_EXEC_STOP, 0); 9778 if (rc != 0) { 9779 pr_err("error %d\n", rc); 9780 goto rw_error; 9781 } 9782 if (primary) { 9783 rc = drxj_dap_write_reg16(dev_addr, IQM_COMM_EXEC__A, IQM_COMM_EXEC_STOP, 0); 9784 if (rc != 0) { 9785 pr_err("error %d\n", rc); 9786 goto rw_error; 9787 } 9788 rc = set_iqm_af(demod, false); 9789 if (rc != 0) { 9790 pr_err("error %d\n", rc); 9791 goto rw_error; 9792 } 9793 } else { 9794 rc = drxj_dap_write_reg16(dev_addr, IQM_FS_COMM_EXEC__A, IQM_FS_COMM_EXEC_STOP, 0); 9795 if (rc != 0) { 9796 pr_err("error %d\n", rc); 9797 goto rw_error; 9798 } 9799 rc = drxj_dap_write_reg16(dev_addr, IQM_FD_COMM_EXEC__A, IQM_FD_COMM_EXEC_STOP, 0); 9800 if (rc != 0) { 9801 pr_err("error %d\n", rc); 9802 goto rw_error; 9803 } 9804 rc = drxj_dap_write_reg16(dev_addr, IQM_RC_COMM_EXEC__A, IQM_RC_COMM_EXEC_STOP, 0); 9805 if (rc != 0) { 9806 pr_err("error %d\n", rc); 9807 goto rw_error; 9808 } 9809 rc = drxj_dap_write_reg16(dev_addr, IQM_RT_COMM_EXEC__A, IQM_RT_COMM_EXEC_STOP, 0); 9810 if (rc != 0) { 9811 pr_err("error %d\n", rc); 9812 goto rw_error; 9813 } 9814 rc = drxj_dap_write_reg16(dev_addr, IQM_CF_COMM_EXEC__A, IQM_CF_COMM_EXEC_STOP, 0); 9815 if (rc != 0) { 9816 pr_err("error %d\n", rc); 9817 goto rw_error; 9818 } 9819 } 9820 rc = power_down_aud(demod); 9821 if (rc != 0) { 9822 pr_err("error %d\n", rc); 9823 goto rw_error; 9824 } 9825 9826 return 0; 9827 rw_error: 9828 return rc; 9829 } 9830 9831 /*============================================================================*/ 9832 9833 /* 9834 * \brief Power up AUD. 9835 * \param demod instance of demodulator 9836 * \return int. 9837 * 9838 */ 9839 static int power_down_aud(struct drx_demod_instance *demod) 9840 { 9841 struct i2c_device_addr *dev_addr = NULL; 9842 struct drxj_data *ext_attr = NULL; 9843 int rc; 9844 9845 dev_addr = (struct i2c_device_addr *)demod->my_i2c_dev_addr; 9846 ext_attr = (struct drxj_data *) demod->my_ext_attr; 9847 9848 rc = drxj_dap_write_reg16(dev_addr, AUD_COMM_EXEC__A, AUD_COMM_EXEC_STOP, 0); 9849 if (rc != 0) { 9850 pr_err("error %d\n", rc); 9851 goto rw_error; 9852 } 9853 9854 ext_attr->aud_data.audio_is_active = false; 9855 9856 return 0; 9857 rw_error: 9858 return rc; 9859 } 9860 9861 /* 9862 * \fn int set_orx_nsu_aox() 9863 * \brief Configure OrxNsuAox for OOB 9864 * \param demod instance of demodulator. 9865 * \param active 9866 * \return int. 9867 */ 9868 static int set_orx_nsu_aox(struct drx_demod_instance *demod, bool active) 9869 { 9870 struct i2c_device_addr *dev_addr = demod->my_i2c_dev_addr; 9871 int rc; 9872 u16 data = 0; 9873 9874 /* Configure NSU_AOX */ 9875 rc = drxj_dap_read_reg16(dev_addr, ORX_NSU_AOX_STDBY_W__A, &data, 0); 9876 if (rc != 0) { 9877 pr_err("error %d\n", rc); 9878 goto rw_error; 9879 } 9880 if (!active) 9881 data &= ((~ORX_NSU_AOX_STDBY_W_STDBYADC_A2_ON) & (~ORX_NSU_AOX_STDBY_W_STDBYAMP_A2_ON) & (~ORX_NSU_AOX_STDBY_W_STDBYBIAS_A2_ON) & (~ORX_NSU_AOX_STDBY_W_STDBYPLL_A2_ON) & (~ORX_NSU_AOX_STDBY_W_STDBYPD_A2_ON) & (~ORX_NSU_AOX_STDBY_W_STDBYTAGC_IF_A2_ON) & (~ORX_NSU_AOX_STDBY_W_STDBYTAGC_RF_A2_ON) & (~ORX_NSU_AOX_STDBY_W_STDBYFLT_A2_ON)); 9882 else 9883 data |= (ORX_NSU_AOX_STDBY_W_STDBYADC_A2_ON | ORX_NSU_AOX_STDBY_W_STDBYAMP_A2_ON | ORX_NSU_AOX_STDBY_W_STDBYBIAS_A2_ON | ORX_NSU_AOX_STDBY_W_STDBYPLL_A2_ON | ORX_NSU_AOX_STDBY_W_STDBYPD_A2_ON | ORX_NSU_AOX_STDBY_W_STDBYTAGC_IF_A2_ON | ORX_NSU_AOX_STDBY_W_STDBYTAGC_RF_A2_ON | ORX_NSU_AOX_STDBY_W_STDBYFLT_A2_ON); 9884 rc = drxj_dap_write_reg16(dev_addr, ORX_NSU_AOX_STDBY_W__A, data, 0); 9885 if (rc != 0) { 9886 pr_err("error %d\n", rc); 9887 goto rw_error; 9888 } 9889 9890 return 0; 9891 rw_error: 9892 return rc; 9893 } 9894 9895 /* 9896 * \fn int ctrl_set_oob() 9897 * \brief Set OOB channel to be used. 9898 * \param demod instance of demodulator 9899 * \param oob_param OOB parameters for channel setting. 9900 * \frequency should be in KHz 9901 * \return int. 9902 * 9903 * Accepts only. Returns error otherwise. 9904 * Demapper value is written after scu_command START 9905 * because START command causes COMM_EXEC transition 9906 * from 0 to 1 which causes all registers to be 9907 * overwritten with initial value 9908 * 9909 */ 9910 9911 /* Nyquist filter impulse response */ 9912 #define IMPULSE_COSINE_ALPHA_0_3 {-3, -4, -1, 6, 10, 7, -5, -20, -25, -10, 29, 79, 123, 140} /*sqrt raised-cosine filter with alpha=0.3 */ 9913 #define IMPULSE_COSINE_ALPHA_0_5 { 2, 0, -2, -2, 2, 5, 2, -10, -20, -14, 20, 74, 125, 145} /*sqrt raised-cosine filter with alpha=0.5 */ 9914 #define IMPULSE_COSINE_ALPHA_RO_0_5 { 0, 0, 1, 2, 3, 0, -7, -15, -16, 0, 34, 77, 114, 128} /*full raised-cosine filter with alpha=0.5 (receiver only) */ 9915 9916 /* Coefficients for the nyquist filter (total: 27 taps) */ 9917 #define NYQFILTERLEN 27 9918 9919 static int ctrl_set_oob(struct drx_demod_instance *demod, struct drxoob *oob_param) 9920 { 9921 int rc; 9922 s32 freq = 0; /* KHz */ 9923 struct i2c_device_addr *dev_addr = NULL; 9924 struct drxj_data *ext_attr = NULL; 9925 u16 i = 0; 9926 bool mirror_freq_spect_oob = false; 9927 u16 trk_filter_value = 0; 9928 struct drxjscu_cmd scu_cmd; 9929 u16 set_param_parameters[3]; 9930 u16 cmd_result[2] = { 0, 0 }; 9931 s16 nyquist_coeffs[4][(NYQFILTERLEN + 1) / 2] = { 9932 IMPULSE_COSINE_ALPHA_0_3, /* Target Mode 0 */ 9933 IMPULSE_COSINE_ALPHA_0_3, /* Target Mode 1 */ 9934 IMPULSE_COSINE_ALPHA_0_5, /* Target Mode 2 */ 9935 IMPULSE_COSINE_ALPHA_RO_0_5 /* Target Mode 3 */ 9936 }; 9937 u8 mode_val[4] = { 2, 2, 0, 1 }; 9938 u8 pfi_coeffs[4][6] = { 9939 {DRXJ_16TO8(-92), DRXJ_16TO8(-108), DRXJ_16TO8(100)}, /* TARGET_MODE = 0: PFI_A = -23/32; PFI_B = -54/32; PFI_C = 25/32; fg = 0.5 MHz (Att=26dB) */ 9940 {DRXJ_16TO8(-64), DRXJ_16TO8(-80), DRXJ_16TO8(80)}, /* TARGET_MODE = 1: PFI_A = -16/32; PFI_B = -40/32; PFI_C = 20/32; fg = 1.0 MHz (Att=28dB) */ 9941 {DRXJ_16TO8(-80), DRXJ_16TO8(-98), DRXJ_16TO8(92)}, /* TARGET_MODE = 2, 3: PFI_A = -20/32; PFI_B = -49/32; PFI_C = 23/32; fg = 0.8 MHz (Att=25dB) */ 9942 {DRXJ_16TO8(-80), DRXJ_16TO8(-98), DRXJ_16TO8(92)} /* TARGET_MODE = 2, 3: PFI_A = -20/32; PFI_B = -49/32; PFI_C = 23/32; fg = 0.8 MHz (Att=25dB) */ 9943 }; 9944 u16 mode_index; 9945 9946 dev_addr = demod->my_i2c_dev_addr; 9947 ext_attr = (struct drxj_data *) demod->my_ext_attr; 9948 mirror_freq_spect_oob = ext_attr->mirror_freq_spect_oob; 9949 9950 /* Check parameters */ 9951 if (oob_param == NULL) { 9952 /* power off oob module */ 9953 scu_cmd.command = SCU_RAM_COMMAND_STANDARD_OOB 9954 | SCU_RAM_COMMAND_CMD_DEMOD_STOP; 9955 scu_cmd.parameter_len = 0; 9956 scu_cmd.result_len = 1; 9957 scu_cmd.result = cmd_result; 9958 rc = scu_command(dev_addr, &scu_cmd); 9959 if (rc != 0) { 9960 pr_err("error %d\n", rc); 9961 goto rw_error; 9962 } 9963 rc = set_orx_nsu_aox(demod, false); 9964 if (rc != 0) { 9965 pr_err("error %d\n", rc); 9966 goto rw_error; 9967 } 9968 rc = drxj_dap_write_reg16(dev_addr, ORX_COMM_EXEC__A, ORX_COMM_EXEC_STOP, 0); 9969 if (rc != 0) { 9970 pr_err("error %d\n", rc); 9971 goto rw_error; 9972 } 9973 9974 ext_attr->oob_power_on = false; 9975 return 0; 9976 } 9977 9978 freq = oob_param->frequency; 9979 if ((freq < 70000) || (freq > 130000)) 9980 return -EIO; 9981 freq = (freq - 50000) / 50; 9982 9983 { 9984 u16 index = 0; 9985 u16 remainder = 0; 9986 u16 *trk_filtercfg = ext_attr->oob_trk_filter_cfg; 9987 9988 index = (u16) ((freq - 400) / 200); 9989 remainder = (u16) ((freq - 400) % 200); 9990 trk_filter_value = 9991 trk_filtercfg[index] - (trk_filtercfg[index] - 9992 trk_filtercfg[index + 9993 1]) / 10 * remainder / 9994 20; 9995 } 9996 9997 /********/ 9998 /* Stop */ 9999 /********/ 10000 rc = drxj_dap_write_reg16(dev_addr, ORX_COMM_EXEC__A, ORX_COMM_EXEC_STOP, 0); 10001 if (rc != 0) { 10002 pr_err("error %d\n", rc); 10003 goto rw_error; 10004 } 10005 scu_cmd.command = SCU_RAM_COMMAND_STANDARD_OOB 10006 | SCU_RAM_COMMAND_CMD_DEMOD_STOP; 10007 scu_cmd.parameter_len = 0; 10008 scu_cmd.result_len = 1; 10009 scu_cmd.result = cmd_result; 10010 rc = scu_command(dev_addr, &scu_cmd); 10011 if (rc != 0) { 10012 pr_err("error %d\n", rc); 10013 goto rw_error; 10014 } 10015 /********/ 10016 /* Reset */ 10017 /********/ 10018 scu_cmd.command = SCU_RAM_COMMAND_STANDARD_OOB 10019 | SCU_RAM_COMMAND_CMD_DEMOD_RESET; 10020 scu_cmd.parameter_len = 0; 10021 scu_cmd.result_len = 1; 10022 scu_cmd.result = cmd_result; 10023 rc = scu_command(dev_addr, &scu_cmd); 10024 if (rc != 0) { 10025 pr_err("error %d\n", rc); 10026 goto rw_error; 10027 } 10028 /**********/ 10029 /* SET_ENV */ 10030 /**********/ 10031 /* set frequency, spectrum inversion and data rate */ 10032 scu_cmd.command = SCU_RAM_COMMAND_STANDARD_OOB 10033 | SCU_RAM_COMMAND_CMD_DEMOD_SET_ENV; 10034 scu_cmd.parameter_len = 3; 10035 /* 1-data rate;2-frequency */ 10036 switch (oob_param->standard) { 10037 case DRX_OOB_MODE_A: 10038 if ( 10039 /* signal is transmitted inverted */ 10040 ((oob_param->spectrum_inverted == true) && 10041 /* and tuner is not mirroring the signal */ 10042 (!mirror_freq_spect_oob)) | 10043 /* or */ 10044 /* signal is transmitted noninverted */ 10045 ((oob_param->spectrum_inverted == false) && 10046 /* and tuner is mirroring the signal */ 10047 (mirror_freq_spect_oob)) 10048 ) 10049 set_param_parameters[0] = 10050 SCU_RAM_ORX_RF_RX_DATA_RATE_2048KBPS_INVSPEC; 10051 else 10052 set_param_parameters[0] = 10053 SCU_RAM_ORX_RF_RX_DATA_RATE_2048KBPS_REGSPEC; 10054 break; 10055 case DRX_OOB_MODE_B_GRADE_A: 10056 if ( 10057 /* signal is transmitted inverted */ 10058 ((oob_param->spectrum_inverted == true) && 10059 /* and tuner is not mirroring the signal */ 10060 (!mirror_freq_spect_oob)) | 10061 /* or */ 10062 /* signal is transmitted noninverted */ 10063 ((oob_param->spectrum_inverted == false) && 10064 /* and tuner is mirroring the signal */ 10065 (mirror_freq_spect_oob)) 10066 ) 10067 set_param_parameters[0] = 10068 SCU_RAM_ORX_RF_RX_DATA_RATE_1544KBPS_INVSPEC; 10069 else 10070 set_param_parameters[0] = 10071 SCU_RAM_ORX_RF_RX_DATA_RATE_1544KBPS_REGSPEC; 10072 break; 10073 case DRX_OOB_MODE_B_GRADE_B: 10074 default: 10075 if ( 10076 /* signal is transmitted inverted */ 10077 ((oob_param->spectrum_inverted == true) && 10078 /* and tuner is not mirroring the signal */ 10079 (!mirror_freq_spect_oob)) | 10080 /* or */ 10081 /* signal is transmitted noninverted */ 10082 ((oob_param->spectrum_inverted == false) && 10083 /* and tuner is mirroring the signal */ 10084 (mirror_freq_spect_oob)) 10085 ) 10086 set_param_parameters[0] = 10087 SCU_RAM_ORX_RF_RX_DATA_RATE_3088KBPS_INVSPEC; 10088 else 10089 set_param_parameters[0] = 10090 SCU_RAM_ORX_RF_RX_DATA_RATE_3088KBPS_REGSPEC; 10091 break; 10092 } 10093 set_param_parameters[1] = (u16) (freq & 0xFFFF); 10094 set_param_parameters[2] = trk_filter_value; 10095 scu_cmd.parameter = set_param_parameters; 10096 scu_cmd.result_len = 1; 10097 scu_cmd.result = cmd_result; 10098 mode_index = mode_val[(set_param_parameters[0] & 0xC0) >> 6]; 10099 rc = scu_command(dev_addr, &scu_cmd); 10100 if (rc != 0) { 10101 pr_err("error %d\n", rc); 10102 goto rw_error; 10103 } 10104 10105 rc = drxj_dap_write_reg16(dev_addr, SIO_TOP_COMM_KEY__A, 0xFABA, 0); 10106 if (rc != 0) { 10107 pr_err("error %d\n", rc); 10108 goto rw_error; 10109 } /* Write magic word to enable pdr reg write */ 10110 rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_OOB_CRX_CFG__A, OOB_CRX_DRIVE_STRENGTH << SIO_PDR_OOB_CRX_CFG_DRIVE__B | 0x03 << SIO_PDR_OOB_CRX_CFG_MODE__B, 0); 10111 if (rc != 0) { 10112 pr_err("error %d\n", rc); 10113 goto rw_error; 10114 } 10115 rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_OOB_DRX_CFG__A, OOB_DRX_DRIVE_STRENGTH << SIO_PDR_OOB_DRX_CFG_DRIVE__B | 0x03 << SIO_PDR_OOB_DRX_CFG_MODE__B, 0); 10116 if (rc != 0) { 10117 pr_err("error %d\n", rc); 10118 goto rw_error; 10119 } 10120 rc = drxj_dap_write_reg16(dev_addr, SIO_TOP_COMM_KEY__A, 0x0000, 0); 10121 if (rc != 0) { 10122 pr_err("error %d\n", rc); 10123 goto rw_error; 10124 } /* Write magic word to disable pdr reg write */ 10125 10126 rc = drxj_dap_write_reg16(dev_addr, ORX_TOP_COMM_KEY__A, 0, 0); 10127 if (rc != 0) { 10128 pr_err("error %d\n", rc); 10129 goto rw_error; 10130 } 10131 rc = drxj_dap_write_reg16(dev_addr, ORX_FWP_AAG_LEN_W__A, 16000, 0); 10132 if (rc != 0) { 10133 pr_err("error %d\n", rc); 10134 goto rw_error; 10135 } 10136 rc = drxj_dap_write_reg16(dev_addr, ORX_FWP_AAG_THR_W__A, 40, 0); 10137 if (rc != 0) { 10138 pr_err("error %d\n", rc); 10139 goto rw_error; 10140 } 10141 10142 /* ddc */ 10143 rc = drxj_dap_write_reg16(dev_addr, ORX_DDC_OFO_SET_W__A, ORX_DDC_OFO_SET_W__PRE, 0); 10144 if (rc != 0) { 10145 pr_err("error %d\n", rc); 10146 goto rw_error; 10147 } 10148 10149 /* nsu */ 10150 rc = drxj_dap_write_reg16(dev_addr, ORX_NSU_AOX_LOPOW_W__A, ext_attr->oob_lo_pow, 0); 10151 if (rc != 0) { 10152 pr_err("error %d\n", rc); 10153 goto rw_error; 10154 } 10155 10156 /* initialization for target mode */ 10157 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_TARGET_MODE__A, SCU_RAM_ORX_TARGET_MODE_2048KBPS_SQRT, 0); 10158 if (rc != 0) { 10159 pr_err("error %d\n", rc); 10160 goto rw_error; 10161 } 10162 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_FREQ_GAIN_CORR__A, SCU_RAM_ORX_FREQ_GAIN_CORR_2048KBPS, 0); 10163 if (rc != 0) { 10164 pr_err("error %d\n", rc); 10165 goto rw_error; 10166 } 10167 10168 /* Reset bits for timing and freq. recovery */ 10169 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_RST_CPH__A, 0x0001, 0); 10170 if (rc != 0) { 10171 pr_err("error %d\n", rc); 10172 goto rw_error; 10173 } 10174 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_RST_CTI__A, 0x0002, 0); 10175 if (rc != 0) { 10176 pr_err("error %d\n", rc); 10177 goto rw_error; 10178 } 10179 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_RST_KRN__A, 0x0004, 0); 10180 if (rc != 0) { 10181 pr_err("error %d\n", rc); 10182 goto rw_error; 10183 } 10184 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_RST_KRP__A, 0x0008, 0); 10185 if (rc != 0) { 10186 pr_err("error %d\n", rc); 10187 goto rw_error; 10188 } 10189 10190 /* AGN_LOCK = {2048>>3, -2048, 8, -8, 0, 1}; */ 10191 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_AGN_LOCK_TH__A, 2048 >> 3, 0); 10192 if (rc != 0) { 10193 pr_err("error %d\n", rc); 10194 goto rw_error; 10195 } 10196 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_AGN_LOCK_TOTH__A, (u16)(-2048), 0); 10197 if (rc != 0) { 10198 pr_err("error %d\n", rc); 10199 goto rw_error; 10200 } 10201 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_AGN_ONLOCK_TTH__A, 8, 0); 10202 if (rc != 0) { 10203 pr_err("error %d\n", rc); 10204 goto rw_error; 10205 } 10206 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_AGN_UNLOCK_TTH__A, (u16)(-8), 0); 10207 if (rc != 0) { 10208 pr_err("error %d\n", rc); 10209 goto rw_error; 10210 } 10211 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_AGN_LOCK_MASK__A, 1, 0); 10212 if (rc != 0) { 10213 pr_err("error %d\n", rc); 10214 goto rw_error; 10215 } 10216 10217 /* DGN_LOCK = {10, -2048, 8, -8, 0, 1<<1}; */ 10218 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_DGN_LOCK_TH__A, 10, 0); 10219 if (rc != 0) { 10220 pr_err("error %d\n", rc); 10221 goto rw_error; 10222 } 10223 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_DGN_LOCK_TOTH__A, (u16)(-2048), 0); 10224 if (rc != 0) { 10225 pr_err("error %d\n", rc); 10226 goto rw_error; 10227 } 10228 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_DGN_ONLOCK_TTH__A, 8, 0); 10229 if (rc != 0) { 10230 pr_err("error %d\n", rc); 10231 goto rw_error; 10232 } 10233 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_DGN_UNLOCK_TTH__A, (u16)(-8), 0); 10234 if (rc != 0) { 10235 pr_err("error %d\n", rc); 10236 goto rw_error; 10237 } 10238 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_DGN_LOCK_MASK__A, 1 << 1, 0); 10239 if (rc != 0) { 10240 pr_err("error %d\n", rc); 10241 goto rw_error; 10242 } 10243 10244 /* FRQ_LOCK = {15,-2048, 8, -8, 0, 1<<2}; */ 10245 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_FRQ_LOCK_TH__A, 17, 0); 10246 if (rc != 0) { 10247 pr_err("error %d\n", rc); 10248 goto rw_error; 10249 } 10250 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_FRQ_LOCK_TOTH__A, (u16)(-2048), 0); 10251 if (rc != 0) { 10252 pr_err("error %d\n", rc); 10253 goto rw_error; 10254 } 10255 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_FRQ_ONLOCK_TTH__A, 8, 0); 10256 if (rc != 0) { 10257 pr_err("error %d\n", rc); 10258 goto rw_error; 10259 } 10260 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_FRQ_UNLOCK_TTH__A, (u16)(-8), 0); 10261 if (rc != 0) { 10262 pr_err("error %d\n", rc); 10263 goto rw_error; 10264 } 10265 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_FRQ_LOCK_MASK__A, 1 << 2, 0); 10266 if (rc != 0) { 10267 pr_err("error %d\n", rc); 10268 goto rw_error; 10269 } 10270 10271 /* PHA_LOCK = {5000, -2048, 8, -8, 0, 1<<3}; */ 10272 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_PHA_LOCK_TH__A, 3000, 0); 10273 if (rc != 0) { 10274 pr_err("error %d\n", rc); 10275 goto rw_error; 10276 } 10277 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_PHA_LOCK_TOTH__A, (u16)(-2048), 0); 10278 if (rc != 0) { 10279 pr_err("error %d\n", rc); 10280 goto rw_error; 10281 } 10282 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_PHA_ONLOCK_TTH__A, 8, 0); 10283 if (rc != 0) { 10284 pr_err("error %d\n", rc); 10285 goto rw_error; 10286 } 10287 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_PHA_UNLOCK_TTH__A, (u16)(-8), 0); 10288 if (rc != 0) { 10289 pr_err("error %d\n", rc); 10290 goto rw_error; 10291 } 10292 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_PHA_LOCK_MASK__A, 1 << 3, 0); 10293 if (rc != 0) { 10294 pr_err("error %d\n", rc); 10295 goto rw_error; 10296 } 10297 10298 /* TIM_LOCK = {300, -2048, 8, -8, 0, 1<<4}; */ 10299 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_TIM_LOCK_TH__A, 400, 0); 10300 if (rc != 0) { 10301 pr_err("error %d\n", rc); 10302 goto rw_error; 10303 } 10304 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_TIM_LOCK_TOTH__A, (u16)(-2048), 0); 10305 if (rc != 0) { 10306 pr_err("error %d\n", rc); 10307 goto rw_error; 10308 } 10309 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_TIM_ONLOCK_TTH__A, 8, 0); 10310 if (rc != 0) { 10311 pr_err("error %d\n", rc); 10312 goto rw_error; 10313 } 10314 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_TIM_UNLOCK_TTH__A, (u16)(-8), 0); 10315 if (rc != 0) { 10316 pr_err("error %d\n", rc); 10317 goto rw_error; 10318 } 10319 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_TIM_LOCK_MASK__A, 1 << 4, 0); 10320 if (rc != 0) { 10321 pr_err("error %d\n", rc); 10322 goto rw_error; 10323 } 10324 10325 /* EQU_LOCK = {20, -2048, 8, -8, 0, 1<<5}; */ 10326 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_EQU_LOCK_TH__A, 20, 0); 10327 if (rc != 0) { 10328 pr_err("error %d\n", rc); 10329 goto rw_error; 10330 } 10331 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_EQU_LOCK_TOTH__A, (u16)(-2048), 0); 10332 if (rc != 0) { 10333 pr_err("error %d\n", rc); 10334 goto rw_error; 10335 } 10336 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_EQU_ONLOCK_TTH__A, 4, 0); 10337 if (rc != 0) { 10338 pr_err("error %d\n", rc); 10339 goto rw_error; 10340 } 10341 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_EQU_UNLOCK_TTH__A, (u16)(-4), 0); 10342 if (rc != 0) { 10343 pr_err("error %d\n", rc); 10344 goto rw_error; 10345 } 10346 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_EQU_LOCK_MASK__A, 1 << 5, 0); 10347 if (rc != 0) { 10348 pr_err("error %d\n", rc); 10349 goto rw_error; 10350 } 10351 10352 /* PRE-Filter coefficients (PFI) */ 10353 rc = drxdap_fasi_write_block(dev_addr, ORX_FWP_PFI_A_W__A, sizeof(pfi_coeffs[mode_index]), ((u8 *)pfi_coeffs[mode_index]), 0); 10354 if (rc != 0) { 10355 pr_err("error %d\n", rc); 10356 goto rw_error; 10357 } 10358 rc = drxj_dap_write_reg16(dev_addr, ORX_TOP_MDE_W__A, mode_index, 0); 10359 if (rc != 0) { 10360 pr_err("error %d\n", rc); 10361 goto rw_error; 10362 } 10363 10364 /* NYQUIST-Filter coefficients (NYQ) */ 10365 for (i = 0; i < (NYQFILTERLEN + 1) / 2; i++) { 10366 rc = drxj_dap_write_reg16(dev_addr, ORX_FWP_NYQ_ADR_W__A, i, 0); 10367 if (rc != 0) { 10368 pr_err("error %d\n", rc); 10369 goto rw_error; 10370 } 10371 rc = drxj_dap_write_reg16(dev_addr, ORX_FWP_NYQ_COF_RW__A, nyquist_coeffs[mode_index][i], 0); 10372 if (rc != 0) { 10373 pr_err("error %d\n", rc); 10374 goto rw_error; 10375 } 10376 } 10377 rc = drxj_dap_write_reg16(dev_addr, ORX_FWP_NYQ_ADR_W__A, 31, 0); 10378 if (rc != 0) { 10379 pr_err("error %d\n", rc); 10380 goto rw_error; 10381 } 10382 rc = drxj_dap_write_reg16(dev_addr, ORX_COMM_EXEC__A, ORX_COMM_EXEC_ACTIVE, 0); 10383 if (rc != 0) { 10384 pr_err("error %d\n", rc); 10385 goto rw_error; 10386 } 10387 /********/ 10388 /* Start */ 10389 /********/ 10390 scu_cmd.command = SCU_RAM_COMMAND_STANDARD_OOB 10391 | SCU_RAM_COMMAND_CMD_DEMOD_START; 10392 scu_cmd.parameter_len = 0; 10393 scu_cmd.result_len = 1; 10394 scu_cmd.result = cmd_result; 10395 rc = scu_command(dev_addr, &scu_cmd); 10396 if (rc != 0) { 10397 pr_err("error %d\n", rc); 10398 goto rw_error; 10399 } 10400 10401 rc = set_orx_nsu_aox(demod, true); 10402 if (rc != 0) { 10403 pr_err("error %d\n", rc); 10404 goto rw_error; 10405 } 10406 rc = drxj_dap_write_reg16(dev_addr, ORX_NSU_AOX_STHR_W__A, ext_attr->oob_pre_saw, 0); 10407 if (rc != 0) { 10408 pr_err("error %d\n", rc); 10409 goto rw_error; 10410 } 10411 10412 ext_attr->oob_power_on = true; 10413 10414 return 0; 10415 rw_error: 10416 return rc; 10417 } 10418 10419 /*============================================================================*/ 10420 /*== END OOB DATAPATH FUNCTIONS ==*/ 10421 /*============================================================================*/ 10422 10423 /*============================================================================= 10424 ===== MC command related functions ========================================== 10425 ===========================================================================*/ 10426 10427 /*============================================================================= 10428 ===== ctrl_set_channel() ========================================================== 10429 ===========================================================================*/ 10430 /* 10431 * \fn int ctrl_set_channel() 10432 * \brief Select a new transmission channel. 10433 * \param demod instance of demod. 10434 * \param channel Pointer to channel data. 10435 * \return int. 10436 * 10437 * In case the tuner module is not used and in case of NTSC/FM the pogrammer 10438 * must tune the tuner to the centre frequency of the NTSC/FM channel. 10439 * 10440 */ 10441 static int 10442 ctrl_set_channel(struct drx_demod_instance *demod, struct drx_channel *channel) 10443 { 10444 int rc; 10445 s32 tuner_freq_offset = 0; 10446 struct drxj_data *ext_attr = NULL; 10447 struct i2c_device_addr *dev_addr = NULL; 10448 enum drx_standard standard = DRX_STANDARD_UNKNOWN; 10449 #ifndef DRXJ_VSB_ONLY 10450 u32 min_symbol_rate = 0; 10451 u32 max_symbol_rate = 0; 10452 int bandwidth_temp = 0; 10453 int bandwidth = 0; 10454 #endif 10455 /*== check arguments ======================================================*/ 10456 if ((demod == NULL) || (channel == NULL)) 10457 return -EINVAL; 10458 10459 dev_addr = demod->my_i2c_dev_addr; 10460 ext_attr = (struct drxj_data *) demod->my_ext_attr; 10461 standard = ext_attr->standard; 10462 10463 /* check valid standards */ 10464 switch (standard) { 10465 case DRX_STANDARD_8VSB: 10466 #ifndef DRXJ_VSB_ONLY 10467 case DRX_STANDARD_ITU_A: 10468 case DRX_STANDARD_ITU_B: 10469 case DRX_STANDARD_ITU_C: 10470 #endif /* DRXJ_VSB_ONLY */ 10471 break; 10472 case DRX_STANDARD_UNKNOWN: 10473 default: 10474 return -EINVAL; 10475 } 10476 10477 /* check bandwidth QAM annex B, NTSC and 8VSB */ 10478 if ((standard == DRX_STANDARD_ITU_B) || 10479 (standard == DRX_STANDARD_8VSB) || 10480 (standard == DRX_STANDARD_NTSC)) { 10481 switch (channel->bandwidth) { 10482 case DRX_BANDWIDTH_6MHZ: 10483 case DRX_BANDWIDTH_UNKNOWN: 10484 channel->bandwidth = DRX_BANDWIDTH_6MHZ; 10485 break; 10486 case DRX_BANDWIDTH_8MHZ: 10487 case DRX_BANDWIDTH_7MHZ: 10488 default: 10489 return -EINVAL; 10490 } 10491 } 10492 10493 /* For QAM annex A and annex C: 10494 -check symbolrate and constellation 10495 -derive bandwidth from symbolrate (input bandwidth is ignored) 10496 */ 10497 #ifndef DRXJ_VSB_ONLY 10498 if ((standard == DRX_STANDARD_ITU_A) || 10499 (standard == DRX_STANDARD_ITU_C)) { 10500 struct drxuio_cfg uio_cfg = { DRX_UIO1, DRX_UIO_MODE_FIRMWARE_SAW }; 10501 int bw_rolloff_factor = 0; 10502 10503 bw_rolloff_factor = (standard == DRX_STANDARD_ITU_A) ? 115 : 113; 10504 min_symbol_rate = DRXJ_QAM_SYMBOLRATE_MIN; 10505 max_symbol_rate = DRXJ_QAM_SYMBOLRATE_MAX; 10506 /* config SMA_TX pin to SAW switch mode */ 10507 rc = ctrl_set_uio_cfg(demod, &uio_cfg); 10508 if (rc != 0) { 10509 pr_err("error %d\n", rc); 10510 goto rw_error; 10511 } 10512 10513 if (channel->symbolrate < min_symbol_rate || 10514 channel->symbolrate > max_symbol_rate) { 10515 return -EINVAL; 10516 } 10517 10518 switch (channel->constellation) { 10519 case DRX_CONSTELLATION_QAM16: 10520 case DRX_CONSTELLATION_QAM32: 10521 case DRX_CONSTELLATION_QAM64: 10522 case DRX_CONSTELLATION_QAM128: 10523 case DRX_CONSTELLATION_QAM256: 10524 bandwidth_temp = channel->symbolrate * bw_rolloff_factor; 10525 bandwidth = bandwidth_temp / 100; 10526 10527 if ((bandwidth_temp % 100) >= 50) 10528 bandwidth++; 10529 10530 if (bandwidth <= 6100000) { 10531 channel->bandwidth = DRX_BANDWIDTH_6MHZ; 10532 } else if ((bandwidth > 6100000) 10533 && (bandwidth <= 7100000)) { 10534 channel->bandwidth = DRX_BANDWIDTH_7MHZ; 10535 } else if (bandwidth > 7100000) { 10536 channel->bandwidth = DRX_BANDWIDTH_8MHZ; 10537 } 10538 break; 10539 default: 10540 return -EINVAL; 10541 } 10542 } 10543 10544 /* For QAM annex B: 10545 -check constellation 10546 */ 10547 if (standard == DRX_STANDARD_ITU_B) { 10548 switch (channel->constellation) { 10549 case DRX_CONSTELLATION_AUTO: 10550 case DRX_CONSTELLATION_QAM256: 10551 case DRX_CONSTELLATION_QAM64: 10552 break; 10553 default: 10554 return -EINVAL; 10555 } 10556 10557 switch (channel->interleavemode) { 10558 case DRX_INTERLEAVEMODE_I128_J1: 10559 case DRX_INTERLEAVEMODE_I128_J1_V2: 10560 case DRX_INTERLEAVEMODE_I128_J2: 10561 case DRX_INTERLEAVEMODE_I64_J2: 10562 case DRX_INTERLEAVEMODE_I128_J3: 10563 case DRX_INTERLEAVEMODE_I32_J4: 10564 case DRX_INTERLEAVEMODE_I128_J4: 10565 case DRX_INTERLEAVEMODE_I16_J8: 10566 case DRX_INTERLEAVEMODE_I128_J5: 10567 case DRX_INTERLEAVEMODE_I8_J16: 10568 case DRX_INTERLEAVEMODE_I128_J6: 10569 case DRX_INTERLEAVEMODE_I128_J7: 10570 case DRX_INTERLEAVEMODE_I128_J8: 10571 case DRX_INTERLEAVEMODE_I12_J17: 10572 case DRX_INTERLEAVEMODE_I5_J4: 10573 case DRX_INTERLEAVEMODE_B52_M240: 10574 case DRX_INTERLEAVEMODE_B52_M720: 10575 case DRX_INTERLEAVEMODE_UNKNOWN: 10576 case DRX_INTERLEAVEMODE_AUTO: 10577 break; 10578 default: 10579 return -EINVAL; 10580 } 10581 } 10582 10583 if ((ext_attr->uio_sma_tx_mode) == DRX_UIO_MODE_FIRMWARE_SAW) { 10584 /* SAW SW, user UIO is used for switchable SAW */ 10585 struct drxuio_data uio1 = { DRX_UIO1, false }; 10586 10587 switch (channel->bandwidth) { 10588 case DRX_BANDWIDTH_8MHZ: 10589 uio1.value = true; 10590 break; 10591 case DRX_BANDWIDTH_7MHZ: 10592 uio1.value = false; 10593 break; 10594 case DRX_BANDWIDTH_6MHZ: 10595 uio1.value = false; 10596 break; 10597 case DRX_BANDWIDTH_UNKNOWN: 10598 default: 10599 return -EINVAL; 10600 } 10601 10602 rc = ctrl_uio_write(demod, &uio1); 10603 if (rc != 0) { 10604 pr_err("error %d\n", rc); 10605 goto rw_error; 10606 } 10607 } 10608 #endif /* DRXJ_VSB_ONLY */ 10609 rc = drxj_dap_write_reg16(dev_addr, SCU_COMM_EXEC__A, SCU_COMM_EXEC_ACTIVE, 0); 10610 if (rc != 0) { 10611 pr_err("error %d\n", rc); 10612 goto rw_error; 10613 } 10614 10615 tuner_freq_offset = 0; 10616 10617 /*== Setup demod for specific standard ====================================*/ 10618 switch (standard) { 10619 case DRX_STANDARD_8VSB: 10620 if (channel->mirror == DRX_MIRROR_AUTO) 10621 ext_attr->mirror = DRX_MIRROR_NO; 10622 else 10623 ext_attr->mirror = channel->mirror; 10624 rc = set_vsb(demod); 10625 if (rc != 0) { 10626 pr_err("error %d\n", rc); 10627 goto rw_error; 10628 } 10629 rc = set_frequency(demod, channel, tuner_freq_offset); 10630 if (rc != 0) { 10631 pr_err("error %d\n", rc); 10632 goto rw_error; 10633 } 10634 break; 10635 #ifndef DRXJ_VSB_ONLY 10636 case DRX_STANDARD_ITU_A: 10637 case DRX_STANDARD_ITU_B: 10638 case DRX_STANDARD_ITU_C: 10639 rc = set_qam_channel(demod, channel, tuner_freq_offset); 10640 if (rc != 0) { 10641 pr_err("error %d\n", rc); 10642 goto rw_error; 10643 } 10644 break; 10645 #endif 10646 case DRX_STANDARD_UNKNOWN: 10647 default: 10648 return -EIO; 10649 } 10650 10651 /* flag the packet error counter reset */ 10652 ext_attr->reset_pkt_err_acc = true; 10653 10654 return 0; 10655 rw_error: 10656 return rc; 10657 } 10658 10659 /*============================================================================= 10660 ===== SigQuality() ========================================================== 10661 ===========================================================================*/ 10662 10663 /* 10664 * \fn int ctrl_sig_quality() 10665 * \brief Retrieve signal quality form device. 10666 * \param devmod Pointer to demodulator instance. 10667 * \param sig_quality Pointer to signal quality data. 10668 * \return int. 10669 * \retval 0 sig_quality contains valid data. 10670 * \retval -EINVAL sig_quality is NULL. 10671 * \retval -EIO Erroneous data, sig_quality contains invalid data. 10672 10673 */ 10674 static int 10675 ctrl_sig_quality(struct drx_demod_instance *demod, 10676 enum drx_lock_status lock_status) 10677 { 10678 struct i2c_device_addr *dev_addr = demod->my_i2c_dev_addr; 10679 struct drxj_data *ext_attr = demod->my_ext_attr; 10680 struct drx39xxj_state *state = dev_addr->user_data; 10681 struct dtv_frontend_properties *p = &state->frontend.dtv_property_cache; 10682 enum drx_standard standard = ext_attr->standard; 10683 int rc; 10684 u32 ber, cnt, err, pkt; 10685 u16 mer, strength = 0; 10686 10687 rc = get_sig_strength(demod, &strength); 10688 if (rc < 0) { 10689 pr_err("error getting signal strength %d\n", rc); 10690 p->strength.stat[0].scale = FE_SCALE_NOT_AVAILABLE; 10691 } else { 10692 p->strength.stat[0].scale = FE_SCALE_RELATIVE; 10693 p->strength.stat[0].uvalue = 65535UL * strength/ 100; 10694 } 10695 10696 switch (standard) { 10697 case DRX_STANDARD_8VSB: 10698 #ifdef DRXJ_SIGNAL_ACCUM_ERR 10699 rc = get_acc_pkt_err(demod, &pkt); 10700 if (rc != 0) { 10701 pr_err("error %d\n", rc); 10702 goto rw_error; 10703 } 10704 #endif 10705 if (lock_status != DRXJ_DEMOD_LOCK && lock_status != DRX_LOCKED) { 10706 p->pre_bit_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE; 10707 p->pre_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE; 10708 p->post_bit_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE; 10709 p->post_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE; 10710 p->block_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE; 10711 p->block_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE; 10712 p->cnr.stat[0].scale = FE_SCALE_NOT_AVAILABLE; 10713 } else { 10714 rc = get_vsb_post_rs_pck_err(dev_addr, &err, &pkt); 10715 if (rc != 0) { 10716 pr_err("error %d getting UCB\n", rc); 10717 p->block_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE; 10718 } else { 10719 p->block_error.stat[0].scale = FE_SCALE_COUNTER; 10720 p->block_error.stat[0].uvalue += err; 10721 p->block_count.stat[0].scale = FE_SCALE_COUNTER; 10722 p->block_count.stat[0].uvalue += pkt; 10723 } 10724 10725 /* PostViterbi is compute in steps of 10^(-6) */ 10726 rc = get_vs_bpre_viterbi_ber(dev_addr, &ber, &cnt); 10727 if (rc != 0) { 10728 pr_err("error %d getting pre-ber\n", rc); 10729 p->pre_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE; 10730 } else { 10731 p->pre_bit_error.stat[0].scale = FE_SCALE_COUNTER; 10732 p->pre_bit_error.stat[0].uvalue += ber; 10733 p->pre_bit_count.stat[0].scale = FE_SCALE_COUNTER; 10734 p->pre_bit_count.stat[0].uvalue += cnt; 10735 } 10736 10737 rc = get_vs_bpost_viterbi_ber(dev_addr, &ber, &cnt); 10738 if (rc != 0) { 10739 pr_err("error %d getting post-ber\n", rc); 10740 p->post_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE; 10741 } else { 10742 p->post_bit_error.stat[0].scale = FE_SCALE_COUNTER; 10743 p->post_bit_error.stat[0].uvalue += ber; 10744 p->post_bit_count.stat[0].scale = FE_SCALE_COUNTER; 10745 p->post_bit_count.stat[0].uvalue += cnt; 10746 } 10747 rc = get_vsbmer(dev_addr, &mer); 10748 if (rc != 0) { 10749 pr_err("error %d getting MER\n", rc); 10750 p->cnr.stat[0].scale = FE_SCALE_NOT_AVAILABLE; 10751 } else { 10752 p->cnr.stat[0].svalue = mer * 100; 10753 p->cnr.stat[0].scale = FE_SCALE_DECIBEL; 10754 } 10755 } 10756 break; 10757 #ifndef DRXJ_VSB_ONLY 10758 case DRX_STANDARD_ITU_A: 10759 case DRX_STANDARD_ITU_B: 10760 case DRX_STANDARD_ITU_C: 10761 rc = ctrl_get_qam_sig_quality(demod); 10762 if (rc != 0) { 10763 pr_err("error %d\n", rc); 10764 goto rw_error; 10765 } 10766 break; 10767 #endif 10768 default: 10769 return -EIO; 10770 } 10771 10772 return 0; 10773 rw_error: 10774 return rc; 10775 } 10776 10777 /*============================================================================*/ 10778 10779 /* 10780 * \fn int ctrl_lock_status() 10781 * \brief Retrieve lock status . 10782 * \param dev_addr Pointer to demodulator device address. 10783 * \param lock_stat Pointer to lock status structure. 10784 * \return int. 10785 * 10786 */ 10787 static int 10788 ctrl_lock_status(struct drx_demod_instance *demod, enum drx_lock_status *lock_stat) 10789 { 10790 enum drx_standard standard = DRX_STANDARD_UNKNOWN; 10791 struct drxj_data *ext_attr = NULL; 10792 struct i2c_device_addr *dev_addr = NULL; 10793 struct drxjscu_cmd cmd_scu = { /* command */ 0, 10794 /* parameter_len */ 0, 10795 /* result_len */ 0, 10796 /* *parameter */ NULL, 10797 /* *result */ NULL 10798 }; 10799 int rc; 10800 u16 cmd_result[2] = { 0, 0 }; 10801 u16 demod_lock = SCU_RAM_PARAM_1_RES_DEMOD_GET_LOCK_DEMOD_LOCKED; 10802 10803 /* check arguments */ 10804 if ((demod == NULL) || (lock_stat == NULL)) 10805 return -EINVAL; 10806 10807 dev_addr = demod->my_i2c_dev_addr; 10808 ext_attr = (struct drxj_data *) demod->my_ext_attr; 10809 standard = ext_attr->standard; 10810 10811 *lock_stat = DRX_NOT_LOCKED; 10812 10813 /* define the SCU command code */ 10814 switch (standard) { 10815 case DRX_STANDARD_8VSB: 10816 cmd_scu.command = SCU_RAM_COMMAND_STANDARD_VSB | 10817 SCU_RAM_COMMAND_CMD_DEMOD_GET_LOCK; 10818 demod_lock |= 0x6; 10819 break; 10820 #ifndef DRXJ_VSB_ONLY 10821 case DRX_STANDARD_ITU_A: 10822 case DRX_STANDARD_ITU_B: 10823 case DRX_STANDARD_ITU_C: 10824 cmd_scu.command = SCU_RAM_COMMAND_STANDARD_QAM | 10825 SCU_RAM_COMMAND_CMD_DEMOD_GET_LOCK; 10826 break; 10827 #endif 10828 case DRX_STANDARD_UNKNOWN: 10829 default: 10830 return -EIO; 10831 } 10832 10833 /* define the SCU command parameters and execute the command */ 10834 cmd_scu.parameter_len = 0; 10835 cmd_scu.result_len = 2; 10836 cmd_scu.parameter = NULL; 10837 cmd_scu.result = cmd_result; 10838 rc = scu_command(dev_addr, &cmd_scu); 10839 if (rc != 0) { 10840 pr_err("error %d\n", rc); 10841 goto rw_error; 10842 } 10843 10844 /* set the lock status */ 10845 if (cmd_scu.result[1] < demod_lock) { 10846 /* 0x0000 NOT LOCKED */ 10847 *lock_stat = DRX_NOT_LOCKED; 10848 } else if (cmd_scu.result[1] < SCU_RAM_PARAM_1_RES_DEMOD_GET_LOCK_LOCKED) { 10849 *lock_stat = DRXJ_DEMOD_LOCK; 10850 } else if (cmd_scu.result[1] < 10851 SCU_RAM_PARAM_1_RES_DEMOD_GET_LOCK_NEVER_LOCK) { 10852 /* 0x8000 DEMOD + FEC LOCKED (system lock) */ 10853 *lock_stat = DRX_LOCKED; 10854 } else { 10855 /* 0xC000 NEVER LOCKED */ 10856 /* (system will never be able to lock to the signal) */ 10857 *lock_stat = DRX_NEVER_LOCK; 10858 } 10859 10860 return 0; 10861 rw_error: 10862 return rc; 10863 } 10864 10865 /*============================================================================*/ 10866 10867 /* 10868 * \fn int ctrl_set_standard() 10869 * \brief Set modulation standard to be used. 10870 * \param standard Modulation standard. 10871 * \return int. 10872 * 10873 * Setup stuff for the desired demodulation standard. 10874 * Disable and power down the previous selected demodulation standard 10875 * 10876 */ 10877 static int 10878 ctrl_set_standard(struct drx_demod_instance *demod, enum drx_standard *standard) 10879 { 10880 struct drxj_data *ext_attr = NULL; 10881 int rc; 10882 enum drx_standard prev_standard; 10883 10884 /* check arguments */ 10885 if ((standard == NULL) || (demod == NULL)) 10886 return -EINVAL; 10887 10888 ext_attr = (struct drxj_data *) demod->my_ext_attr; 10889 prev_standard = ext_attr->standard; 10890 10891 /* 10892 Stop and power down previous standard 10893 */ 10894 switch (prev_standard) { 10895 #ifndef DRXJ_VSB_ONLY 10896 case DRX_STANDARD_ITU_A: 10897 case DRX_STANDARD_ITU_B: 10898 case DRX_STANDARD_ITU_C: 10899 rc = power_down_qam(demod, false); 10900 if (rc != 0) { 10901 pr_err("error %d\n", rc); 10902 goto rw_error; 10903 } 10904 break; 10905 #endif 10906 case DRX_STANDARD_8VSB: 10907 rc = power_down_vsb(demod, false); 10908 if (rc != 0) { 10909 pr_err("error %d\n", rc); 10910 goto rw_error; 10911 } 10912 break; 10913 case DRX_STANDARD_UNKNOWN: 10914 /* Do nothing */ 10915 break; 10916 case DRX_STANDARD_AUTO: 10917 default: 10918 rc = -EINVAL; 10919 goto rw_error; 10920 } 10921 10922 /* 10923 Initialize channel independent registers 10924 Power up new standard 10925 */ 10926 ext_attr->standard = *standard; 10927 10928 switch (*standard) { 10929 #ifndef DRXJ_VSB_ONLY 10930 case DRX_STANDARD_ITU_A: 10931 case DRX_STANDARD_ITU_B: 10932 case DRX_STANDARD_ITU_C: 10933 do { 10934 u16 dummy; 10935 rc = drxj_dap_read_reg16(demod->my_i2c_dev_addr, SCU_RAM_VERSION_HI__A, &dummy, 0); 10936 if (rc != 0) { 10937 pr_err("error %d\n", rc); 10938 goto rw_error; 10939 } 10940 } while (0); 10941 break; 10942 #endif 10943 case DRX_STANDARD_8VSB: 10944 rc = set_vsb_leak_n_gain(demod); 10945 if (rc != 0) { 10946 pr_err("error %d\n", rc); 10947 goto rw_error; 10948 } 10949 break; 10950 default: 10951 ext_attr->standard = DRX_STANDARD_UNKNOWN; 10952 return -EINVAL; 10953 } 10954 10955 return 0; 10956 rw_error: 10957 /* Don't know what the standard is now ... try again */ 10958 ext_attr->standard = DRX_STANDARD_UNKNOWN; 10959 return rc; 10960 } 10961 10962 /*============================================================================*/ 10963 10964 static void drxj_reset_mode(struct drxj_data *ext_attr) 10965 { 10966 /* Initialize default AFE configuration for QAM */ 10967 if (ext_attr->has_lna) { 10968 /* IF AGC off, PGA active */ 10969 #ifndef DRXJ_VSB_ONLY 10970 ext_attr->qam_if_agc_cfg.standard = DRX_STANDARD_ITU_B; 10971 ext_attr->qam_if_agc_cfg.ctrl_mode = DRX_AGC_CTRL_OFF; 10972 ext_attr->qam_pga_cfg = 140 + (11 * 13); 10973 #endif 10974 ext_attr->vsb_if_agc_cfg.standard = DRX_STANDARD_8VSB; 10975 ext_attr->vsb_if_agc_cfg.ctrl_mode = DRX_AGC_CTRL_OFF; 10976 ext_attr->vsb_pga_cfg = 140 + (11 * 13); 10977 } else { 10978 /* IF AGC on, PGA not active */ 10979 #ifndef DRXJ_VSB_ONLY 10980 ext_attr->qam_if_agc_cfg.standard = DRX_STANDARD_ITU_B; 10981 ext_attr->qam_if_agc_cfg.ctrl_mode = DRX_AGC_CTRL_AUTO; 10982 ext_attr->qam_if_agc_cfg.min_output_level = 0; 10983 ext_attr->qam_if_agc_cfg.max_output_level = 0x7FFF; 10984 ext_attr->qam_if_agc_cfg.speed = 3; 10985 ext_attr->qam_if_agc_cfg.top = 1297; 10986 ext_attr->qam_pga_cfg = 140; 10987 #endif 10988 ext_attr->vsb_if_agc_cfg.standard = DRX_STANDARD_8VSB; 10989 ext_attr->vsb_if_agc_cfg.ctrl_mode = DRX_AGC_CTRL_AUTO; 10990 ext_attr->vsb_if_agc_cfg.min_output_level = 0; 10991 ext_attr->vsb_if_agc_cfg.max_output_level = 0x7FFF; 10992 ext_attr->vsb_if_agc_cfg.speed = 3; 10993 ext_attr->vsb_if_agc_cfg.top = 1024; 10994 ext_attr->vsb_pga_cfg = 140; 10995 } 10996 /* TODO: remove min_output_level and max_output_level for both QAM and VSB after */ 10997 /* mc has not used them */ 10998 #ifndef DRXJ_VSB_ONLY 10999 ext_attr->qam_rf_agc_cfg.standard = DRX_STANDARD_ITU_B; 11000 ext_attr->qam_rf_agc_cfg.ctrl_mode = DRX_AGC_CTRL_AUTO; 11001 ext_attr->qam_rf_agc_cfg.min_output_level = 0; 11002 ext_attr->qam_rf_agc_cfg.max_output_level = 0x7FFF; 11003 ext_attr->qam_rf_agc_cfg.speed = 3; 11004 ext_attr->qam_rf_agc_cfg.top = 9500; 11005 ext_attr->qam_rf_agc_cfg.cut_off_current = 4000; 11006 ext_attr->qam_pre_saw_cfg.standard = DRX_STANDARD_ITU_B; 11007 ext_attr->qam_pre_saw_cfg.reference = 0x07; 11008 ext_attr->qam_pre_saw_cfg.use_pre_saw = true; 11009 #endif 11010 /* Initialize default AFE configuration for VSB */ 11011 ext_attr->vsb_rf_agc_cfg.standard = DRX_STANDARD_8VSB; 11012 ext_attr->vsb_rf_agc_cfg.ctrl_mode = DRX_AGC_CTRL_AUTO; 11013 ext_attr->vsb_rf_agc_cfg.min_output_level = 0; 11014 ext_attr->vsb_rf_agc_cfg.max_output_level = 0x7FFF; 11015 ext_attr->vsb_rf_agc_cfg.speed = 3; 11016 ext_attr->vsb_rf_agc_cfg.top = 9500; 11017 ext_attr->vsb_rf_agc_cfg.cut_off_current = 4000; 11018 ext_attr->vsb_pre_saw_cfg.standard = DRX_STANDARD_8VSB; 11019 ext_attr->vsb_pre_saw_cfg.reference = 0x07; 11020 ext_attr->vsb_pre_saw_cfg.use_pre_saw = true; 11021 } 11022 11023 /* 11024 * \fn int ctrl_power_mode() 11025 * \brief Set the power mode of the device to the specified power mode 11026 * \param demod Pointer to demodulator instance. 11027 * \param mode Pointer to new power mode. 11028 * \return int. 11029 * \retval 0 Success 11030 * \retval -EIO I2C error or other failure 11031 * \retval -EINVAL Invalid mode argument. 11032 * 11033 * 11034 */ 11035 static int 11036 ctrl_power_mode(struct drx_demod_instance *demod, enum drx_power_mode *mode) 11037 { 11038 struct drx_common_attr *common_attr = (struct drx_common_attr *) NULL; 11039 struct drxj_data *ext_attr = (struct drxj_data *) NULL; 11040 struct i2c_device_addr *dev_addr = (struct i2c_device_addr *)NULL; 11041 int rc; 11042 u16 sio_cc_pwd_mode = 0; 11043 11044 common_attr = (struct drx_common_attr *) demod->my_common_attr; 11045 ext_attr = (struct drxj_data *) demod->my_ext_attr; 11046 dev_addr = demod->my_i2c_dev_addr; 11047 11048 /* Check arguments */ 11049 if (mode == NULL) 11050 return -EINVAL; 11051 11052 /* If already in requested power mode, do nothing */ 11053 if (common_attr->current_power_mode == *mode) 11054 return 0; 11055 11056 switch (*mode) { 11057 case DRX_POWER_UP: 11058 case DRXJ_POWER_DOWN_MAIN_PATH: 11059 sio_cc_pwd_mode = SIO_CC_PWD_MODE_LEVEL_NONE; 11060 break; 11061 case DRXJ_POWER_DOWN_CORE: 11062 sio_cc_pwd_mode = SIO_CC_PWD_MODE_LEVEL_CLOCK; 11063 break; 11064 case DRXJ_POWER_DOWN_PLL: 11065 sio_cc_pwd_mode = SIO_CC_PWD_MODE_LEVEL_PLL; 11066 break; 11067 case DRX_POWER_DOWN: 11068 sio_cc_pwd_mode = SIO_CC_PWD_MODE_LEVEL_OSC; 11069 break; 11070 default: 11071 /* Unknown sleep mode */ 11072 return -EINVAL; 11073 } 11074 11075 /* Check if device needs to be powered up */ 11076 if ((common_attr->current_power_mode != DRX_POWER_UP)) { 11077 rc = power_up_device(demod); 11078 if (rc != 0) { 11079 pr_err("error %d\n", rc); 11080 goto rw_error; 11081 } 11082 } 11083 11084 if (*mode == DRX_POWER_UP) { 11085 /* Restore analog & pin configuration */ 11086 11087 /* Initialize default AFE configuration for VSB */ 11088 drxj_reset_mode(ext_attr); 11089 } else { 11090 /* Power down to requested mode */ 11091 /* Backup some register settings */ 11092 /* Set pins with possible pull-ups connected to them in input mode */ 11093 /* Analog power down */ 11094 /* ADC power down */ 11095 /* Power down device */ 11096 /* stop all comm_exec */ 11097 /* 11098 Stop and power down previous standard 11099 */ 11100 11101 switch (ext_attr->standard) { 11102 case DRX_STANDARD_ITU_A: 11103 case DRX_STANDARD_ITU_B: 11104 case DRX_STANDARD_ITU_C: 11105 rc = power_down_qam(demod, true); 11106 if (rc != 0) { 11107 pr_err("error %d\n", rc); 11108 goto rw_error; 11109 } 11110 break; 11111 case DRX_STANDARD_8VSB: 11112 rc = power_down_vsb(demod, true); 11113 if (rc != 0) { 11114 pr_err("error %d\n", rc); 11115 goto rw_error; 11116 } 11117 break; 11118 case DRX_STANDARD_PAL_SECAM_BG: 11119 case DRX_STANDARD_PAL_SECAM_DK: 11120 case DRX_STANDARD_PAL_SECAM_I: 11121 case DRX_STANDARD_PAL_SECAM_L: 11122 case DRX_STANDARD_PAL_SECAM_LP: 11123 case DRX_STANDARD_NTSC: 11124 case DRX_STANDARD_FM: 11125 rc = power_down_atv(demod, ext_attr->standard, true); 11126 if (rc != 0) { 11127 pr_err("error %d\n", rc); 11128 goto rw_error; 11129 } 11130 break; 11131 case DRX_STANDARD_UNKNOWN: 11132 /* Do nothing */ 11133 break; 11134 case DRX_STANDARD_AUTO: 11135 default: 11136 return -EIO; 11137 } 11138 ext_attr->standard = DRX_STANDARD_UNKNOWN; 11139 } 11140 11141 if (*mode != DRXJ_POWER_DOWN_MAIN_PATH) { 11142 rc = drxj_dap_write_reg16(dev_addr, SIO_CC_PWD_MODE__A, sio_cc_pwd_mode, 0); 11143 if (rc != 0) { 11144 pr_err("error %d\n", rc); 11145 goto rw_error; 11146 } 11147 rc = drxj_dap_write_reg16(dev_addr, SIO_CC_UPDATE__A, SIO_CC_UPDATE_KEY, 0); 11148 if (rc != 0) { 11149 pr_err("error %d\n", rc); 11150 goto rw_error; 11151 } 11152 11153 if ((*mode != DRX_POWER_UP)) { 11154 /* Initialize HI, wakeup key especially before put IC to sleep */ 11155 rc = init_hi(demod); 11156 if (rc != 0) { 11157 pr_err("error %d\n", rc); 11158 goto rw_error; 11159 } 11160 11161 ext_attr->hi_cfg_ctrl |= SIO_HI_RA_RAM_PAR_5_CFG_SLEEP_ZZZ; 11162 rc = hi_cfg_command(demod); 11163 if (rc != 0) { 11164 pr_err("error %d\n", rc); 11165 goto rw_error; 11166 } 11167 } 11168 } 11169 11170 common_attr->current_power_mode = *mode; 11171 11172 return 0; 11173 rw_error: 11174 return rc; 11175 } 11176 11177 /*============================================================================*/ 11178 /*== CTRL Set/Get Config related functions ===================================*/ 11179 /*============================================================================*/ 11180 11181 /* 11182 * \fn int ctrl_set_cfg_pre_saw() 11183 * \brief Set Pre-saw reference. 11184 * \param demod demod instance 11185 * \param u16 * 11186 * \return int. 11187 * 11188 * Check arguments 11189 * Dispatch handling to standard specific function. 11190 * 11191 */ 11192 static int 11193 ctrl_set_cfg_pre_saw(struct drx_demod_instance *demod, struct drxj_cfg_pre_saw *pre_saw) 11194 { 11195 struct i2c_device_addr *dev_addr = NULL; 11196 struct drxj_data *ext_attr = NULL; 11197 int rc; 11198 11199 dev_addr = demod->my_i2c_dev_addr; 11200 ext_attr = (struct drxj_data *) demod->my_ext_attr; 11201 11202 /* check arguments */ 11203 if ((pre_saw == NULL) || (pre_saw->reference > IQM_AF_PDREF__M) 11204 ) { 11205 return -EINVAL; 11206 } 11207 11208 /* Only if standard is currently active */ 11209 if ((ext_attr->standard == pre_saw->standard) || 11210 (DRXJ_ISQAMSTD(ext_attr->standard) && 11211 DRXJ_ISQAMSTD(pre_saw->standard)) || 11212 (DRXJ_ISATVSTD(ext_attr->standard) && 11213 DRXJ_ISATVSTD(pre_saw->standard))) { 11214 rc = drxj_dap_write_reg16(dev_addr, IQM_AF_PDREF__A, pre_saw->reference, 0); 11215 if (rc != 0) { 11216 pr_err("error %d\n", rc); 11217 goto rw_error; 11218 } 11219 } 11220 11221 /* Store pre-saw settings */ 11222 switch (pre_saw->standard) { 11223 case DRX_STANDARD_8VSB: 11224 ext_attr->vsb_pre_saw_cfg = *pre_saw; 11225 break; 11226 #ifndef DRXJ_VSB_ONLY 11227 case DRX_STANDARD_ITU_A: 11228 case DRX_STANDARD_ITU_B: 11229 case DRX_STANDARD_ITU_C: 11230 ext_attr->qam_pre_saw_cfg = *pre_saw; 11231 break; 11232 #endif 11233 default: 11234 return -EINVAL; 11235 } 11236 11237 return 0; 11238 rw_error: 11239 return rc; 11240 } 11241 11242 /*============================================================================*/ 11243 11244 /* 11245 * \fn int ctrl_set_cfg_afe_gain() 11246 * \brief Set AFE Gain. 11247 * \param demod demod instance 11248 * \param u16 * 11249 * \return int. 11250 * 11251 * Check arguments 11252 * Dispatch handling to standard specific function. 11253 * 11254 */ 11255 static int 11256 ctrl_set_cfg_afe_gain(struct drx_demod_instance *demod, struct drxj_cfg_afe_gain *afe_gain) 11257 { 11258 struct i2c_device_addr *dev_addr = NULL; 11259 struct drxj_data *ext_attr = NULL; 11260 int rc; 11261 u8 gain = 0; 11262 11263 /* check arguments */ 11264 if (afe_gain == NULL) 11265 return -EINVAL; 11266 11267 dev_addr = demod->my_i2c_dev_addr; 11268 ext_attr = (struct drxj_data *) demod->my_ext_attr; 11269 11270 switch (afe_gain->standard) { 11271 case DRX_STANDARD_8VSB: fallthrough; 11272 #ifndef DRXJ_VSB_ONLY 11273 case DRX_STANDARD_ITU_A: 11274 case DRX_STANDARD_ITU_B: 11275 case DRX_STANDARD_ITU_C: 11276 #endif 11277 /* Do nothing */ 11278 break; 11279 default: 11280 return -EINVAL; 11281 } 11282 11283 /* TODO PGA gain is also written by microcode (at least by QAM and VSB) 11284 So I (PJ) think interface requires choice between auto, user mode */ 11285 11286 if (afe_gain->gain >= 329) 11287 gain = 15; 11288 else if (afe_gain->gain <= 147) 11289 gain = 0; 11290 else 11291 gain = (afe_gain->gain - 140 + 6) / 13; 11292 11293 /* Only if standard is currently active */ 11294 if (ext_attr->standard == afe_gain->standard) { 11295 rc = drxj_dap_write_reg16(dev_addr, IQM_AF_PGA_GAIN__A, gain, 0); 11296 if (rc != 0) { 11297 pr_err("error %d\n", rc); 11298 goto rw_error; 11299 } 11300 } 11301 11302 /* Store AFE Gain settings */ 11303 switch (afe_gain->standard) { 11304 case DRX_STANDARD_8VSB: 11305 ext_attr->vsb_pga_cfg = gain * 13 + 140; 11306 break; 11307 #ifndef DRXJ_VSB_ONLY 11308 case DRX_STANDARD_ITU_A: 11309 case DRX_STANDARD_ITU_B: 11310 case DRX_STANDARD_ITU_C: 11311 ext_attr->qam_pga_cfg = gain * 13 + 140; 11312 break; 11313 #endif 11314 default: 11315 return -EIO; 11316 } 11317 11318 return 0; 11319 rw_error: 11320 return rc; 11321 } 11322 11323 /*============================================================================*/ 11324 11325 11326 /*============================================================================= 11327 ===== EXPORTED FUNCTIONS ====================================================*/ 11328 11329 static int drx_ctrl_u_code(struct drx_demod_instance *demod, 11330 struct drxu_code_info *mc_info, 11331 enum drxu_code_action action); 11332 static int drxj_set_lna_state(struct drx_demod_instance *demod, bool state); 11333 11334 /* 11335 * \fn drxj_open() 11336 * \brief Open the demod instance, configure device, configure drxdriver 11337 * \return Status_t Return status. 11338 * 11339 * drxj_open() can be called with a NULL ucode image => no ucode upload. 11340 * This means that drxj_open() must NOT contain SCU commands or, in general, 11341 * rely on SCU or AUD ucode to be present. 11342 * 11343 */ 11344 11345 static int drxj_open(struct drx_demod_instance *demod) 11346 { 11347 struct i2c_device_addr *dev_addr = NULL; 11348 struct drxj_data *ext_attr = NULL; 11349 struct drx_common_attr *common_attr = NULL; 11350 u32 driver_version = 0; 11351 struct drxu_code_info ucode_info; 11352 struct drx_cfg_mpeg_output cfg_mpeg_output; 11353 int rc; 11354 enum drx_power_mode power_mode = DRX_POWER_UP; 11355 11356 if ((demod == NULL) || 11357 (demod->my_common_attr == NULL) || 11358 (demod->my_ext_attr == NULL) || 11359 (demod->my_i2c_dev_addr == NULL) || 11360 (demod->my_common_attr->is_opened)) { 11361 return -EINVAL; 11362 } 11363 11364 /* Check arguments */ 11365 if (demod->my_ext_attr == NULL) 11366 return -EINVAL; 11367 11368 dev_addr = demod->my_i2c_dev_addr; 11369 ext_attr = (struct drxj_data *) demod->my_ext_attr; 11370 common_attr = (struct drx_common_attr *) demod->my_common_attr; 11371 11372 rc = ctrl_power_mode(demod, &power_mode); 11373 if (rc != 0) { 11374 pr_err("error %d\n", rc); 11375 goto rw_error; 11376 } 11377 if (power_mode != DRX_POWER_UP) { 11378 rc = -EINVAL; 11379 pr_err("failed to powerup device\n"); 11380 goto rw_error; 11381 } 11382 11383 /* has to be in front of setIqmAf and setOrxNsuAox */ 11384 rc = get_device_capabilities(demod); 11385 if (rc != 0) { 11386 pr_err("error %d\n", rc); 11387 goto rw_error; 11388 } 11389 11390 /* 11391 * Soft reset of sys- and osc-clockdomain 11392 * 11393 * HACK: On windows, it writes a 0x07 here, instead of just 0x03. 11394 * As we didn't load the firmware here yet, we should do the same. 11395 * Btw, this is coherent with DRX-K, where we send reset codes 11396 * for modulation (OFTM, in DRX-k), SYS and OSC clock domains. 11397 */ 11398 rc = drxj_dap_write_reg16(dev_addr, SIO_CC_SOFT_RST__A, (0x04 | SIO_CC_SOFT_RST_SYS__M | SIO_CC_SOFT_RST_OSC__M), 0); 11399 if (rc != 0) { 11400 pr_err("error %d\n", rc); 11401 goto rw_error; 11402 } 11403 rc = drxj_dap_write_reg16(dev_addr, SIO_CC_UPDATE__A, SIO_CC_UPDATE_KEY, 0); 11404 if (rc != 0) { 11405 pr_err("error %d\n", rc); 11406 goto rw_error; 11407 } 11408 msleep(1); 11409 11410 /* TODO first make sure that everything keeps working before enabling this */ 11411 /* PowerDownAnalogBlocks() */ 11412 rc = drxj_dap_write_reg16(dev_addr, ATV_TOP_STDBY__A, (~ATV_TOP_STDBY_CVBS_STDBY_A2_ACTIVE) | ATV_TOP_STDBY_SIF_STDBY_STANDBY, 0); 11413 if (rc != 0) { 11414 pr_err("error %d\n", rc); 11415 goto rw_error; 11416 } 11417 11418 rc = set_iqm_af(demod, false); 11419 if (rc != 0) { 11420 pr_err("error %d\n", rc); 11421 goto rw_error; 11422 } 11423 rc = set_orx_nsu_aox(demod, false); 11424 if (rc != 0) { 11425 pr_err("error %d\n", rc); 11426 goto rw_error; 11427 } 11428 11429 rc = init_hi(demod); 11430 if (rc != 0) { 11431 pr_err("error %d\n", rc); 11432 goto rw_error; 11433 } 11434 11435 /* disable mpegoutput pins */ 11436 memcpy(&cfg_mpeg_output, &common_attr->mpeg_cfg, sizeof(cfg_mpeg_output)); 11437 cfg_mpeg_output.enable_mpeg_output = false; 11438 11439 rc = ctrl_set_cfg_mpeg_output(demod, &cfg_mpeg_output); 11440 if (rc != 0) { 11441 pr_err("error %d\n", rc); 11442 goto rw_error; 11443 } 11444 /* Stop AUD Inform SetAudio it will need to do all setting */ 11445 rc = power_down_aud(demod); 11446 if (rc != 0) { 11447 pr_err("error %d\n", rc); 11448 goto rw_error; 11449 } 11450 /* Stop SCU */ 11451 rc = drxj_dap_write_reg16(dev_addr, SCU_COMM_EXEC__A, SCU_COMM_EXEC_STOP, 0); 11452 if (rc != 0) { 11453 pr_err("error %d\n", rc); 11454 goto rw_error; 11455 } 11456 11457 /* Upload microcode */ 11458 if (common_attr->microcode_file != NULL) { 11459 /* Dirty trick to use common ucode upload & verify, 11460 pretend device is already open */ 11461 common_attr->is_opened = true; 11462 ucode_info.mc_file = common_attr->microcode_file; 11463 11464 if (DRX_ISPOWERDOWNMODE(demod->my_common_attr->current_power_mode)) { 11465 pr_err("Should powerup before loading the firmware."); 11466 rc = -EINVAL; 11467 goto rw_error; 11468 } 11469 11470 rc = drx_ctrl_u_code(demod, &ucode_info, UCODE_UPLOAD); 11471 if (rc != 0) { 11472 pr_err("error %d while uploading the firmware\n", rc); 11473 goto rw_error; 11474 } 11475 if (common_attr->verify_microcode == true) { 11476 rc = drx_ctrl_u_code(demod, &ucode_info, UCODE_VERIFY); 11477 if (rc != 0) { 11478 pr_err("error %d while verifying the firmware\n", 11479 rc); 11480 goto rw_error; 11481 } 11482 } 11483 common_attr->is_opened = false; 11484 } 11485 11486 /* Run SCU for a little while to initialize microcode version numbers */ 11487 rc = drxj_dap_write_reg16(dev_addr, SCU_COMM_EXEC__A, SCU_COMM_EXEC_ACTIVE, 0); 11488 if (rc != 0) { 11489 pr_err("error %d\n", rc); 11490 goto rw_error; 11491 } 11492 11493 /* Initialize scan timeout */ 11494 common_attr->scan_demod_lock_timeout = DRXJ_SCAN_TIMEOUT; 11495 common_attr->scan_desired_lock = DRX_LOCKED; 11496 11497 drxj_reset_mode(ext_attr); 11498 ext_attr->standard = DRX_STANDARD_UNKNOWN; 11499 11500 rc = smart_ant_init(demod); 11501 if (rc != 0) { 11502 pr_err("error %d\n", rc); 11503 goto rw_error; 11504 } 11505 11506 /* Stamp driver version number in SCU data RAM in BCD code 11507 Done to enable field application engineers to retrieve drxdriver version 11508 via I2C from SCU RAM 11509 */ 11510 driver_version = (VERSION_MAJOR / 100) % 10; 11511 driver_version <<= 4; 11512 driver_version += (VERSION_MAJOR / 10) % 10; 11513 driver_version <<= 4; 11514 driver_version += (VERSION_MAJOR % 10); 11515 driver_version <<= 4; 11516 driver_version += (VERSION_MINOR % 10); 11517 driver_version <<= 4; 11518 driver_version += (VERSION_PATCH / 1000) % 10; 11519 driver_version <<= 4; 11520 driver_version += (VERSION_PATCH / 100) % 10; 11521 driver_version <<= 4; 11522 driver_version += (VERSION_PATCH / 10) % 10; 11523 driver_version <<= 4; 11524 driver_version += (VERSION_PATCH % 10); 11525 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_DRIVER_VER_HI__A, (u16)(driver_version >> 16), 0); 11526 if (rc != 0) { 11527 pr_err("error %d\n", rc); 11528 goto rw_error; 11529 } 11530 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_DRIVER_VER_LO__A, (u16)(driver_version & 0xFFFF), 0); 11531 if (rc != 0) { 11532 pr_err("error %d\n", rc); 11533 goto rw_error; 11534 } 11535 11536 rc = ctrl_set_oob(demod, NULL); 11537 if (rc != 0) { 11538 pr_err("error %d\n", rc); 11539 goto rw_error; 11540 } 11541 11542 /* refresh the audio data structure with default */ 11543 ext_attr->aud_data = drxj_default_aud_data_g; 11544 11545 demod->my_common_attr->is_opened = true; 11546 drxj_set_lna_state(demod, false); 11547 return 0; 11548 rw_error: 11549 common_attr->is_opened = false; 11550 return rc; 11551 } 11552 11553 /*============================================================================*/ 11554 /* 11555 * \fn drxj_close() 11556 * \brief Close the demod instance, power down the device 11557 * \return Status_t Return status. 11558 * 11559 */ 11560 static int drxj_close(struct drx_demod_instance *demod) 11561 { 11562 struct i2c_device_addr *dev_addr = demod->my_i2c_dev_addr; 11563 int rc; 11564 enum drx_power_mode power_mode = DRX_POWER_UP; 11565 11566 if ((demod->my_common_attr == NULL) || 11567 (demod->my_ext_attr == NULL) || 11568 (demod->my_i2c_dev_addr == NULL) || 11569 (!demod->my_common_attr->is_opened)) { 11570 return -EINVAL; 11571 } 11572 11573 /* power up */ 11574 rc = ctrl_power_mode(demod, &power_mode); 11575 if (rc != 0) { 11576 pr_err("error %d\n", rc); 11577 goto rw_error; 11578 } 11579 11580 rc = drxj_dap_write_reg16(dev_addr, SCU_COMM_EXEC__A, SCU_COMM_EXEC_ACTIVE, 0); 11581 if (rc != 0) { 11582 pr_err("error %d\n", rc); 11583 goto rw_error; 11584 } 11585 power_mode = DRX_POWER_DOWN; 11586 rc = ctrl_power_mode(demod, &power_mode); 11587 if (rc != 0) { 11588 pr_err("error %d\n", rc); 11589 goto rw_error; 11590 } 11591 11592 DRX_ATTR_ISOPENED(demod) = false; 11593 11594 return 0; 11595 rw_error: 11596 DRX_ATTR_ISOPENED(demod) = false; 11597 11598 return rc; 11599 } 11600 11601 /* 11602 * Microcode related functions 11603 */ 11604 11605 /* 11606 * drx_u_code_compute_crc - Compute CRC of block of microcode data. 11607 * @block_data: Pointer to microcode data. 11608 * @nr_words: Size of microcode block (number of 16 bits words). 11609 * 11610 * returns The computed CRC residue. 11611 */ 11612 static u16 drx_u_code_compute_crc(u8 *block_data, u16 nr_words) 11613 { 11614 u16 i = 0; 11615 u16 j = 0; 11616 u32 crc_word = 0; 11617 u32 carry = 0; 11618 11619 while (i < nr_words) { 11620 crc_word |= (u32)be16_to_cpu(*(__be16 *)(block_data)); 11621 for (j = 0; j < 16; j++) { 11622 crc_word <<= 1; 11623 if (carry != 0) 11624 crc_word ^= 0x80050000UL; 11625 carry = crc_word & 0x80000000UL; 11626 } 11627 i++; 11628 block_data += (sizeof(u16)); 11629 } 11630 return (u16)(crc_word >> 16); 11631 } 11632 11633 /* 11634 * drx_check_firmware - checks if the loaded firmware is valid 11635 * 11636 * @demod: demod structure 11637 * @mc_data: pointer to the start of the firmware 11638 * @size: firmware size 11639 */ 11640 static int drx_check_firmware(struct drx_demod_instance *demod, u8 *mc_data, 11641 unsigned size) 11642 { 11643 struct drxu_code_block_hdr block_hdr; 11644 int i; 11645 unsigned count = 2 * sizeof(u16); 11646 u32 mc_dev_type, mc_version, mc_base_version; 11647 u16 mc_nr_of_blks = be16_to_cpu(*(__be16 *)(mc_data + sizeof(u16))); 11648 11649 /* 11650 * Scan microcode blocks first for version info 11651 * and firmware check 11652 */ 11653 11654 /* Clear version block */ 11655 DRX_ATTR_MCRECORD(demod).aux_type = 0; 11656 DRX_ATTR_MCRECORD(demod).mc_dev_type = 0; 11657 DRX_ATTR_MCRECORD(demod).mc_version = 0; 11658 DRX_ATTR_MCRECORD(demod).mc_base_version = 0; 11659 11660 for (i = 0; i < mc_nr_of_blks; i++) { 11661 if (count + 3 * sizeof(u16) + sizeof(u32) > size) 11662 goto eof; 11663 11664 /* Process block header */ 11665 block_hdr.addr = be32_to_cpu(*(__be32 *)(mc_data + count)); 11666 count += sizeof(u32); 11667 block_hdr.size = be16_to_cpu(*(__be16 *)(mc_data + count)); 11668 count += sizeof(u16); 11669 block_hdr.flags = be16_to_cpu(*(__be16 *)(mc_data + count)); 11670 count += sizeof(u16); 11671 block_hdr.CRC = be16_to_cpu(*(__be16 *)(mc_data + count)); 11672 count += sizeof(u16); 11673 11674 pr_debug("%u: addr %u, size %u, flags 0x%04x, CRC 0x%04x\n", 11675 count, block_hdr.addr, block_hdr.size, block_hdr.flags, 11676 block_hdr.CRC); 11677 11678 if (block_hdr.flags & 0x8) { 11679 u8 *auxblk = ((void *)mc_data) + block_hdr.addr; 11680 u16 auxtype; 11681 11682 if (block_hdr.addr + sizeof(u16) > size) 11683 goto eof; 11684 11685 auxtype = be16_to_cpu(*(__be16 *)(auxblk)); 11686 11687 /* Aux block. Check type */ 11688 if (DRX_ISMCVERTYPE(auxtype)) { 11689 if (block_hdr.addr + 2 * sizeof(u16) + 2 * sizeof (u32) > size) 11690 goto eof; 11691 11692 auxblk += sizeof(u16); 11693 mc_dev_type = be32_to_cpu(*(__be32 *)(auxblk)); 11694 auxblk += sizeof(u32); 11695 mc_version = be32_to_cpu(*(__be32 *)(auxblk)); 11696 auxblk += sizeof(u32); 11697 mc_base_version = be32_to_cpu(*(__be32 *)(auxblk)); 11698 11699 DRX_ATTR_MCRECORD(demod).aux_type = auxtype; 11700 DRX_ATTR_MCRECORD(demod).mc_dev_type = mc_dev_type; 11701 DRX_ATTR_MCRECORD(demod).mc_version = mc_version; 11702 DRX_ATTR_MCRECORD(demod).mc_base_version = mc_base_version; 11703 11704 pr_info("Firmware dev %x, ver %x, base ver %x\n", 11705 mc_dev_type, mc_version, mc_base_version); 11706 11707 } 11708 } else if (count + block_hdr.size * sizeof(u16) > size) 11709 goto eof; 11710 11711 count += block_hdr.size * sizeof(u16); 11712 } 11713 return 0; 11714 eof: 11715 pr_err("Firmware is truncated at pos %u/%u\n", count, size); 11716 return -EINVAL; 11717 } 11718 11719 /* 11720 * drx_ctrl_u_code - Handle microcode upload or verify. 11721 * @dev_addr: Address of device. 11722 * @mc_info: Pointer to information about microcode data. 11723 * @action: Either UCODE_UPLOAD or UCODE_VERIFY 11724 * 11725 * This function returns: 11726 * 0: 11727 * - In case of UCODE_UPLOAD: code is successfully uploaded. 11728 * - In case of UCODE_VERIFY: image on device is equal to 11729 * image provided to this control function. 11730 * -EIO: 11731 * - In case of UCODE_UPLOAD: I2C error. 11732 * - In case of UCODE_VERIFY: I2C error or image on device 11733 * is not equal to image provided to this control function. 11734 * -EINVAL: 11735 * - Invalid arguments. 11736 * - Provided image is corrupt 11737 */ 11738 static int drx_ctrl_u_code(struct drx_demod_instance *demod, 11739 struct drxu_code_info *mc_info, 11740 enum drxu_code_action action) 11741 { 11742 struct i2c_device_addr *dev_addr = demod->my_i2c_dev_addr; 11743 int rc; 11744 u16 i = 0; 11745 u16 mc_nr_of_blks = 0; 11746 u16 mc_magic_word = 0; 11747 const u8 *mc_data_init = NULL; 11748 u8 *mc_data = NULL; 11749 unsigned size; 11750 char *mc_file; 11751 const struct firmware *fw; 11752 11753 /* Check arguments */ 11754 if (!mc_info || !mc_info->mc_file) 11755 return -EINVAL; 11756 11757 mc_file = mc_info->mc_file; 11758 11759 rc = request_firmware(&fw, mc_file, demod->i2c->dev.parent); 11760 if (rc < 0) { 11761 pr_err("Couldn't read firmware %s\n", mc_file); 11762 return rc; 11763 } 11764 11765 if (fw->size < 2 * sizeof(u16)) { 11766 rc = -EINVAL; 11767 pr_err("Firmware is too short!\n"); 11768 goto release; 11769 } 11770 11771 pr_info("Firmware %s, size %zu\n", mc_file, fw->size); 11772 11773 mc_data_init = fw->data; 11774 size = fw->size; 11775 11776 mc_data = (void *)mc_data_init; 11777 /* Check data */ 11778 mc_magic_word = be16_to_cpu(*(__be16 *)(mc_data)); 11779 mc_data += sizeof(u16); 11780 mc_nr_of_blks = be16_to_cpu(*(__be16 *)(mc_data)); 11781 mc_data += sizeof(u16); 11782 11783 if ((mc_magic_word != DRX_UCODE_MAGIC_WORD) || (mc_nr_of_blks == 0)) { 11784 rc = -EINVAL; 11785 pr_err("Firmware magic word doesn't match\n"); 11786 goto release; 11787 } 11788 11789 if (action == UCODE_UPLOAD) { 11790 rc = drx_check_firmware(demod, (u8 *)mc_data_init, size); 11791 if (rc) 11792 goto release; 11793 pr_info("Uploading firmware %s\n", mc_file); 11794 } else { 11795 pr_info("Verifying if firmware upload was ok.\n"); 11796 } 11797 11798 /* Process microcode blocks */ 11799 for (i = 0; i < mc_nr_of_blks; i++) { 11800 struct drxu_code_block_hdr block_hdr; 11801 u16 mc_block_nr_bytes = 0; 11802 11803 /* Process block header */ 11804 block_hdr.addr = be32_to_cpu(*(__be32 *)(mc_data)); 11805 mc_data += sizeof(u32); 11806 block_hdr.size = be16_to_cpu(*(__be16 *)(mc_data)); 11807 mc_data += sizeof(u16); 11808 block_hdr.flags = be16_to_cpu(*(__be16 *)(mc_data)); 11809 mc_data += sizeof(u16); 11810 block_hdr.CRC = be16_to_cpu(*(__be16 *)(mc_data)); 11811 mc_data += sizeof(u16); 11812 11813 pr_debug("%zd: addr %u, size %u, flags 0x%04x, CRC 0x%04x\n", 11814 (mc_data - mc_data_init), block_hdr.addr, 11815 block_hdr.size, block_hdr.flags, block_hdr.CRC); 11816 11817 /* Check block header on: 11818 - data larger than 64Kb 11819 - if CRC enabled check CRC 11820 */ 11821 if ((block_hdr.size > 0x7FFF) || 11822 (((block_hdr.flags & DRX_UCODE_CRC_FLAG) != 0) && 11823 (block_hdr.CRC != drx_u_code_compute_crc(mc_data, block_hdr.size))) 11824 ) { 11825 /* Wrong data ! */ 11826 rc = -EINVAL; 11827 pr_err("firmware CRC is wrong\n"); 11828 goto release; 11829 } 11830 11831 if (!block_hdr.size) 11832 continue; 11833 11834 mc_block_nr_bytes = block_hdr.size * ((u16) sizeof(u16)); 11835 11836 /* Perform the desired action */ 11837 switch (action) { 11838 case UCODE_UPLOAD: /* Upload microcode */ 11839 if (drxdap_fasi_write_block(dev_addr, 11840 block_hdr.addr, 11841 mc_block_nr_bytes, 11842 mc_data, 0x0000)) { 11843 rc = -EIO; 11844 pr_err("error writing firmware at pos %zd\n", 11845 mc_data - mc_data_init); 11846 goto release; 11847 } 11848 break; 11849 case UCODE_VERIFY: { /* Verify uploaded microcode */ 11850 int result = 0; 11851 u8 mc_data_buffer[DRX_UCODE_MAX_BUF_SIZE]; 11852 u32 bytes_to_comp = 0; 11853 u32 bytes_left = mc_block_nr_bytes; 11854 u32 curr_addr = block_hdr.addr; 11855 u8 *curr_ptr = mc_data; 11856 11857 while (bytes_left != 0) { 11858 if (bytes_left > DRX_UCODE_MAX_BUF_SIZE) 11859 bytes_to_comp = DRX_UCODE_MAX_BUF_SIZE; 11860 else 11861 bytes_to_comp = bytes_left; 11862 11863 if (drxdap_fasi_read_block(dev_addr, 11864 curr_addr, 11865 (u16)bytes_to_comp, 11866 (u8 *)mc_data_buffer, 11867 0x0000)) { 11868 pr_err("error reading firmware at pos %zd\n", 11869 mc_data - mc_data_init); 11870 rc = -EIO; 11871 goto release; 11872 } 11873 11874 result = memcmp(curr_ptr, mc_data_buffer, 11875 bytes_to_comp); 11876 11877 if (result) { 11878 pr_err("error verifying firmware at pos %zd\n", 11879 mc_data - mc_data_init); 11880 rc = -EIO; 11881 goto release; 11882 } 11883 11884 curr_addr += ((dr_xaddr_t)(bytes_to_comp / 2)); 11885 curr_ptr =&(curr_ptr[bytes_to_comp]); 11886 bytes_left -=((u32) bytes_to_comp); 11887 } 11888 break; 11889 } 11890 default: 11891 rc = -EINVAL; 11892 goto release; 11893 11894 } 11895 mc_data += mc_block_nr_bytes; 11896 } 11897 11898 rc = 0; 11899 11900 release: 11901 release_firmware(fw); 11902 11903 return rc; 11904 } 11905 11906 /* caller is expected to check if lna is supported before enabling */ 11907 static int drxj_set_lna_state(struct drx_demod_instance *demod, bool state) 11908 { 11909 struct drxuio_cfg uio_cfg; 11910 struct drxuio_data uio_data; 11911 int result; 11912 11913 uio_cfg.uio = DRX_UIO1; 11914 uio_cfg.mode = DRX_UIO_MODE_READWRITE; 11915 /* Configure user-I/O #3: enable read/write */ 11916 result = ctrl_set_uio_cfg(demod, &uio_cfg); 11917 if (result) { 11918 pr_err("Failed to setup LNA GPIO!\n"); 11919 return result; 11920 } 11921 11922 uio_data.uio = DRX_UIO1; 11923 uio_data.value = state; 11924 result = ctrl_uio_write(demod, &uio_data); 11925 if (result != 0) { 11926 pr_err("Failed to %sable LNA!\n", 11927 state ? "en" : "dis"); 11928 return result; 11929 } 11930 return 0; 11931 } 11932 11933 /* 11934 * The Linux DVB Driver for Micronas DRX39xx family (drx3933j) 11935 * 11936 * Written by Devin Heitmueller <devin.heitmueller@kernellabs.com> 11937 */ 11938 11939 static int drx39xxj_set_powerstate(struct dvb_frontend *fe, int enable) 11940 { 11941 struct drx39xxj_state *state = fe->demodulator_priv; 11942 struct drx_demod_instance *demod = state->demod; 11943 int result; 11944 enum drx_power_mode power_mode; 11945 11946 if (enable) 11947 power_mode = DRX_POWER_UP; 11948 else 11949 power_mode = DRX_POWER_DOWN; 11950 11951 result = ctrl_power_mode(demod, &power_mode); 11952 if (result != 0) { 11953 pr_err("Power state change failed\n"); 11954 return 0; 11955 } 11956 11957 return 0; 11958 } 11959 11960 static int drx39xxj_read_status(struct dvb_frontend *fe, enum fe_status *status) 11961 { 11962 struct drx39xxj_state *state = fe->demodulator_priv; 11963 struct drx_demod_instance *demod = state->demod; 11964 int result; 11965 enum drx_lock_status lock_status; 11966 11967 *status = 0; 11968 11969 result = ctrl_lock_status(demod, &lock_status); 11970 if (result != 0) { 11971 pr_err("drx39xxj: could not get lock status!\n"); 11972 *status = 0; 11973 } 11974 11975 switch (lock_status) { 11976 case DRX_NEVER_LOCK: 11977 *status = 0; 11978 pr_err("drx says NEVER_LOCK\n"); 11979 break; 11980 case DRX_NOT_LOCKED: 11981 *status = 0; 11982 break; 11983 case DRX_LOCK_STATE_1: 11984 case DRX_LOCK_STATE_2: 11985 case DRX_LOCK_STATE_3: 11986 case DRX_LOCK_STATE_4: 11987 case DRX_LOCK_STATE_5: 11988 case DRX_LOCK_STATE_6: 11989 case DRX_LOCK_STATE_7: 11990 case DRX_LOCK_STATE_8: 11991 case DRX_LOCK_STATE_9: 11992 *status = FE_HAS_SIGNAL 11993 | FE_HAS_CARRIER | FE_HAS_VITERBI | FE_HAS_SYNC; 11994 break; 11995 case DRX_LOCKED: 11996 *status = FE_HAS_SIGNAL 11997 | FE_HAS_CARRIER 11998 | FE_HAS_VITERBI | FE_HAS_SYNC | FE_HAS_LOCK; 11999 break; 12000 default: 12001 pr_err("Lock state unknown %d\n", lock_status); 12002 } 12003 ctrl_sig_quality(demod, lock_status); 12004 12005 return 0; 12006 } 12007 12008 static int drx39xxj_read_ber(struct dvb_frontend *fe, u32 *ber) 12009 { 12010 struct dtv_frontend_properties *p = &fe->dtv_property_cache; 12011 12012 if (p->pre_bit_error.stat[0].scale == FE_SCALE_NOT_AVAILABLE) { 12013 *ber = 0; 12014 return 0; 12015 } 12016 12017 if (!p->pre_bit_count.stat[0].uvalue) { 12018 if (!p->pre_bit_error.stat[0].uvalue) 12019 *ber = 0; 12020 else 12021 *ber = 1000000; 12022 } else { 12023 *ber = frac_times1e6(p->pre_bit_error.stat[0].uvalue, 12024 p->pre_bit_count.stat[0].uvalue); 12025 } 12026 return 0; 12027 } 12028 12029 static int drx39xxj_read_signal_strength(struct dvb_frontend *fe, 12030 u16 *strength) 12031 { 12032 struct dtv_frontend_properties *p = &fe->dtv_property_cache; 12033 12034 if (p->strength.stat[0].scale == FE_SCALE_NOT_AVAILABLE) { 12035 *strength = 0; 12036 return 0; 12037 } 12038 12039 *strength = p->strength.stat[0].uvalue; 12040 return 0; 12041 } 12042 12043 static int drx39xxj_read_snr(struct dvb_frontend *fe, u16 *snr) 12044 { 12045 struct dtv_frontend_properties *p = &fe->dtv_property_cache; 12046 u64 tmp64; 12047 12048 if (p->cnr.stat[0].scale == FE_SCALE_NOT_AVAILABLE) { 12049 *snr = 0; 12050 return 0; 12051 } 12052 12053 tmp64 = p->cnr.stat[0].svalue; 12054 do_div(tmp64, 10); 12055 *snr = tmp64; 12056 return 0; 12057 } 12058 12059 static int drx39xxj_read_ucblocks(struct dvb_frontend *fe, u32 *ucb) 12060 { 12061 struct dtv_frontend_properties *p = &fe->dtv_property_cache; 12062 12063 if (p->block_error.stat[0].scale == FE_SCALE_NOT_AVAILABLE) { 12064 *ucb = 0; 12065 return 0; 12066 } 12067 12068 *ucb = p->block_error.stat[0].uvalue; 12069 return 0; 12070 } 12071 12072 static int drx39xxj_set_frontend(struct dvb_frontend *fe) 12073 { 12074 #ifdef DJH_DEBUG 12075 int i; 12076 #endif 12077 struct dtv_frontend_properties *p = &fe->dtv_property_cache; 12078 struct drx39xxj_state *state = fe->demodulator_priv; 12079 struct drx_demod_instance *demod = state->demod; 12080 enum drx_standard standard = DRX_STANDARD_8VSB; 12081 struct drx_channel channel; 12082 int result; 12083 static const struct drx_channel def_channel = { 12084 /* frequency */ 0, 12085 /* bandwidth */ DRX_BANDWIDTH_6MHZ, 12086 /* mirror */ DRX_MIRROR_NO, 12087 /* constellation */ DRX_CONSTELLATION_AUTO, 12088 /* hierarchy */ DRX_HIERARCHY_UNKNOWN, 12089 /* priority */ DRX_PRIORITY_UNKNOWN, 12090 /* coderate */ DRX_CODERATE_UNKNOWN, 12091 /* guard */ DRX_GUARD_UNKNOWN, 12092 /* fftmode */ DRX_FFTMODE_UNKNOWN, 12093 /* classification */ DRX_CLASSIFICATION_AUTO, 12094 /* symbolrate */ 5057000, 12095 /* interleavemode */ DRX_INTERLEAVEMODE_UNKNOWN, 12096 /* ldpc */ DRX_LDPC_UNKNOWN, 12097 /* carrier */ DRX_CARRIER_UNKNOWN, 12098 /* frame mode */ DRX_FRAMEMODE_UNKNOWN 12099 }; 12100 u32 constellation = DRX_CONSTELLATION_AUTO; 12101 12102 /* Bring the demod out of sleep */ 12103 drx39xxj_set_powerstate(fe, 1); 12104 12105 if (fe->ops.tuner_ops.set_params) { 12106 u32 int_freq; 12107 12108 if (fe->ops.i2c_gate_ctrl) 12109 fe->ops.i2c_gate_ctrl(fe, 1); 12110 12111 /* Set tuner to desired frequency and standard */ 12112 fe->ops.tuner_ops.set_params(fe); 12113 12114 /* Use the tuner's IF */ 12115 if (fe->ops.tuner_ops.get_if_frequency) { 12116 fe->ops.tuner_ops.get_if_frequency(fe, &int_freq); 12117 demod->my_common_attr->intermediate_freq = int_freq / 1000; 12118 } 12119 12120 if (fe->ops.i2c_gate_ctrl) 12121 fe->ops.i2c_gate_ctrl(fe, 0); 12122 } 12123 12124 switch (p->delivery_system) { 12125 case SYS_ATSC: 12126 standard = DRX_STANDARD_8VSB; 12127 break; 12128 case SYS_DVBC_ANNEX_B: 12129 standard = DRX_STANDARD_ITU_B; 12130 12131 switch (p->modulation) { 12132 case QAM_64: 12133 constellation = DRX_CONSTELLATION_QAM64; 12134 break; 12135 case QAM_256: 12136 constellation = DRX_CONSTELLATION_QAM256; 12137 break; 12138 default: 12139 constellation = DRX_CONSTELLATION_AUTO; 12140 break; 12141 } 12142 break; 12143 default: 12144 return -EINVAL; 12145 } 12146 /* Set the standard (will be powered up if necessary */ 12147 result = ctrl_set_standard(demod, &standard); 12148 if (result != 0) { 12149 pr_err("Failed to set standard! result=%02x\n", 12150 result); 12151 return -EINVAL; 12152 } 12153 12154 /* set channel parameters */ 12155 channel = def_channel; 12156 channel.frequency = p->frequency / 1000; 12157 channel.bandwidth = DRX_BANDWIDTH_6MHZ; 12158 channel.constellation = constellation; 12159 12160 /* program channel */ 12161 result = ctrl_set_channel(demod, &channel); 12162 if (result != 0) { 12163 pr_err("Failed to set channel!\n"); 12164 return -EINVAL; 12165 } 12166 /* Just for giggles, let's shut off the LNA again.... */ 12167 drxj_set_lna_state(demod, false); 12168 12169 /* After set_frontend, except for strength, stats aren't available */ 12170 p->strength.stat[0].scale = FE_SCALE_RELATIVE; 12171 12172 return 0; 12173 } 12174 12175 static int drx39xxj_sleep(struct dvb_frontend *fe) 12176 { 12177 /* power-down the demodulator */ 12178 return drx39xxj_set_powerstate(fe, 0); 12179 } 12180 12181 static int drx39xxj_i2c_gate_ctrl(struct dvb_frontend *fe, int enable) 12182 { 12183 struct drx39xxj_state *state = fe->demodulator_priv; 12184 struct drx_demod_instance *demod = state->demod; 12185 bool i2c_gate_state; 12186 int result; 12187 12188 #ifdef DJH_DEBUG 12189 pr_debug("i2c gate call: enable=%d state=%d\n", enable, 12190 state->i2c_gate_open); 12191 #endif 12192 12193 if (enable) 12194 i2c_gate_state = true; 12195 else 12196 i2c_gate_state = false; 12197 12198 if (state->i2c_gate_open == enable) { 12199 /* We're already in the desired state */ 12200 return 0; 12201 } 12202 12203 result = ctrl_i2c_bridge(demod, &i2c_gate_state); 12204 if (result != 0) { 12205 pr_err("drx39xxj: could not open i2c gate [%d]\n", 12206 result); 12207 dump_stack(); 12208 } else { 12209 state->i2c_gate_open = enable; 12210 } 12211 return 0; 12212 } 12213 12214 static int drx39xxj_init(struct dvb_frontend *fe) 12215 { 12216 struct drx39xxj_state *state = fe->demodulator_priv; 12217 struct drx_demod_instance *demod = state->demod; 12218 int rc = 0; 12219 12220 if (fe->exit == DVB_FE_DEVICE_RESUME) { 12221 /* so drxj_open() does what it needs to do */ 12222 demod->my_common_attr->is_opened = false; 12223 rc = drxj_open(demod); 12224 if (rc != 0) 12225 pr_err("drx39xxj_init(): DRX open failed rc=%d!\n", rc); 12226 } else 12227 drx39xxj_set_powerstate(fe, 1); 12228 12229 return rc; 12230 } 12231 12232 static int drx39xxj_set_lna(struct dvb_frontend *fe) 12233 { 12234 struct dtv_frontend_properties *c = &fe->dtv_property_cache; 12235 struct drx39xxj_state *state = fe->demodulator_priv; 12236 struct drx_demod_instance *demod = state->demod; 12237 struct drxj_data *ext_attr = demod->my_ext_attr; 12238 12239 if (c->lna) { 12240 if (!ext_attr->has_lna) { 12241 pr_err("LNA is not supported on this device!\n"); 12242 return -EINVAL; 12243 12244 } 12245 } 12246 12247 return drxj_set_lna_state(demod, c->lna); 12248 } 12249 12250 static int drx39xxj_get_tune_settings(struct dvb_frontend *fe, 12251 struct dvb_frontend_tune_settings *tune) 12252 { 12253 tune->min_delay_ms = 1000; 12254 return 0; 12255 } 12256 12257 static void drx39xxj_release(struct dvb_frontend *fe) 12258 { 12259 struct drx39xxj_state *state = fe->demodulator_priv; 12260 struct drx_demod_instance *demod = state->demod; 12261 12262 /* if device is removed don't access it */ 12263 if (fe->exit != DVB_FE_DEVICE_REMOVED) 12264 drxj_close(demod); 12265 12266 kfree(demod->my_ext_attr); 12267 kfree(demod->my_common_attr); 12268 kfree(demod->my_i2c_dev_addr); 12269 kfree(demod); 12270 kfree(state); 12271 } 12272 12273 static const struct dvb_frontend_ops drx39xxj_ops; 12274 12275 struct dvb_frontend *drx39xxj_attach(struct i2c_adapter *i2c) 12276 { 12277 struct drx39xxj_state *state = NULL; 12278 struct i2c_device_addr *demod_addr = NULL; 12279 struct drx_common_attr *demod_comm_attr = NULL; 12280 struct drxj_data *demod_ext_attr = NULL; 12281 struct drx_demod_instance *demod = NULL; 12282 struct dtv_frontend_properties *p; 12283 int result; 12284 12285 /* allocate memory for the internal state */ 12286 state = kzalloc(sizeof(struct drx39xxj_state), GFP_KERNEL); 12287 if (state == NULL) 12288 goto error; 12289 12290 demod = kmemdup(&drxj_default_demod_g, 12291 sizeof(struct drx_demod_instance), GFP_KERNEL); 12292 if (demod == NULL) 12293 goto error; 12294 12295 demod_addr = kmemdup(&drxj_default_addr_g, 12296 sizeof(struct i2c_device_addr), GFP_KERNEL); 12297 if (demod_addr == NULL) 12298 goto error; 12299 12300 demod_comm_attr = kmemdup(&drxj_default_comm_attr_g, 12301 sizeof(struct drx_common_attr), GFP_KERNEL); 12302 if (demod_comm_attr == NULL) 12303 goto error; 12304 12305 demod_ext_attr = kmemdup(&drxj_data_g, sizeof(struct drxj_data), 12306 GFP_KERNEL); 12307 if (demod_ext_attr == NULL) 12308 goto error; 12309 12310 /* setup the state */ 12311 state->i2c = i2c; 12312 state->demod = demod; 12313 12314 /* setup the demod data */ 12315 demod->my_i2c_dev_addr = demod_addr; 12316 demod->my_common_attr = demod_comm_attr; 12317 demod->my_i2c_dev_addr->user_data = state; 12318 demod->my_common_attr->microcode_file = DRX39XX_MAIN_FIRMWARE; 12319 demod->my_common_attr->verify_microcode = true; 12320 demod->my_common_attr->intermediate_freq = 5000; 12321 demod->my_common_attr->current_power_mode = DRX_POWER_DOWN; 12322 demod->my_ext_attr = demod_ext_attr; 12323 ((struct drxj_data *)demod_ext_attr)->uio_sma_tx_mode = DRX_UIO_MODE_READWRITE; 12324 demod->i2c = i2c; 12325 12326 result = drxj_open(demod); 12327 if (result != 0) { 12328 pr_err("DRX open failed! Aborting\n"); 12329 goto error; 12330 } 12331 12332 /* create dvb_frontend */ 12333 memcpy(&state->frontend.ops, &drx39xxj_ops, 12334 sizeof(struct dvb_frontend_ops)); 12335 12336 state->frontend.demodulator_priv = state; 12337 12338 /* Initialize stats - needed for DVBv5 stats to work */ 12339 p = &state->frontend.dtv_property_cache; 12340 p->strength.len = 1; 12341 p->pre_bit_count.len = 1; 12342 p->pre_bit_error.len = 1; 12343 p->post_bit_count.len = 1; 12344 p->post_bit_error.len = 1; 12345 p->block_count.len = 1; 12346 p->block_error.len = 1; 12347 p->cnr.len = 1; 12348 12349 p->strength.stat[0].scale = FE_SCALE_RELATIVE; 12350 p->pre_bit_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE; 12351 p->pre_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE; 12352 p->post_bit_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE; 12353 p->post_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE; 12354 p->block_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE; 12355 p->block_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE; 12356 p->cnr.stat[0].scale = FE_SCALE_NOT_AVAILABLE; 12357 12358 return &state->frontend; 12359 12360 error: 12361 kfree(demod_ext_attr); 12362 kfree(demod_comm_attr); 12363 kfree(demod_addr); 12364 kfree(demod); 12365 kfree(state); 12366 12367 return NULL; 12368 } 12369 EXPORT_SYMBOL_GPL(drx39xxj_attach); 12370 12371 static const struct dvb_frontend_ops drx39xxj_ops = { 12372 .delsys = { SYS_ATSC, SYS_DVBC_ANNEX_B }, 12373 .info = { 12374 .name = "Micronas DRX39xxj family Frontend", 12375 .frequency_min_hz = 51 * MHz, 12376 .frequency_max_hz = 858 * MHz, 12377 .frequency_stepsize_hz = 62500, 12378 .caps = FE_CAN_QAM_64 | FE_CAN_QAM_256 | FE_CAN_8VSB 12379 }, 12380 12381 .init = drx39xxj_init, 12382 .i2c_gate_ctrl = drx39xxj_i2c_gate_ctrl, 12383 .sleep = drx39xxj_sleep, 12384 .set_frontend = drx39xxj_set_frontend, 12385 .get_tune_settings = drx39xxj_get_tune_settings, 12386 .read_status = drx39xxj_read_status, 12387 .read_ber = drx39xxj_read_ber, 12388 .read_signal_strength = drx39xxj_read_signal_strength, 12389 .read_snr = drx39xxj_read_snr, 12390 .read_ucblocks = drx39xxj_read_ucblocks, 12391 .release = drx39xxj_release, 12392 .set_lna = drx39xxj_set_lna, 12393 }; 12394 12395 MODULE_DESCRIPTION("Micronas DRX39xxj Frontend"); 12396 MODULE_AUTHOR("Devin Heitmueller"); 12397 MODULE_LICENSE("GPL"); 12398 MODULE_FIRMWARE(DRX39XX_MAIN_FIRMWARE); 12399