1 /* 2 Copyright (c), 2004-2005,2007-2010 Trident Microsystems, Inc. 3 All rights reserved. 4 5 Redistribution and use in source and binary forms, with or without 6 modification, are permitted provided that the following conditions are met: 7 8 * Redistributions of source code must retain the above copyright notice, 9 this list of conditions and the following disclaimer. 10 * Redistributions in binary form must reproduce the above copyright notice, 11 this list of conditions and the following disclaimer in the documentation 12 and/or other materials provided with the distribution. 13 * Neither the name of Trident Microsystems nor Hauppauge Computer Works 14 nor the names of its contributors may be used to endorse or promote 15 products derived from this software without specific prior written 16 permission. 17 18 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 19 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 22 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28 POSSIBILITY OF SUCH DAMAGE. 29 */ 30 31 #ifndef __DRXDRIVER_H__ 32 #define __DRXDRIVER_H__ 33 34 #include <linux/kernel.h> 35 #include <linux/errno.h> 36 #include <linux/firmware.h> 37 #include <linux/i2c.h> 38 39 /* 40 * This structure contains the I2C address, the device ID and a user_data pointer. 41 * The user_data pointer can be used for application specific purposes. 42 */ 43 struct i2c_device_addr { 44 u16 i2c_addr; /* The I2C address of the device. */ 45 u16 i2c_dev_id; /* The device identifier. */ 46 void *user_data; /* User data pointer */ 47 }; 48 49 /** 50 * \def IS_I2C_10BIT( addr ) 51 * \brief Determine if I2C address 'addr' is a 10 bits address or not. 52 * \param addr The I2C address. 53 * \return int. 54 * \retval 0 if address is not a 10 bits I2C address. 55 * \retval 1 if address is a 10 bits I2C address. 56 */ 57 #define IS_I2C_10BIT(addr) \ 58 (((addr) & 0xF8) == 0xF0) 59 60 /*------------------------------------------------------------------------------ 61 Exported FUNCTIONS 62 ------------------------------------------------------------------------------*/ 63 64 /** 65 * \fn drxbsp_i2c_init() 66 * \brief Initialize I2C communication module. 67 * \return int Return status. 68 * \retval 0 Initialization successful. 69 * \retval -EIO Initialization failed. 70 */ 71 int drxbsp_i2c_init(void); 72 73 /** 74 * \fn drxbsp_i2c_term() 75 * \brief Terminate I2C communication module. 76 * \return int Return status. 77 * \retval 0 Termination successful. 78 * \retval -EIO Termination failed. 79 */ 80 int drxbsp_i2c_term(void); 81 82 /** 83 * \fn int drxbsp_i2c_write_read( struct i2c_device_addr *w_dev_addr, 84 * u16 w_count, 85 * u8 * wData, 86 * struct i2c_device_addr *r_dev_addr, 87 * u16 r_count, 88 * u8 * r_data) 89 * \brief Read and/or write count bytes from I2C bus, store them in data[]. 90 * \param w_dev_addr The device i2c address and the device ID to write to 91 * \param w_count The number of bytes to write 92 * \param wData The array to write the data to 93 * \param r_dev_addr The device i2c address and the device ID to read from 94 * \param r_count The number of bytes to read 95 * \param r_data The array to read the data from 96 * \return int Return status. 97 * \retval 0 Succes. 98 * \retval -EIO Failure. 99 * \retval -EINVAL Parameter 'wcount' is not zero but parameter 100 * 'wdata' contains NULL. 101 * Idem for 'rcount' and 'rdata'. 102 * Both w_dev_addr and r_dev_addr are NULL. 103 * 104 * This function must implement an atomic write and/or read action on the I2C bus 105 * No other process may use the I2C bus when this function is executing. 106 * The critical section of this function runs from and including the I2C 107 * write, up to and including the I2C read action. 108 * 109 * The device ID can be useful if several devices share an I2C address. 110 * It can be used to control a "switch" on the I2C bus to the correct device. 111 */ 112 int drxbsp_i2c_write_read(struct i2c_device_addr *w_dev_addr, 113 u16 w_count, 114 u8 *wData, 115 struct i2c_device_addr *r_dev_addr, 116 u16 r_count, u8 *r_data); 117 118 /** 119 * \fn drxbsp_i2c_error_text() 120 * \brief Returns a human readable error. 121 * Counter part of numerical drx_i2c_error_g. 122 * 123 * \return char* Pointer to human readable error text. 124 */ 125 char *drxbsp_i2c_error_text(void); 126 127 /** 128 * \var drx_i2c_error_g; 129 * \brief I2C specific error codes, platform dependent. 130 */ 131 extern int drx_i2c_error_g; 132 133 #define TUNER_MODE_SUB0 0x0001 /* for sub-mode (e.g. RF-AGC setting) */ 134 #define TUNER_MODE_SUB1 0x0002 /* for sub-mode (e.g. RF-AGC setting) */ 135 #define TUNER_MODE_SUB2 0x0004 /* for sub-mode (e.g. RF-AGC setting) */ 136 #define TUNER_MODE_SUB3 0x0008 /* for sub-mode (e.g. RF-AGC setting) */ 137 #define TUNER_MODE_SUB4 0x0010 /* for sub-mode (e.g. RF-AGC setting) */ 138 #define TUNER_MODE_SUB5 0x0020 /* for sub-mode (e.g. RF-AGC setting) */ 139 #define TUNER_MODE_SUB6 0x0040 /* for sub-mode (e.g. RF-AGC setting) */ 140 #define TUNER_MODE_SUB7 0x0080 /* for sub-mode (e.g. RF-AGC setting) */ 141 142 #define TUNER_MODE_DIGITAL 0x0100 /* for digital channel (e.g. DVB-T) */ 143 #define TUNER_MODE_ANALOG 0x0200 /* for analog channel (e.g. PAL) */ 144 #define TUNER_MODE_SWITCH 0x0400 /* during channel switch & scanning */ 145 #define TUNER_MODE_LOCK 0x0800 /* after tuner has locked */ 146 #define TUNER_MODE_6MHZ 0x1000 /* for 6MHz bandwidth channels */ 147 #define TUNER_MODE_7MHZ 0x2000 /* for 7MHz bandwidth channels */ 148 #define TUNER_MODE_8MHZ 0x4000 /* for 8MHz bandwidth channels */ 149 150 #define TUNER_MODE_SUB_MAX 8 151 #define TUNER_MODE_SUBALL (TUNER_MODE_SUB0 | TUNER_MODE_SUB1 | \ 152 TUNER_MODE_SUB2 | TUNER_MODE_SUB3 | \ 153 TUNER_MODE_SUB4 | TUNER_MODE_SUB5 | \ 154 TUNER_MODE_SUB6 | TUNER_MODE_SUB7) 155 156 157 enum tuner_lock_status { 158 TUNER_LOCKED, 159 TUNER_NOT_LOCKED 160 }; 161 162 struct tuner_common { 163 char *name; /* Tuner brand & type name */ 164 s32 min_freq_rf; /* Lowest RF input frequency, in kHz */ 165 s32 max_freq_rf; /* Highest RF input frequency, in kHz */ 166 167 u8 sub_mode; /* Index to sub-mode in use */ 168 char ***sub_mode_descriptions; /* Pointer to description of sub-modes */ 169 u8 sub_modes; /* Number of available sub-modes */ 170 171 /* The following fields will be either 0, NULL or false and do not need 172 initialisation */ 173 void *self_check; /* gives proof of initialization */ 174 bool programmed; /* only valid if self_check is OK */ 175 s32 r_ffrequency; /* only valid if programmed */ 176 s32 i_ffrequency; /* only valid if programmed */ 177 178 void *my_user_data; /* pointer to associated demod instance */ 179 u16 my_capabilities; /* value for storing application flags */ 180 }; 181 182 struct tuner_instance; 183 184 typedef int(*tuner_open_func_t) (struct tuner_instance *tuner); 185 typedef int(*tuner_close_func_t) (struct tuner_instance *tuner); 186 187 typedef int(*tuner_set_frequency_func_t) (struct tuner_instance *tuner, 188 u32 mode, 189 s32 190 frequency); 191 192 typedef int(*tuner_get_frequency_func_t) (struct tuner_instance *tuner, 193 u32 mode, 194 s32 * 195 r_ffrequency, 196 s32 * 197 i_ffrequency); 198 199 typedef int(*tuner_lock_status_func_t) (struct tuner_instance *tuner, 200 enum tuner_lock_status * 201 lock_stat); 202 203 typedef int(*tune_ri2c_write_read_func_t) (struct tuner_instance *tuner, 204 struct i2c_device_addr * 205 w_dev_addr, u16 w_count, 206 u8 *wData, 207 struct i2c_device_addr * 208 r_dev_addr, u16 r_count, 209 u8 *r_data); 210 211 struct tuner_ops { 212 tuner_open_func_t open_func; 213 tuner_close_func_t close_func; 214 tuner_set_frequency_func_t set_frequency_func; 215 tuner_get_frequency_func_t get_frequency_func; 216 tuner_lock_status_func_t lock_status_func; 217 tune_ri2c_write_read_func_t i2c_write_read_func; 218 219 }; 220 221 struct tuner_instance { 222 struct i2c_device_addr my_i2c_dev_addr; 223 struct tuner_common *my_common_attr; 224 void *my_ext_attr; 225 struct tuner_ops *my_funct; 226 }; 227 228 int drxbsp_tuner_set_frequency(struct tuner_instance *tuner, 229 u32 mode, 230 s32 frequency); 231 232 int drxbsp_tuner_get_frequency(struct tuner_instance *tuner, 233 u32 mode, 234 s32 *r_ffrequency, 235 s32 *i_ffrequency); 236 237 int drxbsp_tuner_default_i2c_write_read(struct tuner_instance *tuner, 238 struct i2c_device_addr *w_dev_addr, 239 u16 w_count, 240 u8 *wData, 241 struct i2c_device_addr *r_dev_addr, 242 u16 r_count, u8 *r_data); 243 244 /************** 245 * 246 * This section configures the DRX Data Access Protocols (DAPs). 247 * 248 **************/ 249 250 /** 251 * \def DRXDAP_SINGLE_MASTER 252 * \brief Enable I2C single or I2C multimaster mode on host. 253 * 254 * Set to 1 to enable single master mode 255 * Set to 0 to enable multi master mode 256 * 257 * The actual DAP implementation may be restricted to only one of the modes. 258 * A compiler warning or error will be generated if the DAP implementation 259 * overrides or cannot handle the mode defined below. 260 */ 261 #ifndef DRXDAP_SINGLE_MASTER 262 #define DRXDAP_SINGLE_MASTER 1 263 #endif 264 265 /** 266 * \def DRXDAP_MAX_WCHUNKSIZE 267 * \brief Defines maximum chunksize of an i2c write action by host. 268 * 269 * This indicates the maximum size of data the I2C device driver is able to 270 * write at a time. This includes I2C device address and register addressing. 271 * 272 * This maximum size may be restricted by the actual DAP implementation. 273 * A compiler warning or error will be generated if the DAP implementation 274 * overrides or cannot handle the chunksize defined below. 275 * 276 * Beware that the DAP uses DRXDAP_MAX_WCHUNKSIZE to create a temporary data 277 * buffer. Do not undefine or choose too large, unless your system is able to 278 * handle a stack buffer of that size. 279 * 280 */ 281 #ifndef DRXDAP_MAX_WCHUNKSIZE 282 #define DRXDAP_MAX_WCHUNKSIZE 60 283 #endif 284 285 /** 286 * \def DRXDAP_MAX_RCHUNKSIZE 287 * \brief Defines maximum chunksize of an i2c read action by host. 288 * 289 * This indicates the maximum size of data the I2C device driver is able to read 290 * at a time. Minimum value is 2. Also, the read chunk size must be even. 291 * 292 * This maximum size may be restricted by the actual DAP implementation. 293 * A compiler warning or error will be generated if the DAP implementation 294 * overrides or cannot handle the chunksize defined below. 295 */ 296 #ifndef DRXDAP_MAX_RCHUNKSIZE 297 #define DRXDAP_MAX_RCHUNKSIZE 60 298 #endif 299 300 /************** 301 * 302 * This section describes drxdriver defines. 303 * 304 **************/ 305 306 /** 307 * \def DRX_UNKNOWN 308 * \brief Generic UNKNOWN value for DRX enumerated types. 309 * 310 * Used to indicate that the parameter value is unknown or not yet initalized. 311 */ 312 #ifndef DRX_UNKNOWN 313 #define DRX_UNKNOWN (254) 314 #endif 315 316 /** 317 * \def DRX_AUTO 318 * \brief Generic AUTO value for DRX enumerated types. 319 * 320 * Used to instruct the driver to automatically determine the value of the 321 * parameter. 322 */ 323 #ifndef DRX_AUTO 324 #define DRX_AUTO (255) 325 #endif 326 327 /************** 328 * 329 * This section describes flag definitions for the device capbilities. 330 * 331 **************/ 332 333 /** 334 * \brief LNA capability flag 335 * 336 * Device has a Low Noise Amplifier 337 * 338 */ 339 #define DRX_CAPABILITY_HAS_LNA (1UL << 0) 340 /** 341 * \brief OOB-RX capability flag 342 * 343 * Device has OOB-RX 344 * 345 */ 346 #define DRX_CAPABILITY_HAS_OOBRX (1UL << 1) 347 /** 348 * \brief ATV capability flag 349 * 350 * Device has ATV 351 * 352 */ 353 #define DRX_CAPABILITY_HAS_ATV (1UL << 2) 354 /** 355 * \brief DVB-T capability flag 356 * 357 * Device has DVB-T 358 * 359 */ 360 #define DRX_CAPABILITY_HAS_DVBT (1UL << 3) 361 /** 362 * \brief ITU-B capability flag 363 * 364 * Device has ITU-B 365 * 366 */ 367 #define DRX_CAPABILITY_HAS_ITUB (1UL << 4) 368 /** 369 * \brief Audio capability flag 370 * 371 * Device has Audio 372 * 373 */ 374 #define DRX_CAPABILITY_HAS_AUD (1UL << 5) 375 /** 376 * \brief SAW switch capability flag 377 * 378 * Device has SAW switch 379 * 380 */ 381 #define DRX_CAPABILITY_HAS_SAWSW (1UL << 6) 382 /** 383 * \brief GPIO1 capability flag 384 * 385 * Device has GPIO1 386 * 387 */ 388 #define DRX_CAPABILITY_HAS_GPIO1 (1UL << 7) 389 /** 390 * \brief GPIO2 capability flag 391 * 392 * Device has GPIO2 393 * 394 */ 395 #define DRX_CAPABILITY_HAS_GPIO2 (1UL << 8) 396 /** 397 * \brief IRQN capability flag 398 * 399 * Device has IRQN 400 * 401 */ 402 #define DRX_CAPABILITY_HAS_IRQN (1UL << 9) 403 /** 404 * \brief 8VSB capability flag 405 * 406 * Device has 8VSB 407 * 408 */ 409 #define DRX_CAPABILITY_HAS_8VSB (1UL << 10) 410 /** 411 * \brief SMA-TX capability flag 412 * 413 * Device has SMATX 414 * 415 */ 416 #define DRX_CAPABILITY_HAS_SMATX (1UL << 11) 417 /** 418 * \brief SMA-RX capability flag 419 * 420 * Device has SMARX 421 * 422 */ 423 #define DRX_CAPABILITY_HAS_SMARX (1UL << 12) 424 /** 425 * \brief ITU-A/C capability flag 426 * 427 * Device has ITU-A/C 428 * 429 */ 430 #define DRX_CAPABILITY_HAS_ITUAC (1UL << 13) 431 432 /*------------------------------------------------------------------------- 433 MACROS 434 -------------------------------------------------------------------------*/ 435 /* Macros to stringify the version number */ 436 #define DRX_VERSIONSTRING(MAJOR, MINOR, PATCH) \ 437 DRX_VERSIONSTRING_HELP(MAJOR)"." \ 438 DRX_VERSIONSTRING_HELP(MINOR)"." \ 439 DRX_VERSIONSTRING_HELP(PATCH) 440 #define DRX_VERSIONSTRING_HELP(NUM) #NUM 441 442 /** 443 * \brief Macro to create byte array elements from 16 bit integers. 444 * This macro is used to create byte arrays for block writes. 445 * Block writes speed up I2C traffic between host and demod. 446 * The macro takes care of the required byte order in a 16 bits word. 447 * x->lowbyte(x), highbyte(x) 448 */ 449 #define DRX_16TO8(x) ((u8) (((u16)x) & 0xFF)), \ 450 ((u8)((((u16)x)>>8)&0xFF)) 451 452 /** 453 * \brief Macro to sign extend signed 9 bit value to signed 16 bit value 454 */ 455 #define DRX_S9TOS16(x) ((((u16)x)&0x100) ? ((s16)((u16)(x)|0xFF00)) : (x)) 456 457 /** 458 * \brief Macro to sign extend signed 9 bit value to signed 16 bit value 459 */ 460 #define DRX_S24TODRXFREQ(x) ((((u32) x) & 0x00800000UL) ? \ 461 ((s32) \ 462 (((u32) x) | 0xFF000000)) : \ 463 ((s32) x)) 464 465 /** 466 * \brief Macro to convert 16 bit register value to a s32 467 */ 468 #define DRX_U16TODRXFREQ(x) ((x & 0x8000) ? \ 469 ((s32) \ 470 (((u32) x) | 0xFFFF0000)) : \ 471 ((s32) x)) 472 473 /*------------------------------------------------------------------------- 474 ENUM 475 -------------------------------------------------------------------------*/ 476 477 /** 478 * \enum enum drx_standard 479 * \brief Modulation standards. 480 */ 481 enum drx_standard { 482 DRX_STANDARD_DVBT = 0, /**< Terrestrial DVB-T. */ 483 DRX_STANDARD_8VSB, /**< Terrestrial 8VSB. */ 484 DRX_STANDARD_NTSC, /**< Terrestrial\Cable analog NTSC. */ 485 DRX_STANDARD_PAL_SECAM_BG, 486 /**< Terrestrial analog PAL/SECAM B/G */ 487 DRX_STANDARD_PAL_SECAM_DK, 488 /**< Terrestrial analog PAL/SECAM D/K */ 489 DRX_STANDARD_PAL_SECAM_I, 490 /**< Terrestrial analog PAL/SECAM I */ 491 DRX_STANDARD_PAL_SECAM_L, 492 /**< Terrestrial analog PAL/SECAM L 493 with negative modulation */ 494 DRX_STANDARD_PAL_SECAM_LP, 495 /**< Terrestrial analog PAL/SECAM L 496 with positive modulation */ 497 DRX_STANDARD_ITU_A, /**< Cable ITU ANNEX A. */ 498 DRX_STANDARD_ITU_B, /**< Cable ITU ANNEX B. */ 499 DRX_STANDARD_ITU_C, /**< Cable ITU ANNEX C. */ 500 DRX_STANDARD_ITU_D, /**< Cable ITU ANNEX D. */ 501 DRX_STANDARD_FM, /**< Terrestrial\Cable FM radio */ 502 DRX_STANDARD_DTMB, /**< Terrestrial DTMB standard (China)*/ 503 DRX_STANDARD_UNKNOWN = DRX_UNKNOWN, 504 /**< Standard unknown. */ 505 DRX_STANDARD_AUTO = DRX_AUTO 506 /**< Autodetect standard. */ 507 }; 508 509 /** 510 * \enum enum drx_standard 511 * \brief Modulation sub-standards. 512 */ 513 enum drx_substandard { 514 DRX_SUBSTANDARD_MAIN = 0, /**< Main subvariant of standard */ 515 DRX_SUBSTANDARD_ATV_BG_SCANDINAVIA, 516 DRX_SUBSTANDARD_ATV_DK_POLAND, 517 DRX_SUBSTANDARD_ATV_DK_CHINA, 518 DRX_SUBSTANDARD_UNKNOWN = DRX_UNKNOWN, 519 /**< Sub-standard unknown. */ 520 DRX_SUBSTANDARD_AUTO = DRX_AUTO 521 /**< Auto (default) sub-standard */ 522 }; 523 524 /** 525 * \enum enum drx_bandwidth 526 * \brief Channel bandwidth or channel spacing. 527 */ 528 enum drx_bandwidth { 529 DRX_BANDWIDTH_8MHZ = 0, /**< Bandwidth 8 MHz. */ 530 DRX_BANDWIDTH_7MHZ, /**< Bandwidth 7 MHz. */ 531 DRX_BANDWIDTH_6MHZ, /**< Bandwidth 6 MHz. */ 532 DRX_BANDWIDTH_UNKNOWN = DRX_UNKNOWN, 533 /**< Bandwidth unknown. */ 534 DRX_BANDWIDTH_AUTO = DRX_AUTO 535 /**< Auto Set Bandwidth */ 536 }; 537 538 /** 539 * \enum enum drx_mirror 540 * \brief Indicate if channel spectrum is mirrored or not. 541 */ 542 enum drx_mirror { 543 DRX_MIRROR_NO = 0, /**< Spectrum is not mirrored. */ 544 DRX_MIRROR_YES, /**< Spectrum is mirrored. */ 545 DRX_MIRROR_UNKNOWN = DRX_UNKNOWN, 546 /**< Unknown if spectrum is mirrored. */ 547 DRX_MIRROR_AUTO = DRX_AUTO 548 /**< Autodetect if spectrum is mirrored. */ 549 }; 550 551 /** 552 * \enum enum drx_modulation 553 * \brief Constellation type of the channel. 554 */ 555 enum drx_modulation { 556 DRX_CONSTELLATION_BPSK = 0, /**< Modulation is BPSK. */ 557 DRX_CONSTELLATION_QPSK, /**< Constellation is QPSK. */ 558 DRX_CONSTELLATION_PSK8, /**< Constellation is PSK8. */ 559 DRX_CONSTELLATION_QAM16, /**< Constellation is QAM16. */ 560 DRX_CONSTELLATION_QAM32, /**< Constellation is QAM32. */ 561 DRX_CONSTELLATION_QAM64, /**< Constellation is QAM64. */ 562 DRX_CONSTELLATION_QAM128, /**< Constellation is QAM128. */ 563 DRX_CONSTELLATION_QAM256, /**< Constellation is QAM256. */ 564 DRX_CONSTELLATION_QAM512, /**< Constellation is QAM512. */ 565 DRX_CONSTELLATION_QAM1024, /**< Constellation is QAM1024. */ 566 DRX_CONSTELLATION_QPSK_NR, /**< Constellation is QPSK_NR */ 567 DRX_CONSTELLATION_UNKNOWN = DRX_UNKNOWN, 568 /**< Constellation unknown. */ 569 DRX_CONSTELLATION_AUTO = DRX_AUTO 570 /**< Autodetect constellation. */ 571 }; 572 573 /** 574 * \enum enum drx_hierarchy 575 * \brief Hierarchy of the channel. 576 */ 577 enum drx_hierarchy { 578 DRX_HIERARCHY_NONE = 0, /**< None hierarchical channel. */ 579 DRX_HIERARCHY_ALPHA1, /**< Hierarchical channel, alpha=1. */ 580 DRX_HIERARCHY_ALPHA2, /**< Hierarchical channel, alpha=2. */ 581 DRX_HIERARCHY_ALPHA4, /**< Hierarchical channel, alpha=4. */ 582 DRX_HIERARCHY_UNKNOWN = DRX_UNKNOWN, 583 /**< Hierarchy unknown. */ 584 DRX_HIERARCHY_AUTO = DRX_AUTO 585 /**< Autodetect hierarchy. */ 586 }; 587 588 /** 589 * \enum enum drx_priority 590 * \brief Channel priority in case of hierarchical transmission. 591 */ 592 enum drx_priority { 593 DRX_PRIORITY_LOW = 0, /**< Low priority channel. */ 594 DRX_PRIORITY_HIGH, /**< High priority channel. */ 595 DRX_PRIORITY_UNKNOWN = DRX_UNKNOWN 596 /**< Priority unknown. */ 597 }; 598 599 /** 600 * \enum enum drx_coderate 601 * \brief Channel priority in case of hierarchical transmission. 602 */ 603 enum drx_coderate { 604 DRX_CODERATE_1DIV2 = 0, /**< Code rate 1/2nd. */ 605 DRX_CODERATE_2DIV3, /**< Code rate 2/3nd. */ 606 DRX_CODERATE_3DIV4, /**< Code rate 3/4nd. */ 607 DRX_CODERATE_5DIV6, /**< Code rate 5/6nd. */ 608 DRX_CODERATE_7DIV8, /**< Code rate 7/8nd. */ 609 DRX_CODERATE_UNKNOWN = DRX_UNKNOWN, 610 /**< Code rate unknown. */ 611 DRX_CODERATE_AUTO = DRX_AUTO 612 /**< Autodetect code rate. */ 613 }; 614 615 /** 616 * \enum enum drx_guard 617 * \brief Guard interval of a channel. 618 */ 619 enum drx_guard { 620 DRX_GUARD_1DIV32 = 0, /**< Guard interval 1/32nd. */ 621 DRX_GUARD_1DIV16, /**< Guard interval 1/16th. */ 622 DRX_GUARD_1DIV8, /**< Guard interval 1/8th. */ 623 DRX_GUARD_1DIV4, /**< Guard interval 1/4th. */ 624 DRX_GUARD_UNKNOWN = DRX_UNKNOWN, 625 /**< Guard interval unknown. */ 626 DRX_GUARD_AUTO = DRX_AUTO 627 /**< Autodetect guard interval. */ 628 }; 629 630 /** 631 * \enum enum drx_fft_mode 632 * \brief FFT mode. 633 */ 634 enum drx_fft_mode { 635 DRX_FFTMODE_2K = 0, /**< 2K FFT mode. */ 636 DRX_FFTMODE_4K, /**< 4K FFT mode. */ 637 DRX_FFTMODE_8K, /**< 8K FFT mode. */ 638 DRX_FFTMODE_UNKNOWN = DRX_UNKNOWN, 639 /**< FFT mode unknown. */ 640 DRX_FFTMODE_AUTO = DRX_AUTO 641 /**< Autodetect FFT mode. */ 642 }; 643 644 /** 645 * \enum enum drx_classification 646 * \brief Channel classification. 647 */ 648 enum drx_classification { 649 DRX_CLASSIFICATION_GAUSS = 0, /**< Gaussion noise. */ 650 DRX_CLASSIFICATION_HVY_GAUSS, /**< Heavy Gaussion noise. */ 651 DRX_CLASSIFICATION_COCHANNEL, /**< Co-channel. */ 652 DRX_CLASSIFICATION_STATIC, /**< Static echo. */ 653 DRX_CLASSIFICATION_MOVING, /**< Moving echo. */ 654 DRX_CLASSIFICATION_ZERODB, /**< Zero dB echo. */ 655 DRX_CLASSIFICATION_UNKNOWN = DRX_UNKNOWN, 656 /**< Unknown classification */ 657 DRX_CLASSIFICATION_AUTO = DRX_AUTO 658 /**< Autodetect classification. */ 659 }; 660 661 /** 662 * /enum enum drx_interleave_mode 663 * /brief Interleave modes 664 */ 665 enum drx_interleave_mode { 666 DRX_INTERLEAVEMODE_I128_J1 = 0, 667 DRX_INTERLEAVEMODE_I128_J1_V2, 668 DRX_INTERLEAVEMODE_I128_J2, 669 DRX_INTERLEAVEMODE_I64_J2, 670 DRX_INTERLEAVEMODE_I128_J3, 671 DRX_INTERLEAVEMODE_I32_J4, 672 DRX_INTERLEAVEMODE_I128_J4, 673 DRX_INTERLEAVEMODE_I16_J8, 674 DRX_INTERLEAVEMODE_I128_J5, 675 DRX_INTERLEAVEMODE_I8_J16, 676 DRX_INTERLEAVEMODE_I128_J6, 677 DRX_INTERLEAVEMODE_RESERVED_11, 678 DRX_INTERLEAVEMODE_I128_J7, 679 DRX_INTERLEAVEMODE_RESERVED_13, 680 DRX_INTERLEAVEMODE_I128_J8, 681 DRX_INTERLEAVEMODE_RESERVED_15, 682 DRX_INTERLEAVEMODE_I12_J17, 683 DRX_INTERLEAVEMODE_I5_J4, 684 DRX_INTERLEAVEMODE_B52_M240, 685 DRX_INTERLEAVEMODE_B52_M720, 686 DRX_INTERLEAVEMODE_B52_M48, 687 DRX_INTERLEAVEMODE_B52_M0, 688 DRX_INTERLEAVEMODE_UNKNOWN = DRX_UNKNOWN, 689 /**< Unknown interleave mode */ 690 DRX_INTERLEAVEMODE_AUTO = DRX_AUTO 691 /**< Autodetect interleave mode */ 692 }; 693 694 /** 695 * \enum enum drx_carrier_mode 696 * \brief Channel Carrier Mode. 697 */ 698 enum drx_carrier_mode { 699 DRX_CARRIER_MULTI = 0, /**< Multi carrier mode */ 700 DRX_CARRIER_SINGLE, /**< Single carrier mode */ 701 DRX_CARRIER_UNKNOWN = DRX_UNKNOWN, 702 /**< Carrier mode unknown. */ 703 DRX_CARRIER_AUTO = DRX_AUTO /**< Autodetect carrier mode */ 704 }; 705 706 /** 707 * \enum enum drx_frame_mode 708 * \brief Channel Frame Mode. 709 */ 710 enum drx_frame_mode { 711 DRX_FRAMEMODE_420 = 0, /**< 420 with variable PN */ 712 DRX_FRAMEMODE_595, /**< 595 */ 713 DRX_FRAMEMODE_945, /**< 945 with variable PN */ 714 DRX_FRAMEMODE_420_FIXED_PN, 715 /**< 420 with fixed PN */ 716 DRX_FRAMEMODE_945_FIXED_PN, 717 /**< 945 with fixed PN */ 718 DRX_FRAMEMODE_UNKNOWN = DRX_UNKNOWN, 719 /**< Frame mode unknown. */ 720 DRX_FRAMEMODE_AUTO = DRX_AUTO 721 /**< Autodetect frame mode */ 722 }; 723 724 /** 725 * \enum enum drx_tps_frame 726 * \brief Frame number in current super-frame. 727 */ 728 enum drx_tps_frame { 729 DRX_TPS_FRAME1 = 0, /**< TPS frame 1. */ 730 DRX_TPS_FRAME2, /**< TPS frame 2. */ 731 DRX_TPS_FRAME3, /**< TPS frame 3. */ 732 DRX_TPS_FRAME4, /**< TPS frame 4. */ 733 DRX_TPS_FRAME_UNKNOWN = DRX_UNKNOWN 734 /**< TPS frame unknown. */ 735 }; 736 737 /** 738 * \enum enum drx_ldpc 739 * \brief TPS LDPC . 740 */ 741 enum drx_ldpc { 742 DRX_LDPC_0_4 = 0, /**< LDPC 0.4 */ 743 DRX_LDPC_0_6, /**< LDPC 0.6 */ 744 DRX_LDPC_0_8, /**< LDPC 0.8 */ 745 DRX_LDPC_UNKNOWN = DRX_UNKNOWN, 746 /**< LDPC unknown. */ 747 DRX_LDPC_AUTO = DRX_AUTO /**< Autodetect LDPC */ 748 }; 749 750 /** 751 * \enum enum drx_pilot_mode 752 * \brief Pilot modes in DTMB. 753 */ 754 enum drx_pilot_mode { 755 DRX_PILOT_ON = 0, /**< Pilot On */ 756 DRX_PILOT_OFF, /**< Pilot Off */ 757 DRX_PILOT_UNKNOWN = DRX_UNKNOWN, 758 /**< Pilot unknown. */ 759 DRX_PILOT_AUTO = DRX_AUTO /**< Autodetect Pilot */ 760 }; 761 762 /** 763 * enum drxu_code_action - indicate if firmware has to be uploaded or verified. 764 * @UCODE_UPLOAD: Upload the microcode image to device 765 * @UCODE_VERIFY: Compare microcode image with code on device 766 */ 767 enum drxu_code_action { 768 UCODE_UPLOAD, 769 UCODE_VERIFY 770 }; 771 772 /** 773 * \enum enum drx_lock_status * \brief Used to reflect current lock status of demodulator. 774 * 775 * The generic lock states have device dependent semantics. 776 777 DRX_NEVER_LOCK = 0, 778 **< Device will never lock on this signal * 779 DRX_NOT_LOCKED, 780 **< Device has no lock at all * 781 DRX_LOCK_STATE_1, 782 **< Generic lock state * 783 DRX_LOCK_STATE_2, 784 **< Generic lock state * 785 DRX_LOCK_STATE_3, 786 **< Generic lock state * 787 DRX_LOCK_STATE_4, 788 **< Generic lock state * 789 DRX_LOCK_STATE_5, 790 **< Generic lock state * 791 DRX_LOCK_STATE_6, 792 **< Generic lock state * 793 DRX_LOCK_STATE_7, 794 **< Generic lock state * 795 DRX_LOCK_STATE_8, 796 **< Generic lock state * 797 DRX_LOCK_STATE_9, 798 **< Generic lock state * 799 DRX_LOCKED **< Device is in lock * 800 */ 801 802 enum drx_lock_status { 803 DRX_NEVER_LOCK = 0, 804 DRX_NOT_LOCKED, 805 DRX_LOCK_STATE_1, 806 DRX_LOCK_STATE_2, 807 DRX_LOCK_STATE_3, 808 DRX_LOCK_STATE_4, 809 DRX_LOCK_STATE_5, 810 DRX_LOCK_STATE_6, 811 DRX_LOCK_STATE_7, 812 DRX_LOCK_STATE_8, 813 DRX_LOCK_STATE_9, 814 DRX_LOCKED 815 }; 816 817 /** 818 * \enum enum drx_uio* \brief Used to address a User IO (UIO). 819 */ 820 enum drx_uio { 821 DRX_UIO1, 822 DRX_UIO2, 823 DRX_UIO3, 824 DRX_UIO4, 825 DRX_UIO5, 826 DRX_UIO6, 827 DRX_UIO7, 828 DRX_UIO8, 829 DRX_UIO9, 830 DRX_UIO10, 831 DRX_UIO11, 832 DRX_UIO12, 833 DRX_UIO13, 834 DRX_UIO14, 835 DRX_UIO15, 836 DRX_UIO16, 837 DRX_UIO17, 838 DRX_UIO18, 839 DRX_UIO19, 840 DRX_UIO20, 841 DRX_UIO21, 842 DRX_UIO22, 843 DRX_UIO23, 844 DRX_UIO24, 845 DRX_UIO25, 846 DRX_UIO26, 847 DRX_UIO27, 848 DRX_UIO28, 849 DRX_UIO29, 850 DRX_UIO30, 851 DRX_UIO31, 852 DRX_UIO32, 853 DRX_UIO_MAX = DRX_UIO32 854 }; 855 856 /** 857 * \enum enum drxuio_mode * \brief Used to configure the modus oprandi of a UIO. 858 * 859 * DRX_UIO_MODE_FIRMWARE is an old uio mode. 860 * It is replaced by the modes DRX_UIO_MODE_FIRMWARE0 .. DRX_UIO_MODE_FIRMWARE9. 861 * To be backward compatible DRX_UIO_MODE_FIRMWARE is equivalent to 862 * DRX_UIO_MODE_FIRMWARE0. 863 */ 864 enum drxuio_mode { 865 DRX_UIO_MODE_DISABLE = 0x01, 866 /**< not used, pin is configured as input */ 867 DRX_UIO_MODE_READWRITE = 0x02, 868 /**< used for read/write by application */ 869 DRX_UIO_MODE_FIRMWARE = 0x04, 870 /**< controlled by firmware, function 0 */ 871 DRX_UIO_MODE_FIRMWARE0 = DRX_UIO_MODE_FIRMWARE, 872 /**< same as above */ 873 DRX_UIO_MODE_FIRMWARE1 = 0x08, 874 /**< controlled by firmware, function 1 */ 875 DRX_UIO_MODE_FIRMWARE2 = 0x10, 876 /**< controlled by firmware, function 2 */ 877 DRX_UIO_MODE_FIRMWARE3 = 0x20, 878 /**< controlled by firmware, function 3 */ 879 DRX_UIO_MODE_FIRMWARE4 = 0x40, 880 /**< controlled by firmware, function 4 */ 881 DRX_UIO_MODE_FIRMWARE5 = 0x80 882 /**< controlled by firmware, function 5 */ 883 }; 884 885 /** 886 * \enum enum drxoob_downstream_standard * \brief Used to select OOB standard. 887 * 888 * Based on ANSI 55-1 and 55-2 889 */ 890 enum drxoob_downstream_standard { 891 DRX_OOB_MODE_A = 0, 892 /**< ANSI 55-1 */ 893 DRX_OOB_MODE_B_GRADE_A, 894 /**< ANSI 55-2 A */ 895 DRX_OOB_MODE_B_GRADE_B 896 /**< ANSI 55-2 B */ 897 }; 898 899 /*------------------------------------------------------------------------- 900 STRUCTS 901 -------------------------------------------------------------------------*/ 902 903 /*============================================================================*/ 904 /*============================================================================*/ 905 /*== CTRL CFG related data structures ========================================*/ 906 /*============================================================================*/ 907 /*============================================================================*/ 908 909 #ifndef DRX_CFG_BASE 910 #define DRX_CFG_BASE 0 911 #endif 912 913 #define DRX_CFG_MPEG_OUTPUT (DRX_CFG_BASE + 0) /* MPEG TS output */ 914 #define DRX_CFG_PKTERR (DRX_CFG_BASE + 1) /* Packet Error */ 915 #define DRX_CFG_SYMCLK_OFFS (DRX_CFG_BASE + 2) /* Symbol Clk Offset */ 916 #define DRX_CFG_SMA (DRX_CFG_BASE + 3) /* Smart Antenna */ 917 #define DRX_CFG_PINSAFE (DRX_CFG_BASE + 4) /* Pin safe mode */ 918 #define DRX_CFG_SUBSTANDARD (DRX_CFG_BASE + 5) /* substandard */ 919 #define DRX_CFG_AUD_VOLUME (DRX_CFG_BASE + 6) /* volume */ 920 #define DRX_CFG_AUD_RDS (DRX_CFG_BASE + 7) /* rds */ 921 #define DRX_CFG_AUD_AUTOSOUND (DRX_CFG_BASE + 8) /* ASS & ASC */ 922 #define DRX_CFG_AUD_ASS_THRES (DRX_CFG_BASE + 9) /* ASS Thresholds */ 923 #define DRX_CFG_AUD_DEVIATION (DRX_CFG_BASE + 10) /* Deviation */ 924 #define DRX_CFG_AUD_PRESCALE (DRX_CFG_BASE + 11) /* Prescale */ 925 #define DRX_CFG_AUD_MIXER (DRX_CFG_BASE + 12) /* Mixer */ 926 #define DRX_CFG_AUD_AVSYNC (DRX_CFG_BASE + 13) /* AVSync */ 927 #define DRX_CFG_AUD_CARRIER (DRX_CFG_BASE + 14) /* Audio carriers */ 928 #define DRX_CFG_I2S_OUTPUT (DRX_CFG_BASE + 15) /* I2S output */ 929 #define DRX_CFG_ATV_STANDARD (DRX_CFG_BASE + 16) /* ATV standard */ 930 #define DRX_CFG_SQI_SPEED (DRX_CFG_BASE + 17) /* SQI speed */ 931 #define DRX_CTRL_CFG_MAX (DRX_CFG_BASE + 18) /* never to be used */ 932 933 #define DRX_CFG_PINS_SAFE_MODE DRX_CFG_PINSAFE 934 /*============================================================================*/ 935 /*============================================================================*/ 936 /*== CTRL related data structures ============================================*/ 937 /*============================================================================*/ 938 /*============================================================================*/ 939 940 /** 941 * struct drxu_code_info Parameters for microcode upload and verfiy. 942 * 943 * @mc_file: microcode file name 944 * 945 * Used by DRX_CTRL_LOAD_UCODE and DRX_CTRL_VERIFY_UCODE 946 */ 947 struct drxu_code_info { 948 char *mc_file; 949 }; 950 951 /** 952 * \struct drx_mc_version_rec_t 953 * \brief Microcode version record 954 * Version numbers are stored in BCD format, as usual: 955 * o major number = bits 31-20 (first three nibbles of MSW) 956 * o minor number = bits 19-16 (fourth nibble of MSW) 957 * o patch number = bits 15-0 (remaining nibbles in LSW) 958 * 959 * The device type indicates for which the device is meant. It is based on the 960 * JTAG ID, using everything except the bond ID and the metal fix. 961 * 962 * Special values: 963 * - mc_dev_type == 0 => any device allowed 964 * - mc_base_version == 0.0.0 => full microcode (mc_version is the version) 965 * - mc_base_version != 0.0.0 => patch microcode, the base microcode version 966 * (mc_version is the version) 967 */ 968 #define AUX_VER_RECORD 0x8000 969 970 struct drx_mc_version_rec { 971 u16 aux_type; /* type of aux data - 0x8000 for version record */ 972 u32 mc_dev_type; /* device type, based on JTAG ID */ 973 u32 mc_version; /* version of microcode */ 974 u32 mc_base_version; /* in case of patch: the original microcode version */ 975 }; 976 977 /*========================================*/ 978 979 /** 980 * \struct drx_filter_info_t 981 * \brief Parameters for loading filter coefficients 982 * 983 * Used by DRX_CTRL_LOAD_FILTER 984 */ 985 struct drx_filter_info { 986 u8 *data_re; 987 /**< pointer to coefficients for RE */ 988 u8 *data_im; 989 /**< pointer to coefficients for IM */ 990 u16 size_re; 991 /**< size of coefficients for RE */ 992 u16 size_im; 993 /**< size of coefficients for IM */ 994 }; 995 996 /*========================================*/ 997 998 /** 999 * \struct struct drx_channel * \brief The set of parameters describing a single channel. 1000 * 1001 * Used by DRX_CTRL_SET_CHANNEL and DRX_CTRL_GET_CHANNEL. 1002 * Only certain fields need to be used for a specfic standard. 1003 * 1004 */ 1005 struct drx_channel { 1006 s32 frequency; 1007 /**< frequency in kHz */ 1008 enum drx_bandwidth bandwidth; 1009 /**< bandwidth */ 1010 enum drx_mirror mirror; /**< mirrored or not on RF */ 1011 enum drx_modulation constellation; 1012 /**< constellation */ 1013 enum drx_hierarchy hierarchy; 1014 /**< hierarchy */ 1015 enum drx_priority priority; /**< priority */ 1016 enum drx_coderate coderate; /**< coderate */ 1017 enum drx_guard guard; /**< guard interval */ 1018 enum drx_fft_mode fftmode; /**< fftmode */ 1019 enum drx_classification classification; 1020 /**< classification */ 1021 u32 symbolrate; 1022 /**< symbolrate in symbols/sec */ 1023 enum drx_interleave_mode interleavemode; 1024 /**< interleaveMode QAM */ 1025 enum drx_ldpc ldpc; /**< ldpc */ 1026 enum drx_carrier_mode carrier; /**< carrier */ 1027 enum drx_frame_mode framemode; 1028 /**< frame mode */ 1029 enum drx_pilot_mode pilot; /**< pilot mode */ 1030 }; 1031 1032 /*========================================*/ 1033 1034 enum drx_cfg_sqi_speed { 1035 DRX_SQI_SPEED_FAST = 0, 1036 DRX_SQI_SPEED_MEDIUM, 1037 DRX_SQI_SPEED_SLOW, 1038 DRX_SQI_SPEED_UNKNOWN = DRX_UNKNOWN 1039 }; 1040 1041 /*========================================*/ 1042 1043 /** 1044 * \struct struct drx_complex * A complex number. 1045 * 1046 * Used by DRX_CTRL_CONSTEL. 1047 */ 1048 struct drx_complex { 1049 s16 im; 1050 /**< Imaginary part. */ 1051 s16 re; 1052 /**< Real part. */ 1053 }; 1054 1055 /*========================================*/ 1056 1057 /** 1058 * \struct struct drx_frequency_plan * Array element of a frequency plan. 1059 * 1060 * Used by DRX_CTRL_SCAN_INIT. 1061 */ 1062 struct drx_frequency_plan { 1063 s32 first; 1064 /**< First centre frequency in this band */ 1065 s32 last; 1066 /**< Last centre frequency in this band */ 1067 s32 step; 1068 /**< Stepping frequency in this band */ 1069 enum drx_bandwidth bandwidth; 1070 /**< Bandwidth within this frequency band */ 1071 u16 ch_number; 1072 /**< First channel number in this band, or first 1073 index in ch_names */ 1074 char **ch_names; 1075 /**< Optional list of channel names in this 1076 band */ 1077 }; 1078 1079 /*========================================*/ 1080 1081 /** 1082 * \struct struct drx_scan_param * Parameters for channel scan. 1083 * 1084 * Used by DRX_CTRL_SCAN_INIT. 1085 */ 1086 struct drx_scan_param { 1087 struct drx_frequency_plan *frequency_plan; 1088 /**< Frequency plan (array)*/ 1089 u16 frequency_plan_size; /**< Number of bands */ 1090 u32 num_tries; /**< Max channels tried */ 1091 s32 skip; /**< Minimum frequency step to take 1092 after a channel is found */ 1093 void *ext_params; /**< Standard specific params */ 1094 }; 1095 1096 /*========================================*/ 1097 1098 /** 1099 * \brief Scan commands. 1100 * Used by scanning algorithms. 1101 */ 1102 enum drx_scan_command { 1103 DRX_SCAN_COMMAND_INIT = 0,/**< Initialize scanning */ 1104 DRX_SCAN_COMMAND_NEXT, /**< Next scan */ 1105 DRX_SCAN_COMMAND_STOP /**< Stop scanning */ 1106 }; 1107 1108 /*========================================*/ 1109 1110 /** 1111 * \brief Inner scan function prototype. 1112 */ 1113 typedef int(*drx_scan_func_t) (void *scan_context, 1114 enum drx_scan_command scan_command, 1115 struct drx_channel *scan_channel, 1116 bool *get_next_channel); 1117 1118 /*========================================*/ 1119 1120 /** 1121 * \struct struct drxtps_info * TPS information, DVB-T specific. 1122 * 1123 * Used by DRX_CTRL_TPS_INFO. 1124 */ 1125 struct drxtps_info { 1126 enum drx_fft_mode fftmode; /**< Fft mode */ 1127 enum drx_guard guard; /**< Guard interval */ 1128 enum drx_modulation constellation; 1129 /**< Constellation */ 1130 enum drx_hierarchy hierarchy; 1131 /**< Hierarchy */ 1132 enum drx_coderate high_coderate; 1133 /**< High code rate */ 1134 enum drx_coderate low_coderate; 1135 /**< Low cod rate */ 1136 enum drx_tps_frame frame; /**< Tps frame */ 1137 u8 length; /**< Length */ 1138 u16 cell_id; /**< Cell id */ 1139 }; 1140 1141 /*========================================*/ 1142 1143 /** 1144 * \brief Power mode of device. 1145 * 1146 * Used by DRX_CTRL_SET_POWER_MODE. 1147 */ 1148 enum drx_power_mode { 1149 DRX_POWER_UP = 0, 1150 /**< Generic , Power Up Mode */ 1151 DRX_POWER_MODE_1, 1152 /**< Device specific , Power Up Mode */ 1153 DRX_POWER_MODE_2, 1154 /**< Device specific , Power Up Mode */ 1155 DRX_POWER_MODE_3, 1156 /**< Device specific , Power Up Mode */ 1157 DRX_POWER_MODE_4, 1158 /**< Device specific , Power Up Mode */ 1159 DRX_POWER_MODE_5, 1160 /**< Device specific , Power Up Mode */ 1161 DRX_POWER_MODE_6, 1162 /**< Device specific , Power Up Mode */ 1163 DRX_POWER_MODE_7, 1164 /**< Device specific , Power Up Mode */ 1165 DRX_POWER_MODE_8, 1166 /**< Device specific , Power Up Mode */ 1167 1168 DRX_POWER_MODE_9, 1169 /**< Device specific , Power Down Mode */ 1170 DRX_POWER_MODE_10, 1171 /**< Device specific , Power Down Mode */ 1172 DRX_POWER_MODE_11, 1173 /**< Device specific , Power Down Mode */ 1174 DRX_POWER_MODE_12, 1175 /**< Device specific , Power Down Mode */ 1176 DRX_POWER_MODE_13, 1177 /**< Device specific , Power Down Mode */ 1178 DRX_POWER_MODE_14, 1179 /**< Device specific , Power Down Mode */ 1180 DRX_POWER_MODE_15, 1181 /**< Device specific , Power Down Mode */ 1182 DRX_POWER_MODE_16, 1183 /**< Device specific , Power Down Mode */ 1184 DRX_POWER_DOWN = 255 1185 /**< Generic , Power Down Mode */ 1186 }; 1187 1188 /*========================================*/ 1189 1190 /** 1191 * \enum enum drx_module * \brief Software module identification. 1192 * 1193 * Used by DRX_CTRL_VERSION. 1194 */ 1195 enum drx_module { 1196 DRX_MODULE_DEVICE, 1197 DRX_MODULE_MICROCODE, 1198 DRX_MODULE_DRIVERCORE, 1199 DRX_MODULE_DEVICEDRIVER, 1200 DRX_MODULE_DAP, 1201 DRX_MODULE_BSP_I2C, 1202 DRX_MODULE_BSP_TUNER, 1203 DRX_MODULE_BSP_HOST, 1204 DRX_MODULE_UNKNOWN 1205 }; 1206 1207 /** 1208 * \enum struct drx_version * \brief Version information of one software module. 1209 * 1210 * Used by DRX_CTRL_VERSION. 1211 */ 1212 struct drx_version { 1213 enum drx_module module_type; 1214 /**< Type identifier of the module */ 1215 char *module_name; 1216 /**< Name or description of module */ 1217 u16 v_major; /**< Major version number */ 1218 u16 v_minor; /**< Minor version number */ 1219 u16 v_patch; /**< Patch version number */ 1220 char *v_string; /**< Version as text string */ 1221 }; 1222 1223 /** 1224 * \enum struct drx_version_list * \brief List element of NULL terminated, linked list for version information. 1225 * 1226 * Used by DRX_CTRL_VERSION. 1227 */ 1228 struct drx_version_list { 1229 struct drx_version *version;/**< Version information */ 1230 struct drx_version_list *next; 1231 /**< Next list element */ 1232 }; 1233 1234 /*========================================*/ 1235 1236 /** 1237 * \brief Parameters needed to confiugure a UIO. 1238 * 1239 * Used by DRX_CTRL_UIO_CFG. 1240 */ 1241 struct drxuio_cfg { 1242 enum drx_uio uio; 1243 /**< UIO identifier */ 1244 enum drxuio_mode mode; 1245 /**< UIO operational mode */ 1246 }; 1247 1248 /*========================================*/ 1249 1250 /** 1251 * \brief Parameters needed to read from or write to a UIO. 1252 * 1253 * Used by DRX_CTRL_UIO_READ and DRX_CTRL_UIO_WRITE. 1254 */ 1255 struct drxuio_data { 1256 enum drx_uio uio; 1257 /**< UIO identifier */ 1258 bool value; 1259 /**< UIO value (true=1, false=0) */ 1260 }; 1261 1262 /*========================================*/ 1263 1264 /** 1265 * \brief Parameters needed to configure OOB. 1266 * 1267 * Used by DRX_CTRL_SET_OOB. 1268 */ 1269 struct drxoob { 1270 s32 frequency; /**< Frequency in kHz */ 1271 enum drxoob_downstream_standard standard; 1272 /**< OOB standard */ 1273 bool spectrum_inverted; /**< If true, then spectrum 1274 is inverted */ 1275 }; 1276 1277 /*========================================*/ 1278 1279 /** 1280 * \brief Metrics from OOB. 1281 * 1282 * Used by DRX_CTRL_GET_OOB. 1283 */ 1284 struct drxoob_status { 1285 s32 frequency; /**< Frequency in Khz */ 1286 enum drx_lock_status lock; /**< Lock status */ 1287 u32 mer; /**< MER */ 1288 s32 symbol_rate_offset; /**< Symbolrate offset in ppm */ 1289 }; 1290 1291 /*========================================*/ 1292 1293 /** 1294 * \brief Device dependent configuration data. 1295 * 1296 * Used by DRX_CTRL_SET_CFG and DRX_CTRL_GET_CFG. 1297 * A sort of nested drx_ctrl() functionality for device specific controls. 1298 */ 1299 struct drx_cfg { 1300 u32 cfg_type; 1301 /**< Function identifier */ 1302 void *cfg_data; 1303 /**< Function data */ 1304 }; 1305 1306 /*========================================*/ 1307 1308 /** 1309 * /struct DRXMpegStartWidth_t 1310 * MStart width [nr MCLK cycles] for serial MPEG output. 1311 */ 1312 1313 enum drxmpeg_str_width { 1314 DRX_MPEG_STR_WIDTH_1, 1315 DRX_MPEG_STR_WIDTH_8 1316 }; 1317 1318 /* CTRL CFG MPEG output */ 1319 /** 1320 * \struct struct drx_cfg_mpeg_output * \brief Configuration parameters for MPEG output control. 1321 * 1322 * Used by DRX_CFG_MPEG_OUTPUT, in combination with DRX_CTRL_SET_CFG and 1323 * DRX_CTRL_GET_CFG. 1324 */ 1325 1326 struct drx_cfg_mpeg_output { 1327 bool enable_mpeg_output;/**< If true, enable MPEG output */ 1328 bool insert_rs_byte; /**< If true, insert RS byte */ 1329 bool enable_parallel; /**< If true, parallel out otherwise 1330 serial */ 1331 bool invert_data; /**< If true, invert DATA signals */ 1332 bool invert_err; /**< If true, invert ERR signal */ 1333 bool invert_str; /**< If true, invert STR signals */ 1334 bool invert_val; /**< If true, invert VAL signals */ 1335 bool invert_clk; /**< If true, invert CLK signals */ 1336 bool static_clk; /**< If true, static MPEG clockrate 1337 will be used, otherwise clockrate 1338 will adapt to the bitrate of the 1339 TS */ 1340 u32 bitrate; /**< Maximum bitrate in b/s in case 1341 static clockrate is selected */ 1342 enum drxmpeg_str_width width_str; 1343 /**< MPEG start width */ 1344 }; 1345 1346 1347 /*========================================*/ 1348 1349 /** 1350 * \struct struct drxi2c_data * \brief Data for I2C via 2nd or 3rd or etc I2C port. 1351 * 1352 * Used by DRX_CTRL_I2C_READWRITE. 1353 * If port_nr is equal to primairy port_nr BSPI2C will be used. 1354 * 1355 */ 1356 struct drxi2c_data { 1357 u16 port_nr; /**< I2C port number */ 1358 struct i2c_device_addr *w_dev_addr; 1359 /**< Write device address */ 1360 u16 w_count; /**< Size of write data in bytes */ 1361 u8 *wData; /**< Pointer to write data */ 1362 struct i2c_device_addr *r_dev_addr; 1363 /**< Read device address */ 1364 u16 r_count; /**< Size of data to read in bytes */ 1365 u8 *r_data; /**< Pointer to read buffer */ 1366 }; 1367 1368 /*========================================*/ 1369 1370 /** 1371 * \enum enum drx_aud_standard * \brief Audio standard identifier. 1372 * 1373 * Used by DRX_CTRL_SET_AUD. 1374 */ 1375 enum drx_aud_standard { 1376 DRX_AUD_STANDARD_BTSC, /**< set BTSC standard (USA) */ 1377 DRX_AUD_STANDARD_A2, /**< set A2-Korea FM Stereo */ 1378 DRX_AUD_STANDARD_EIAJ, /**< set to Japanese FM Stereo */ 1379 DRX_AUD_STANDARD_FM_STEREO,/**< set to FM-Stereo Radio */ 1380 DRX_AUD_STANDARD_M_MONO, /**< for 4.5 MHz mono detected */ 1381 DRX_AUD_STANDARD_D_K_MONO, /**< for 6.5 MHz mono detected */ 1382 DRX_AUD_STANDARD_BG_FM, /**< set BG_FM standard */ 1383 DRX_AUD_STANDARD_D_K1, /**< set D_K1 standard */ 1384 DRX_AUD_STANDARD_D_K2, /**< set D_K2 standard */ 1385 DRX_AUD_STANDARD_D_K3, /**< set D_K3 standard */ 1386 DRX_AUD_STANDARD_BG_NICAM_FM, 1387 /**< set BG_NICAM_FM standard */ 1388 DRX_AUD_STANDARD_L_NICAM_AM, 1389 /**< set L_NICAM_AM standard */ 1390 DRX_AUD_STANDARD_I_NICAM_FM, 1391 /**< set I_NICAM_FM standard */ 1392 DRX_AUD_STANDARD_D_K_NICAM_FM, 1393 /**< set D_K_NICAM_FM standard */ 1394 DRX_AUD_STANDARD_NOT_READY,/**< used to detect audio standard */ 1395 DRX_AUD_STANDARD_AUTO = DRX_AUTO, 1396 /**< Automatic Standard Detection */ 1397 DRX_AUD_STANDARD_UNKNOWN = DRX_UNKNOWN 1398 /**< used as auto and for readback */ 1399 }; 1400 1401 /* CTRL_AUD_GET_STATUS - struct drx_aud_status */ 1402 /** 1403 * \enum enum drx_aud_nicam_status * \brief Status of NICAM carrier. 1404 */ 1405 enum drx_aud_nicam_status { 1406 DRX_AUD_NICAM_DETECTED = 0, 1407 /**< NICAM carrier detected */ 1408 DRX_AUD_NICAM_NOT_DETECTED, 1409 /**< NICAM carrier not detected */ 1410 DRX_AUD_NICAM_BAD /**< NICAM carrier bad quality */ 1411 }; 1412 1413 /** 1414 * \struct struct drx_aud_status * \brief Audio status characteristics. 1415 */ 1416 struct drx_aud_status { 1417 bool stereo; /**< stereo detection */ 1418 bool carrier_a; /**< carrier A detected */ 1419 bool carrier_b; /**< carrier B detected */ 1420 bool sap; /**< sap / bilingual detection */ 1421 bool rds; /**< RDS data array present */ 1422 enum drx_aud_nicam_status nicam_status; 1423 /**< status of NICAM carrier */ 1424 s8 fm_ident; /**< FM Identification value */ 1425 }; 1426 1427 /* CTRL_AUD_READ_RDS - DRXRDSdata_t */ 1428 1429 /** 1430 * \struct DRXRDSdata_t 1431 * \brief Raw RDS data array. 1432 */ 1433 struct drx_cfg_aud_rds { 1434 bool valid; /**< RDS data validation */ 1435 u16 data[18]; /**< data from one RDS data array */ 1436 }; 1437 1438 /* DRX_CFG_AUD_VOLUME - struct drx_cfg_aud_volume - set/get */ 1439 /** 1440 * \enum DRXAudAVCDecayTime_t 1441 * \brief Automatic volume control configuration. 1442 */ 1443 enum drx_aud_avc_mode { 1444 DRX_AUD_AVC_OFF, /**< Automatic volume control off */ 1445 DRX_AUD_AVC_DECAYTIME_8S, /**< level volume in 8 seconds */ 1446 DRX_AUD_AVC_DECAYTIME_4S, /**< level volume in 4 seconds */ 1447 DRX_AUD_AVC_DECAYTIME_2S, /**< level volume in 2 seconds */ 1448 DRX_AUD_AVC_DECAYTIME_20MS/**< level volume in 20 millisec */ 1449 }; 1450 1451 /** 1452 * /enum DRXAudMaxAVCGain_t 1453 * /brief Automatic volume control max gain in audio baseband. 1454 */ 1455 enum drx_aud_avc_max_gain { 1456 DRX_AUD_AVC_MAX_GAIN_0DB, /**< maximum AVC gain 0 dB */ 1457 DRX_AUD_AVC_MAX_GAIN_6DB, /**< maximum AVC gain 6 dB */ 1458 DRX_AUD_AVC_MAX_GAIN_12DB /**< maximum AVC gain 12 dB */ 1459 }; 1460 1461 /** 1462 * /enum DRXAudMaxAVCAtten_t 1463 * /brief Automatic volume control max attenuation in audio baseband. 1464 */ 1465 enum drx_aud_avc_max_atten { 1466 DRX_AUD_AVC_MAX_ATTEN_12DB, 1467 /**< maximum AVC attenuation 12 dB */ 1468 DRX_AUD_AVC_MAX_ATTEN_18DB, 1469 /**< maximum AVC attenuation 18 dB */ 1470 DRX_AUD_AVC_MAX_ATTEN_24DB/**< maximum AVC attenuation 24 dB */ 1471 }; 1472 /** 1473 * \struct struct drx_cfg_aud_volume * \brief Audio volume configuration. 1474 */ 1475 struct drx_cfg_aud_volume { 1476 bool mute; /**< mute overrides volume setting */ 1477 s16 volume; /**< volume, range -114 to 12 dB */ 1478 enum drx_aud_avc_mode avc_mode; /**< AVC auto volume control mode */ 1479 u16 avc_ref_level; /**< AVC reference level */ 1480 enum drx_aud_avc_max_gain avc_max_gain; 1481 /**< AVC max gain selection */ 1482 enum drx_aud_avc_max_atten avc_max_atten; 1483 /**< AVC max attenuation selection */ 1484 s16 strength_left; /**< quasi-peak, left speaker */ 1485 s16 strength_right; /**< quasi-peak, right speaker */ 1486 }; 1487 1488 /* DRX_CFG_I2S_OUTPUT - struct drx_cfg_i2s_output - set/get */ 1489 /** 1490 * \enum enum drxi2s_mode * \brief I2S output mode. 1491 */ 1492 enum drxi2s_mode { 1493 DRX_I2S_MODE_MASTER, /**< I2S is in master mode */ 1494 DRX_I2S_MODE_SLAVE /**< I2S is in slave mode */ 1495 }; 1496 1497 /** 1498 * \enum enum drxi2s_word_length * \brief Width of I2S data. 1499 */ 1500 enum drxi2s_word_length { 1501 DRX_I2S_WORDLENGTH_32 = 0,/**< I2S data is 32 bit wide */ 1502 DRX_I2S_WORDLENGTH_16 = 1 /**< I2S data is 16 bit wide */ 1503 }; 1504 1505 /** 1506 * \enum enum drxi2s_format * \brief Data wordstrobe alignment for I2S. 1507 */ 1508 enum drxi2s_format { 1509 DRX_I2S_FORMAT_WS_WITH_DATA, 1510 /**< I2S data and wordstrobe are aligned */ 1511 DRX_I2S_FORMAT_WS_ADVANCED 1512 /**< I2S data one cycle after wordstrobe */ 1513 }; 1514 1515 /** 1516 * \enum enum drxi2s_polarity * \brief Polarity of I2S data. 1517 */ 1518 enum drxi2s_polarity { 1519 DRX_I2S_POLARITY_RIGHT,/**< wordstrobe - right high, left low */ 1520 DRX_I2S_POLARITY_LEFT /**< wordstrobe - right low, left high */ 1521 }; 1522 1523 /** 1524 * \struct struct drx_cfg_i2s_output * \brief I2S output configuration. 1525 */ 1526 struct drx_cfg_i2s_output { 1527 bool output_enable; /**< I2S output enable */ 1528 u32 frequency; /**< range from 8000-48000 Hz */ 1529 enum drxi2s_mode mode; /**< I2S mode, master or slave */ 1530 enum drxi2s_word_length word_length; 1531 /**< I2S wordlength, 16 or 32 bits */ 1532 enum drxi2s_polarity polarity;/**< I2S wordstrobe polarity */ 1533 enum drxi2s_format format; /**< I2S wordstrobe delay to data */ 1534 }; 1535 1536 /* ------------------------------expert interface-----------------------------*/ 1537 /** 1538 * /enum enum drx_aud_fm_deemphasis * setting for FM-Deemphasis in audio demodulator. 1539 * 1540 */ 1541 enum drx_aud_fm_deemphasis { 1542 DRX_AUD_FM_DEEMPH_50US, 1543 DRX_AUD_FM_DEEMPH_75US, 1544 DRX_AUD_FM_DEEMPH_OFF 1545 }; 1546 1547 /** 1548 * /enum DRXAudDeviation_t 1549 * setting for deviation mode in audio demodulator. 1550 * 1551 */ 1552 enum drx_cfg_aud_deviation { 1553 DRX_AUD_DEVIATION_NORMAL, 1554 DRX_AUD_DEVIATION_HIGH 1555 }; 1556 1557 /** 1558 * /enum enum drx_no_carrier_option * setting for carrier, mute/noise. 1559 * 1560 */ 1561 enum drx_no_carrier_option { 1562 DRX_NO_CARRIER_MUTE, 1563 DRX_NO_CARRIER_NOISE 1564 }; 1565 1566 /** 1567 * \enum DRXAudAutoSound_t 1568 * \brief Automatic Sound 1569 */ 1570 enum drx_cfg_aud_auto_sound { 1571 DRX_AUD_AUTO_SOUND_OFF = 0, 1572 DRX_AUD_AUTO_SOUND_SELECT_ON_CHANGE_ON, 1573 DRX_AUD_AUTO_SOUND_SELECT_ON_CHANGE_OFF 1574 }; 1575 1576 /** 1577 * \enum DRXAudASSThres_t 1578 * \brief Automatic Sound Select Thresholds 1579 */ 1580 struct drx_cfg_aud_ass_thres { 1581 u16 a2; /* A2 Threshold for ASS configuration */ 1582 u16 btsc; /* BTSC Threshold for ASS configuration */ 1583 u16 nicam; /* Nicam Threshold for ASS configuration */ 1584 }; 1585 1586 /** 1587 * \struct struct drx_aud_carrier * \brief Carrier detection related parameters 1588 */ 1589 struct drx_aud_carrier { 1590 u16 thres; /* carrier detetcion threshold for primary carrier (A) */ 1591 enum drx_no_carrier_option opt; /* Mute or noise at no carrier detection (A) */ 1592 s32 shift; /* DC level of incoming signal (A) */ 1593 s32 dco; /* frequency adjustment (A) */ 1594 }; 1595 1596 /** 1597 * \struct struct drx_cfg_aud_carriers * \brief combining carrier A & B to one struct 1598 */ 1599 struct drx_cfg_aud_carriers { 1600 struct drx_aud_carrier a; 1601 struct drx_aud_carrier b; 1602 }; 1603 1604 /** 1605 * /enum enum drx_aud_i2s_src * Selection of audio source 1606 */ 1607 enum drx_aud_i2s_src { 1608 DRX_AUD_SRC_MONO, 1609 DRX_AUD_SRC_STEREO_OR_AB, 1610 DRX_AUD_SRC_STEREO_OR_A, 1611 DRX_AUD_SRC_STEREO_OR_B}; 1612 1613 /** 1614 * \enum enum drx_aud_i2s_matrix * \brief Used for selecting I2S output. 1615 */ 1616 enum drx_aud_i2s_matrix { 1617 DRX_AUD_I2S_MATRIX_A_MONO, 1618 /**< A sound only, stereo or mono */ 1619 DRX_AUD_I2S_MATRIX_B_MONO, 1620 /**< B sound only, stereo or mono */ 1621 DRX_AUD_I2S_MATRIX_STEREO, 1622 /**< A+B sound, transparant */ 1623 DRX_AUD_I2S_MATRIX_MONO /**< A+B mixed to mono sum, (L+R)/2 */}; 1624 1625 /** 1626 * /enum enum drx_aud_fm_matrix * setting for FM-Matrix in audio demodulator. 1627 * 1628 */ 1629 enum drx_aud_fm_matrix { 1630 DRX_AUD_FM_MATRIX_NO_MATRIX, 1631 DRX_AUD_FM_MATRIX_GERMAN, 1632 DRX_AUD_FM_MATRIX_KOREAN, 1633 DRX_AUD_FM_MATRIX_SOUND_A, 1634 DRX_AUD_FM_MATRIX_SOUND_B}; 1635 1636 /** 1637 * \struct DRXAudMatrices_t 1638 * \brief Mixer settings 1639 */ 1640 struct drx_cfg_aud_mixer { 1641 enum drx_aud_i2s_src source_i2s; 1642 enum drx_aud_i2s_matrix matrix_i2s; 1643 enum drx_aud_fm_matrix matrix_fm; 1644 }; 1645 1646 /** 1647 * \enum DRXI2SVidSync_t 1648 * \brief Audio/video synchronization, interacts with I2S mode. 1649 * AUTO_1 and AUTO_2 are for automatic video standard detection with preference 1650 * for NTSC or Monochrome, because the frequencies are too close (59.94 & 60 Hz) 1651 */ 1652 enum drx_cfg_aud_av_sync { 1653 DRX_AUD_AVSYNC_OFF,/**< audio/video synchronization is off */ 1654 DRX_AUD_AVSYNC_NTSC, 1655 /**< it is an NTSC system */ 1656 DRX_AUD_AVSYNC_MONOCHROME, 1657 /**< it is a MONOCHROME system */ 1658 DRX_AUD_AVSYNC_PAL_SECAM 1659 /**< it is a PAL/SECAM system */}; 1660 1661 /** 1662 * \struct struct drx_cfg_aud_prescale * \brief Prescalers 1663 */ 1664 struct drx_cfg_aud_prescale { 1665 u16 fm_deviation; 1666 s16 nicam_gain; 1667 }; 1668 1669 /** 1670 * \struct struct drx_aud_beep * \brief Beep 1671 */ 1672 struct drx_aud_beep { 1673 s16 volume; /* dB */ 1674 u16 frequency; /* Hz */ 1675 bool mute; 1676 }; 1677 1678 /** 1679 * \enum enum drx_aud_btsc_detect * \brief BTSC detetcion mode 1680 */ 1681 enum drx_aud_btsc_detect { 1682 DRX_BTSC_STEREO, 1683 DRX_BTSC_MONO_AND_SAP}; 1684 1685 /** 1686 * \struct struct drx_aud_data * \brief Audio data structure 1687 */ 1688 struct drx_aud_data { 1689 /* audio storage */ 1690 bool audio_is_active; 1691 enum drx_aud_standard audio_standard; 1692 struct drx_cfg_i2s_output i2sdata; 1693 struct drx_cfg_aud_volume volume; 1694 enum drx_cfg_aud_auto_sound auto_sound; 1695 struct drx_cfg_aud_ass_thres ass_thresholds; 1696 struct drx_cfg_aud_carriers carriers; 1697 struct drx_cfg_aud_mixer mixer; 1698 enum drx_cfg_aud_deviation deviation; 1699 enum drx_cfg_aud_av_sync av_sync; 1700 struct drx_cfg_aud_prescale prescale; 1701 enum drx_aud_fm_deemphasis deemph; 1702 enum drx_aud_btsc_detect btsc_detect; 1703 /* rds */ 1704 u16 rds_data_counter; 1705 bool rds_data_present; 1706 }; 1707 1708 /** 1709 * \enum enum drx_qam_lock_range * \brief QAM lock range mode 1710 */ 1711 enum drx_qam_lock_range { 1712 DRX_QAM_LOCKRANGE_NORMAL, 1713 DRX_QAM_LOCKRANGE_EXTENDED}; 1714 1715 /*============================================================================*/ 1716 /*============================================================================*/ 1717 /*== Data access structures ==================================================*/ 1718 /*============================================================================*/ 1719 /*============================================================================*/ 1720 1721 /* Address on device */ 1722 typedef u32 dr_xaddr_t, *pdr_xaddr_t; 1723 1724 /* Protocol specific flags */ 1725 typedef u32 dr_xflags_t, *pdr_xflags_t; 1726 1727 /* Write block of data to device */ 1728 typedef int(*drx_write_block_func_t) (struct i2c_device_addr *dev_addr, /* address of I2C device */ 1729 u32 addr, /* address of register/memory */ 1730 u16 datasize, /* size of data in bytes */ 1731 u8 *data, /* data to send */ 1732 u32 flags); 1733 1734 /* Read block of data from device */ 1735 typedef int(*drx_read_block_func_t) (struct i2c_device_addr *dev_addr, /* address of I2C device */ 1736 u32 addr, /* address of register/memory */ 1737 u16 datasize, /* size of data in bytes */ 1738 u8 *data, /* receive buffer */ 1739 u32 flags); 1740 1741 /* Write 8-bits value to device */ 1742 typedef int(*drx_write_reg8func_t) (struct i2c_device_addr *dev_addr, /* address of I2C device */ 1743 u32 addr, /* address of register/memory */ 1744 u8 data, /* data to send */ 1745 u32 flags); 1746 1747 /* Read 8-bits value to device */ 1748 typedef int(*drx_read_reg8func_t) (struct i2c_device_addr *dev_addr, /* address of I2C device */ 1749 u32 addr, /* address of register/memory */ 1750 u8 *data, /* receive buffer */ 1751 u32 flags); 1752 1753 /* Read modify write 8-bits value to device */ 1754 typedef int(*drx_read_modify_write_reg8func_t) (struct i2c_device_addr *dev_addr, /* address of I2C device */ 1755 u32 waddr, /* write address of register */ 1756 u32 raddr, /* read address of register */ 1757 u8 wdata, /* data to write */ 1758 u8 *rdata); /* data to read */ 1759 1760 /* Write 16-bits value to device */ 1761 typedef int(*drx_write_reg16func_t) (struct i2c_device_addr *dev_addr, /* address of I2C device */ 1762 u32 addr, /* address of register/memory */ 1763 u16 data, /* data to send */ 1764 u32 flags); 1765 1766 /* Read 16-bits value to device */ 1767 typedef int(*drx_read_reg16func_t) (struct i2c_device_addr *dev_addr, /* address of I2C device */ 1768 u32 addr, /* address of register/memory */ 1769 u16 *data, /* receive buffer */ 1770 u32 flags); 1771 1772 /* Read modify write 16-bits value to device */ 1773 typedef int(*drx_read_modify_write_reg16func_t) (struct i2c_device_addr *dev_addr, /* address of I2C device */ 1774 u32 waddr, /* write address of register */ 1775 u32 raddr, /* read address of register */ 1776 u16 wdata, /* data to write */ 1777 u16 *rdata); /* data to read */ 1778 1779 /* Write 32-bits value to device */ 1780 typedef int(*drx_write_reg32func_t) (struct i2c_device_addr *dev_addr, /* address of I2C device */ 1781 u32 addr, /* address of register/memory */ 1782 u32 data, /* data to send */ 1783 u32 flags); 1784 1785 /* Read 32-bits value to device */ 1786 typedef int(*drx_read_reg32func_t) (struct i2c_device_addr *dev_addr, /* address of I2C device */ 1787 u32 addr, /* address of register/memory */ 1788 u32 *data, /* receive buffer */ 1789 u32 flags); 1790 1791 /* Read modify write 32-bits value to device */ 1792 typedef int(*drx_read_modify_write_reg32func_t) (struct i2c_device_addr *dev_addr, /* address of I2C device */ 1793 u32 waddr, /* write address of register */ 1794 u32 raddr, /* read address of register */ 1795 u32 wdata, /* data to write */ 1796 u32 *rdata); /* data to read */ 1797 1798 /** 1799 * \struct struct drx_access_func * \brief Interface to an access protocol. 1800 */ 1801 struct drx_access_func { 1802 drx_write_block_func_t write_block_func; 1803 drx_read_block_func_t read_block_func; 1804 drx_write_reg8func_t write_reg8func; 1805 drx_read_reg8func_t read_reg8func; 1806 drx_read_modify_write_reg8func_t read_modify_write_reg8func; 1807 drx_write_reg16func_t write_reg16func; 1808 drx_read_reg16func_t read_reg16func; 1809 drx_read_modify_write_reg16func_t read_modify_write_reg16func; 1810 drx_write_reg32func_t write_reg32func; 1811 drx_read_reg32func_t read_reg32func; 1812 drx_read_modify_write_reg32func_t read_modify_write_reg32func; 1813 }; 1814 1815 /* Register address and data for register dump function */ 1816 struct drx_reg_dump { 1817 u32 address; 1818 u32 data; 1819 }; 1820 1821 /*============================================================================*/ 1822 /*============================================================================*/ 1823 /*== Demod instance data structures ==========================================*/ 1824 /*============================================================================*/ 1825 /*============================================================================*/ 1826 1827 /** 1828 * \struct struct drx_common_attr * \brief Set of common attributes, shared by all DRX devices. 1829 */ 1830 struct drx_common_attr { 1831 /* Microcode (firmware) attributes */ 1832 char *microcode_file; /**< microcode filename */ 1833 bool verify_microcode; 1834 /**< Use microcode verify or not. */ 1835 struct drx_mc_version_rec mcversion; 1836 /**< Version record of microcode from file */ 1837 1838 /* Clocks and tuner attributes */ 1839 s32 intermediate_freq; 1840 /**< IF,if tuner instance not used. (kHz)*/ 1841 s32 sys_clock_freq; 1842 /**< Systemclock frequency. (kHz) */ 1843 s32 osc_clock_freq; 1844 /**< Oscillator clock frequency. (kHz) */ 1845 s16 osc_clock_deviation; 1846 /**< Oscillator clock deviation. (ppm) */ 1847 bool mirror_freq_spect; 1848 /**< Mirror IF frequency spectrum or not.*/ 1849 1850 /* Initial MPEG output attributes */ 1851 struct drx_cfg_mpeg_output mpeg_cfg; 1852 /**< MPEG configuration */ 1853 1854 bool is_opened; /**< if true instance is already opened. */ 1855 1856 /* Channel scan */ 1857 struct drx_scan_param *scan_param; 1858 /**< scan parameters */ 1859 u16 scan_freq_plan_index; 1860 /**< next index in freq plan */ 1861 s32 scan_next_frequency; 1862 /**< next freq to scan */ 1863 bool scan_ready; /**< scan ready flag */ 1864 u32 scan_max_channels;/**< number of channels in freqplan */ 1865 u32 scan_channels_scanned; 1866 /**< number of channels scanned */ 1867 /* Channel scan - inner loop: demod related */ 1868 drx_scan_func_t scan_function; 1869 /**< function to check channel */ 1870 /* Channel scan - inner loop: SYSObj related */ 1871 void *scan_context; /**< Context Pointer of SYSObj */ 1872 /* Channel scan - parameters for default DTV scan function in core driver */ 1873 u16 scan_demod_lock_timeout; 1874 /**< millisecs to wait for lock */ 1875 enum drx_lock_status scan_desired_lock; 1876 /**< lock requirement for channel found */ 1877 /* scan_active can be used by SetChannel to decide how to program the tuner, 1878 fast or slow (but stable). Usually fast during scan. */ 1879 bool scan_active; /**< true when scan routines are active */ 1880 1881 /* Power management */ 1882 enum drx_power_mode current_power_mode; 1883 /**< current power management mode */ 1884 1885 /* Tuner */ 1886 u8 tuner_port_nr; /**< nr of I2C port to wich tuner is */ 1887 s32 tuner_min_freq_rf; 1888 /**< minimum RF input frequency, in kHz */ 1889 s32 tuner_max_freq_rf; 1890 /**< maximum RF input frequency, in kHz */ 1891 bool tuner_rf_agc_pol; /**< if true invert RF AGC polarity */ 1892 bool tuner_if_agc_pol; /**< if true invert IF AGC polarity */ 1893 bool tuner_slow_mode; /**< if true invert IF AGC polarity */ 1894 1895 struct drx_channel current_channel; 1896 /**< current channel parameters */ 1897 enum drx_standard current_standard; 1898 /**< current standard selection */ 1899 enum drx_standard prev_standard; 1900 /**< previous standard selection */ 1901 enum drx_standard di_cache_standard; 1902 /**< standard in DI cache if available */ 1903 bool use_bootloader; /**< use bootloader in open */ 1904 u32 capabilities; /**< capabilities flags */ 1905 u32 product_id; /**< product ID inc. metal fix number */}; 1906 1907 /* 1908 * Generic functions for DRX devices. 1909 */ 1910 1911 struct drx_demod_instance; 1912 1913 /** 1914 * \struct struct drx_demod_instance * \brief Top structure of demodulator instance. 1915 */ 1916 struct drx_demod_instance { 1917 /**< data access protocol functions */ 1918 struct i2c_device_addr *my_i2c_dev_addr; 1919 /**< i2c address and device identifier */ 1920 struct drx_common_attr *my_common_attr; 1921 /**< common DRX attributes */ 1922 void *my_ext_attr; /**< device specific attributes */ 1923 /* generic demodulator data */ 1924 1925 struct i2c_adapter *i2c; 1926 const struct firmware *firmware; 1927 }; 1928 1929 /*------------------------------------------------------------------------- 1930 MACROS 1931 Conversion from enum values to human readable form. 1932 -------------------------------------------------------------------------*/ 1933 1934 /* standard */ 1935 1936 #define DRX_STR_STANDARD(x) ( \ 1937 (x == DRX_STANDARD_DVBT) ? "DVB-T" : \ 1938 (x == DRX_STANDARD_8VSB) ? "8VSB" : \ 1939 (x == DRX_STANDARD_NTSC) ? "NTSC" : \ 1940 (x == DRX_STANDARD_PAL_SECAM_BG) ? "PAL/SECAM B/G" : \ 1941 (x == DRX_STANDARD_PAL_SECAM_DK) ? "PAL/SECAM D/K" : \ 1942 (x == DRX_STANDARD_PAL_SECAM_I) ? "PAL/SECAM I" : \ 1943 (x == DRX_STANDARD_PAL_SECAM_L) ? "PAL/SECAM L" : \ 1944 (x == DRX_STANDARD_PAL_SECAM_LP) ? "PAL/SECAM LP" : \ 1945 (x == DRX_STANDARD_ITU_A) ? "ITU-A" : \ 1946 (x == DRX_STANDARD_ITU_B) ? "ITU-B" : \ 1947 (x == DRX_STANDARD_ITU_C) ? "ITU-C" : \ 1948 (x == DRX_STANDARD_ITU_D) ? "ITU-D" : \ 1949 (x == DRX_STANDARD_FM) ? "FM" : \ 1950 (x == DRX_STANDARD_DTMB) ? "DTMB" : \ 1951 (x == DRX_STANDARD_AUTO) ? "Auto" : \ 1952 (x == DRX_STANDARD_UNKNOWN) ? "Unknown" : \ 1953 "(Invalid)") 1954 1955 /* channel */ 1956 1957 #define DRX_STR_BANDWIDTH(x) ( \ 1958 (x == DRX_BANDWIDTH_8MHZ) ? "8 MHz" : \ 1959 (x == DRX_BANDWIDTH_7MHZ) ? "7 MHz" : \ 1960 (x == DRX_BANDWIDTH_6MHZ) ? "6 MHz" : \ 1961 (x == DRX_BANDWIDTH_AUTO) ? "Auto" : \ 1962 (x == DRX_BANDWIDTH_UNKNOWN) ? "Unknown" : \ 1963 "(Invalid)") 1964 #define DRX_STR_FFTMODE(x) ( \ 1965 (x == DRX_FFTMODE_2K) ? "2k" : \ 1966 (x == DRX_FFTMODE_4K) ? "4k" : \ 1967 (x == DRX_FFTMODE_8K) ? "8k" : \ 1968 (x == DRX_FFTMODE_AUTO) ? "Auto" : \ 1969 (x == DRX_FFTMODE_UNKNOWN) ? "Unknown" : \ 1970 "(Invalid)") 1971 #define DRX_STR_GUARD(x) ( \ 1972 (x == DRX_GUARD_1DIV32) ? "1/32nd" : \ 1973 (x == DRX_GUARD_1DIV16) ? "1/16th" : \ 1974 (x == DRX_GUARD_1DIV8) ? "1/8th" : \ 1975 (x == DRX_GUARD_1DIV4) ? "1/4th" : \ 1976 (x == DRX_GUARD_AUTO) ? "Auto" : \ 1977 (x == DRX_GUARD_UNKNOWN) ? "Unknown" : \ 1978 "(Invalid)") 1979 #define DRX_STR_CONSTELLATION(x) ( \ 1980 (x == DRX_CONSTELLATION_BPSK) ? "BPSK" : \ 1981 (x == DRX_CONSTELLATION_QPSK) ? "QPSK" : \ 1982 (x == DRX_CONSTELLATION_PSK8) ? "PSK8" : \ 1983 (x == DRX_CONSTELLATION_QAM16) ? "QAM16" : \ 1984 (x == DRX_CONSTELLATION_QAM32) ? "QAM32" : \ 1985 (x == DRX_CONSTELLATION_QAM64) ? "QAM64" : \ 1986 (x == DRX_CONSTELLATION_QAM128) ? "QAM128" : \ 1987 (x == DRX_CONSTELLATION_QAM256) ? "QAM256" : \ 1988 (x == DRX_CONSTELLATION_QAM512) ? "QAM512" : \ 1989 (x == DRX_CONSTELLATION_QAM1024) ? "QAM1024" : \ 1990 (x == DRX_CONSTELLATION_QPSK_NR) ? "QPSK_NR" : \ 1991 (x == DRX_CONSTELLATION_AUTO) ? "Auto" : \ 1992 (x == DRX_CONSTELLATION_UNKNOWN) ? "Unknown" : \ 1993 "(Invalid)") 1994 #define DRX_STR_CODERATE(x) ( \ 1995 (x == DRX_CODERATE_1DIV2) ? "1/2nd" : \ 1996 (x == DRX_CODERATE_2DIV3) ? "2/3rd" : \ 1997 (x == DRX_CODERATE_3DIV4) ? "3/4th" : \ 1998 (x == DRX_CODERATE_5DIV6) ? "5/6th" : \ 1999 (x == DRX_CODERATE_7DIV8) ? "7/8th" : \ 2000 (x == DRX_CODERATE_AUTO) ? "Auto" : \ 2001 (x == DRX_CODERATE_UNKNOWN) ? "Unknown" : \ 2002 "(Invalid)") 2003 #define DRX_STR_HIERARCHY(x) ( \ 2004 (x == DRX_HIERARCHY_NONE) ? "None" : \ 2005 (x == DRX_HIERARCHY_ALPHA1) ? "Alpha=1" : \ 2006 (x == DRX_HIERARCHY_ALPHA2) ? "Alpha=2" : \ 2007 (x == DRX_HIERARCHY_ALPHA4) ? "Alpha=4" : \ 2008 (x == DRX_HIERARCHY_AUTO) ? "Auto" : \ 2009 (x == DRX_HIERARCHY_UNKNOWN) ? "Unknown" : \ 2010 "(Invalid)") 2011 #define DRX_STR_PRIORITY(x) ( \ 2012 (x == DRX_PRIORITY_LOW) ? "Low" : \ 2013 (x == DRX_PRIORITY_HIGH) ? "High" : \ 2014 (x == DRX_PRIORITY_UNKNOWN) ? "Unknown" : \ 2015 "(Invalid)") 2016 #define DRX_STR_MIRROR(x) ( \ 2017 (x == DRX_MIRROR_NO) ? "Normal" : \ 2018 (x == DRX_MIRROR_YES) ? "Mirrored" : \ 2019 (x == DRX_MIRROR_AUTO) ? "Auto" : \ 2020 (x == DRX_MIRROR_UNKNOWN) ? "Unknown" : \ 2021 "(Invalid)") 2022 #define DRX_STR_CLASSIFICATION(x) ( \ 2023 (x == DRX_CLASSIFICATION_GAUSS) ? "Gaussion" : \ 2024 (x == DRX_CLASSIFICATION_HVY_GAUSS) ? "Heavy Gaussion" : \ 2025 (x == DRX_CLASSIFICATION_COCHANNEL) ? "Co-channel" : \ 2026 (x == DRX_CLASSIFICATION_STATIC) ? "Static echo" : \ 2027 (x == DRX_CLASSIFICATION_MOVING) ? "Moving echo" : \ 2028 (x == DRX_CLASSIFICATION_ZERODB) ? "Zero dB echo" : \ 2029 (x == DRX_CLASSIFICATION_UNKNOWN) ? "Unknown" : \ 2030 (x == DRX_CLASSIFICATION_AUTO) ? "Auto" : \ 2031 "(Invalid)") 2032 2033 #define DRX_STR_INTERLEAVEMODE(x) ( \ 2034 (x == DRX_INTERLEAVEMODE_I128_J1) ? "I128_J1" : \ 2035 (x == DRX_INTERLEAVEMODE_I128_J1_V2) ? "I128_J1_V2" : \ 2036 (x == DRX_INTERLEAVEMODE_I128_J2) ? "I128_J2" : \ 2037 (x == DRX_INTERLEAVEMODE_I64_J2) ? "I64_J2" : \ 2038 (x == DRX_INTERLEAVEMODE_I128_J3) ? "I128_J3" : \ 2039 (x == DRX_INTERLEAVEMODE_I32_J4) ? "I32_J4" : \ 2040 (x == DRX_INTERLEAVEMODE_I128_J4) ? "I128_J4" : \ 2041 (x == DRX_INTERLEAVEMODE_I16_J8) ? "I16_J8" : \ 2042 (x == DRX_INTERLEAVEMODE_I128_J5) ? "I128_J5" : \ 2043 (x == DRX_INTERLEAVEMODE_I8_J16) ? "I8_J16" : \ 2044 (x == DRX_INTERLEAVEMODE_I128_J6) ? "I128_J6" : \ 2045 (x == DRX_INTERLEAVEMODE_RESERVED_11) ? "Reserved 11" : \ 2046 (x == DRX_INTERLEAVEMODE_I128_J7) ? "I128_J7" : \ 2047 (x == DRX_INTERLEAVEMODE_RESERVED_13) ? "Reserved 13" : \ 2048 (x == DRX_INTERLEAVEMODE_I128_J8) ? "I128_J8" : \ 2049 (x == DRX_INTERLEAVEMODE_RESERVED_15) ? "Reserved 15" : \ 2050 (x == DRX_INTERLEAVEMODE_I12_J17) ? "I12_J17" : \ 2051 (x == DRX_INTERLEAVEMODE_I5_J4) ? "I5_J4" : \ 2052 (x == DRX_INTERLEAVEMODE_B52_M240) ? "B52_M240" : \ 2053 (x == DRX_INTERLEAVEMODE_B52_M720) ? "B52_M720" : \ 2054 (x == DRX_INTERLEAVEMODE_B52_M48) ? "B52_M48" : \ 2055 (x == DRX_INTERLEAVEMODE_B52_M0) ? "B52_M0" : \ 2056 (x == DRX_INTERLEAVEMODE_UNKNOWN) ? "Unknown" : \ 2057 (x == DRX_INTERLEAVEMODE_AUTO) ? "Auto" : \ 2058 "(Invalid)") 2059 2060 #define DRX_STR_LDPC(x) ( \ 2061 (x == DRX_LDPC_0_4) ? "0.4" : \ 2062 (x == DRX_LDPC_0_6) ? "0.6" : \ 2063 (x == DRX_LDPC_0_8) ? "0.8" : \ 2064 (x == DRX_LDPC_AUTO) ? "Auto" : \ 2065 (x == DRX_LDPC_UNKNOWN) ? "Unknown" : \ 2066 "(Invalid)") 2067 2068 #define DRX_STR_CARRIER(x) ( \ 2069 (x == DRX_CARRIER_MULTI) ? "Multi" : \ 2070 (x == DRX_CARRIER_SINGLE) ? "Single" : \ 2071 (x == DRX_CARRIER_AUTO) ? "Auto" : \ 2072 (x == DRX_CARRIER_UNKNOWN) ? "Unknown" : \ 2073 "(Invalid)") 2074 2075 #define DRX_STR_FRAMEMODE(x) ( \ 2076 (x == DRX_FRAMEMODE_420) ? "420" : \ 2077 (x == DRX_FRAMEMODE_595) ? "595" : \ 2078 (x == DRX_FRAMEMODE_945) ? "945" : \ 2079 (x == DRX_FRAMEMODE_420_FIXED_PN) ? "420 with fixed PN" : \ 2080 (x == DRX_FRAMEMODE_945_FIXED_PN) ? "945 with fixed PN" : \ 2081 (x == DRX_FRAMEMODE_AUTO) ? "Auto" : \ 2082 (x == DRX_FRAMEMODE_UNKNOWN) ? "Unknown" : \ 2083 "(Invalid)") 2084 2085 #define DRX_STR_PILOT(x) ( \ 2086 (x == DRX_PILOT_ON) ? "On" : \ 2087 (x == DRX_PILOT_OFF) ? "Off" : \ 2088 (x == DRX_PILOT_AUTO) ? "Auto" : \ 2089 (x == DRX_PILOT_UNKNOWN) ? "Unknown" : \ 2090 "(Invalid)") 2091 /* TPS */ 2092 2093 #define DRX_STR_TPS_FRAME(x) ( \ 2094 (x == DRX_TPS_FRAME1) ? "Frame1" : \ 2095 (x == DRX_TPS_FRAME2) ? "Frame2" : \ 2096 (x == DRX_TPS_FRAME3) ? "Frame3" : \ 2097 (x == DRX_TPS_FRAME4) ? "Frame4" : \ 2098 (x == DRX_TPS_FRAME_UNKNOWN) ? "Unknown" : \ 2099 "(Invalid)") 2100 2101 /* lock status */ 2102 2103 #define DRX_STR_LOCKSTATUS(x) ( \ 2104 (x == DRX_NEVER_LOCK) ? "Never" : \ 2105 (x == DRX_NOT_LOCKED) ? "No" : \ 2106 (x == DRX_LOCKED) ? "Locked" : \ 2107 (x == DRX_LOCK_STATE_1) ? "Lock state 1" : \ 2108 (x == DRX_LOCK_STATE_2) ? "Lock state 2" : \ 2109 (x == DRX_LOCK_STATE_3) ? "Lock state 3" : \ 2110 (x == DRX_LOCK_STATE_4) ? "Lock state 4" : \ 2111 (x == DRX_LOCK_STATE_5) ? "Lock state 5" : \ 2112 (x == DRX_LOCK_STATE_6) ? "Lock state 6" : \ 2113 (x == DRX_LOCK_STATE_7) ? "Lock state 7" : \ 2114 (x == DRX_LOCK_STATE_8) ? "Lock state 8" : \ 2115 (x == DRX_LOCK_STATE_9) ? "Lock state 9" : \ 2116 "(Invalid)") 2117 2118 /* version information , modules */ 2119 #define DRX_STR_MODULE(x) ( \ 2120 (x == DRX_MODULE_DEVICE) ? "Device" : \ 2121 (x == DRX_MODULE_MICROCODE) ? "Microcode" : \ 2122 (x == DRX_MODULE_DRIVERCORE) ? "CoreDriver" : \ 2123 (x == DRX_MODULE_DEVICEDRIVER) ? "DeviceDriver" : \ 2124 (x == DRX_MODULE_BSP_I2C) ? "BSP I2C" : \ 2125 (x == DRX_MODULE_BSP_TUNER) ? "BSP Tuner" : \ 2126 (x == DRX_MODULE_BSP_HOST) ? "BSP Host" : \ 2127 (x == DRX_MODULE_DAP) ? "Data Access Protocol" : \ 2128 (x == DRX_MODULE_UNKNOWN) ? "Unknown" : \ 2129 "(Invalid)") 2130 2131 #define DRX_STR_POWER_MODE(x) ( \ 2132 (x == DRX_POWER_UP) ? "DRX_POWER_UP " : \ 2133 (x == DRX_POWER_MODE_1) ? "DRX_POWER_MODE_1" : \ 2134 (x == DRX_POWER_MODE_2) ? "DRX_POWER_MODE_2" : \ 2135 (x == DRX_POWER_MODE_3) ? "DRX_POWER_MODE_3" : \ 2136 (x == DRX_POWER_MODE_4) ? "DRX_POWER_MODE_4" : \ 2137 (x == DRX_POWER_MODE_5) ? "DRX_POWER_MODE_5" : \ 2138 (x == DRX_POWER_MODE_6) ? "DRX_POWER_MODE_6" : \ 2139 (x == DRX_POWER_MODE_7) ? "DRX_POWER_MODE_7" : \ 2140 (x == DRX_POWER_MODE_8) ? "DRX_POWER_MODE_8" : \ 2141 (x == DRX_POWER_MODE_9) ? "DRX_POWER_MODE_9" : \ 2142 (x == DRX_POWER_MODE_10) ? "DRX_POWER_MODE_10" : \ 2143 (x == DRX_POWER_MODE_11) ? "DRX_POWER_MODE_11" : \ 2144 (x == DRX_POWER_MODE_12) ? "DRX_POWER_MODE_12" : \ 2145 (x == DRX_POWER_MODE_13) ? "DRX_POWER_MODE_13" : \ 2146 (x == DRX_POWER_MODE_14) ? "DRX_POWER_MODE_14" : \ 2147 (x == DRX_POWER_MODE_15) ? "DRX_POWER_MODE_15" : \ 2148 (x == DRX_POWER_MODE_16) ? "DRX_POWER_MODE_16" : \ 2149 (x == DRX_POWER_DOWN) ? "DRX_POWER_DOWN " : \ 2150 "(Invalid)") 2151 2152 #define DRX_STR_OOB_STANDARD(x) ( \ 2153 (x == DRX_OOB_MODE_A) ? "ANSI 55-1 " : \ 2154 (x == DRX_OOB_MODE_B_GRADE_A) ? "ANSI 55-2 A" : \ 2155 (x == DRX_OOB_MODE_B_GRADE_B) ? "ANSI 55-2 B" : \ 2156 "(Invalid)") 2157 2158 #define DRX_STR_AUD_STANDARD(x) ( \ 2159 (x == DRX_AUD_STANDARD_BTSC) ? "BTSC" : \ 2160 (x == DRX_AUD_STANDARD_A2) ? "A2" : \ 2161 (x == DRX_AUD_STANDARD_EIAJ) ? "EIAJ" : \ 2162 (x == DRX_AUD_STANDARD_FM_STEREO) ? "FM Stereo" : \ 2163 (x == DRX_AUD_STANDARD_AUTO) ? "Auto" : \ 2164 (x == DRX_AUD_STANDARD_M_MONO) ? "M-Standard Mono" : \ 2165 (x == DRX_AUD_STANDARD_D_K_MONO) ? "D/K Mono FM" : \ 2166 (x == DRX_AUD_STANDARD_BG_FM) ? "B/G-Dual Carrier FM (A2)" : \ 2167 (x == DRX_AUD_STANDARD_D_K1) ? "D/K1-Dual Carrier FM" : \ 2168 (x == DRX_AUD_STANDARD_D_K2) ? "D/K2-Dual Carrier FM" : \ 2169 (x == DRX_AUD_STANDARD_D_K3) ? "D/K3-Dual Carrier FM" : \ 2170 (x == DRX_AUD_STANDARD_BG_NICAM_FM) ? "B/G-NICAM-FM" : \ 2171 (x == DRX_AUD_STANDARD_L_NICAM_AM) ? "L-NICAM-AM" : \ 2172 (x == DRX_AUD_STANDARD_I_NICAM_FM) ? "I-NICAM-FM" : \ 2173 (x == DRX_AUD_STANDARD_D_K_NICAM_FM) ? "D/K-NICAM-FM" : \ 2174 (x == DRX_AUD_STANDARD_UNKNOWN) ? "Unknown" : \ 2175 "(Invalid)") 2176 #define DRX_STR_AUD_STEREO(x) ( \ 2177 (x == true) ? "Stereo" : \ 2178 (x == false) ? "Mono" : \ 2179 "(Invalid)") 2180 2181 #define DRX_STR_AUD_SAP(x) ( \ 2182 (x == true) ? "Present" : \ 2183 (x == false) ? "Not present" : \ 2184 "(Invalid)") 2185 2186 #define DRX_STR_AUD_CARRIER(x) ( \ 2187 (x == true) ? "Present" : \ 2188 (x == false) ? "Not present" : \ 2189 "(Invalid)") 2190 2191 #define DRX_STR_AUD_RDS(x) ( \ 2192 (x == true) ? "Available" : \ 2193 (x == false) ? "Not Available" : \ 2194 "(Invalid)") 2195 2196 #define DRX_STR_AUD_NICAM_STATUS(x) ( \ 2197 (x == DRX_AUD_NICAM_DETECTED) ? "Detected" : \ 2198 (x == DRX_AUD_NICAM_NOT_DETECTED) ? "Not detected" : \ 2199 (x == DRX_AUD_NICAM_BAD) ? "Bad" : \ 2200 "(Invalid)") 2201 2202 #define DRX_STR_RDS_VALID(x) ( \ 2203 (x == true) ? "Valid" : \ 2204 (x == false) ? "Not Valid" : \ 2205 "(Invalid)") 2206 2207 /*------------------------------------------------------------------------- 2208 Access macros 2209 -------------------------------------------------------------------------*/ 2210 2211 /** 2212 * \brief Create a compilable reference to the microcode attribute 2213 * \param d pointer to demod instance 2214 * 2215 * Used as main reference to an attribute field. 2216 * Used by both macro implementation and function implementation. 2217 * These macros are defined to avoid duplication of code in macro and function 2218 * definitions that handle access of demod common or extended attributes. 2219 * 2220 */ 2221 2222 #define DRX_ATTR_MCRECORD(d) ((d)->my_common_attr->mcversion) 2223 #define DRX_ATTR_MIRRORFREQSPECT(d) ((d)->my_common_attr->mirror_freq_spect) 2224 #define DRX_ATTR_CURRENTPOWERMODE(d)((d)->my_common_attr->current_power_mode) 2225 #define DRX_ATTR_ISOPENED(d) ((d)->my_common_attr->is_opened) 2226 #define DRX_ATTR_USEBOOTLOADER(d) ((d)->my_common_attr->use_bootloader) 2227 #define DRX_ATTR_CURRENTSTANDARD(d) ((d)->my_common_attr->current_standard) 2228 #define DRX_ATTR_PREVSTANDARD(d) ((d)->my_common_attr->prev_standard) 2229 #define DRX_ATTR_CACHESTANDARD(d) ((d)->my_common_attr->di_cache_standard) 2230 #define DRX_ATTR_CURRENTCHANNEL(d) ((d)->my_common_attr->current_channel) 2231 #define DRX_ATTR_MICROCODE(d) ((d)->my_common_attr->microcode) 2232 #define DRX_ATTR_VERIFYMICROCODE(d) ((d)->my_common_attr->verify_microcode) 2233 #define DRX_ATTR_CAPABILITIES(d) ((d)->my_common_attr->capabilities) 2234 #define DRX_ATTR_PRODUCTID(d) ((d)->my_common_attr->product_id) 2235 #define DRX_ATTR_INTERMEDIATEFREQ(d) ((d)->my_common_attr->intermediate_freq) 2236 #define DRX_ATTR_SYSCLOCKFREQ(d) ((d)->my_common_attr->sys_clock_freq) 2237 #define DRX_ATTR_TUNERRFAGCPOL(d) ((d)->my_common_attr->tuner_rf_agc_pol) 2238 #define DRX_ATTR_TUNERIFAGCPOL(d) ((d)->my_common_attr->tuner_if_agc_pol) 2239 #define DRX_ATTR_TUNERSLOWMODE(d) ((d)->my_common_attr->tuner_slow_mode) 2240 #define DRX_ATTR_TUNERSPORTNR(d) ((d)->my_common_attr->tuner_port_nr) 2241 #define DRX_ATTR_I2CADDR(d) ((d)->my_i2c_dev_addr->i2c_addr) 2242 #define DRX_ATTR_I2CDEVID(d) ((d)->my_i2c_dev_addr->i2c_dev_id) 2243 #define DRX_ISMCVERTYPE(x) ((x) == AUX_VER_RECORD) 2244 2245 /**************************/ 2246 2247 /* Macros with device-specific handling are converted to CFG functions */ 2248 2249 #define DRX_ACCESSMACRO_SET(demod, value, cfg_name, data_type) \ 2250 do { \ 2251 struct drx_cfg config; \ 2252 data_type cfg_data; \ 2253 config.cfg_type = cfg_name; \ 2254 config.cfg_data = &cfg_data; \ 2255 cfg_data = value; \ 2256 drx_ctrl(demod, DRX_CTRL_SET_CFG, &config); \ 2257 } while (0) 2258 2259 #define DRX_ACCESSMACRO_GET(demod, value, cfg_name, data_type, error_value) \ 2260 do { \ 2261 int cfg_status; \ 2262 struct drx_cfg config; \ 2263 data_type cfg_data; \ 2264 config.cfg_type = cfg_name; \ 2265 config.cfg_data = &cfg_data; \ 2266 cfg_status = drx_ctrl(demod, DRX_CTRL_GET_CFG, &config); \ 2267 if (cfg_status == 0) { \ 2268 value = cfg_data; \ 2269 } else { \ 2270 value = (data_type)error_value; \ 2271 } \ 2272 } while (0) 2273 2274 /* Configuration functions for usage by Access (XS) Macros */ 2275 2276 #ifndef DRX_XS_CFG_BASE 2277 #define DRX_XS_CFG_BASE (500) 2278 #endif 2279 2280 #define DRX_XS_CFG_PRESET (DRX_XS_CFG_BASE + 0) 2281 #define DRX_XS_CFG_AUD_BTSC_DETECT (DRX_XS_CFG_BASE + 1) 2282 #define DRX_XS_CFG_QAM_LOCKRANGE (DRX_XS_CFG_BASE + 2) 2283 2284 /* Access Macros with device-specific handling */ 2285 2286 #define DRX_SET_PRESET(d, x) \ 2287 DRX_ACCESSMACRO_SET((d), (x), DRX_XS_CFG_PRESET, char*) 2288 #define DRX_GET_PRESET(d, x) \ 2289 DRX_ACCESSMACRO_GET((d), (x), DRX_XS_CFG_PRESET, char*, "ERROR") 2290 2291 #define DRX_SET_AUD_BTSC_DETECT(d, x) DRX_ACCESSMACRO_SET((d), (x), \ 2292 DRX_XS_CFG_AUD_BTSC_DETECT, enum drx_aud_btsc_detect) 2293 #define DRX_GET_AUD_BTSC_DETECT(d, x) DRX_ACCESSMACRO_GET((d), (x), \ 2294 DRX_XS_CFG_AUD_BTSC_DETECT, enum drx_aud_btsc_detect, DRX_UNKNOWN) 2295 2296 #define DRX_SET_QAM_LOCKRANGE(d, x) DRX_ACCESSMACRO_SET((d), (x), \ 2297 DRX_XS_CFG_QAM_LOCKRANGE, enum drx_qam_lock_range) 2298 #define DRX_GET_QAM_LOCKRANGE(d, x) DRX_ACCESSMACRO_GET((d), (x), \ 2299 DRX_XS_CFG_QAM_LOCKRANGE, enum drx_qam_lock_range, DRX_UNKNOWN) 2300 2301 /** 2302 * \brief Macro to check if std is an ATV standard 2303 * \retval true std is an ATV standard 2304 * \retval false std is an ATV standard 2305 */ 2306 #define DRX_ISATVSTD(std) (((std) == DRX_STANDARD_PAL_SECAM_BG) || \ 2307 ((std) == DRX_STANDARD_PAL_SECAM_DK) || \ 2308 ((std) == DRX_STANDARD_PAL_SECAM_I) || \ 2309 ((std) == DRX_STANDARD_PAL_SECAM_L) || \ 2310 ((std) == DRX_STANDARD_PAL_SECAM_LP) || \ 2311 ((std) == DRX_STANDARD_NTSC) || \ 2312 ((std) == DRX_STANDARD_FM)) 2313 2314 /** 2315 * \brief Macro to check if std is an QAM standard 2316 * \retval true std is an QAM standards 2317 * \retval false std is an QAM standards 2318 */ 2319 #define DRX_ISQAMSTD(std) (((std) == DRX_STANDARD_ITU_A) || \ 2320 ((std) == DRX_STANDARD_ITU_B) || \ 2321 ((std) == DRX_STANDARD_ITU_C) || \ 2322 ((std) == DRX_STANDARD_ITU_D)) 2323 2324 /** 2325 * \brief Macro to check if std is VSB standard 2326 * \retval true std is VSB standard 2327 * \retval false std is not VSB standard 2328 */ 2329 #define DRX_ISVSBSTD(std) ((std) == DRX_STANDARD_8VSB) 2330 2331 /** 2332 * \brief Macro to check if std is DVBT standard 2333 * \retval true std is DVBT standard 2334 * \retval false std is not DVBT standard 2335 */ 2336 #define DRX_ISDVBTSTD(std) ((std) == DRX_STANDARD_DVBT) 2337 2338 /*------------------------------------------------------------------------- 2339 THE END 2340 -------------------------------------------------------------------------*/ 2341 #endif /* __DRXDRIVER_H__ */ 2342