xref: /linux/drivers/media/dvb-frontends/cxd2820r_t.c (revision d91517839e5d95adc0cf4b28caa7af62a71de526)
1 /*
2  * Sony CXD2820R demodulator driver
3  *
4  * Copyright (C) 2010 Antti Palosaari <crope@iki.fi>
5  *
6  *    This program is free software; you can redistribute it and/or modify
7  *    it under the terms of the GNU General Public License as published by
8  *    the Free Software Foundation; either version 2 of the License, or
9  *    (at your option) any later version.
10  *
11  *    This program is distributed in the hope that it will be useful,
12  *    but WITHOUT ANY WARRANTY; without even the implied warranty of
13  *    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
14  *    GNU General Public License for more details.
15  *
16  *    You should have received a copy of the GNU General Public License along
17  *    with this program; if not, write to the Free Software Foundation, Inc.,
18  *    51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
19  */
20 
21 
22 #include "cxd2820r_priv.h"
23 
24 int cxd2820r_set_frontend_t(struct dvb_frontend *fe)
25 {
26 	struct cxd2820r_priv *priv = fe->demodulator_priv;
27 	struct dtv_frontend_properties *c = &fe->dtv_property_cache;
28 	int ret, i, bw_i;
29 	u32 if_freq, if_ctl;
30 	u64 num;
31 	u8 buf[3], bw_param;
32 	u8 bw_params1[][5] = {
33 		{ 0x17, 0xea, 0xaa, 0xaa, 0xaa }, /* 6 MHz */
34 		{ 0x14, 0x80, 0x00, 0x00, 0x00 }, /* 7 MHz */
35 		{ 0x11, 0xf0, 0x00, 0x00, 0x00 }, /* 8 MHz */
36 	};
37 	u8 bw_params2[][2] = {
38 		{ 0x1f, 0xdc }, /* 6 MHz */
39 		{ 0x12, 0xf8 }, /* 7 MHz */
40 		{ 0x01, 0xe0 }, /* 8 MHz */
41 	};
42 	struct reg_val_mask tab[] = {
43 		{ 0x00080, 0x00, 0xff },
44 		{ 0x00081, 0x03, 0xff },
45 		{ 0x00085, 0x07, 0xff },
46 		{ 0x00088, 0x01, 0xff },
47 
48 		{ 0x00070, priv->cfg.ts_mode, 0xff },
49 		{ 0x000cb, priv->cfg.if_agc_polarity << 6, 0x40 },
50 		{ 0x000a5, 0x00, 0x01 },
51 		{ 0x00082, 0x20, 0x60 },
52 		{ 0x000c2, 0xc3, 0xff },
53 		{ 0x0016a, 0x50, 0xff },
54 		{ 0x00427, 0x41, 0xff },
55 	};
56 
57 	dev_dbg(&priv->i2c->dev, "%s: frequency=%d bandwidth_hz=%d\n", __func__,
58 			c->frequency, c->bandwidth_hz);
59 
60 	switch (c->bandwidth_hz) {
61 	case 6000000:
62 		bw_i = 0;
63 		bw_param = 2;
64 		break;
65 	case 7000000:
66 		bw_i = 1;
67 		bw_param = 1;
68 		break;
69 	case 8000000:
70 		bw_i = 2;
71 		bw_param = 0;
72 		break;
73 	default:
74 		return -EINVAL;
75 	}
76 
77 	/* program tuner */
78 	if (fe->ops.tuner_ops.set_params)
79 		fe->ops.tuner_ops.set_params(fe);
80 
81 	if (priv->delivery_system != SYS_DVBT) {
82 		for (i = 0; i < ARRAY_SIZE(tab); i++) {
83 			ret = cxd2820r_wr_reg_mask(priv, tab[i].reg,
84 				tab[i].val, tab[i].mask);
85 			if (ret)
86 				goto error;
87 		}
88 	}
89 
90 	priv->delivery_system = SYS_DVBT;
91 	priv->ber_running = 0; /* tune stops BER counter */
92 
93 	/* program IF frequency */
94 	if (fe->ops.tuner_ops.get_if_frequency) {
95 		ret = fe->ops.tuner_ops.get_if_frequency(fe, &if_freq);
96 		if (ret)
97 			goto error;
98 	} else
99 		if_freq = 0;
100 
101 	dev_dbg(&priv->i2c->dev, "%s: if_freq=%d\n", __func__, if_freq);
102 
103 	num = if_freq / 1000; /* Hz => kHz */
104 	num *= 0x1000000;
105 	if_ctl = cxd2820r_div_u64_round_closest(num, 41000);
106 	buf[0] = ((if_ctl >> 16) & 0xff);
107 	buf[1] = ((if_ctl >>  8) & 0xff);
108 	buf[2] = ((if_ctl >>  0) & 0xff);
109 
110 	ret = cxd2820r_wr_regs(priv, 0x000b6, buf, 3);
111 	if (ret)
112 		goto error;
113 
114 	ret = cxd2820r_wr_regs(priv, 0x0009f, bw_params1[bw_i], 5);
115 	if (ret)
116 		goto error;
117 
118 	ret = cxd2820r_wr_reg_mask(priv, 0x000d7, bw_param << 6, 0xc0);
119 	if (ret)
120 		goto error;
121 
122 	ret = cxd2820r_wr_regs(priv, 0x000d9, bw_params2[bw_i], 2);
123 	if (ret)
124 		goto error;
125 
126 	ret = cxd2820r_wr_reg(priv, 0x000ff, 0x08);
127 	if (ret)
128 		goto error;
129 
130 	ret = cxd2820r_wr_reg(priv, 0x000fe, 0x01);
131 	if (ret)
132 		goto error;
133 
134 	return ret;
135 error:
136 	dev_dbg(&priv->i2c->dev, "%s: failed=%d\n", __func__, ret);
137 	return ret;
138 }
139 
140 int cxd2820r_get_frontend_t(struct dvb_frontend *fe)
141 {
142 	struct cxd2820r_priv *priv = fe->demodulator_priv;
143 	struct dtv_frontend_properties *c = &fe->dtv_property_cache;
144 	int ret;
145 	u8 buf[2];
146 
147 	ret = cxd2820r_rd_regs(priv, 0x0002f, buf, sizeof(buf));
148 	if (ret)
149 		goto error;
150 
151 	switch ((buf[0] >> 6) & 0x03) {
152 	case 0:
153 		c->modulation = QPSK;
154 		break;
155 	case 1:
156 		c->modulation = QAM_16;
157 		break;
158 	case 2:
159 		c->modulation = QAM_64;
160 		break;
161 	}
162 
163 	switch ((buf[1] >> 1) & 0x03) {
164 	case 0:
165 		c->transmission_mode = TRANSMISSION_MODE_2K;
166 		break;
167 	case 1:
168 		c->transmission_mode = TRANSMISSION_MODE_8K;
169 		break;
170 	}
171 
172 	switch ((buf[1] >> 3) & 0x03) {
173 	case 0:
174 		c->guard_interval = GUARD_INTERVAL_1_32;
175 		break;
176 	case 1:
177 		c->guard_interval = GUARD_INTERVAL_1_16;
178 		break;
179 	case 2:
180 		c->guard_interval = GUARD_INTERVAL_1_8;
181 		break;
182 	case 3:
183 		c->guard_interval = GUARD_INTERVAL_1_4;
184 		break;
185 	}
186 
187 	switch ((buf[0] >> 3) & 0x07) {
188 	case 0:
189 		c->hierarchy = HIERARCHY_NONE;
190 		break;
191 	case 1:
192 		c->hierarchy = HIERARCHY_1;
193 		break;
194 	case 2:
195 		c->hierarchy = HIERARCHY_2;
196 		break;
197 	case 3:
198 		c->hierarchy = HIERARCHY_4;
199 		break;
200 	}
201 
202 	switch ((buf[0] >> 0) & 0x07) {
203 	case 0:
204 		c->code_rate_HP = FEC_1_2;
205 		break;
206 	case 1:
207 		c->code_rate_HP = FEC_2_3;
208 		break;
209 	case 2:
210 		c->code_rate_HP = FEC_3_4;
211 		break;
212 	case 3:
213 		c->code_rate_HP = FEC_5_6;
214 		break;
215 	case 4:
216 		c->code_rate_HP = FEC_7_8;
217 		break;
218 	}
219 
220 	switch ((buf[1] >> 5) & 0x07) {
221 	case 0:
222 		c->code_rate_LP = FEC_1_2;
223 		break;
224 	case 1:
225 		c->code_rate_LP = FEC_2_3;
226 		break;
227 	case 2:
228 		c->code_rate_LP = FEC_3_4;
229 		break;
230 	case 3:
231 		c->code_rate_LP = FEC_5_6;
232 		break;
233 	case 4:
234 		c->code_rate_LP = FEC_7_8;
235 		break;
236 	}
237 
238 	ret = cxd2820r_rd_reg(priv, 0x007c6, &buf[0]);
239 	if (ret)
240 		goto error;
241 
242 	switch ((buf[0] >> 0) & 0x01) {
243 	case 0:
244 		c->inversion = INVERSION_OFF;
245 		break;
246 	case 1:
247 		c->inversion = INVERSION_ON;
248 		break;
249 	}
250 
251 	return ret;
252 error:
253 	dev_dbg(&priv->i2c->dev, "%s: failed=%d\n", __func__, ret);
254 	return ret;
255 }
256 
257 int cxd2820r_read_ber_t(struct dvb_frontend *fe, u32 *ber)
258 {
259 	struct cxd2820r_priv *priv = fe->demodulator_priv;
260 	int ret;
261 	u8 buf[3], start_ber = 0;
262 	*ber = 0;
263 
264 	if (priv->ber_running) {
265 		ret = cxd2820r_rd_regs(priv, 0x00076, buf, sizeof(buf));
266 		if (ret)
267 			goto error;
268 
269 		if ((buf[2] >> 7) & 0x01 || (buf[2] >> 4) & 0x01) {
270 			*ber = (buf[2] & 0x0f) << 16 | buf[1] << 8 | buf[0];
271 			start_ber = 1;
272 		}
273 	} else {
274 		priv->ber_running = 1;
275 		start_ber = 1;
276 	}
277 
278 	if (start_ber) {
279 		/* (re)start BER */
280 		ret = cxd2820r_wr_reg(priv, 0x00079, 0x01);
281 		if (ret)
282 			goto error;
283 	}
284 
285 	return ret;
286 error:
287 	dev_dbg(&priv->i2c->dev, "%s: failed=%d\n", __func__, ret);
288 	return ret;
289 }
290 
291 int cxd2820r_read_signal_strength_t(struct dvb_frontend *fe,
292 	u16 *strength)
293 {
294 	struct cxd2820r_priv *priv = fe->demodulator_priv;
295 	int ret;
296 	u8 buf[2];
297 	u16 tmp;
298 
299 	ret = cxd2820r_rd_regs(priv, 0x00026, buf, sizeof(buf));
300 	if (ret)
301 		goto error;
302 
303 	tmp = (buf[0] & 0x0f) << 8 | buf[1];
304 	tmp = ~tmp & 0x0fff;
305 
306 	/* scale value to 0x0000-0xffff from 0x0000-0x0fff */
307 	*strength = tmp * 0xffff / 0x0fff;
308 
309 	return ret;
310 error:
311 	dev_dbg(&priv->i2c->dev, "%s: failed=%d\n", __func__, ret);
312 	return ret;
313 }
314 
315 int cxd2820r_read_snr_t(struct dvb_frontend *fe, u16 *snr)
316 {
317 	struct cxd2820r_priv *priv = fe->demodulator_priv;
318 	int ret;
319 	u8 buf[2];
320 	u16 tmp;
321 	/* report SNR in dB * 10 */
322 
323 	ret = cxd2820r_rd_regs(priv, 0x00028, buf, sizeof(buf));
324 	if (ret)
325 		goto error;
326 
327 	tmp = (buf[0] & 0x1f) << 8 | buf[1];
328 	#define CXD2820R_LOG10_8_24 15151336 /* log10(8) << 24 */
329 	if (tmp)
330 		*snr = (intlog10(tmp) - CXD2820R_LOG10_8_24) / ((1 << 24)
331 			/ 100);
332 	else
333 		*snr = 0;
334 
335 	dev_dbg(&priv->i2c->dev, "%s: dBx10=%d val=%04x\n", __func__, *snr,
336 			tmp);
337 
338 	return ret;
339 error:
340 	dev_dbg(&priv->i2c->dev, "%s: failed=%d\n", __func__, ret);
341 	return ret;
342 }
343 
344 int cxd2820r_read_ucblocks_t(struct dvb_frontend *fe, u32 *ucblocks)
345 {
346 	*ucblocks = 0;
347 	/* no way to read ? */
348 	return 0;
349 }
350 
351 int cxd2820r_read_status_t(struct dvb_frontend *fe, fe_status_t *status)
352 {
353 	struct cxd2820r_priv *priv = fe->demodulator_priv;
354 	int ret;
355 	u8 buf[4];
356 	*status = 0;
357 
358 	ret = cxd2820r_rd_reg(priv, 0x00010, &buf[0]);
359 	if (ret)
360 		goto error;
361 
362 	if ((buf[0] & 0x07) == 6) {
363 		ret = cxd2820r_rd_reg(priv, 0x00073, &buf[1]);
364 		if (ret)
365 			goto error;
366 
367 		if (((buf[1] >> 3) & 0x01) == 1) {
368 			*status |= FE_HAS_SIGNAL | FE_HAS_CARRIER |
369 				FE_HAS_VITERBI | FE_HAS_SYNC | FE_HAS_LOCK;
370 		} else {
371 			*status |= FE_HAS_SIGNAL | FE_HAS_CARRIER |
372 				FE_HAS_VITERBI | FE_HAS_SYNC;
373 		}
374 	} else {
375 		ret = cxd2820r_rd_reg(priv, 0x00014, &buf[2]);
376 		if (ret)
377 			goto error;
378 
379 		if ((buf[2] & 0x0f) >= 4) {
380 			ret = cxd2820r_rd_reg(priv, 0x00a14, &buf[3]);
381 			if (ret)
382 				goto error;
383 
384 			if (((buf[3] >> 4) & 0x01) == 1)
385 				*status |= FE_HAS_SIGNAL;
386 		}
387 	}
388 
389 	dev_dbg(&priv->i2c->dev, "%s: lock=%*ph\n", __func__, 4, buf);
390 
391 	return ret;
392 error:
393 	dev_dbg(&priv->i2c->dev, "%s: failed=%d\n", __func__, ret);
394 	return ret;
395 }
396 
397 int cxd2820r_init_t(struct dvb_frontend *fe)
398 {
399 	struct cxd2820r_priv *priv = fe->demodulator_priv;
400 	int ret;
401 
402 	ret = cxd2820r_wr_reg(priv, 0x00085, 0x07);
403 	if (ret)
404 		goto error;
405 
406 	return ret;
407 error:
408 	dev_dbg(&priv->i2c->dev, "%s: failed=%d\n", __func__, ret);
409 	return ret;
410 }
411 
412 int cxd2820r_sleep_t(struct dvb_frontend *fe)
413 {
414 	struct cxd2820r_priv *priv = fe->demodulator_priv;
415 	int ret, i;
416 	struct reg_val_mask tab[] = {
417 		{ 0x000ff, 0x1f, 0xff },
418 		{ 0x00085, 0x00, 0xff },
419 		{ 0x00088, 0x01, 0xff },
420 		{ 0x00081, 0x00, 0xff },
421 		{ 0x00080, 0x00, 0xff },
422 	};
423 
424 	dev_dbg(&priv->i2c->dev, "%s\n", __func__);
425 
426 	priv->delivery_system = SYS_UNDEFINED;
427 
428 	for (i = 0; i < ARRAY_SIZE(tab); i++) {
429 		ret = cxd2820r_wr_reg_mask(priv, tab[i].reg, tab[i].val,
430 			tab[i].mask);
431 		if (ret)
432 			goto error;
433 	}
434 
435 	return ret;
436 error:
437 	dev_dbg(&priv->i2c->dev, "%s: failed=%d\n", __func__, ret);
438 	return ret;
439 }
440 
441 int cxd2820r_get_tune_settings_t(struct dvb_frontend *fe,
442 	struct dvb_frontend_tune_settings *s)
443 {
444 	s->min_delay_ms = 500;
445 	s->step_size = fe->ops.info.frequency_stepsize * 2;
446 	s->max_drift = (fe->ops.info.frequency_stepsize * 2) + 1;
447 
448 	return 0;
449 }
450