xref: /linux/drivers/media/dvb-frontends/cx24123.c (revision a2cce7a9f1b8cc3d4edce106fb971529f1d4d9ce)
1 /*
2  *   Conexant cx24123/cx24109 - DVB QPSK Satellite demod/tuner driver
3  *
4  *   Copyright (C) 2005 Steven Toth <stoth@linuxtv.org>
5  *
6  *   Support for KWorld DVB-S 100 by Vadim Catana <skystar@moldova.cc>
7  *
8  *   Support for CX24123/CX24113-NIM by Patrick Boettcher <pb@linuxtv.org>
9  *
10  *   This program is free software; you can redistribute it and/or
11  *   modify it under the terms of the GNU General Public License as
12  *   published by the Free Software Foundation; either version 2 of
13  *   the License, or (at your option) any later version.
14  *
15  *   This program is distributed in the hope that it will be useful,
16  *   but WITHOUT ANY WARRANTY; without even the implied warranty of
17  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
18  *   General Public License for more details.
19  *
20  *   You should have received a copy of the GNU General Public License
21  *   along with this program; if not, write to the Free Software
22  *   Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
23  */
24 
25 #include <linux/slab.h>
26 #include <linux/kernel.h>
27 #include <linux/module.h>
28 #include <linux/init.h>
29 #include <asm/div64.h>
30 
31 #include "dvb_frontend.h"
32 #include "cx24123.h"
33 
34 #define XTAL 10111000
35 
36 static int force_band;
37 module_param(force_band, int, 0644);
38 MODULE_PARM_DESC(force_band, "Force a specific band select "\
39 	"(1-9, default:off).");
40 
41 static int debug;
42 module_param(debug, int, 0644);
43 MODULE_PARM_DESC(debug, "Activates frontend debugging (default:0)");
44 
45 #define info(args...) do { printk(KERN_INFO "CX24123: " args); } while (0)
46 #define err(args...)  do { printk(KERN_ERR  "CX24123: " args); } while (0)
47 
48 #define dprintk(args...) \
49 	do { \
50 		if (debug) { \
51 			printk(KERN_DEBUG "CX24123: %s: ", __func__); \
52 			printk(args); \
53 		} \
54 	} while (0)
55 
56 struct cx24123_state {
57 	struct i2c_adapter *i2c;
58 	const struct cx24123_config *config;
59 
60 	struct dvb_frontend frontend;
61 
62 	/* Some PLL specifics for tuning */
63 	u32 VCAarg;
64 	u32 VGAarg;
65 	u32 bandselectarg;
66 	u32 pllarg;
67 	u32 FILTune;
68 
69 	struct i2c_adapter tuner_i2c_adapter;
70 
71 	u8 demod_rev;
72 
73 	/* The Demod/Tuner can't easily provide these, we cache them */
74 	u32 currentfreq;
75 	u32 currentsymbolrate;
76 };
77 
78 /* Various tuner defaults need to be established for a given symbol rate Sps */
79 static struct cx24123_AGC_val {
80 	u32 symbolrate_low;
81 	u32 symbolrate_high;
82 	u32 VCAprogdata;
83 	u32 VGAprogdata;
84 	u32 FILTune;
85 } cx24123_AGC_vals[] =
86 {
87 	{
88 		.symbolrate_low		= 1000000,
89 		.symbolrate_high	= 4999999,
90 		/* the specs recommend other values for VGA offsets,
91 		   but tests show they are wrong */
92 		.VGAprogdata		= (1 << 19) | (0x180 << 9) | 0x1e0,
93 		.VCAprogdata		= (2 << 19) | (0x07 << 9) | 0x07,
94 		.FILTune		= 0x27f /* 0.41 V */
95 	},
96 	{
97 		.symbolrate_low		=  5000000,
98 		.symbolrate_high	= 14999999,
99 		.VGAprogdata		= (1 << 19) | (0x180 << 9) | 0x1e0,
100 		.VCAprogdata		= (2 << 19) | (0x07 << 9) | 0x1f,
101 		.FILTune		= 0x317 /* 0.90 V */
102 	},
103 	{
104 		.symbolrate_low		= 15000000,
105 		.symbolrate_high	= 45000000,
106 		.VGAprogdata		= (1 << 19) | (0x100 << 9) | 0x180,
107 		.VCAprogdata		= (2 << 19) | (0x07 << 9) | 0x3f,
108 		.FILTune		= 0x145 /* 2.70 V */
109 	},
110 };
111 
112 /*
113  * Various tuner defaults need to be established for a given frequency kHz.
114  * fixme: The bounds on the bands do not match the doc in real life.
115  * fixme: Some of them have been moved, other might need adjustment.
116  */
117 static struct cx24123_bandselect_val {
118 	u32 freq_low;
119 	u32 freq_high;
120 	u32 VCOdivider;
121 	u32 progdata;
122 } cx24123_bandselect_vals[] =
123 {
124 	/* band 1 */
125 	{
126 		.freq_low	= 950000,
127 		.freq_high	= 1074999,
128 		.VCOdivider	= 4,
129 		.progdata	= (0 << 19) | (0 << 9) | 0x40,
130 	},
131 
132 	/* band 2 */
133 	{
134 		.freq_low	= 1075000,
135 		.freq_high	= 1177999,
136 		.VCOdivider	= 4,
137 		.progdata	= (0 << 19) | (0 << 9) | 0x80,
138 	},
139 
140 	/* band 3 */
141 	{
142 		.freq_low	= 1178000,
143 		.freq_high	= 1295999,
144 		.VCOdivider	= 2,
145 		.progdata	= (0 << 19) | (1 << 9) | 0x01,
146 	},
147 
148 	/* band 4 */
149 	{
150 		.freq_low	= 1296000,
151 		.freq_high	= 1431999,
152 		.VCOdivider	= 2,
153 		.progdata	= (0 << 19) | (1 << 9) | 0x02,
154 	},
155 
156 	/* band 5 */
157 	{
158 		.freq_low	= 1432000,
159 		.freq_high	= 1575999,
160 		.VCOdivider	= 2,
161 		.progdata	= (0 << 19) | (1 << 9) | 0x04,
162 	},
163 
164 	/* band 6 */
165 	{
166 		.freq_low	= 1576000,
167 		.freq_high	= 1717999,
168 		.VCOdivider	= 2,
169 		.progdata	= (0 << 19) | (1 << 9) | 0x08,
170 	},
171 
172 	/* band 7 */
173 	{
174 		.freq_low	= 1718000,
175 		.freq_high	= 1855999,
176 		.VCOdivider	= 2,
177 		.progdata	= (0 << 19) | (1 << 9) | 0x10,
178 	},
179 
180 	/* band 8 */
181 	{
182 		.freq_low	= 1856000,
183 		.freq_high	= 2035999,
184 		.VCOdivider	= 2,
185 		.progdata	= (0 << 19) | (1 << 9) | 0x20,
186 	},
187 
188 	/* band 9 */
189 	{
190 		.freq_low	= 2036000,
191 		.freq_high	= 2150000,
192 		.VCOdivider	= 2,
193 		.progdata	= (0 << 19) | (1 << 9) | 0x40,
194 	},
195 };
196 
197 static struct {
198 	u8 reg;
199 	u8 data;
200 } cx24123_regdata[] =
201 {
202 	{0x00, 0x03}, /* Reset system */
203 	{0x00, 0x00}, /* Clear reset */
204 	{0x03, 0x07}, /* QPSK, DVB, Auto Acquisition (default) */
205 	{0x04, 0x10}, /* MPEG */
206 	{0x05, 0x04}, /* MPEG */
207 	{0x06, 0x31}, /* MPEG (default) */
208 	{0x0b, 0x00}, /* Freq search start point (default) */
209 	{0x0c, 0x00}, /* Demodulator sample gain (default) */
210 	{0x0d, 0x7f}, /* Force driver to shift until the maximum (+-10 MHz) */
211 	{0x0e, 0x03}, /* Default non-inverted, FEC 3/4 (default) */
212 	{0x0f, 0xfe}, /* FEC search mask (all supported codes) */
213 	{0x10, 0x01}, /* Default search inversion, no repeat (default) */
214 	{0x16, 0x00}, /* Enable reading of frequency */
215 	{0x17, 0x01}, /* Enable EsNO Ready Counter */
216 	{0x1c, 0x80}, /* Enable error counter */
217 	{0x20, 0x00}, /* Tuner burst clock rate = 500KHz */
218 	{0x21, 0x15}, /* Tuner burst mode, word length = 0x15 */
219 	{0x28, 0x00}, /* Enable FILTERV with positive pol., DiSEqC 2.x off */
220 	{0x29, 0x00}, /* DiSEqC LNB_DC off */
221 	{0x2a, 0xb0}, /* DiSEqC Parameters (default) */
222 	{0x2b, 0x73}, /* DiSEqC Tone Frequency (default) */
223 	{0x2c, 0x00}, /* DiSEqC Message (0x2c - 0x31) */
224 	{0x2d, 0x00},
225 	{0x2e, 0x00},
226 	{0x2f, 0x00},
227 	{0x30, 0x00},
228 	{0x31, 0x00},
229 	{0x32, 0x8c}, /* DiSEqC Parameters (default) */
230 	{0x33, 0x00}, /* Interrupts off (0x33 - 0x34) */
231 	{0x34, 0x00},
232 	{0x35, 0x03}, /* DiSEqC Tone Amplitude (default) */
233 	{0x36, 0x02}, /* DiSEqC Parameters (default) */
234 	{0x37, 0x3a}, /* DiSEqC Parameters (default) */
235 	{0x3a, 0x00}, /* Enable AGC accumulator (for signal strength) */
236 	{0x44, 0x00}, /* Constellation (default) */
237 	{0x45, 0x00}, /* Symbol count (default) */
238 	{0x46, 0x0d}, /* Symbol rate estimator on (default) */
239 	{0x56, 0xc1}, /* Error Counter = Viterbi BER */
240 	{0x57, 0xff}, /* Error Counter Window (default) */
241 	{0x5c, 0x20}, /* Acquisition AFC Expiration window (default is 0x10) */
242 	{0x67, 0x83}, /* Non-DCII symbol clock */
243 };
244 
245 static int cx24123_i2c_writereg(struct cx24123_state *state,
246 	u8 i2c_addr, int reg, int data)
247 {
248 	u8 buf[] = { reg, data };
249 	struct i2c_msg msg = {
250 		.addr = i2c_addr, .flags = 0, .buf = buf, .len = 2
251 	};
252 	int err;
253 
254 	/* printk(KERN_DEBUG "wr(%02x): %02x %02x\n", i2c_addr, reg, data); */
255 
256 	err = i2c_transfer(state->i2c, &msg, 1);
257 	if (err != 1) {
258 		printk("%s: writereg error(err == %i, reg == 0x%02x,"
259 			 " data == 0x%02x)\n", __func__, err, reg, data);
260 		return err;
261 	}
262 
263 	return 0;
264 }
265 
266 static int cx24123_i2c_readreg(struct cx24123_state *state, u8 i2c_addr, u8 reg)
267 {
268 	int ret;
269 	u8 b = 0;
270 	struct i2c_msg msg[] = {
271 		{ .addr = i2c_addr, .flags = 0, .buf = &reg, .len = 1 },
272 		{ .addr = i2c_addr, .flags = I2C_M_RD, .buf = &b, .len = 1 }
273 	};
274 
275 	ret = i2c_transfer(state->i2c, msg, 2);
276 
277 	if (ret != 2) {
278 		err("%s: reg=0x%x (error=%d)\n", __func__, reg, ret);
279 		return ret;
280 	}
281 
282 	/* printk(KERN_DEBUG "rd(%02x): %02x %02x\n", i2c_addr, reg, b); */
283 
284 	return b;
285 }
286 
287 #define cx24123_readreg(state, reg) \
288 	cx24123_i2c_readreg(state, state->config->demod_address, reg)
289 #define cx24123_writereg(state, reg, val) \
290 	cx24123_i2c_writereg(state, state->config->demod_address, reg, val)
291 
292 static int cx24123_set_inversion(struct cx24123_state *state,
293 				 enum fe_spectral_inversion inversion)
294 {
295 	u8 nom_reg = cx24123_readreg(state, 0x0e);
296 	u8 auto_reg = cx24123_readreg(state, 0x10);
297 
298 	switch (inversion) {
299 	case INVERSION_OFF:
300 		dprintk("inversion off\n");
301 		cx24123_writereg(state, 0x0e, nom_reg & ~0x80);
302 		cx24123_writereg(state, 0x10, auto_reg | 0x80);
303 		break;
304 	case INVERSION_ON:
305 		dprintk("inversion on\n");
306 		cx24123_writereg(state, 0x0e, nom_reg | 0x80);
307 		cx24123_writereg(state, 0x10, auto_reg | 0x80);
308 		break;
309 	case INVERSION_AUTO:
310 		dprintk("inversion auto\n");
311 		cx24123_writereg(state, 0x10, auto_reg & ~0x80);
312 		break;
313 	default:
314 		return -EINVAL;
315 	}
316 
317 	return 0;
318 }
319 
320 static int cx24123_get_inversion(struct cx24123_state *state,
321 				 enum fe_spectral_inversion *inversion)
322 {
323 	u8 val;
324 
325 	val = cx24123_readreg(state, 0x1b) >> 7;
326 
327 	if (val == 0) {
328 		dprintk("read inversion off\n");
329 		*inversion = INVERSION_OFF;
330 	} else {
331 		dprintk("read inversion on\n");
332 		*inversion = INVERSION_ON;
333 	}
334 
335 	return 0;
336 }
337 
338 static int cx24123_set_fec(struct cx24123_state *state, enum fe_code_rate fec)
339 {
340 	u8 nom_reg = cx24123_readreg(state, 0x0e) & ~0x07;
341 
342 	if (((int)fec < FEC_NONE) || (fec > FEC_AUTO))
343 		fec = FEC_AUTO;
344 
345 	/* Set the soft decision threshold */
346 	if (fec == FEC_1_2)
347 		cx24123_writereg(state, 0x43,
348 			cx24123_readreg(state, 0x43) | 0x01);
349 	else
350 		cx24123_writereg(state, 0x43,
351 			cx24123_readreg(state, 0x43) & ~0x01);
352 
353 	switch (fec) {
354 	case FEC_1_2:
355 		dprintk("set FEC to 1/2\n");
356 		cx24123_writereg(state, 0x0e, nom_reg | 0x01);
357 		cx24123_writereg(state, 0x0f, 0x02);
358 		break;
359 	case FEC_2_3:
360 		dprintk("set FEC to 2/3\n");
361 		cx24123_writereg(state, 0x0e, nom_reg | 0x02);
362 		cx24123_writereg(state, 0x0f, 0x04);
363 		break;
364 	case FEC_3_4:
365 		dprintk("set FEC to 3/4\n");
366 		cx24123_writereg(state, 0x0e, nom_reg | 0x03);
367 		cx24123_writereg(state, 0x0f, 0x08);
368 		break;
369 	case FEC_4_5:
370 		dprintk("set FEC to 4/5\n");
371 		cx24123_writereg(state, 0x0e, nom_reg | 0x04);
372 		cx24123_writereg(state, 0x0f, 0x10);
373 		break;
374 	case FEC_5_6:
375 		dprintk("set FEC to 5/6\n");
376 		cx24123_writereg(state, 0x0e, nom_reg | 0x05);
377 		cx24123_writereg(state, 0x0f, 0x20);
378 		break;
379 	case FEC_6_7:
380 		dprintk("set FEC to 6/7\n");
381 		cx24123_writereg(state, 0x0e, nom_reg | 0x06);
382 		cx24123_writereg(state, 0x0f, 0x40);
383 		break;
384 	case FEC_7_8:
385 		dprintk("set FEC to 7/8\n");
386 		cx24123_writereg(state, 0x0e, nom_reg | 0x07);
387 		cx24123_writereg(state, 0x0f, 0x80);
388 		break;
389 	case FEC_AUTO:
390 		dprintk("set FEC to auto\n");
391 		cx24123_writereg(state, 0x0f, 0xfe);
392 		break;
393 	default:
394 		return -EOPNOTSUPP;
395 	}
396 
397 	return 0;
398 }
399 
400 static int cx24123_get_fec(struct cx24123_state *state, enum fe_code_rate *fec)
401 {
402 	int ret;
403 
404 	ret = cx24123_readreg(state, 0x1b);
405 	if (ret < 0)
406 		return ret;
407 	ret = ret & 0x07;
408 
409 	switch (ret) {
410 	case 1:
411 		*fec = FEC_1_2;
412 		break;
413 	case 2:
414 		*fec = FEC_2_3;
415 		break;
416 	case 3:
417 		*fec = FEC_3_4;
418 		break;
419 	case 4:
420 		*fec = FEC_4_5;
421 		break;
422 	case 5:
423 		*fec = FEC_5_6;
424 		break;
425 	case 6:
426 		*fec = FEC_6_7;
427 		break;
428 	case 7:
429 		*fec = FEC_7_8;
430 		break;
431 	default:
432 		/* this can happen when there's no lock */
433 		*fec = FEC_NONE;
434 	}
435 
436 	return 0;
437 }
438 
439 /* Approximation of closest integer of log2(a/b). It actually gives the
440    lowest integer i such that 2^i >= round(a/b) */
441 static u32 cx24123_int_log2(u32 a, u32 b)
442 {
443 	u32 exp, nearest = 0;
444 	u32 div = a / b;
445 	if (a % b >= b / 2)
446 		++div;
447 	if (div < (1 << 31)) {
448 		for (exp = 1; div > exp; nearest++)
449 			exp += exp;
450 	}
451 	return nearest;
452 }
453 
454 static int cx24123_set_symbolrate(struct cx24123_state *state, u32 srate)
455 {
456 	u64 tmp;
457 	u32 sample_rate, ratio, sample_gain;
458 	u8 pll_mult;
459 
460 	/*  check if symbol rate is within limits */
461 	if ((srate > state->frontend.ops.info.symbol_rate_max) ||
462 	    (srate < state->frontend.ops.info.symbol_rate_min))
463 		return -EOPNOTSUPP;
464 
465 	/* choose the sampling rate high enough for the required operation,
466 	   while optimizing the power consumed by the demodulator */
467 	if (srate < (XTAL*2)/2)
468 		pll_mult = 2;
469 	else if (srate < (XTAL*3)/2)
470 		pll_mult = 3;
471 	else if (srate < (XTAL*4)/2)
472 		pll_mult = 4;
473 	else if (srate < (XTAL*5)/2)
474 		pll_mult = 5;
475 	else if (srate < (XTAL*6)/2)
476 		pll_mult = 6;
477 	else if (srate < (XTAL*7)/2)
478 		pll_mult = 7;
479 	else if (srate < (XTAL*8)/2)
480 		pll_mult = 8;
481 	else
482 		pll_mult = 9;
483 
484 
485 	sample_rate = pll_mult * XTAL;
486 
487 	/* SYSSymbolRate[21:0] = (srate << 23) / sample_rate */
488 
489 	tmp = ((u64)srate) << 23;
490 	do_div(tmp, sample_rate);
491 	ratio = (u32) tmp;
492 
493 	cx24123_writereg(state, 0x01, pll_mult * 6);
494 
495 	cx24123_writereg(state, 0x08, (ratio >> 16) & 0x3f);
496 	cx24123_writereg(state, 0x09, (ratio >> 8) & 0xff);
497 	cx24123_writereg(state, 0x0a, ratio & 0xff);
498 
499 	/* also set the demodulator sample gain */
500 	sample_gain = cx24123_int_log2(sample_rate, srate);
501 	tmp = cx24123_readreg(state, 0x0c) & ~0xe0;
502 	cx24123_writereg(state, 0x0c, tmp | sample_gain << 5);
503 
504 	dprintk("srate=%d, ratio=0x%08x, sample_rate=%i sample_gain=%d\n",
505 		srate, ratio, sample_rate, sample_gain);
506 
507 	return 0;
508 }
509 
510 /*
511  * Based on the required frequency and symbolrate, the tuner AGC has
512  * to be configured and the correct band selected.
513  * Calculate those values.
514  */
515 static int cx24123_pll_calculate(struct dvb_frontend *fe)
516 {
517 	struct dtv_frontend_properties *p = &fe->dtv_property_cache;
518 	struct cx24123_state *state = fe->demodulator_priv;
519 	u32 ndiv = 0, adiv = 0, vco_div = 0;
520 	int i = 0;
521 	int pump = 2;
522 	int band = 0;
523 	int num_bands = ARRAY_SIZE(cx24123_bandselect_vals);
524 	struct cx24123_bandselect_val *bsv = NULL;
525 	struct cx24123_AGC_val *agcv = NULL;
526 
527 	/* Defaults for low freq, low rate */
528 	state->VCAarg = cx24123_AGC_vals[0].VCAprogdata;
529 	state->VGAarg = cx24123_AGC_vals[0].VGAprogdata;
530 	state->bandselectarg = cx24123_bandselect_vals[0].progdata;
531 	vco_div = cx24123_bandselect_vals[0].VCOdivider;
532 
533 	/* For the given symbol rate, determine the VCA, VGA and
534 	 * FILTUNE programming bits */
535 	for (i = 0; i < ARRAY_SIZE(cx24123_AGC_vals); i++) {
536 		agcv = &cx24123_AGC_vals[i];
537 		if ((agcv->symbolrate_low <= p->symbol_rate) &&
538 		    (agcv->symbolrate_high >= p->symbol_rate)) {
539 			state->VCAarg = agcv->VCAprogdata;
540 			state->VGAarg = agcv->VGAprogdata;
541 			state->FILTune = agcv->FILTune;
542 		}
543 	}
544 
545 	/* determine the band to use */
546 	if (force_band < 1 || force_band > num_bands) {
547 		for (i = 0; i < num_bands; i++) {
548 			bsv = &cx24123_bandselect_vals[i];
549 			if ((bsv->freq_low <= p->frequency) &&
550 				(bsv->freq_high >= p->frequency))
551 				band = i;
552 		}
553 	} else
554 		band = force_band - 1;
555 
556 	state->bandselectarg = cx24123_bandselect_vals[band].progdata;
557 	vco_div = cx24123_bandselect_vals[band].VCOdivider;
558 
559 	/* determine the charge pump current */
560 	if (p->frequency < (cx24123_bandselect_vals[band].freq_low +
561 		cx24123_bandselect_vals[band].freq_high) / 2)
562 		pump = 0x01;
563 	else
564 		pump = 0x02;
565 
566 	/* Determine the N/A dividers for the requested lband freq (in kHz). */
567 	/* Note: the reference divider R=10, frequency is in KHz,
568 	 * XTAL is in Hz */
569 	ndiv = (((p->frequency * vco_div * 10) /
570 		(2 * XTAL / 1000)) / 32) & 0x1ff;
571 	adiv = (((p->frequency * vco_div * 10) /
572 		(2 * XTAL / 1000)) % 32) & 0x1f;
573 
574 	if (adiv == 0 && ndiv > 0)
575 		ndiv--;
576 
577 	/* control bits 11, refdiv 11, charge pump polarity 1,
578 	 * charge pump current, ndiv, adiv */
579 	state->pllarg = (3 << 19) | (3 << 17) | (1 << 16) |
580 		(pump << 14) | (ndiv << 5) | adiv;
581 
582 	return 0;
583 }
584 
585 /*
586  * Tuner data is 21 bits long, must be left-aligned in data.
587  * Tuner cx24109 is written through a dedicated 3wire interface
588  * on the demod chip.
589  */
590 static int cx24123_pll_writereg(struct dvb_frontend *fe, u32 data)
591 {
592 	struct cx24123_state *state = fe->demodulator_priv;
593 	unsigned long timeout;
594 
595 	dprintk("pll writereg called, data=0x%08x\n", data);
596 
597 	/* align the 21 bytes into to bit23 boundary */
598 	data = data << 3;
599 
600 	/* Reset the demod pll word length to 0x15 bits */
601 	cx24123_writereg(state, 0x21, 0x15);
602 
603 	/* write the msb 8 bits, wait for the send to be completed */
604 	timeout = jiffies + msecs_to_jiffies(40);
605 	cx24123_writereg(state, 0x22, (data >> 16) & 0xff);
606 	while ((cx24123_readreg(state, 0x20) & 0x40) == 0) {
607 		if (time_after(jiffies, timeout)) {
608 			err("%s:  demodulator is not responding, "\
609 				"possibly hung, aborting.\n", __func__);
610 			return -EREMOTEIO;
611 		}
612 		msleep(10);
613 	}
614 
615 	/* send another 8 bytes, wait for the send to be completed */
616 	timeout = jiffies + msecs_to_jiffies(40);
617 	cx24123_writereg(state, 0x22, (data >> 8) & 0xff);
618 	while ((cx24123_readreg(state, 0x20) & 0x40) == 0) {
619 		if (time_after(jiffies, timeout)) {
620 			err("%s:  demodulator is not responding, "\
621 				"possibly hung, aborting.\n", __func__);
622 			return -EREMOTEIO;
623 		}
624 		msleep(10);
625 	}
626 
627 	/* send the lower 5 bits of this byte, padded with 3 LBB,
628 	 * wait for the send to be completed */
629 	timeout = jiffies + msecs_to_jiffies(40);
630 	cx24123_writereg(state, 0x22, (data) & 0xff);
631 	while ((cx24123_readreg(state, 0x20) & 0x80)) {
632 		if (time_after(jiffies, timeout)) {
633 			err("%s:  demodulator is not responding," \
634 				"possibly hung, aborting.\n", __func__);
635 			return -EREMOTEIO;
636 		}
637 		msleep(10);
638 	}
639 
640 	/* Trigger the demod to configure the tuner */
641 	cx24123_writereg(state, 0x20, cx24123_readreg(state, 0x20) | 2);
642 	cx24123_writereg(state, 0x20, cx24123_readreg(state, 0x20) & 0xfd);
643 
644 	return 0;
645 }
646 
647 static int cx24123_pll_tune(struct dvb_frontend *fe)
648 {
649 	struct dtv_frontend_properties *p = &fe->dtv_property_cache;
650 	struct cx24123_state *state = fe->demodulator_priv;
651 	u8 val;
652 
653 	dprintk("frequency=%i\n", p->frequency);
654 
655 	if (cx24123_pll_calculate(fe) != 0) {
656 		err("%s: cx24123_pll_calcutate failed\n", __func__);
657 		return -EINVAL;
658 	}
659 
660 	/* Write the new VCO/VGA */
661 	cx24123_pll_writereg(fe, state->VCAarg);
662 	cx24123_pll_writereg(fe, state->VGAarg);
663 
664 	/* Write the new bandselect and pll args */
665 	cx24123_pll_writereg(fe, state->bandselectarg);
666 	cx24123_pll_writereg(fe, state->pllarg);
667 
668 	/* set the FILTUNE voltage */
669 	val = cx24123_readreg(state, 0x28) & ~0x3;
670 	cx24123_writereg(state, 0x27, state->FILTune >> 2);
671 	cx24123_writereg(state, 0x28, val | (state->FILTune & 0x3));
672 
673 	dprintk("pll tune VCA=%d, band=%d, pll=%d\n", state->VCAarg,
674 			state->bandselectarg, state->pllarg);
675 
676 	return 0;
677 }
678 
679 
680 /*
681  * 0x23:
682  *    [7:7] = BTI enabled
683  *    [6:6] = I2C repeater enabled
684  *    [5:5] = I2C repeater start
685  *    [0:0] = BTI start
686  */
687 
688 /* mode == 1 -> i2c-repeater, 0 -> bti */
689 static int cx24123_repeater_mode(struct cx24123_state *state, u8 mode, u8 start)
690 {
691 	u8 r = cx24123_readreg(state, 0x23) & 0x1e;
692 	if (mode)
693 		r |= (1 << 6) | (start << 5);
694 	else
695 		r |= (1 << 7) | (start);
696 	return cx24123_writereg(state, 0x23, r);
697 }
698 
699 static int cx24123_initfe(struct dvb_frontend *fe)
700 {
701 	struct cx24123_state *state = fe->demodulator_priv;
702 	int i;
703 
704 	dprintk("init frontend\n");
705 
706 	/* Configure the demod to a good set of defaults */
707 	for (i = 0; i < ARRAY_SIZE(cx24123_regdata); i++)
708 		cx24123_writereg(state, cx24123_regdata[i].reg,
709 			cx24123_regdata[i].data);
710 
711 	/* Set the LNB polarity */
712 	if (state->config->lnb_polarity)
713 		cx24123_writereg(state, 0x32,
714 			cx24123_readreg(state, 0x32) | 0x02);
715 
716 	if (state->config->dont_use_pll)
717 		cx24123_repeater_mode(state, 1, 0);
718 
719 	return 0;
720 }
721 
722 static int cx24123_set_voltage(struct dvb_frontend *fe,
723 			       enum fe_sec_voltage voltage)
724 {
725 	struct cx24123_state *state = fe->demodulator_priv;
726 	u8 val;
727 
728 	val = cx24123_readreg(state, 0x29) & ~0x40;
729 
730 	switch (voltage) {
731 	case SEC_VOLTAGE_13:
732 		dprintk("setting voltage 13V\n");
733 		return cx24123_writereg(state, 0x29, val & 0x7f);
734 	case SEC_VOLTAGE_18:
735 		dprintk("setting voltage 18V\n");
736 		return cx24123_writereg(state, 0x29, val | 0x80);
737 	case SEC_VOLTAGE_OFF:
738 		/* already handled in cx88-dvb */
739 		return 0;
740 	default:
741 		return -EINVAL;
742 	}
743 
744 	return 0;
745 }
746 
747 /* wait for diseqc queue to become ready (or timeout) */
748 static void cx24123_wait_for_diseqc(struct cx24123_state *state)
749 {
750 	unsigned long timeout = jiffies + msecs_to_jiffies(200);
751 	while (!(cx24123_readreg(state, 0x29) & 0x40)) {
752 		if (time_after(jiffies, timeout)) {
753 			err("%s: diseqc queue not ready, " \
754 				"command may be lost.\n", __func__);
755 			break;
756 		}
757 		msleep(10);
758 	}
759 }
760 
761 static int cx24123_send_diseqc_msg(struct dvb_frontend *fe,
762 	struct dvb_diseqc_master_cmd *cmd)
763 {
764 	struct cx24123_state *state = fe->demodulator_priv;
765 	int i, val, tone;
766 
767 	dprintk("\n");
768 
769 	/* stop continuous tone if enabled */
770 	tone = cx24123_readreg(state, 0x29);
771 	if (tone & 0x10)
772 		cx24123_writereg(state, 0x29, tone & ~0x50);
773 
774 	/* wait for diseqc queue ready */
775 	cx24123_wait_for_diseqc(state);
776 
777 	/* select tone mode */
778 	cx24123_writereg(state, 0x2a, cx24123_readreg(state, 0x2a) & 0xfb);
779 
780 	for (i = 0; i < cmd->msg_len; i++)
781 		cx24123_writereg(state, 0x2C + i, cmd->msg[i]);
782 
783 	val = cx24123_readreg(state, 0x29);
784 	cx24123_writereg(state, 0x29, ((val & 0x90) | 0x40) |
785 		((cmd->msg_len-3) & 3));
786 
787 	/* wait for diseqc message to finish sending */
788 	cx24123_wait_for_diseqc(state);
789 
790 	/* restart continuous tone if enabled */
791 	if (tone & 0x10)
792 		cx24123_writereg(state, 0x29, tone & ~0x40);
793 
794 	return 0;
795 }
796 
797 static int cx24123_diseqc_send_burst(struct dvb_frontend *fe,
798 				     enum fe_sec_mini_cmd burst)
799 {
800 	struct cx24123_state *state = fe->demodulator_priv;
801 	int val, tone;
802 
803 	dprintk("\n");
804 
805 	/* stop continuous tone if enabled */
806 	tone = cx24123_readreg(state, 0x29);
807 	if (tone & 0x10)
808 		cx24123_writereg(state, 0x29, tone & ~0x50);
809 
810 	/* wait for diseqc queue ready */
811 	cx24123_wait_for_diseqc(state);
812 
813 	/* select tone mode */
814 	cx24123_writereg(state, 0x2a, cx24123_readreg(state, 0x2a) | 0x4);
815 	msleep(30);
816 	val = cx24123_readreg(state, 0x29);
817 	if (burst == SEC_MINI_A)
818 		cx24123_writereg(state, 0x29, ((val & 0x90) | 0x40 | 0x00));
819 	else if (burst == SEC_MINI_B)
820 		cx24123_writereg(state, 0x29, ((val & 0x90) | 0x40 | 0x08));
821 	else
822 		return -EINVAL;
823 
824 	cx24123_wait_for_diseqc(state);
825 	cx24123_writereg(state, 0x2a, cx24123_readreg(state, 0x2a) & 0xfb);
826 
827 	/* restart continuous tone if enabled */
828 	if (tone & 0x10)
829 		cx24123_writereg(state, 0x29, tone & ~0x40);
830 
831 	return 0;
832 }
833 
834 static int cx24123_read_status(struct dvb_frontend *fe, enum fe_status *status)
835 {
836 	struct cx24123_state *state = fe->demodulator_priv;
837 	int sync = cx24123_readreg(state, 0x14);
838 
839 	*status = 0;
840 	if (state->config->dont_use_pll) {
841 		u32 tun_status = 0;
842 		if (fe->ops.tuner_ops.get_status)
843 			fe->ops.tuner_ops.get_status(fe, &tun_status);
844 		if (tun_status & TUNER_STATUS_LOCKED)
845 			*status |= FE_HAS_SIGNAL;
846 	} else {
847 		int lock = cx24123_readreg(state, 0x20);
848 		if (lock & 0x01)
849 			*status |= FE_HAS_SIGNAL;
850 	}
851 
852 	if (sync & 0x02)
853 		*status |= FE_HAS_CARRIER;	/* Phase locked */
854 	if (sync & 0x04)
855 		*status |= FE_HAS_VITERBI;
856 
857 	/* Reed-Solomon Status */
858 	if (sync & 0x08)
859 		*status |= FE_HAS_SYNC;
860 	if (sync & 0x80)
861 		*status |= FE_HAS_LOCK;		/*Full Sync */
862 
863 	return 0;
864 }
865 
866 /*
867  * Configured to return the measurement of errors in blocks,
868  * because no UCBLOCKS value is available, so this value doubles up
869  * to satisfy both measurements.
870  */
871 static int cx24123_read_ber(struct dvb_frontend *fe, u32 *ber)
872 {
873 	struct cx24123_state *state = fe->demodulator_priv;
874 
875 	/* The true bit error rate is this value divided by
876 	   the window size (set as 256 * 255) */
877 	*ber = ((cx24123_readreg(state, 0x1c) & 0x3f) << 16) |
878 		(cx24123_readreg(state, 0x1d) << 8 |
879 		 cx24123_readreg(state, 0x1e));
880 
881 	dprintk("BER = %d\n", *ber);
882 
883 	return 0;
884 }
885 
886 static int cx24123_read_signal_strength(struct dvb_frontend *fe,
887 	u16 *signal_strength)
888 {
889 	struct cx24123_state *state = fe->demodulator_priv;
890 
891 	/* larger = better */
892 	*signal_strength = cx24123_readreg(state, 0x3b) << 8;
893 
894 	dprintk("Signal strength = %d\n", *signal_strength);
895 
896 	return 0;
897 }
898 
899 static int cx24123_read_snr(struct dvb_frontend *fe, u16 *snr)
900 {
901 	struct cx24123_state *state = fe->demodulator_priv;
902 
903 	/* Inverted raw Es/N0 count, totally bogus but better than the
904 	   BER threshold. */
905 	*snr = 65535 - (((u16)cx24123_readreg(state, 0x18) << 8) |
906 			 (u16)cx24123_readreg(state, 0x19));
907 
908 	dprintk("read S/N index = %d\n", *snr);
909 
910 	return 0;
911 }
912 
913 static int cx24123_set_frontend(struct dvb_frontend *fe)
914 {
915 	struct cx24123_state *state = fe->demodulator_priv;
916 	struct dtv_frontend_properties *p = &fe->dtv_property_cache;
917 
918 	dprintk("\n");
919 
920 	if (state->config->set_ts_params)
921 		state->config->set_ts_params(fe, 0);
922 
923 	state->currentfreq = p->frequency;
924 	state->currentsymbolrate = p->symbol_rate;
925 
926 	cx24123_set_inversion(state, p->inversion);
927 	cx24123_set_fec(state, p->fec_inner);
928 	cx24123_set_symbolrate(state, p->symbol_rate);
929 
930 	if (!state->config->dont_use_pll)
931 		cx24123_pll_tune(fe);
932 	else if (fe->ops.tuner_ops.set_params)
933 		fe->ops.tuner_ops.set_params(fe);
934 	else
935 		err("it seems I don't have a tuner...");
936 
937 	/* Enable automatic acquisition and reset cycle */
938 	cx24123_writereg(state, 0x03, (cx24123_readreg(state, 0x03) | 0x07));
939 	cx24123_writereg(state, 0x00, 0x10);
940 	cx24123_writereg(state, 0x00, 0);
941 
942 	if (state->config->agc_callback)
943 		state->config->agc_callback(fe);
944 
945 	return 0;
946 }
947 
948 static int cx24123_get_frontend(struct dvb_frontend *fe)
949 {
950 	struct dtv_frontend_properties *p = &fe->dtv_property_cache;
951 	struct cx24123_state *state = fe->demodulator_priv;
952 
953 	dprintk("\n");
954 
955 	if (cx24123_get_inversion(state, &p->inversion) != 0) {
956 		err("%s: Failed to get inversion status\n", __func__);
957 		return -EREMOTEIO;
958 	}
959 	if (cx24123_get_fec(state, &p->fec_inner) != 0) {
960 		err("%s: Failed to get fec status\n", __func__);
961 		return -EREMOTEIO;
962 	}
963 	p->frequency = state->currentfreq;
964 	p->symbol_rate = state->currentsymbolrate;
965 
966 	return 0;
967 }
968 
969 static int cx24123_set_tone(struct dvb_frontend *fe, enum fe_sec_tone_mode tone)
970 {
971 	struct cx24123_state *state = fe->demodulator_priv;
972 	u8 val;
973 
974 	/* wait for diseqc queue ready */
975 	cx24123_wait_for_diseqc(state);
976 
977 	val = cx24123_readreg(state, 0x29) & ~0x40;
978 
979 	switch (tone) {
980 	case SEC_TONE_ON:
981 		dprintk("setting tone on\n");
982 		return cx24123_writereg(state, 0x29, val | 0x10);
983 	case SEC_TONE_OFF:
984 		dprintk("setting tone off\n");
985 		return cx24123_writereg(state, 0x29, val & 0xef);
986 	default:
987 		err("CASE reached default with tone=%d\n", tone);
988 		return -EINVAL;
989 	}
990 
991 	return 0;
992 }
993 
994 static int cx24123_tune(struct dvb_frontend *fe,
995 			bool re_tune,
996 			unsigned int mode_flags,
997 			unsigned int *delay,
998 			enum fe_status *status)
999 {
1000 	int retval = 0;
1001 
1002 	if (re_tune)
1003 		retval = cx24123_set_frontend(fe);
1004 
1005 	if (!(mode_flags & FE_TUNE_MODE_ONESHOT))
1006 		cx24123_read_status(fe, status);
1007 	*delay = HZ/10;
1008 
1009 	return retval;
1010 }
1011 
1012 static int cx24123_get_algo(struct dvb_frontend *fe)
1013 {
1014 	return DVBFE_ALGO_HW;
1015 }
1016 
1017 static void cx24123_release(struct dvb_frontend *fe)
1018 {
1019 	struct cx24123_state *state = fe->demodulator_priv;
1020 	dprintk("\n");
1021 	i2c_del_adapter(&state->tuner_i2c_adapter);
1022 	kfree(state);
1023 }
1024 
1025 static int cx24123_tuner_i2c_tuner_xfer(struct i2c_adapter *i2c_adap,
1026 	struct i2c_msg msg[], int num)
1027 {
1028 	struct cx24123_state *state = i2c_get_adapdata(i2c_adap);
1029 	/* this repeater closes after the first stop */
1030 	cx24123_repeater_mode(state, 1, 1);
1031 	return i2c_transfer(state->i2c, msg, num);
1032 }
1033 
1034 static u32 cx24123_tuner_i2c_func(struct i2c_adapter *adapter)
1035 {
1036 	return I2C_FUNC_I2C;
1037 }
1038 
1039 static struct i2c_algorithm cx24123_tuner_i2c_algo = {
1040 	.master_xfer   = cx24123_tuner_i2c_tuner_xfer,
1041 	.functionality = cx24123_tuner_i2c_func,
1042 };
1043 
1044 struct i2c_adapter *
1045 	cx24123_get_tuner_i2c_adapter(struct dvb_frontend *fe)
1046 {
1047 	struct cx24123_state *state = fe->demodulator_priv;
1048 	return &state->tuner_i2c_adapter;
1049 }
1050 EXPORT_SYMBOL(cx24123_get_tuner_i2c_adapter);
1051 
1052 static struct dvb_frontend_ops cx24123_ops;
1053 
1054 struct dvb_frontend *cx24123_attach(const struct cx24123_config *config,
1055 				    struct i2c_adapter *i2c)
1056 {
1057 	/* allocate memory for the internal state */
1058 	struct cx24123_state *state =
1059 		kzalloc(sizeof(struct cx24123_state), GFP_KERNEL);
1060 
1061 	dprintk("\n");
1062 	if (state == NULL) {
1063 		err("Unable to kzalloc\n");
1064 		goto error;
1065 	}
1066 
1067 	/* setup the state */
1068 	state->config = config;
1069 	state->i2c = i2c;
1070 
1071 	/* check if the demod is there */
1072 	state->demod_rev = cx24123_readreg(state, 0x00);
1073 	switch (state->demod_rev) {
1074 	case 0xe1:
1075 		info("detected CX24123C\n");
1076 		break;
1077 	case 0xd1:
1078 		info("detected CX24123\n");
1079 		break;
1080 	default:
1081 		err("wrong demod revision: %x\n", state->demod_rev);
1082 		goto error;
1083 	}
1084 
1085 	/* create dvb_frontend */
1086 	memcpy(&state->frontend.ops, &cx24123_ops,
1087 		sizeof(struct dvb_frontend_ops));
1088 	state->frontend.demodulator_priv = state;
1089 
1090 	/* create tuner i2c adapter */
1091 	if (config->dont_use_pll)
1092 		cx24123_repeater_mode(state, 1, 0);
1093 
1094 	strlcpy(state->tuner_i2c_adapter.name, "CX24123 tuner I2C bus",
1095 		sizeof(state->tuner_i2c_adapter.name));
1096 	state->tuner_i2c_adapter.algo      = &cx24123_tuner_i2c_algo;
1097 	state->tuner_i2c_adapter.algo_data = NULL;
1098 	state->tuner_i2c_adapter.dev.parent = i2c->dev.parent;
1099 	i2c_set_adapdata(&state->tuner_i2c_adapter, state);
1100 	if (i2c_add_adapter(&state->tuner_i2c_adapter) < 0) {
1101 		err("tuner i2c bus could not be initialized\n");
1102 		goto error;
1103 	}
1104 
1105 	return &state->frontend;
1106 
1107 error:
1108 	kfree(state);
1109 
1110 	return NULL;
1111 }
1112 EXPORT_SYMBOL(cx24123_attach);
1113 
1114 static struct dvb_frontend_ops cx24123_ops = {
1115 	.delsys = { SYS_DVBS },
1116 	.info = {
1117 		.name = "Conexant CX24123/CX24109",
1118 		.frequency_min = 950000,
1119 		.frequency_max = 2150000,
1120 		.frequency_stepsize = 1011, /* kHz for QPSK frontends */
1121 		.frequency_tolerance = 5000,
1122 		.symbol_rate_min = 1000000,
1123 		.symbol_rate_max = 45000000,
1124 		.caps = FE_CAN_INVERSION_AUTO |
1125 			FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 | FE_CAN_FEC_3_4 |
1126 			FE_CAN_FEC_4_5 | FE_CAN_FEC_5_6 | FE_CAN_FEC_6_7 |
1127 			FE_CAN_FEC_7_8 | FE_CAN_FEC_AUTO |
1128 			FE_CAN_QPSK | FE_CAN_RECOVER
1129 	},
1130 
1131 	.release = cx24123_release,
1132 
1133 	.init = cx24123_initfe,
1134 	.set_frontend = cx24123_set_frontend,
1135 	.get_frontend = cx24123_get_frontend,
1136 	.read_status = cx24123_read_status,
1137 	.read_ber = cx24123_read_ber,
1138 	.read_signal_strength = cx24123_read_signal_strength,
1139 	.read_snr = cx24123_read_snr,
1140 	.diseqc_send_master_cmd = cx24123_send_diseqc_msg,
1141 	.diseqc_send_burst = cx24123_diseqc_send_burst,
1142 	.set_tone = cx24123_set_tone,
1143 	.set_voltage = cx24123_set_voltage,
1144 	.tune = cx24123_tune,
1145 	.get_frontend_algo = cx24123_get_algo,
1146 };
1147 
1148 MODULE_DESCRIPTION("DVB Frontend module for Conexant " \
1149 	"CX24123/CX24109/CX24113 hardware");
1150 MODULE_AUTHOR("Steven Toth");
1151 MODULE_LICENSE("GPL");
1152 
1153