1 /* 2 * Conexant cx24123/cx24109 - DVB QPSK Satellite demod/tuner driver 3 * 4 * Copyright (C) 2005 Steven Toth <stoth@linuxtv.org> 5 * 6 * Support for KWorld DVB-S 100 by Vadim Catana <skystar@moldova.cc> 7 * 8 * Support for CX24123/CX24113-NIM by Patrick Boettcher <pb@linuxtv.org> 9 * 10 * This program is free software; you can redistribute it and/or 11 * modify it under the terms of the GNU General Public License as 12 * published by the Free Software Foundation; either version 2 of 13 * the License, or (at your option) any later version. 14 * 15 * This program is distributed in the hope that it will be useful, 16 * but WITHOUT ANY WARRANTY; without even the implied warranty of 17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 18 * General Public License for more details. 19 * 20 * You should have received a copy of the GNU General Public License 21 * along with this program; if not, write to the Free Software 22 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. 23 */ 24 25 #include <linux/slab.h> 26 #include <linux/kernel.h> 27 #include <linux/module.h> 28 #include <linux/init.h> 29 30 #include "dvb_frontend.h" 31 #include "cx24123.h" 32 33 #define XTAL 10111000 34 35 static int force_band; 36 module_param(force_band, int, 0644); 37 MODULE_PARM_DESC(force_band, "Force a specific band select "\ 38 "(1-9, default:off)."); 39 40 static int debug; 41 module_param(debug, int, 0644); 42 MODULE_PARM_DESC(debug, "Activates frontend debugging (default:0)"); 43 44 #define info(args...) do { printk(KERN_INFO "CX24123: " args); } while (0) 45 #define err(args...) do { printk(KERN_ERR "CX24123: " args); } while (0) 46 47 #define dprintk(args...) \ 48 do { \ 49 if (debug) { \ 50 printk(KERN_DEBUG "CX24123: %s: ", __func__); \ 51 printk(args); \ 52 } \ 53 } while (0) 54 55 struct cx24123_state { 56 struct i2c_adapter *i2c; 57 const struct cx24123_config *config; 58 59 struct dvb_frontend frontend; 60 61 /* Some PLL specifics for tuning */ 62 u32 VCAarg; 63 u32 VGAarg; 64 u32 bandselectarg; 65 u32 pllarg; 66 u32 FILTune; 67 68 struct i2c_adapter tuner_i2c_adapter; 69 70 u8 demod_rev; 71 72 /* The Demod/Tuner can't easily provide these, we cache them */ 73 u32 currentfreq; 74 u32 currentsymbolrate; 75 }; 76 77 /* Various tuner defaults need to be established for a given symbol rate Sps */ 78 static struct cx24123_AGC_val { 79 u32 symbolrate_low; 80 u32 symbolrate_high; 81 u32 VCAprogdata; 82 u32 VGAprogdata; 83 u32 FILTune; 84 } cx24123_AGC_vals[] = 85 { 86 { 87 .symbolrate_low = 1000000, 88 .symbolrate_high = 4999999, 89 /* the specs recommend other values for VGA offsets, 90 but tests show they are wrong */ 91 .VGAprogdata = (1 << 19) | (0x180 << 9) | 0x1e0, 92 .VCAprogdata = (2 << 19) | (0x07 << 9) | 0x07, 93 .FILTune = 0x27f /* 0.41 V */ 94 }, 95 { 96 .symbolrate_low = 5000000, 97 .symbolrate_high = 14999999, 98 .VGAprogdata = (1 << 19) | (0x180 << 9) | 0x1e0, 99 .VCAprogdata = (2 << 19) | (0x07 << 9) | 0x1f, 100 .FILTune = 0x317 /* 0.90 V */ 101 }, 102 { 103 .symbolrate_low = 15000000, 104 .symbolrate_high = 45000000, 105 .VGAprogdata = (1 << 19) | (0x100 << 9) | 0x180, 106 .VCAprogdata = (2 << 19) | (0x07 << 9) | 0x3f, 107 .FILTune = 0x145 /* 2.70 V */ 108 }, 109 }; 110 111 /* 112 * Various tuner defaults need to be established for a given frequency kHz. 113 * fixme: The bounds on the bands do not match the doc in real life. 114 * fixme: Some of them have been moved, other might need adjustment. 115 */ 116 static struct cx24123_bandselect_val { 117 u32 freq_low; 118 u32 freq_high; 119 u32 VCOdivider; 120 u32 progdata; 121 } cx24123_bandselect_vals[] = 122 { 123 /* band 1 */ 124 { 125 .freq_low = 950000, 126 .freq_high = 1074999, 127 .VCOdivider = 4, 128 .progdata = (0 << 19) | (0 << 9) | 0x40, 129 }, 130 131 /* band 2 */ 132 { 133 .freq_low = 1075000, 134 .freq_high = 1177999, 135 .VCOdivider = 4, 136 .progdata = (0 << 19) | (0 << 9) | 0x80, 137 }, 138 139 /* band 3 */ 140 { 141 .freq_low = 1178000, 142 .freq_high = 1295999, 143 .VCOdivider = 2, 144 .progdata = (0 << 19) | (1 << 9) | 0x01, 145 }, 146 147 /* band 4 */ 148 { 149 .freq_low = 1296000, 150 .freq_high = 1431999, 151 .VCOdivider = 2, 152 .progdata = (0 << 19) | (1 << 9) | 0x02, 153 }, 154 155 /* band 5 */ 156 { 157 .freq_low = 1432000, 158 .freq_high = 1575999, 159 .VCOdivider = 2, 160 .progdata = (0 << 19) | (1 << 9) | 0x04, 161 }, 162 163 /* band 6 */ 164 { 165 .freq_low = 1576000, 166 .freq_high = 1717999, 167 .VCOdivider = 2, 168 .progdata = (0 << 19) | (1 << 9) | 0x08, 169 }, 170 171 /* band 7 */ 172 { 173 .freq_low = 1718000, 174 .freq_high = 1855999, 175 .VCOdivider = 2, 176 .progdata = (0 << 19) | (1 << 9) | 0x10, 177 }, 178 179 /* band 8 */ 180 { 181 .freq_low = 1856000, 182 .freq_high = 2035999, 183 .VCOdivider = 2, 184 .progdata = (0 << 19) | (1 << 9) | 0x20, 185 }, 186 187 /* band 9 */ 188 { 189 .freq_low = 2036000, 190 .freq_high = 2150000, 191 .VCOdivider = 2, 192 .progdata = (0 << 19) | (1 << 9) | 0x40, 193 }, 194 }; 195 196 static struct { 197 u8 reg; 198 u8 data; 199 } cx24123_regdata[] = 200 { 201 {0x00, 0x03}, /* Reset system */ 202 {0x00, 0x00}, /* Clear reset */ 203 {0x03, 0x07}, /* QPSK, DVB, Auto Acquisition (default) */ 204 {0x04, 0x10}, /* MPEG */ 205 {0x05, 0x04}, /* MPEG */ 206 {0x06, 0x31}, /* MPEG (default) */ 207 {0x0b, 0x00}, /* Freq search start point (default) */ 208 {0x0c, 0x00}, /* Demodulator sample gain (default) */ 209 {0x0d, 0x7f}, /* Force driver to shift until the maximum (+-10 MHz) */ 210 {0x0e, 0x03}, /* Default non-inverted, FEC 3/4 (default) */ 211 {0x0f, 0xfe}, /* FEC search mask (all supported codes) */ 212 {0x10, 0x01}, /* Default search inversion, no repeat (default) */ 213 {0x16, 0x00}, /* Enable reading of frequency */ 214 {0x17, 0x01}, /* Enable EsNO Ready Counter */ 215 {0x1c, 0x80}, /* Enable error counter */ 216 {0x20, 0x00}, /* Tuner burst clock rate = 500KHz */ 217 {0x21, 0x15}, /* Tuner burst mode, word length = 0x15 */ 218 {0x28, 0x00}, /* Enable FILTERV with positive pol., DiSEqC 2.x off */ 219 {0x29, 0x00}, /* DiSEqC LNB_DC off */ 220 {0x2a, 0xb0}, /* DiSEqC Parameters (default) */ 221 {0x2b, 0x73}, /* DiSEqC Tone Frequency (default) */ 222 {0x2c, 0x00}, /* DiSEqC Message (0x2c - 0x31) */ 223 {0x2d, 0x00}, 224 {0x2e, 0x00}, 225 {0x2f, 0x00}, 226 {0x30, 0x00}, 227 {0x31, 0x00}, 228 {0x32, 0x8c}, /* DiSEqC Parameters (default) */ 229 {0x33, 0x00}, /* Interrupts off (0x33 - 0x34) */ 230 {0x34, 0x00}, 231 {0x35, 0x03}, /* DiSEqC Tone Amplitude (default) */ 232 {0x36, 0x02}, /* DiSEqC Parameters (default) */ 233 {0x37, 0x3a}, /* DiSEqC Parameters (default) */ 234 {0x3a, 0x00}, /* Enable AGC accumulator (for signal strength) */ 235 {0x44, 0x00}, /* Constellation (default) */ 236 {0x45, 0x00}, /* Symbol count (default) */ 237 {0x46, 0x0d}, /* Symbol rate estimator on (default) */ 238 {0x56, 0xc1}, /* Error Counter = Viterbi BER */ 239 {0x57, 0xff}, /* Error Counter Window (default) */ 240 {0x5c, 0x20}, /* Acquisition AFC Expiration window (default is 0x10) */ 241 {0x67, 0x83}, /* Non-DCII symbol clock */ 242 }; 243 244 static int cx24123_i2c_writereg(struct cx24123_state *state, 245 u8 i2c_addr, int reg, int data) 246 { 247 u8 buf[] = { reg, data }; 248 struct i2c_msg msg = { 249 .addr = i2c_addr, .flags = 0, .buf = buf, .len = 2 250 }; 251 int err; 252 253 /* printk(KERN_DEBUG "wr(%02x): %02x %02x\n", i2c_addr, reg, data); */ 254 255 err = i2c_transfer(state->i2c, &msg, 1); 256 if (err != 1) { 257 printk("%s: writereg error(err == %i, reg == 0x%02x," 258 " data == 0x%02x)\n", __func__, err, reg, data); 259 return err; 260 } 261 262 return 0; 263 } 264 265 static int cx24123_i2c_readreg(struct cx24123_state *state, u8 i2c_addr, u8 reg) 266 { 267 int ret; 268 u8 b = 0; 269 struct i2c_msg msg[] = { 270 { .addr = i2c_addr, .flags = 0, .buf = ®, .len = 1 }, 271 { .addr = i2c_addr, .flags = I2C_M_RD, .buf = &b, .len = 1 } 272 }; 273 274 ret = i2c_transfer(state->i2c, msg, 2); 275 276 if (ret != 2) { 277 err("%s: reg=0x%x (error=%d)\n", __func__, reg, ret); 278 return ret; 279 } 280 281 /* printk(KERN_DEBUG "rd(%02x): %02x %02x\n", i2c_addr, reg, b); */ 282 283 return b; 284 } 285 286 #define cx24123_readreg(state, reg) \ 287 cx24123_i2c_readreg(state, state->config->demod_address, reg) 288 #define cx24123_writereg(state, reg, val) \ 289 cx24123_i2c_writereg(state, state->config->demod_address, reg, val) 290 291 static int cx24123_set_inversion(struct cx24123_state *state, 292 fe_spectral_inversion_t inversion) 293 { 294 u8 nom_reg = cx24123_readreg(state, 0x0e); 295 u8 auto_reg = cx24123_readreg(state, 0x10); 296 297 switch (inversion) { 298 case INVERSION_OFF: 299 dprintk("inversion off\n"); 300 cx24123_writereg(state, 0x0e, nom_reg & ~0x80); 301 cx24123_writereg(state, 0x10, auto_reg | 0x80); 302 break; 303 case INVERSION_ON: 304 dprintk("inversion on\n"); 305 cx24123_writereg(state, 0x0e, nom_reg | 0x80); 306 cx24123_writereg(state, 0x10, auto_reg | 0x80); 307 break; 308 case INVERSION_AUTO: 309 dprintk("inversion auto\n"); 310 cx24123_writereg(state, 0x10, auto_reg & ~0x80); 311 break; 312 default: 313 return -EINVAL; 314 } 315 316 return 0; 317 } 318 319 static int cx24123_get_inversion(struct cx24123_state *state, 320 fe_spectral_inversion_t *inversion) 321 { 322 u8 val; 323 324 val = cx24123_readreg(state, 0x1b) >> 7; 325 326 if (val == 0) { 327 dprintk("read inversion off\n"); 328 *inversion = INVERSION_OFF; 329 } else { 330 dprintk("read inversion on\n"); 331 *inversion = INVERSION_ON; 332 } 333 334 return 0; 335 } 336 337 static int cx24123_set_fec(struct cx24123_state *state, fe_code_rate_t fec) 338 { 339 u8 nom_reg = cx24123_readreg(state, 0x0e) & ~0x07; 340 341 if (((int)fec < FEC_NONE) || (fec > FEC_AUTO)) 342 fec = FEC_AUTO; 343 344 /* Set the soft decision threshold */ 345 if (fec == FEC_1_2) 346 cx24123_writereg(state, 0x43, 347 cx24123_readreg(state, 0x43) | 0x01); 348 else 349 cx24123_writereg(state, 0x43, 350 cx24123_readreg(state, 0x43) & ~0x01); 351 352 switch (fec) { 353 case FEC_1_2: 354 dprintk("set FEC to 1/2\n"); 355 cx24123_writereg(state, 0x0e, nom_reg | 0x01); 356 cx24123_writereg(state, 0x0f, 0x02); 357 break; 358 case FEC_2_3: 359 dprintk("set FEC to 2/3\n"); 360 cx24123_writereg(state, 0x0e, nom_reg | 0x02); 361 cx24123_writereg(state, 0x0f, 0x04); 362 break; 363 case FEC_3_4: 364 dprintk("set FEC to 3/4\n"); 365 cx24123_writereg(state, 0x0e, nom_reg | 0x03); 366 cx24123_writereg(state, 0x0f, 0x08); 367 break; 368 case FEC_4_5: 369 dprintk("set FEC to 4/5\n"); 370 cx24123_writereg(state, 0x0e, nom_reg | 0x04); 371 cx24123_writereg(state, 0x0f, 0x10); 372 break; 373 case FEC_5_6: 374 dprintk("set FEC to 5/6\n"); 375 cx24123_writereg(state, 0x0e, nom_reg | 0x05); 376 cx24123_writereg(state, 0x0f, 0x20); 377 break; 378 case FEC_6_7: 379 dprintk("set FEC to 6/7\n"); 380 cx24123_writereg(state, 0x0e, nom_reg | 0x06); 381 cx24123_writereg(state, 0x0f, 0x40); 382 break; 383 case FEC_7_8: 384 dprintk("set FEC to 7/8\n"); 385 cx24123_writereg(state, 0x0e, nom_reg | 0x07); 386 cx24123_writereg(state, 0x0f, 0x80); 387 break; 388 case FEC_AUTO: 389 dprintk("set FEC to auto\n"); 390 cx24123_writereg(state, 0x0f, 0xfe); 391 break; 392 default: 393 return -EOPNOTSUPP; 394 } 395 396 return 0; 397 } 398 399 static int cx24123_get_fec(struct cx24123_state *state, fe_code_rate_t *fec) 400 { 401 int ret; 402 403 ret = cx24123_readreg(state, 0x1b); 404 if (ret < 0) 405 return ret; 406 ret = ret & 0x07; 407 408 switch (ret) { 409 case 1: 410 *fec = FEC_1_2; 411 break; 412 case 2: 413 *fec = FEC_2_3; 414 break; 415 case 3: 416 *fec = FEC_3_4; 417 break; 418 case 4: 419 *fec = FEC_4_5; 420 break; 421 case 5: 422 *fec = FEC_5_6; 423 break; 424 case 6: 425 *fec = FEC_6_7; 426 break; 427 case 7: 428 *fec = FEC_7_8; 429 break; 430 default: 431 /* this can happen when there's no lock */ 432 *fec = FEC_NONE; 433 } 434 435 return 0; 436 } 437 438 /* Approximation of closest integer of log2(a/b). It actually gives the 439 lowest integer i such that 2^i >= round(a/b) */ 440 static u32 cx24123_int_log2(u32 a, u32 b) 441 { 442 u32 exp, nearest = 0; 443 u32 div = a / b; 444 if (a % b >= b / 2) 445 ++div; 446 if (div < (1 << 31)) { 447 for (exp = 1; div > exp; nearest++) 448 exp += exp; 449 } 450 return nearest; 451 } 452 453 static int cx24123_set_symbolrate(struct cx24123_state *state, u32 srate) 454 { 455 u32 tmp, sample_rate, ratio, sample_gain; 456 u8 pll_mult; 457 458 /* check if symbol rate is within limits */ 459 if ((srate > state->frontend.ops.info.symbol_rate_max) || 460 (srate < state->frontend.ops.info.symbol_rate_min)) 461 return -EOPNOTSUPP; 462 463 /* choose the sampling rate high enough for the required operation, 464 while optimizing the power consumed by the demodulator */ 465 if (srate < (XTAL*2)/2) 466 pll_mult = 2; 467 else if (srate < (XTAL*3)/2) 468 pll_mult = 3; 469 else if (srate < (XTAL*4)/2) 470 pll_mult = 4; 471 else if (srate < (XTAL*5)/2) 472 pll_mult = 5; 473 else if (srate < (XTAL*6)/2) 474 pll_mult = 6; 475 else if (srate < (XTAL*7)/2) 476 pll_mult = 7; 477 else if (srate < (XTAL*8)/2) 478 pll_mult = 8; 479 else 480 pll_mult = 9; 481 482 483 sample_rate = pll_mult * XTAL; 484 485 /* 486 SYSSymbolRate[21:0] = (srate << 23) / sample_rate 487 488 We have to use 32 bit unsigned arithmetic without precision loss. 489 The maximum srate is 45000000 or 0x02AEA540. This number has 490 only 6 clear bits on top, hence we can shift it left only 6 bits 491 at a time. Borrowed from cx24110.c 492 */ 493 494 tmp = srate << 6; 495 ratio = tmp / sample_rate; 496 497 tmp = (tmp % sample_rate) << 6; 498 ratio = (ratio << 6) + (tmp / sample_rate); 499 500 tmp = (tmp % sample_rate) << 6; 501 ratio = (ratio << 6) + (tmp / sample_rate); 502 503 tmp = (tmp % sample_rate) << 5; 504 ratio = (ratio << 5) + (tmp / sample_rate); 505 506 507 cx24123_writereg(state, 0x01, pll_mult * 6); 508 509 cx24123_writereg(state, 0x08, (ratio >> 16) & 0x3f); 510 cx24123_writereg(state, 0x09, (ratio >> 8) & 0xff); 511 cx24123_writereg(state, 0x0a, ratio & 0xff); 512 513 /* also set the demodulator sample gain */ 514 sample_gain = cx24123_int_log2(sample_rate, srate); 515 tmp = cx24123_readreg(state, 0x0c) & ~0xe0; 516 cx24123_writereg(state, 0x0c, tmp | sample_gain << 5); 517 518 dprintk("srate=%d, ratio=0x%08x, sample_rate=%i sample_gain=%d\n", 519 srate, ratio, sample_rate, sample_gain); 520 521 return 0; 522 } 523 524 /* 525 * Based on the required frequency and symbolrate, the tuner AGC has 526 * to be configured and the correct band selected. 527 * Calculate those values. 528 */ 529 static int cx24123_pll_calculate(struct dvb_frontend *fe) 530 { 531 struct dtv_frontend_properties *p = &fe->dtv_property_cache; 532 struct cx24123_state *state = fe->demodulator_priv; 533 u32 ndiv = 0, adiv = 0, vco_div = 0; 534 int i = 0; 535 int pump = 2; 536 int band = 0; 537 int num_bands = ARRAY_SIZE(cx24123_bandselect_vals); 538 struct cx24123_bandselect_val *bsv = NULL; 539 struct cx24123_AGC_val *agcv = NULL; 540 541 /* Defaults for low freq, low rate */ 542 state->VCAarg = cx24123_AGC_vals[0].VCAprogdata; 543 state->VGAarg = cx24123_AGC_vals[0].VGAprogdata; 544 state->bandselectarg = cx24123_bandselect_vals[0].progdata; 545 vco_div = cx24123_bandselect_vals[0].VCOdivider; 546 547 /* For the given symbol rate, determine the VCA, VGA and 548 * FILTUNE programming bits */ 549 for (i = 0; i < ARRAY_SIZE(cx24123_AGC_vals); i++) { 550 agcv = &cx24123_AGC_vals[i]; 551 if ((agcv->symbolrate_low <= p->symbol_rate) && 552 (agcv->symbolrate_high >= p->symbol_rate)) { 553 state->VCAarg = agcv->VCAprogdata; 554 state->VGAarg = agcv->VGAprogdata; 555 state->FILTune = agcv->FILTune; 556 } 557 } 558 559 /* determine the band to use */ 560 if (force_band < 1 || force_band > num_bands) { 561 for (i = 0; i < num_bands; i++) { 562 bsv = &cx24123_bandselect_vals[i]; 563 if ((bsv->freq_low <= p->frequency) && 564 (bsv->freq_high >= p->frequency)) 565 band = i; 566 } 567 } else 568 band = force_band - 1; 569 570 state->bandselectarg = cx24123_bandselect_vals[band].progdata; 571 vco_div = cx24123_bandselect_vals[band].VCOdivider; 572 573 /* determine the charge pump current */ 574 if (p->frequency < (cx24123_bandselect_vals[band].freq_low + 575 cx24123_bandselect_vals[band].freq_high) / 2) 576 pump = 0x01; 577 else 578 pump = 0x02; 579 580 /* Determine the N/A dividers for the requested lband freq (in kHz). */ 581 /* Note: the reference divider R=10, frequency is in KHz, 582 * XTAL is in Hz */ 583 ndiv = (((p->frequency * vco_div * 10) / 584 (2 * XTAL / 1000)) / 32) & 0x1ff; 585 adiv = (((p->frequency * vco_div * 10) / 586 (2 * XTAL / 1000)) % 32) & 0x1f; 587 588 if (adiv == 0 && ndiv > 0) 589 ndiv--; 590 591 /* control bits 11, refdiv 11, charge pump polarity 1, 592 * charge pump current, ndiv, adiv */ 593 state->pllarg = (3 << 19) | (3 << 17) | (1 << 16) | 594 (pump << 14) | (ndiv << 5) | adiv; 595 596 return 0; 597 } 598 599 /* 600 * Tuner data is 21 bits long, must be left-aligned in data. 601 * Tuner cx24109 is written through a dedicated 3wire interface 602 * on the demod chip. 603 */ 604 static int cx24123_pll_writereg(struct dvb_frontend *fe, u32 data) 605 { 606 struct cx24123_state *state = fe->demodulator_priv; 607 unsigned long timeout; 608 609 dprintk("pll writereg called, data=0x%08x\n", data); 610 611 /* align the 21 bytes into to bit23 boundary */ 612 data = data << 3; 613 614 /* Reset the demod pll word length to 0x15 bits */ 615 cx24123_writereg(state, 0x21, 0x15); 616 617 /* write the msb 8 bits, wait for the send to be completed */ 618 timeout = jiffies + msecs_to_jiffies(40); 619 cx24123_writereg(state, 0x22, (data >> 16) & 0xff); 620 while ((cx24123_readreg(state, 0x20) & 0x40) == 0) { 621 if (time_after(jiffies, timeout)) { 622 err("%s: demodulator is not responding, "\ 623 "possibly hung, aborting.\n", __func__); 624 return -EREMOTEIO; 625 } 626 msleep(10); 627 } 628 629 /* send another 8 bytes, wait for the send to be completed */ 630 timeout = jiffies + msecs_to_jiffies(40); 631 cx24123_writereg(state, 0x22, (data >> 8) & 0xff); 632 while ((cx24123_readreg(state, 0x20) & 0x40) == 0) { 633 if (time_after(jiffies, timeout)) { 634 err("%s: demodulator is not responding, "\ 635 "possibly hung, aborting.\n", __func__); 636 return -EREMOTEIO; 637 } 638 msleep(10); 639 } 640 641 /* send the lower 5 bits of this byte, padded with 3 LBB, 642 * wait for the send to be completed */ 643 timeout = jiffies + msecs_to_jiffies(40); 644 cx24123_writereg(state, 0x22, (data) & 0xff); 645 while ((cx24123_readreg(state, 0x20) & 0x80)) { 646 if (time_after(jiffies, timeout)) { 647 err("%s: demodulator is not responding," \ 648 "possibly hung, aborting.\n", __func__); 649 return -EREMOTEIO; 650 } 651 msleep(10); 652 } 653 654 /* Trigger the demod to configure the tuner */ 655 cx24123_writereg(state, 0x20, cx24123_readreg(state, 0x20) | 2); 656 cx24123_writereg(state, 0x20, cx24123_readreg(state, 0x20) & 0xfd); 657 658 return 0; 659 } 660 661 static int cx24123_pll_tune(struct dvb_frontend *fe) 662 { 663 struct dtv_frontend_properties *p = &fe->dtv_property_cache; 664 struct cx24123_state *state = fe->demodulator_priv; 665 u8 val; 666 667 dprintk("frequency=%i\n", p->frequency); 668 669 if (cx24123_pll_calculate(fe) != 0) { 670 err("%s: cx24123_pll_calcutate failed\n", __func__); 671 return -EINVAL; 672 } 673 674 /* Write the new VCO/VGA */ 675 cx24123_pll_writereg(fe, state->VCAarg); 676 cx24123_pll_writereg(fe, state->VGAarg); 677 678 /* Write the new bandselect and pll args */ 679 cx24123_pll_writereg(fe, state->bandselectarg); 680 cx24123_pll_writereg(fe, state->pllarg); 681 682 /* set the FILTUNE voltage */ 683 val = cx24123_readreg(state, 0x28) & ~0x3; 684 cx24123_writereg(state, 0x27, state->FILTune >> 2); 685 cx24123_writereg(state, 0x28, val | (state->FILTune & 0x3)); 686 687 dprintk("pll tune VCA=%d, band=%d, pll=%d\n", state->VCAarg, 688 state->bandselectarg, state->pllarg); 689 690 return 0; 691 } 692 693 694 /* 695 * 0x23: 696 * [7:7] = BTI enabled 697 * [6:6] = I2C repeater enabled 698 * [5:5] = I2C repeater start 699 * [0:0] = BTI start 700 */ 701 702 /* mode == 1 -> i2c-repeater, 0 -> bti */ 703 static int cx24123_repeater_mode(struct cx24123_state *state, u8 mode, u8 start) 704 { 705 u8 r = cx24123_readreg(state, 0x23) & 0x1e; 706 if (mode) 707 r |= (1 << 6) | (start << 5); 708 else 709 r |= (1 << 7) | (start); 710 return cx24123_writereg(state, 0x23, r); 711 } 712 713 static int cx24123_initfe(struct dvb_frontend *fe) 714 { 715 struct cx24123_state *state = fe->demodulator_priv; 716 int i; 717 718 dprintk("init frontend\n"); 719 720 /* Configure the demod to a good set of defaults */ 721 for (i = 0; i < ARRAY_SIZE(cx24123_regdata); i++) 722 cx24123_writereg(state, cx24123_regdata[i].reg, 723 cx24123_regdata[i].data); 724 725 /* Set the LNB polarity */ 726 if (state->config->lnb_polarity) 727 cx24123_writereg(state, 0x32, 728 cx24123_readreg(state, 0x32) | 0x02); 729 730 if (state->config->dont_use_pll) 731 cx24123_repeater_mode(state, 1, 0); 732 733 return 0; 734 } 735 736 static int cx24123_set_voltage(struct dvb_frontend *fe, 737 fe_sec_voltage_t voltage) 738 { 739 struct cx24123_state *state = fe->demodulator_priv; 740 u8 val; 741 742 val = cx24123_readreg(state, 0x29) & ~0x40; 743 744 switch (voltage) { 745 case SEC_VOLTAGE_13: 746 dprintk("setting voltage 13V\n"); 747 return cx24123_writereg(state, 0x29, val & 0x7f); 748 case SEC_VOLTAGE_18: 749 dprintk("setting voltage 18V\n"); 750 return cx24123_writereg(state, 0x29, val | 0x80); 751 case SEC_VOLTAGE_OFF: 752 /* already handled in cx88-dvb */ 753 return 0; 754 default: 755 return -EINVAL; 756 }; 757 758 return 0; 759 } 760 761 /* wait for diseqc queue to become ready (or timeout) */ 762 static void cx24123_wait_for_diseqc(struct cx24123_state *state) 763 { 764 unsigned long timeout = jiffies + msecs_to_jiffies(200); 765 while (!(cx24123_readreg(state, 0x29) & 0x40)) { 766 if (time_after(jiffies, timeout)) { 767 err("%s: diseqc queue not ready, " \ 768 "command may be lost.\n", __func__); 769 break; 770 } 771 msleep(10); 772 } 773 } 774 775 static int cx24123_send_diseqc_msg(struct dvb_frontend *fe, 776 struct dvb_diseqc_master_cmd *cmd) 777 { 778 struct cx24123_state *state = fe->demodulator_priv; 779 int i, val, tone; 780 781 dprintk("\n"); 782 783 /* stop continuous tone if enabled */ 784 tone = cx24123_readreg(state, 0x29); 785 if (tone & 0x10) 786 cx24123_writereg(state, 0x29, tone & ~0x50); 787 788 /* wait for diseqc queue ready */ 789 cx24123_wait_for_diseqc(state); 790 791 /* select tone mode */ 792 cx24123_writereg(state, 0x2a, cx24123_readreg(state, 0x2a) & 0xfb); 793 794 for (i = 0; i < cmd->msg_len; i++) 795 cx24123_writereg(state, 0x2C + i, cmd->msg[i]); 796 797 val = cx24123_readreg(state, 0x29); 798 cx24123_writereg(state, 0x29, ((val & 0x90) | 0x40) | 799 ((cmd->msg_len-3) & 3)); 800 801 /* wait for diseqc message to finish sending */ 802 cx24123_wait_for_diseqc(state); 803 804 /* restart continuous tone if enabled */ 805 if (tone & 0x10) 806 cx24123_writereg(state, 0x29, tone & ~0x40); 807 808 return 0; 809 } 810 811 static int cx24123_diseqc_send_burst(struct dvb_frontend *fe, 812 fe_sec_mini_cmd_t burst) 813 { 814 struct cx24123_state *state = fe->demodulator_priv; 815 int val, tone; 816 817 dprintk("\n"); 818 819 /* stop continuous tone if enabled */ 820 tone = cx24123_readreg(state, 0x29); 821 if (tone & 0x10) 822 cx24123_writereg(state, 0x29, tone & ~0x50); 823 824 /* wait for diseqc queue ready */ 825 cx24123_wait_for_diseqc(state); 826 827 /* select tone mode */ 828 cx24123_writereg(state, 0x2a, cx24123_readreg(state, 0x2a) | 0x4); 829 msleep(30); 830 val = cx24123_readreg(state, 0x29); 831 if (burst == SEC_MINI_A) 832 cx24123_writereg(state, 0x29, ((val & 0x90) | 0x40 | 0x00)); 833 else if (burst == SEC_MINI_B) 834 cx24123_writereg(state, 0x29, ((val & 0x90) | 0x40 | 0x08)); 835 else 836 return -EINVAL; 837 838 cx24123_wait_for_diseqc(state); 839 cx24123_writereg(state, 0x2a, cx24123_readreg(state, 0x2a) & 0xfb); 840 841 /* restart continuous tone if enabled */ 842 if (tone & 0x10) 843 cx24123_writereg(state, 0x29, tone & ~0x40); 844 845 return 0; 846 } 847 848 static int cx24123_read_status(struct dvb_frontend *fe, fe_status_t *status) 849 { 850 struct cx24123_state *state = fe->demodulator_priv; 851 int sync = cx24123_readreg(state, 0x14); 852 853 *status = 0; 854 if (state->config->dont_use_pll) { 855 u32 tun_status = 0; 856 if (fe->ops.tuner_ops.get_status) 857 fe->ops.tuner_ops.get_status(fe, &tun_status); 858 if (tun_status & TUNER_STATUS_LOCKED) 859 *status |= FE_HAS_SIGNAL; 860 } else { 861 int lock = cx24123_readreg(state, 0x20); 862 if (lock & 0x01) 863 *status |= FE_HAS_SIGNAL; 864 } 865 866 if (sync & 0x02) 867 *status |= FE_HAS_CARRIER; /* Phase locked */ 868 if (sync & 0x04) 869 *status |= FE_HAS_VITERBI; 870 871 /* Reed-Solomon Status */ 872 if (sync & 0x08) 873 *status |= FE_HAS_SYNC; 874 if (sync & 0x80) 875 *status |= FE_HAS_LOCK; /*Full Sync */ 876 877 return 0; 878 } 879 880 /* 881 * Configured to return the measurement of errors in blocks, 882 * because no UCBLOCKS value is available, so this value doubles up 883 * to satisfy both measurements. 884 */ 885 static int cx24123_read_ber(struct dvb_frontend *fe, u32 *ber) 886 { 887 struct cx24123_state *state = fe->demodulator_priv; 888 889 /* The true bit error rate is this value divided by 890 the window size (set as 256 * 255) */ 891 *ber = ((cx24123_readreg(state, 0x1c) & 0x3f) << 16) | 892 (cx24123_readreg(state, 0x1d) << 8 | 893 cx24123_readreg(state, 0x1e)); 894 895 dprintk("BER = %d\n", *ber); 896 897 return 0; 898 } 899 900 static int cx24123_read_signal_strength(struct dvb_frontend *fe, 901 u16 *signal_strength) 902 { 903 struct cx24123_state *state = fe->demodulator_priv; 904 905 /* larger = better */ 906 *signal_strength = cx24123_readreg(state, 0x3b) << 8; 907 908 dprintk("Signal strength = %d\n", *signal_strength); 909 910 return 0; 911 } 912 913 static int cx24123_read_snr(struct dvb_frontend *fe, u16 *snr) 914 { 915 struct cx24123_state *state = fe->demodulator_priv; 916 917 /* Inverted raw Es/N0 count, totally bogus but better than the 918 BER threshold. */ 919 *snr = 65535 - (((u16)cx24123_readreg(state, 0x18) << 8) | 920 (u16)cx24123_readreg(state, 0x19)); 921 922 dprintk("read S/N index = %d\n", *snr); 923 924 return 0; 925 } 926 927 static int cx24123_set_frontend(struct dvb_frontend *fe) 928 { 929 struct cx24123_state *state = fe->demodulator_priv; 930 struct dtv_frontend_properties *p = &fe->dtv_property_cache; 931 932 dprintk("\n"); 933 934 if (state->config->set_ts_params) 935 state->config->set_ts_params(fe, 0); 936 937 state->currentfreq = p->frequency; 938 state->currentsymbolrate = p->symbol_rate; 939 940 cx24123_set_inversion(state, p->inversion); 941 cx24123_set_fec(state, p->fec_inner); 942 cx24123_set_symbolrate(state, p->symbol_rate); 943 944 if (!state->config->dont_use_pll) 945 cx24123_pll_tune(fe); 946 else if (fe->ops.tuner_ops.set_params) 947 fe->ops.tuner_ops.set_params(fe); 948 else 949 err("it seems I don't have a tuner..."); 950 951 /* Enable automatic acquisition and reset cycle */ 952 cx24123_writereg(state, 0x03, (cx24123_readreg(state, 0x03) | 0x07)); 953 cx24123_writereg(state, 0x00, 0x10); 954 cx24123_writereg(state, 0x00, 0); 955 956 if (state->config->agc_callback) 957 state->config->agc_callback(fe); 958 959 return 0; 960 } 961 962 static int cx24123_get_frontend(struct dvb_frontend *fe) 963 { 964 struct dtv_frontend_properties *p = &fe->dtv_property_cache; 965 struct cx24123_state *state = fe->demodulator_priv; 966 967 dprintk("\n"); 968 969 if (cx24123_get_inversion(state, &p->inversion) != 0) { 970 err("%s: Failed to get inversion status\n", __func__); 971 return -EREMOTEIO; 972 } 973 if (cx24123_get_fec(state, &p->fec_inner) != 0) { 974 err("%s: Failed to get fec status\n", __func__); 975 return -EREMOTEIO; 976 } 977 p->frequency = state->currentfreq; 978 p->symbol_rate = state->currentsymbolrate; 979 980 return 0; 981 } 982 983 static int cx24123_set_tone(struct dvb_frontend *fe, fe_sec_tone_mode_t tone) 984 { 985 struct cx24123_state *state = fe->demodulator_priv; 986 u8 val; 987 988 /* wait for diseqc queue ready */ 989 cx24123_wait_for_diseqc(state); 990 991 val = cx24123_readreg(state, 0x29) & ~0x40; 992 993 switch (tone) { 994 case SEC_TONE_ON: 995 dprintk("setting tone on\n"); 996 return cx24123_writereg(state, 0x29, val | 0x10); 997 case SEC_TONE_OFF: 998 dprintk("setting tone off\n"); 999 return cx24123_writereg(state, 0x29, val & 0xef); 1000 default: 1001 err("CASE reached default with tone=%d\n", tone); 1002 return -EINVAL; 1003 } 1004 1005 return 0; 1006 } 1007 1008 static int cx24123_tune(struct dvb_frontend *fe, 1009 bool re_tune, 1010 unsigned int mode_flags, 1011 unsigned int *delay, 1012 fe_status_t *status) 1013 { 1014 int retval = 0; 1015 1016 if (re_tune) 1017 retval = cx24123_set_frontend(fe); 1018 1019 if (!(mode_flags & FE_TUNE_MODE_ONESHOT)) 1020 cx24123_read_status(fe, status); 1021 *delay = HZ/10; 1022 1023 return retval; 1024 } 1025 1026 static int cx24123_get_algo(struct dvb_frontend *fe) 1027 { 1028 return 1; /* FE_ALGO_HW */ 1029 } 1030 1031 static void cx24123_release(struct dvb_frontend *fe) 1032 { 1033 struct cx24123_state *state = fe->demodulator_priv; 1034 dprintk("\n"); 1035 i2c_del_adapter(&state->tuner_i2c_adapter); 1036 kfree(state); 1037 } 1038 1039 static int cx24123_tuner_i2c_tuner_xfer(struct i2c_adapter *i2c_adap, 1040 struct i2c_msg msg[], int num) 1041 { 1042 struct cx24123_state *state = i2c_get_adapdata(i2c_adap); 1043 /* this repeater closes after the first stop */ 1044 cx24123_repeater_mode(state, 1, 1); 1045 return i2c_transfer(state->i2c, msg, num); 1046 } 1047 1048 static u32 cx24123_tuner_i2c_func(struct i2c_adapter *adapter) 1049 { 1050 return I2C_FUNC_I2C; 1051 } 1052 1053 static struct i2c_algorithm cx24123_tuner_i2c_algo = { 1054 .master_xfer = cx24123_tuner_i2c_tuner_xfer, 1055 .functionality = cx24123_tuner_i2c_func, 1056 }; 1057 1058 struct i2c_adapter * 1059 cx24123_get_tuner_i2c_adapter(struct dvb_frontend *fe) 1060 { 1061 struct cx24123_state *state = fe->demodulator_priv; 1062 return &state->tuner_i2c_adapter; 1063 } 1064 EXPORT_SYMBOL(cx24123_get_tuner_i2c_adapter); 1065 1066 static struct dvb_frontend_ops cx24123_ops; 1067 1068 struct dvb_frontend *cx24123_attach(const struct cx24123_config *config, 1069 struct i2c_adapter *i2c) 1070 { 1071 /* allocate memory for the internal state */ 1072 struct cx24123_state *state = 1073 kzalloc(sizeof(struct cx24123_state), GFP_KERNEL); 1074 1075 dprintk("\n"); 1076 if (state == NULL) { 1077 err("Unable to kzalloc\n"); 1078 goto error; 1079 } 1080 1081 /* setup the state */ 1082 state->config = config; 1083 state->i2c = i2c; 1084 1085 /* check if the demod is there */ 1086 state->demod_rev = cx24123_readreg(state, 0x00); 1087 switch (state->demod_rev) { 1088 case 0xe1: 1089 info("detected CX24123C\n"); 1090 break; 1091 case 0xd1: 1092 info("detected CX24123\n"); 1093 break; 1094 default: 1095 err("wrong demod revision: %x\n", state->demod_rev); 1096 goto error; 1097 } 1098 1099 /* create dvb_frontend */ 1100 memcpy(&state->frontend.ops, &cx24123_ops, 1101 sizeof(struct dvb_frontend_ops)); 1102 state->frontend.demodulator_priv = state; 1103 1104 /* create tuner i2c adapter */ 1105 if (config->dont_use_pll) 1106 cx24123_repeater_mode(state, 1, 0); 1107 1108 strlcpy(state->tuner_i2c_adapter.name, "CX24123 tuner I2C bus", 1109 sizeof(state->tuner_i2c_adapter.name)); 1110 state->tuner_i2c_adapter.algo = &cx24123_tuner_i2c_algo; 1111 state->tuner_i2c_adapter.algo_data = NULL; 1112 i2c_set_adapdata(&state->tuner_i2c_adapter, state); 1113 if (i2c_add_adapter(&state->tuner_i2c_adapter) < 0) { 1114 err("tuner i2c bus could not be initialized\n"); 1115 goto error; 1116 } 1117 1118 return &state->frontend; 1119 1120 error: 1121 kfree(state); 1122 1123 return NULL; 1124 } 1125 EXPORT_SYMBOL(cx24123_attach); 1126 1127 static struct dvb_frontend_ops cx24123_ops = { 1128 .delsys = { SYS_DVBS }, 1129 .info = { 1130 .name = "Conexant CX24123/CX24109", 1131 .frequency_min = 950000, 1132 .frequency_max = 2150000, 1133 .frequency_stepsize = 1011, /* kHz for QPSK frontends */ 1134 .frequency_tolerance = 5000, 1135 .symbol_rate_min = 1000000, 1136 .symbol_rate_max = 45000000, 1137 .caps = FE_CAN_INVERSION_AUTO | 1138 FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 | FE_CAN_FEC_3_4 | 1139 FE_CAN_FEC_4_5 | FE_CAN_FEC_5_6 | FE_CAN_FEC_6_7 | 1140 FE_CAN_FEC_7_8 | FE_CAN_FEC_AUTO | 1141 FE_CAN_QPSK | FE_CAN_RECOVER 1142 }, 1143 1144 .release = cx24123_release, 1145 1146 .init = cx24123_initfe, 1147 .set_frontend = cx24123_set_frontend, 1148 .get_frontend = cx24123_get_frontend, 1149 .read_status = cx24123_read_status, 1150 .read_ber = cx24123_read_ber, 1151 .read_signal_strength = cx24123_read_signal_strength, 1152 .read_snr = cx24123_read_snr, 1153 .diseqc_send_master_cmd = cx24123_send_diseqc_msg, 1154 .diseqc_send_burst = cx24123_diseqc_send_burst, 1155 .set_tone = cx24123_set_tone, 1156 .set_voltage = cx24123_set_voltage, 1157 .tune = cx24123_tune, 1158 .get_frontend_algo = cx24123_get_algo, 1159 }; 1160 1161 MODULE_DESCRIPTION("DVB Frontend module for Conexant " \ 1162 "CX24123/CX24109/CX24113 hardware"); 1163 MODULE_AUTHOR("Steven Toth"); 1164 MODULE_LICENSE("GPL"); 1165 1166