xref: /linux/drivers/media/dvb-frontends/cx24116.c (revision 9a0bf528b4d66b605f02634236da085595c22101)
1*9a0bf528SMauro Carvalho Chehab /*
2*9a0bf528SMauro Carvalho Chehab     Conexant cx24116/cx24118 - DVBS/S2 Satellite demod/tuner driver
3*9a0bf528SMauro Carvalho Chehab 
4*9a0bf528SMauro Carvalho Chehab     Copyright (C) 2006-2008 Steven Toth <stoth@hauppauge.com>
5*9a0bf528SMauro Carvalho Chehab     Copyright (C) 2006-2007 Georg Acher
6*9a0bf528SMauro Carvalho Chehab     Copyright (C) 2007-2008 Darron Broad
7*9a0bf528SMauro Carvalho Chehab 	March 2007
8*9a0bf528SMauro Carvalho Chehab 	    Fixed some bugs.
9*9a0bf528SMauro Carvalho Chehab 	    Added diseqc support.
10*9a0bf528SMauro Carvalho Chehab 	    Added corrected signal strength support.
11*9a0bf528SMauro Carvalho Chehab 	August 2007
12*9a0bf528SMauro Carvalho Chehab 	    Sync with legacy version.
13*9a0bf528SMauro Carvalho Chehab 	    Some clean ups.
14*9a0bf528SMauro Carvalho Chehab     Copyright (C) 2008 Igor Liplianin
15*9a0bf528SMauro Carvalho Chehab 	September, 9th 2008
16*9a0bf528SMauro Carvalho Chehab 	    Fixed locking on high symbol rates (>30000).
17*9a0bf528SMauro Carvalho Chehab 	    Implement MPEG initialization parameter.
18*9a0bf528SMauro Carvalho Chehab 	January, 17th 2009
19*9a0bf528SMauro Carvalho Chehab 	    Fill set_voltage with actually control voltage code.
20*9a0bf528SMauro Carvalho Chehab 	    Correct set tone to not affect voltage.
21*9a0bf528SMauro Carvalho Chehab 
22*9a0bf528SMauro Carvalho Chehab     This program is free software; you can redistribute it and/or modify
23*9a0bf528SMauro Carvalho Chehab     it under the terms of the GNU General Public License as published by
24*9a0bf528SMauro Carvalho Chehab     the Free Software Foundation; either version 2 of the License, or
25*9a0bf528SMauro Carvalho Chehab     (at your option) any later version.
26*9a0bf528SMauro Carvalho Chehab 
27*9a0bf528SMauro Carvalho Chehab     This program is distributed in the hope that it will be useful,
28*9a0bf528SMauro Carvalho Chehab     but WITHOUT ANY WARRANTY; without even the implied warranty of
29*9a0bf528SMauro Carvalho Chehab     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
30*9a0bf528SMauro Carvalho Chehab     GNU General Public License for more details.
31*9a0bf528SMauro Carvalho Chehab 
32*9a0bf528SMauro Carvalho Chehab     You should have received a copy of the GNU General Public License
33*9a0bf528SMauro Carvalho Chehab     along with this program; if not, write to the Free Software
34*9a0bf528SMauro Carvalho Chehab     Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
35*9a0bf528SMauro Carvalho Chehab */
36*9a0bf528SMauro Carvalho Chehab 
37*9a0bf528SMauro Carvalho Chehab #include <linux/slab.h>
38*9a0bf528SMauro Carvalho Chehab #include <linux/kernel.h>
39*9a0bf528SMauro Carvalho Chehab #include <linux/module.h>
40*9a0bf528SMauro Carvalho Chehab #include <linux/moduleparam.h>
41*9a0bf528SMauro Carvalho Chehab #include <linux/init.h>
42*9a0bf528SMauro Carvalho Chehab #include <linux/firmware.h>
43*9a0bf528SMauro Carvalho Chehab 
44*9a0bf528SMauro Carvalho Chehab #include "dvb_frontend.h"
45*9a0bf528SMauro Carvalho Chehab #include "cx24116.h"
46*9a0bf528SMauro Carvalho Chehab 
47*9a0bf528SMauro Carvalho Chehab static int debug;
48*9a0bf528SMauro Carvalho Chehab module_param(debug, int, 0644);
49*9a0bf528SMauro Carvalho Chehab MODULE_PARM_DESC(debug, "Activates frontend debugging (default:0)");
50*9a0bf528SMauro Carvalho Chehab 
51*9a0bf528SMauro Carvalho Chehab #define dprintk(args...) \
52*9a0bf528SMauro Carvalho Chehab 	do { \
53*9a0bf528SMauro Carvalho Chehab 		if (debug) \
54*9a0bf528SMauro Carvalho Chehab 			printk(KERN_INFO "cx24116: " args); \
55*9a0bf528SMauro Carvalho Chehab 	} while (0)
56*9a0bf528SMauro Carvalho Chehab 
57*9a0bf528SMauro Carvalho Chehab #define CX24116_DEFAULT_FIRMWARE "dvb-fe-cx24116.fw"
58*9a0bf528SMauro Carvalho Chehab #define CX24116_SEARCH_RANGE_KHZ 5000
59*9a0bf528SMauro Carvalho Chehab 
60*9a0bf528SMauro Carvalho Chehab /* known registers */
61*9a0bf528SMauro Carvalho Chehab #define CX24116_REG_COMMAND (0x00)      /* command args 0x00..0x1e */
62*9a0bf528SMauro Carvalho Chehab #define CX24116_REG_EXECUTE (0x1f)      /* execute command */
63*9a0bf528SMauro Carvalho Chehab #define CX24116_REG_MAILBOX (0x96)      /* FW or multipurpose mailbox? */
64*9a0bf528SMauro Carvalho Chehab #define CX24116_REG_RESET   (0x20)      /* reset status > 0     */
65*9a0bf528SMauro Carvalho Chehab #define CX24116_REG_SIGNAL  (0x9e)      /* signal low           */
66*9a0bf528SMauro Carvalho Chehab #define CX24116_REG_SSTATUS (0x9d)      /* signal high / status */
67*9a0bf528SMauro Carvalho Chehab #define CX24116_REG_QUALITY8 (0xa3)
68*9a0bf528SMauro Carvalho Chehab #define CX24116_REG_QSTATUS (0xbc)
69*9a0bf528SMauro Carvalho Chehab #define CX24116_REG_QUALITY0 (0xd5)
70*9a0bf528SMauro Carvalho Chehab #define CX24116_REG_BER0    (0xc9)
71*9a0bf528SMauro Carvalho Chehab #define CX24116_REG_BER8    (0xc8)
72*9a0bf528SMauro Carvalho Chehab #define CX24116_REG_BER16   (0xc7)
73*9a0bf528SMauro Carvalho Chehab #define CX24116_REG_BER24   (0xc6)
74*9a0bf528SMauro Carvalho Chehab #define CX24116_REG_UCB0    (0xcb)
75*9a0bf528SMauro Carvalho Chehab #define CX24116_REG_UCB8    (0xca)
76*9a0bf528SMauro Carvalho Chehab #define CX24116_REG_CLKDIV  (0xf3)
77*9a0bf528SMauro Carvalho Chehab #define CX24116_REG_RATEDIV (0xf9)
78*9a0bf528SMauro Carvalho Chehab 
79*9a0bf528SMauro Carvalho Chehab /* configured fec (not tuned) or actual FEC (tuned) 1=1/2 2=2/3 etc */
80*9a0bf528SMauro Carvalho Chehab #define CX24116_REG_FECSTATUS (0x9c)
81*9a0bf528SMauro Carvalho Chehab 
82*9a0bf528SMauro Carvalho Chehab /* FECSTATUS bits */
83*9a0bf528SMauro Carvalho Chehab /* mask to determine configured fec (not tuned) or actual fec (tuned) */
84*9a0bf528SMauro Carvalho Chehab #define CX24116_FEC_FECMASK   (0x1f)
85*9a0bf528SMauro Carvalho Chehab 
86*9a0bf528SMauro Carvalho Chehab /* Select DVB-S demodulator, else DVB-S2 */
87*9a0bf528SMauro Carvalho Chehab #define CX24116_FEC_DVBS      (0x20)
88*9a0bf528SMauro Carvalho Chehab #define CX24116_FEC_UNKNOWN   (0x40)    /* Unknown/unused */
89*9a0bf528SMauro Carvalho Chehab 
90*9a0bf528SMauro Carvalho Chehab /* Pilot mode requested when tuning else always reset when tuned */
91*9a0bf528SMauro Carvalho Chehab #define CX24116_FEC_PILOT     (0x80)
92*9a0bf528SMauro Carvalho Chehab 
93*9a0bf528SMauro Carvalho Chehab /* arg buffer size */
94*9a0bf528SMauro Carvalho Chehab #define CX24116_ARGLEN (0x1e)
95*9a0bf528SMauro Carvalho Chehab 
96*9a0bf528SMauro Carvalho Chehab /* rolloff */
97*9a0bf528SMauro Carvalho Chehab #define CX24116_ROLLOFF_020 (0x00)
98*9a0bf528SMauro Carvalho Chehab #define CX24116_ROLLOFF_025 (0x01)
99*9a0bf528SMauro Carvalho Chehab #define CX24116_ROLLOFF_035 (0x02)
100*9a0bf528SMauro Carvalho Chehab 
101*9a0bf528SMauro Carvalho Chehab /* pilot bit */
102*9a0bf528SMauro Carvalho Chehab #define CX24116_PILOT_OFF (0x00)
103*9a0bf528SMauro Carvalho Chehab #define CX24116_PILOT_ON (0x40)
104*9a0bf528SMauro Carvalho Chehab 
105*9a0bf528SMauro Carvalho Chehab /* signal status */
106*9a0bf528SMauro Carvalho Chehab #define CX24116_HAS_SIGNAL   (0x01)
107*9a0bf528SMauro Carvalho Chehab #define CX24116_HAS_CARRIER  (0x02)
108*9a0bf528SMauro Carvalho Chehab #define CX24116_HAS_VITERBI  (0x04)
109*9a0bf528SMauro Carvalho Chehab #define CX24116_HAS_SYNCLOCK (0x08)
110*9a0bf528SMauro Carvalho Chehab #define CX24116_HAS_UNKNOWN1 (0x10)
111*9a0bf528SMauro Carvalho Chehab #define CX24116_HAS_UNKNOWN2 (0x20)
112*9a0bf528SMauro Carvalho Chehab #define CX24116_STATUS_MASK  (0x0f)
113*9a0bf528SMauro Carvalho Chehab #define CX24116_SIGNAL_MASK  (0xc0)
114*9a0bf528SMauro Carvalho Chehab 
115*9a0bf528SMauro Carvalho Chehab #define CX24116_DISEQC_TONEOFF   (0)    /* toneburst never sent */
116*9a0bf528SMauro Carvalho Chehab #define CX24116_DISEQC_TONECACHE (1)    /* toneburst cached     */
117*9a0bf528SMauro Carvalho Chehab #define CX24116_DISEQC_MESGCACHE (2)    /* message cached       */
118*9a0bf528SMauro Carvalho Chehab 
119*9a0bf528SMauro Carvalho Chehab /* arg offset for DiSEqC */
120*9a0bf528SMauro Carvalho Chehab #define CX24116_DISEQC_BURST  (1)
121*9a0bf528SMauro Carvalho Chehab #define CX24116_DISEQC_ARG2_2 (2)   /* unknown value=2 */
122*9a0bf528SMauro Carvalho Chehab #define CX24116_DISEQC_ARG3_0 (3)   /* unknown value=0 */
123*9a0bf528SMauro Carvalho Chehab #define CX24116_DISEQC_ARG4_0 (4)   /* unknown value=0 */
124*9a0bf528SMauro Carvalho Chehab #define CX24116_DISEQC_MSGLEN (5)
125*9a0bf528SMauro Carvalho Chehab #define CX24116_DISEQC_MSGOFS (6)
126*9a0bf528SMauro Carvalho Chehab 
127*9a0bf528SMauro Carvalho Chehab /* DiSEqC burst */
128*9a0bf528SMauro Carvalho Chehab #define CX24116_DISEQC_MINI_A (0)
129*9a0bf528SMauro Carvalho Chehab #define CX24116_DISEQC_MINI_B (1)
130*9a0bf528SMauro Carvalho Chehab 
131*9a0bf528SMauro Carvalho Chehab /* DiSEqC tone burst */
132*9a0bf528SMauro Carvalho Chehab static int toneburst = 1;
133*9a0bf528SMauro Carvalho Chehab module_param(toneburst, int, 0644);
134*9a0bf528SMauro Carvalho Chehab MODULE_PARM_DESC(toneburst, "DiSEqC toneburst 0=OFF, 1=TONE CACHE, "\
135*9a0bf528SMauro Carvalho Chehab 	"2=MESSAGE CACHE (default:1)");
136*9a0bf528SMauro Carvalho Chehab 
137*9a0bf528SMauro Carvalho Chehab /* SNR measurements */
138*9a0bf528SMauro Carvalho Chehab static int esno_snr;
139*9a0bf528SMauro Carvalho Chehab module_param(esno_snr, int, 0644);
140*9a0bf528SMauro Carvalho Chehab MODULE_PARM_DESC(esno_snr, "SNR return units, 0=PERCENTAGE 0-100, "\
141*9a0bf528SMauro Carvalho Chehab 	"1=ESNO(db * 10) (default:0)");
142*9a0bf528SMauro Carvalho Chehab 
143*9a0bf528SMauro Carvalho Chehab enum cmds {
144*9a0bf528SMauro Carvalho Chehab 	CMD_SET_VCO     = 0x10,
145*9a0bf528SMauro Carvalho Chehab 	CMD_TUNEREQUEST = 0x11,
146*9a0bf528SMauro Carvalho Chehab 	CMD_MPEGCONFIG  = 0x13,
147*9a0bf528SMauro Carvalho Chehab 	CMD_TUNERINIT   = 0x14,
148*9a0bf528SMauro Carvalho Chehab 	CMD_BANDWIDTH   = 0x15,
149*9a0bf528SMauro Carvalho Chehab 	CMD_GETAGC      = 0x19,
150*9a0bf528SMauro Carvalho Chehab 	CMD_LNBCONFIG   = 0x20,
151*9a0bf528SMauro Carvalho Chehab 	CMD_LNBSEND     = 0x21, /* Formerly CMD_SEND_DISEQC */
152*9a0bf528SMauro Carvalho Chehab 	CMD_LNBDCLEVEL  = 0x22,
153*9a0bf528SMauro Carvalho Chehab 	CMD_SET_TONE    = 0x23,
154*9a0bf528SMauro Carvalho Chehab 	CMD_UPDFWVERS   = 0x35,
155*9a0bf528SMauro Carvalho Chehab 	CMD_TUNERSLEEP  = 0x36,
156*9a0bf528SMauro Carvalho Chehab 	CMD_AGCCONTROL  = 0x3b, /* Unknown */
157*9a0bf528SMauro Carvalho Chehab };
158*9a0bf528SMauro Carvalho Chehab 
159*9a0bf528SMauro Carvalho Chehab /* The Demod/Tuner can't easily provide these, we cache them */
160*9a0bf528SMauro Carvalho Chehab struct cx24116_tuning {
161*9a0bf528SMauro Carvalho Chehab 	u32 frequency;
162*9a0bf528SMauro Carvalho Chehab 	u32 symbol_rate;
163*9a0bf528SMauro Carvalho Chehab 	fe_spectral_inversion_t inversion;
164*9a0bf528SMauro Carvalho Chehab 	fe_code_rate_t fec;
165*9a0bf528SMauro Carvalho Chehab 
166*9a0bf528SMauro Carvalho Chehab 	fe_delivery_system_t delsys;
167*9a0bf528SMauro Carvalho Chehab 	fe_modulation_t modulation;
168*9a0bf528SMauro Carvalho Chehab 	fe_pilot_t pilot;
169*9a0bf528SMauro Carvalho Chehab 	fe_rolloff_t rolloff;
170*9a0bf528SMauro Carvalho Chehab 
171*9a0bf528SMauro Carvalho Chehab 	/* Demod values */
172*9a0bf528SMauro Carvalho Chehab 	u8 fec_val;
173*9a0bf528SMauro Carvalho Chehab 	u8 fec_mask;
174*9a0bf528SMauro Carvalho Chehab 	u8 inversion_val;
175*9a0bf528SMauro Carvalho Chehab 	u8 pilot_val;
176*9a0bf528SMauro Carvalho Chehab 	u8 rolloff_val;
177*9a0bf528SMauro Carvalho Chehab };
178*9a0bf528SMauro Carvalho Chehab 
179*9a0bf528SMauro Carvalho Chehab /* Basic commands that are sent to the firmware */
180*9a0bf528SMauro Carvalho Chehab struct cx24116_cmd {
181*9a0bf528SMauro Carvalho Chehab 	u8 len;
182*9a0bf528SMauro Carvalho Chehab 	u8 args[CX24116_ARGLEN];
183*9a0bf528SMauro Carvalho Chehab };
184*9a0bf528SMauro Carvalho Chehab 
185*9a0bf528SMauro Carvalho Chehab struct cx24116_state {
186*9a0bf528SMauro Carvalho Chehab 	struct i2c_adapter *i2c;
187*9a0bf528SMauro Carvalho Chehab 	const struct cx24116_config *config;
188*9a0bf528SMauro Carvalho Chehab 
189*9a0bf528SMauro Carvalho Chehab 	struct dvb_frontend frontend;
190*9a0bf528SMauro Carvalho Chehab 
191*9a0bf528SMauro Carvalho Chehab 	struct cx24116_tuning dcur;
192*9a0bf528SMauro Carvalho Chehab 	struct cx24116_tuning dnxt;
193*9a0bf528SMauro Carvalho Chehab 
194*9a0bf528SMauro Carvalho Chehab 	u8 skip_fw_load;
195*9a0bf528SMauro Carvalho Chehab 	u8 burst;
196*9a0bf528SMauro Carvalho Chehab 	struct cx24116_cmd dsec_cmd;
197*9a0bf528SMauro Carvalho Chehab };
198*9a0bf528SMauro Carvalho Chehab 
199*9a0bf528SMauro Carvalho Chehab static int cx24116_writereg(struct cx24116_state *state, int reg, int data)
200*9a0bf528SMauro Carvalho Chehab {
201*9a0bf528SMauro Carvalho Chehab 	u8 buf[] = { reg, data };
202*9a0bf528SMauro Carvalho Chehab 	struct i2c_msg msg = { .addr = state->config->demod_address,
203*9a0bf528SMauro Carvalho Chehab 		.flags = 0, .buf = buf, .len = 2 };
204*9a0bf528SMauro Carvalho Chehab 	int err;
205*9a0bf528SMauro Carvalho Chehab 
206*9a0bf528SMauro Carvalho Chehab 	if (debug > 1)
207*9a0bf528SMauro Carvalho Chehab 		printk("cx24116: %s: write reg 0x%02x, value 0x%02x\n",
208*9a0bf528SMauro Carvalho Chehab 			__func__, reg, data);
209*9a0bf528SMauro Carvalho Chehab 
210*9a0bf528SMauro Carvalho Chehab 	err = i2c_transfer(state->i2c, &msg, 1);
211*9a0bf528SMauro Carvalho Chehab 	if (err != 1) {
212*9a0bf528SMauro Carvalho Chehab 		printk(KERN_ERR "%s: writereg error(err == %i, reg == 0x%02x,"
213*9a0bf528SMauro Carvalho Chehab 			 " value == 0x%02x)\n", __func__, err, reg, data);
214*9a0bf528SMauro Carvalho Chehab 		return -EREMOTEIO;
215*9a0bf528SMauro Carvalho Chehab 	}
216*9a0bf528SMauro Carvalho Chehab 
217*9a0bf528SMauro Carvalho Chehab 	return 0;
218*9a0bf528SMauro Carvalho Chehab }
219*9a0bf528SMauro Carvalho Chehab 
220*9a0bf528SMauro Carvalho Chehab /* Bulk byte writes to a single I2C address, for 32k firmware load */
221*9a0bf528SMauro Carvalho Chehab static int cx24116_writeregN(struct cx24116_state *state, int reg,
222*9a0bf528SMauro Carvalho Chehab 			     const u8 *data, u16 len)
223*9a0bf528SMauro Carvalho Chehab {
224*9a0bf528SMauro Carvalho Chehab 	int ret = -EREMOTEIO;
225*9a0bf528SMauro Carvalho Chehab 	struct i2c_msg msg;
226*9a0bf528SMauro Carvalho Chehab 	u8 *buf;
227*9a0bf528SMauro Carvalho Chehab 
228*9a0bf528SMauro Carvalho Chehab 	buf = kmalloc(len + 1, GFP_KERNEL);
229*9a0bf528SMauro Carvalho Chehab 	if (buf == NULL) {
230*9a0bf528SMauro Carvalho Chehab 		printk("Unable to kmalloc\n");
231*9a0bf528SMauro Carvalho Chehab 		ret = -ENOMEM;
232*9a0bf528SMauro Carvalho Chehab 		goto error;
233*9a0bf528SMauro Carvalho Chehab 	}
234*9a0bf528SMauro Carvalho Chehab 
235*9a0bf528SMauro Carvalho Chehab 	*(buf) = reg;
236*9a0bf528SMauro Carvalho Chehab 	memcpy(buf + 1, data, len);
237*9a0bf528SMauro Carvalho Chehab 
238*9a0bf528SMauro Carvalho Chehab 	msg.addr = state->config->demod_address;
239*9a0bf528SMauro Carvalho Chehab 	msg.flags = 0;
240*9a0bf528SMauro Carvalho Chehab 	msg.buf = buf;
241*9a0bf528SMauro Carvalho Chehab 	msg.len = len + 1;
242*9a0bf528SMauro Carvalho Chehab 
243*9a0bf528SMauro Carvalho Chehab 	if (debug > 1)
244*9a0bf528SMauro Carvalho Chehab 		printk(KERN_INFO "cx24116: %s:  write regN 0x%02x, len = %d\n",
245*9a0bf528SMauro Carvalho Chehab 			__func__, reg, len);
246*9a0bf528SMauro Carvalho Chehab 
247*9a0bf528SMauro Carvalho Chehab 	ret = i2c_transfer(state->i2c, &msg, 1);
248*9a0bf528SMauro Carvalho Chehab 	if (ret != 1) {
249*9a0bf528SMauro Carvalho Chehab 		printk(KERN_ERR "%s: writereg error(err == %i, reg == 0x%02x\n",
250*9a0bf528SMauro Carvalho Chehab 			 __func__, ret, reg);
251*9a0bf528SMauro Carvalho Chehab 		ret = -EREMOTEIO;
252*9a0bf528SMauro Carvalho Chehab 	}
253*9a0bf528SMauro Carvalho Chehab 
254*9a0bf528SMauro Carvalho Chehab error:
255*9a0bf528SMauro Carvalho Chehab 	kfree(buf);
256*9a0bf528SMauro Carvalho Chehab 
257*9a0bf528SMauro Carvalho Chehab 	return ret;
258*9a0bf528SMauro Carvalho Chehab }
259*9a0bf528SMauro Carvalho Chehab 
260*9a0bf528SMauro Carvalho Chehab static int cx24116_readreg(struct cx24116_state *state, u8 reg)
261*9a0bf528SMauro Carvalho Chehab {
262*9a0bf528SMauro Carvalho Chehab 	int ret;
263*9a0bf528SMauro Carvalho Chehab 	u8 b0[] = { reg };
264*9a0bf528SMauro Carvalho Chehab 	u8 b1[] = { 0 };
265*9a0bf528SMauro Carvalho Chehab 	struct i2c_msg msg[] = {
266*9a0bf528SMauro Carvalho Chehab 		{ .addr = state->config->demod_address, .flags = 0,
267*9a0bf528SMauro Carvalho Chehab 			.buf = b0, .len = 1 },
268*9a0bf528SMauro Carvalho Chehab 		{ .addr = state->config->demod_address, .flags = I2C_M_RD,
269*9a0bf528SMauro Carvalho Chehab 			.buf = b1, .len = 1 }
270*9a0bf528SMauro Carvalho Chehab 	};
271*9a0bf528SMauro Carvalho Chehab 
272*9a0bf528SMauro Carvalho Chehab 	ret = i2c_transfer(state->i2c, msg, 2);
273*9a0bf528SMauro Carvalho Chehab 
274*9a0bf528SMauro Carvalho Chehab 	if (ret != 2) {
275*9a0bf528SMauro Carvalho Chehab 		printk(KERN_ERR "%s: reg=0x%x (error=%d)\n",
276*9a0bf528SMauro Carvalho Chehab 			__func__, reg, ret);
277*9a0bf528SMauro Carvalho Chehab 		return ret;
278*9a0bf528SMauro Carvalho Chehab 	}
279*9a0bf528SMauro Carvalho Chehab 
280*9a0bf528SMauro Carvalho Chehab 	if (debug > 1)
281*9a0bf528SMauro Carvalho Chehab 		printk(KERN_INFO "cx24116: read reg 0x%02x, value 0x%02x\n",
282*9a0bf528SMauro Carvalho Chehab 			reg, b1[0]);
283*9a0bf528SMauro Carvalho Chehab 
284*9a0bf528SMauro Carvalho Chehab 	return b1[0];
285*9a0bf528SMauro Carvalho Chehab }
286*9a0bf528SMauro Carvalho Chehab 
287*9a0bf528SMauro Carvalho Chehab static int cx24116_set_inversion(struct cx24116_state *state,
288*9a0bf528SMauro Carvalho Chehab 	fe_spectral_inversion_t inversion)
289*9a0bf528SMauro Carvalho Chehab {
290*9a0bf528SMauro Carvalho Chehab 	dprintk("%s(%d)\n", __func__, inversion);
291*9a0bf528SMauro Carvalho Chehab 
292*9a0bf528SMauro Carvalho Chehab 	switch (inversion) {
293*9a0bf528SMauro Carvalho Chehab 	case INVERSION_OFF:
294*9a0bf528SMauro Carvalho Chehab 		state->dnxt.inversion_val = 0x00;
295*9a0bf528SMauro Carvalho Chehab 		break;
296*9a0bf528SMauro Carvalho Chehab 	case INVERSION_ON:
297*9a0bf528SMauro Carvalho Chehab 		state->dnxt.inversion_val = 0x04;
298*9a0bf528SMauro Carvalho Chehab 		break;
299*9a0bf528SMauro Carvalho Chehab 	case INVERSION_AUTO:
300*9a0bf528SMauro Carvalho Chehab 		state->dnxt.inversion_val = 0x0C;
301*9a0bf528SMauro Carvalho Chehab 		break;
302*9a0bf528SMauro Carvalho Chehab 	default:
303*9a0bf528SMauro Carvalho Chehab 		return -EINVAL;
304*9a0bf528SMauro Carvalho Chehab 	}
305*9a0bf528SMauro Carvalho Chehab 
306*9a0bf528SMauro Carvalho Chehab 	state->dnxt.inversion = inversion;
307*9a0bf528SMauro Carvalho Chehab 
308*9a0bf528SMauro Carvalho Chehab 	return 0;
309*9a0bf528SMauro Carvalho Chehab }
310*9a0bf528SMauro Carvalho Chehab 
311*9a0bf528SMauro Carvalho Chehab /*
312*9a0bf528SMauro Carvalho Chehab  * modfec (modulation and FEC)
313*9a0bf528SMauro Carvalho Chehab  * ===========================
314*9a0bf528SMauro Carvalho Chehab  *
315*9a0bf528SMauro Carvalho Chehab  * MOD          FEC             mask/val    standard
316*9a0bf528SMauro Carvalho Chehab  * ----         --------        ----------- --------
317*9a0bf528SMauro Carvalho Chehab  * QPSK         FEC_1_2         0x02 0x02+X DVB-S
318*9a0bf528SMauro Carvalho Chehab  * QPSK         FEC_2_3         0x04 0x02+X DVB-S
319*9a0bf528SMauro Carvalho Chehab  * QPSK         FEC_3_4         0x08 0x02+X DVB-S
320*9a0bf528SMauro Carvalho Chehab  * QPSK         FEC_4_5         0x10 0x02+X DVB-S (?)
321*9a0bf528SMauro Carvalho Chehab  * QPSK         FEC_5_6         0x20 0x02+X DVB-S
322*9a0bf528SMauro Carvalho Chehab  * QPSK         FEC_6_7         0x40 0x02+X DVB-S
323*9a0bf528SMauro Carvalho Chehab  * QPSK         FEC_7_8         0x80 0x02+X DVB-S
324*9a0bf528SMauro Carvalho Chehab  * QPSK         FEC_8_9         0x01 0x02+X DVB-S (?) (NOT SUPPORTED?)
325*9a0bf528SMauro Carvalho Chehab  * QPSK         AUTO            0xff 0x02+X DVB-S
326*9a0bf528SMauro Carvalho Chehab  *
327*9a0bf528SMauro Carvalho Chehab  * For DVB-S high byte probably represents FEC
328*9a0bf528SMauro Carvalho Chehab  * and low byte selects the modulator. The high
329*9a0bf528SMauro Carvalho Chehab  * byte is search range mask. Bit 5 may turn
330*9a0bf528SMauro Carvalho Chehab  * on DVB-S and remaining bits represent some
331*9a0bf528SMauro Carvalho Chehab  * kind of calibration (how/what i do not know).
332*9a0bf528SMauro Carvalho Chehab  *
333*9a0bf528SMauro Carvalho Chehab  * Eg.(2/3) szap "Zone Horror"
334*9a0bf528SMauro Carvalho Chehab  *
335*9a0bf528SMauro Carvalho Chehab  * mask/val = 0x04, 0x20
336*9a0bf528SMauro Carvalho Chehab  * status 1f | signal c3c0 | snr a333 | ber 00000098 | unc 0 | FE_HAS_LOCK
337*9a0bf528SMauro Carvalho Chehab  *
338*9a0bf528SMauro Carvalho Chehab  * mask/val = 0x04, 0x30
339*9a0bf528SMauro Carvalho Chehab  * status 1f | signal c3c0 | snr a333 | ber 00000000 | unc 0 | FE_HAS_LOCK
340*9a0bf528SMauro Carvalho Chehab  *
341*9a0bf528SMauro Carvalho Chehab  * After tuning FECSTATUS contains actual FEC
342*9a0bf528SMauro Carvalho Chehab  * in use numbered 1 through to 8 for 1/2 .. 2/3 etc
343*9a0bf528SMauro Carvalho Chehab  *
344*9a0bf528SMauro Carvalho Chehab  * NBC=NOT/NON BACKWARD COMPATIBLE WITH DVB-S (DVB-S2 only)
345*9a0bf528SMauro Carvalho Chehab  *
346*9a0bf528SMauro Carvalho Chehab  * NBC-QPSK     FEC_1_2         0x00, 0x04      DVB-S2
347*9a0bf528SMauro Carvalho Chehab  * NBC-QPSK     FEC_3_5         0x00, 0x05      DVB-S2
348*9a0bf528SMauro Carvalho Chehab  * NBC-QPSK     FEC_2_3         0x00, 0x06      DVB-S2
349*9a0bf528SMauro Carvalho Chehab  * NBC-QPSK     FEC_3_4         0x00, 0x07      DVB-S2
350*9a0bf528SMauro Carvalho Chehab  * NBC-QPSK     FEC_4_5         0x00, 0x08      DVB-S2
351*9a0bf528SMauro Carvalho Chehab  * NBC-QPSK     FEC_5_6         0x00, 0x09      DVB-S2
352*9a0bf528SMauro Carvalho Chehab  * NBC-QPSK     FEC_8_9         0x00, 0x0a      DVB-S2
353*9a0bf528SMauro Carvalho Chehab  * NBC-QPSK     FEC_9_10        0x00, 0x0b      DVB-S2
354*9a0bf528SMauro Carvalho Chehab  *
355*9a0bf528SMauro Carvalho Chehab  * NBC-8PSK     FEC_3_5         0x00, 0x0c      DVB-S2
356*9a0bf528SMauro Carvalho Chehab  * NBC-8PSK     FEC_2_3         0x00, 0x0d      DVB-S2
357*9a0bf528SMauro Carvalho Chehab  * NBC-8PSK     FEC_3_4         0x00, 0x0e      DVB-S2
358*9a0bf528SMauro Carvalho Chehab  * NBC-8PSK     FEC_5_6         0x00, 0x0f      DVB-S2
359*9a0bf528SMauro Carvalho Chehab  * NBC-8PSK     FEC_8_9         0x00, 0x10      DVB-S2
360*9a0bf528SMauro Carvalho Chehab  * NBC-8PSK     FEC_9_10        0x00, 0x11      DVB-S2
361*9a0bf528SMauro Carvalho Chehab  *
362*9a0bf528SMauro Carvalho Chehab  * For DVB-S2 low bytes selects both modulator
363*9a0bf528SMauro Carvalho Chehab  * and FEC. High byte is meaningless here. To
364*9a0bf528SMauro Carvalho Chehab  * set pilot, bit 6 (0x40) is set. When inspecting
365*9a0bf528SMauro Carvalho Chehab  * FECSTATUS bit 7 (0x80) represents the pilot
366*9a0bf528SMauro Carvalho Chehab  * selection whilst not tuned. When tuned, actual FEC
367*9a0bf528SMauro Carvalho Chehab  * in use is found in FECSTATUS as per above. Pilot
368*9a0bf528SMauro Carvalho Chehab  * value is reset.
369*9a0bf528SMauro Carvalho Chehab  */
370*9a0bf528SMauro Carvalho Chehab 
371*9a0bf528SMauro Carvalho Chehab /* A table of modulation, fec and configuration bytes for the demod.
372*9a0bf528SMauro Carvalho Chehab  * Not all S2 mmodulation schemes are support and not all rates with
373*9a0bf528SMauro Carvalho Chehab  * a scheme are support. Especially, no auto detect when in S2 mode.
374*9a0bf528SMauro Carvalho Chehab  */
375*9a0bf528SMauro Carvalho Chehab static struct cx24116_modfec {
376*9a0bf528SMauro Carvalho Chehab 	fe_delivery_system_t delivery_system;
377*9a0bf528SMauro Carvalho Chehab 	fe_modulation_t modulation;
378*9a0bf528SMauro Carvalho Chehab 	fe_code_rate_t fec;
379*9a0bf528SMauro Carvalho Chehab 	u8 mask;	/* In DVBS mode this is used to autodetect */
380*9a0bf528SMauro Carvalho Chehab 	u8 val;		/* Passed to the firmware to indicate mode selection */
381*9a0bf528SMauro Carvalho Chehab } CX24116_MODFEC_MODES[] = {
382*9a0bf528SMauro Carvalho Chehab  /* QPSK. For unknown rates we set hardware to auto detect 0xfe 0x30 */
383*9a0bf528SMauro Carvalho Chehab 
384*9a0bf528SMauro Carvalho Chehab  /*mod   fec       mask  val */
385*9a0bf528SMauro Carvalho Chehab  { SYS_DVBS, QPSK, FEC_NONE, 0xfe, 0x30 },
386*9a0bf528SMauro Carvalho Chehab  { SYS_DVBS, QPSK, FEC_1_2,  0x02, 0x2e }, /* 00000010 00101110 */
387*9a0bf528SMauro Carvalho Chehab  { SYS_DVBS, QPSK, FEC_2_3,  0x04, 0x2f }, /* 00000100 00101111 */
388*9a0bf528SMauro Carvalho Chehab  { SYS_DVBS, QPSK, FEC_3_4,  0x08, 0x30 }, /* 00001000 00110000 */
389*9a0bf528SMauro Carvalho Chehab  { SYS_DVBS, QPSK, FEC_4_5,  0xfe, 0x30 }, /* 000?0000 ?        */
390*9a0bf528SMauro Carvalho Chehab  { SYS_DVBS, QPSK, FEC_5_6,  0x20, 0x31 }, /* 00100000 00110001 */
391*9a0bf528SMauro Carvalho Chehab  { SYS_DVBS, QPSK, FEC_6_7,  0xfe, 0x30 }, /* 0?000000 ?        */
392*9a0bf528SMauro Carvalho Chehab  { SYS_DVBS, QPSK, FEC_7_8,  0x80, 0x32 }, /* 10000000 00110010 */
393*9a0bf528SMauro Carvalho Chehab  { SYS_DVBS, QPSK, FEC_8_9,  0xfe, 0x30 }, /* 0000000? ?        */
394*9a0bf528SMauro Carvalho Chehab  { SYS_DVBS, QPSK, FEC_AUTO, 0xfe, 0x30 },
395*9a0bf528SMauro Carvalho Chehab  /* NBC-QPSK */
396*9a0bf528SMauro Carvalho Chehab  { SYS_DVBS2, QPSK, FEC_1_2,  0x00, 0x04 },
397*9a0bf528SMauro Carvalho Chehab  { SYS_DVBS2, QPSK, FEC_3_5,  0x00, 0x05 },
398*9a0bf528SMauro Carvalho Chehab  { SYS_DVBS2, QPSK, FEC_2_3,  0x00, 0x06 },
399*9a0bf528SMauro Carvalho Chehab  { SYS_DVBS2, QPSK, FEC_3_4,  0x00, 0x07 },
400*9a0bf528SMauro Carvalho Chehab  { SYS_DVBS2, QPSK, FEC_4_5,  0x00, 0x08 },
401*9a0bf528SMauro Carvalho Chehab  { SYS_DVBS2, QPSK, FEC_5_6,  0x00, 0x09 },
402*9a0bf528SMauro Carvalho Chehab  { SYS_DVBS2, QPSK, FEC_8_9,  0x00, 0x0a },
403*9a0bf528SMauro Carvalho Chehab  { SYS_DVBS2, QPSK, FEC_9_10, 0x00, 0x0b },
404*9a0bf528SMauro Carvalho Chehab  /* 8PSK */
405*9a0bf528SMauro Carvalho Chehab  { SYS_DVBS2, PSK_8, FEC_3_5,  0x00, 0x0c },
406*9a0bf528SMauro Carvalho Chehab  { SYS_DVBS2, PSK_8, FEC_2_3,  0x00, 0x0d },
407*9a0bf528SMauro Carvalho Chehab  { SYS_DVBS2, PSK_8, FEC_3_4,  0x00, 0x0e },
408*9a0bf528SMauro Carvalho Chehab  { SYS_DVBS2, PSK_8, FEC_5_6,  0x00, 0x0f },
409*9a0bf528SMauro Carvalho Chehab  { SYS_DVBS2, PSK_8, FEC_8_9,  0x00, 0x10 },
410*9a0bf528SMauro Carvalho Chehab  { SYS_DVBS2, PSK_8, FEC_9_10, 0x00, 0x11 },
411*9a0bf528SMauro Carvalho Chehab  /*
412*9a0bf528SMauro Carvalho Chehab   * `val' can be found in the FECSTATUS register when tuning.
413*9a0bf528SMauro Carvalho Chehab   * FECSTATUS will give the actual FEC in use if tuning was successful.
414*9a0bf528SMauro Carvalho Chehab   */
415*9a0bf528SMauro Carvalho Chehab };
416*9a0bf528SMauro Carvalho Chehab 
417*9a0bf528SMauro Carvalho Chehab static int cx24116_lookup_fecmod(struct cx24116_state *state,
418*9a0bf528SMauro Carvalho Chehab 	fe_delivery_system_t d, fe_modulation_t m, fe_code_rate_t f)
419*9a0bf528SMauro Carvalho Chehab {
420*9a0bf528SMauro Carvalho Chehab 	int i, ret = -EOPNOTSUPP;
421*9a0bf528SMauro Carvalho Chehab 
422*9a0bf528SMauro Carvalho Chehab 	dprintk("%s(0x%02x,0x%02x)\n", __func__, m, f);
423*9a0bf528SMauro Carvalho Chehab 
424*9a0bf528SMauro Carvalho Chehab 	for (i = 0; i < ARRAY_SIZE(CX24116_MODFEC_MODES); i++) {
425*9a0bf528SMauro Carvalho Chehab 		if ((d == CX24116_MODFEC_MODES[i].delivery_system) &&
426*9a0bf528SMauro Carvalho Chehab 			(m == CX24116_MODFEC_MODES[i].modulation) &&
427*9a0bf528SMauro Carvalho Chehab 			(f == CX24116_MODFEC_MODES[i].fec)) {
428*9a0bf528SMauro Carvalho Chehab 				ret = i;
429*9a0bf528SMauro Carvalho Chehab 				break;
430*9a0bf528SMauro Carvalho Chehab 			}
431*9a0bf528SMauro Carvalho Chehab 	}
432*9a0bf528SMauro Carvalho Chehab 
433*9a0bf528SMauro Carvalho Chehab 	return ret;
434*9a0bf528SMauro Carvalho Chehab }
435*9a0bf528SMauro Carvalho Chehab 
436*9a0bf528SMauro Carvalho Chehab static int cx24116_set_fec(struct cx24116_state *state,
437*9a0bf528SMauro Carvalho Chehab 	fe_delivery_system_t delsys, fe_modulation_t mod, fe_code_rate_t fec)
438*9a0bf528SMauro Carvalho Chehab {
439*9a0bf528SMauro Carvalho Chehab 	int ret = 0;
440*9a0bf528SMauro Carvalho Chehab 
441*9a0bf528SMauro Carvalho Chehab 	dprintk("%s(0x%02x,0x%02x)\n", __func__, mod, fec);
442*9a0bf528SMauro Carvalho Chehab 
443*9a0bf528SMauro Carvalho Chehab 	ret = cx24116_lookup_fecmod(state, delsys, mod, fec);
444*9a0bf528SMauro Carvalho Chehab 
445*9a0bf528SMauro Carvalho Chehab 	if (ret < 0)
446*9a0bf528SMauro Carvalho Chehab 		return ret;
447*9a0bf528SMauro Carvalho Chehab 
448*9a0bf528SMauro Carvalho Chehab 	state->dnxt.fec = fec;
449*9a0bf528SMauro Carvalho Chehab 	state->dnxt.fec_val = CX24116_MODFEC_MODES[ret].val;
450*9a0bf528SMauro Carvalho Chehab 	state->dnxt.fec_mask = CX24116_MODFEC_MODES[ret].mask;
451*9a0bf528SMauro Carvalho Chehab 	dprintk("%s() mask/val = 0x%02x/0x%02x\n", __func__,
452*9a0bf528SMauro Carvalho Chehab 		state->dnxt.fec_mask, state->dnxt.fec_val);
453*9a0bf528SMauro Carvalho Chehab 
454*9a0bf528SMauro Carvalho Chehab 	return 0;
455*9a0bf528SMauro Carvalho Chehab }
456*9a0bf528SMauro Carvalho Chehab 
457*9a0bf528SMauro Carvalho Chehab static int cx24116_set_symbolrate(struct cx24116_state *state, u32 rate)
458*9a0bf528SMauro Carvalho Chehab {
459*9a0bf528SMauro Carvalho Chehab 	dprintk("%s(%d)\n", __func__, rate);
460*9a0bf528SMauro Carvalho Chehab 
461*9a0bf528SMauro Carvalho Chehab 	/*  check if symbol rate is within limits */
462*9a0bf528SMauro Carvalho Chehab 	if ((rate > state->frontend.ops.info.symbol_rate_max) ||
463*9a0bf528SMauro Carvalho Chehab 	    (rate < state->frontend.ops.info.symbol_rate_min)) {
464*9a0bf528SMauro Carvalho Chehab 		dprintk("%s() unsupported symbol_rate = %d\n", __func__, rate);
465*9a0bf528SMauro Carvalho Chehab 		return -EOPNOTSUPP;
466*9a0bf528SMauro Carvalho Chehab 	}
467*9a0bf528SMauro Carvalho Chehab 
468*9a0bf528SMauro Carvalho Chehab 	state->dnxt.symbol_rate = rate;
469*9a0bf528SMauro Carvalho Chehab 	dprintk("%s() symbol_rate = %d\n", __func__, rate);
470*9a0bf528SMauro Carvalho Chehab 
471*9a0bf528SMauro Carvalho Chehab 	return 0;
472*9a0bf528SMauro Carvalho Chehab }
473*9a0bf528SMauro Carvalho Chehab 
474*9a0bf528SMauro Carvalho Chehab static int cx24116_load_firmware(struct dvb_frontend *fe,
475*9a0bf528SMauro Carvalho Chehab 	const struct firmware *fw);
476*9a0bf528SMauro Carvalho Chehab 
477*9a0bf528SMauro Carvalho Chehab static int cx24116_firmware_ondemand(struct dvb_frontend *fe)
478*9a0bf528SMauro Carvalho Chehab {
479*9a0bf528SMauro Carvalho Chehab 	struct cx24116_state *state = fe->demodulator_priv;
480*9a0bf528SMauro Carvalho Chehab 	const struct firmware *fw;
481*9a0bf528SMauro Carvalho Chehab 	int ret = 0;
482*9a0bf528SMauro Carvalho Chehab 
483*9a0bf528SMauro Carvalho Chehab 	dprintk("%s()\n", __func__);
484*9a0bf528SMauro Carvalho Chehab 
485*9a0bf528SMauro Carvalho Chehab 	if (cx24116_readreg(state, 0x20) > 0) {
486*9a0bf528SMauro Carvalho Chehab 
487*9a0bf528SMauro Carvalho Chehab 		if (state->skip_fw_load)
488*9a0bf528SMauro Carvalho Chehab 			return 0;
489*9a0bf528SMauro Carvalho Chehab 
490*9a0bf528SMauro Carvalho Chehab 		/* Load firmware */
491*9a0bf528SMauro Carvalho Chehab 		/* request the firmware, this will block until loaded */
492*9a0bf528SMauro Carvalho Chehab 		printk(KERN_INFO "%s: Waiting for firmware upload (%s)...\n",
493*9a0bf528SMauro Carvalho Chehab 			__func__, CX24116_DEFAULT_FIRMWARE);
494*9a0bf528SMauro Carvalho Chehab 		ret = request_firmware(&fw, CX24116_DEFAULT_FIRMWARE,
495*9a0bf528SMauro Carvalho Chehab 			state->i2c->dev.parent);
496*9a0bf528SMauro Carvalho Chehab 		printk(KERN_INFO "%s: Waiting for firmware upload(2)...\n",
497*9a0bf528SMauro Carvalho Chehab 			__func__);
498*9a0bf528SMauro Carvalho Chehab 		if (ret) {
499*9a0bf528SMauro Carvalho Chehab 			printk(KERN_ERR "%s: No firmware uploaded "
500*9a0bf528SMauro Carvalho Chehab 				"(timeout or file not found?)\n", __func__);
501*9a0bf528SMauro Carvalho Chehab 			return ret;
502*9a0bf528SMauro Carvalho Chehab 		}
503*9a0bf528SMauro Carvalho Chehab 
504*9a0bf528SMauro Carvalho Chehab 		/* Make sure we don't recurse back through here
505*9a0bf528SMauro Carvalho Chehab 		 * during loading */
506*9a0bf528SMauro Carvalho Chehab 		state->skip_fw_load = 1;
507*9a0bf528SMauro Carvalho Chehab 
508*9a0bf528SMauro Carvalho Chehab 		ret = cx24116_load_firmware(fe, fw);
509*9a0bf528SMauro Carvalho Chehab 		if (ret)
510*9a0bf528SMauro Carvalho Chehab 			printk(KERN_ERR "%s: Writing firmware to device failed\n",
511*9a0bf528SMauro Carvalho Chehab 				__func__);
512*9a0bf528SMauro Carvalho Chehab 
513*9a0bf528SMauro Carvalho Chehab 		release_firmware(fw);
514*9a0bf528SMauro Carvalho Chehab 
515*9a0bf528SMauro Carvalho Chehab 		printk(KERN_INFO "%s: Firmware upload %s\n", __func__,
516*9a0bf528SMauro Carvalho Chehab 			ret == 0 ? "complete" : "failed");
517*9a0bf528SMauro Carvalho Chehab 
518*9a0bf528SMauro Carvalho Chehab 		/* Ensure firmware is always loaded if required */
519*9a0bf528SMauro Carvalho Chehab 		state->skip_fw_load = 0;
520*9a0bf528SMauro Carvalho Chehab 	}
521*9a0bf528SMauro Carvalho Chehab 
522*9a0bf528SMauro Carvalho Chehab 	return ret;
523*9a0bf528SMauro Carvalho Chehab }
524*9a0bf528SMauro Carvalho Chehab 
525*9a0bf528SMauro Carvalho Chehab /* Take a basic firmware command structure, format it
526*9a0bf528SMauro Carvalho Chehab  * and forward it for processing
527*9a0bf528SMauro Carvalho Chehab  */
528*9a0bf528SMauro Carvalho Chehab static int cx24116_cmd_execute(struct dvb_frontend *fe, struct cx24116_cmd *cmd)
529*9a0bf528SMauro Carvalho Chehab {
530*9a0bf528SMauro Carvalho Chehab 	struct cx24116_state *state = fe->demodulator_priv;
531*9a0bf528SMauro Carvalho Chehab 	int i, ret;
532*9a0bf528SMauro Carvalho Chehab 
533*9a0bf528SMauro Carvalho Chehab 	dprintk("%s()\n", __func__);
534*9a0bf528SMauro Carvalho Chehab 
535*9a0bf528SMauro Carvalho Chehab 	/* Load the firmware if required */
536*9a0bf528SMauro Carvalho Chehab 	ret = cx24116_firmware_ondemand(fe);
537*9a0bf528SMauro Carvalho Chehab 	if (ret != 0) {
538*9a0bf528SMauro Carvalho Chehab 		printk(KERN_ERR "%s(): Unable initialise the firmware\n",
539*9a0bf528SMauro Carvalho Chehab 			__func__);
540*9a0bf528SMauro Carvalho Chehab 		return ret;
541*9a0bf528SMauro Carvalho Chehab 	}
542*9a0bf528SMauro Carvalho Chehab 
543*9a0bf528SMauro Carvalho Chehab 	/* Write the command */
544*9a0bf528SMauro Carvalho Chehab 	for (i = 0; i < cmd->len ; i++) {
545*9a0bf528SMauro Carvalho Chehab 		dprintk("%s: 0x%02x == 0x%02x\n", __func__, i, cmd->args[i]);
546*9a0bf528SMauro Carvalho Chehab 		cx24116_writereg(state, i, cmd->args[i]);
547*9a0bf528SMauro Carvalho Chehab 	}
548*9a0bf528SMauro Carvalho Chehab 
549*9a0bf528SMauro Carvalho Chehab 	/* Start execution and wait for cmd to terminate */
550*9a0bf528SMauro Carvalho Chehab 	cx24116_writereg(state, CX24116_REG_EXECUTE, 0x01);
551*9a0bf528SMauro Carvalho Chehab 	while (cx24116_readreg(state, CX24116_REG_EXECUTE)) {
552*9a0bf528SMauro Carvalho Chehab 		msleep(10);
553*9a0bf528SMauro Carvalho Chehab 		if (i++ > 64) {
554*9a0bf528SMauro Carvalho Chehab 			/* Avoid looping forever if the firmware does
555*9a0bf528SMauro Carvalho Chehab 				not respond */
556*9a0bf528SMauro Carvalho Chehab 			printk(KERN_WARNING "%s() Firmware not responding\n",
557*9a0bf528SMauro Carvalho Chehab 				__func__);
558*9a0bf528SMauro Carvalho Chehab 			return -EREMOTEIO;
559*9a0bf528SMauro Carvalho Chehab 		}
560*9a0bf528SMauro Carvalho Chehab 	}
561*9a0bf528SMauro Carvalho Chehab 	return 0;
562*9a0bf528SMauro Carvalho Chehab }
563*9a0bf528SMauro Carvalho Chehab 
564*9a0bf528SMauro Carvalho Chehab static int cx24116_load_firmware(struct dvb_frontend *fe,
565*9a0bf528SMauro Carvalho Chehab 	const struct firmware *fw)
566*9a0bf528SMauro Carvalho Chehab {
567*9a0bf528SMauro Carvalho Chehab 	struct cx24116_state *state = fe->demodulator_priv;
568*9a0bf528SMauro Carvalho Chehab 	struct cx24116_cmd cmd;
569*9a0bf528SMauro Carvalho Chehab 	int i, ret, len, max, remaining;
570*9a0bf528SMauro Carvalho Chehab 	unsigned char vers[4];
571*9a0bf528SMauro Carvalho Chehab 
572*9a0bf528SMauro Carvalho Chehab 	dprintk("%s\n", __func__);
573*9a0bf528SMauro Carvalho Chehab 	dprintk("Firmware is %zu bytes (%02x %02x .. %02x %02x)\n",
574*9a0bf528SMauro Carvalho Chehab 			fw->size,
575*9a0bf528SMauro Carvalho Chehab 			fw->data[0],
576*9a0bf528SMauro Carvalho Chehab 			fw->data[1],
577*9a0bf528SMauro Carvalho Chehab 			fw->data[fw->size-2],
578*9a0bf528SMauro Carvalho Chehab 			fw->data[fw->size-1]);
579*9a0bf528SMauro Carvalho Chehab 
580*9a0bf528SMauro Carvalho Chehab 	/* Toggle 88x SRST pin to reset demod */
581*9a0bf528SMauro Carvalho Chehab 	if (state->config->reset_device)
582*9a0bf528SMauro Carvalho Chehab 		state->config->reset_device(fe);
583*9a0bf528SMauro Carvalho Chehab 
584*9a0bf528SMauro Carvalho Chehab 	/* Begin the firmware load process */
585*9a0bf528SMauro Carvalho Chehab 	/* Prepare the demod, load the firmware, cleanup after load */
586*9a0bf528SMauro Carvalho Chehab 
587*9a0bf528SMauro Carvalho Chehab 	/* Init PLL */
588*9a0bf528SMauro Carvalho Chehab 	cx24116_writereg(state, 0xE5, 0x00);
589*9a0bf528SMauro Carvalho Chehab 	cx24116_writereg(state, 0xF1, 0x08);
590*9a0bf528SMauro Carvalho Chehab 	cx24116_writereg(state, 0xF2, 0x13);
591*9a0bf528SMauro Carvalho Chehab 
592*9a0bf528SMauro Carvalho Chehab 	/* Start PLL */
593*9a0bf528SMauro Carvalho Chehab 	cx24116_writereg(state, 0xe0, 0x03);
594*9a0bf528SMauro Carvalho Chehab 	cx24116_writereg(state, 0xe0, 0x00);
595*9a0bf528SMauro Carvalho Chehab 
596*9a0bf528SMauro Carvalho Chehab 	/* Unknown */
597*9a0bf528SMauro Carvalho Chehab 	cx24116_writereg(state, CX24116_REG_CLKDIV, 0x46);
598*9a0bf528SMauro Carvalho Chehab 	cx24116_writereg(state, CX24116_REG_RATEDIV, 0x00);
599*9a0bf528SMauro Carvalho Chehab 
600*9a0bf528SMauro Carvalho Chehab 	/* Unknown */
601*9a0bf528SMauro Carvalho Chehab 	cx24116_writereg(state, 0xF0, 0x03);
602*9a0bf528SMauro Carvalho Chehab 	cx24116_writereg(state, 0xF4, 0x81);
603*9a0bf528SMauro Carvalho Chehab 	cx24116_writereg(state, 0xF5, 0x00);
604*9a0bf528SMauro Carvalho Chehab 	cx24116_writereg(state, 0xF6, 0x00);
605*9a0bf528SMauro Carvalho Chehab 
606*9a0bf528SMauro Carvalho Chehab 	/* Split firmware to the max I2C write len and write.
607*9a0bf528SMauro Carvalho Chehab 	 * Writes whole firmware as one write when i2c_wr_max is set to 0. */
608*9a0bf528SMauro Carvalho Chehab 	if (state->config->i2c_wr_max)
609*9a0bf528SMauro Carvalho Chehab 		max = state->config->i2c_wr_max;
610*9a0bf528SMauro Carvalho Chehab 	else
611*9a0bf528SMauro Carvalho Chehab 		max = INT_MAX; /* enough for 32k firmware */
612*9a0bf528SMauro Carvalho Chehab 
613*9a0bf528SMauro Carvalho Chehab 	for (remaining = fw->size; remaining > 0; remaining -= max - 1) {
614*9a0bf528SMauro Carvalho Chehab 		len = remaining;
615*9a0bf528SMauro Carvalho Chehab 		if (len > max - 1)
616*9a0bf528SMauro Carvalho Chehab 			len = max - 1;
617*9a0bf528SMauro Carvalho Chehab 
618*9a0bf528SMauro Carvalho Chehab 		cx24116_writeregN(state, 0xF7, &fw->data[fw->size - remaining],
619*9a0bf528SMauro Carvalho Chehab 			len);
620*9a0bf528SMauro Carvalho Chehab 	}
621*9a0bf528SMauro Carvalho Chehab 
622*9a0bf528SMauro Carvalho Chehab 	cx24116_writereg(state, 0xF4, 0x10);
623*9a0bf528SMauro Carvalho Chehab 	cx24116_writereg(state, 0xF0, 0x00);
624*9a0bf528SMauro Carvalho Chehab 	cx24116_writereg(state, 0xF8, 0x06);
625*9a0bf528SMauro Carvalho Chehab 
626*9a0bf528SMauro Carvalho Chehab 	/* Firmware CMD 10: VCO config */
627*9a0bf528SMauro Carvalho Chehab 	cmd.args[0x00] = CMD_SET_VCO;
628*9a0bf528SMauro Carvalho Chehab 	cmd.args[0x01] = 0x05;
629*9a0bf528SMauro Carvalho Chehab 	cmd.args[0x02] = 0xdc;
630*9a0bf528SMauro Carvalho Chehab 	cmd.args[0x03] = 0xda;
631*9a0bf528SMauro Carvalho Chehab 	cmd.args[0x04] = 0xae;
632*9a0bf528SMauro Carvalho Chehab 	cmd.args[0x05] = 0xaa;
633*9a0bf528SMauro Carvalho Chehab 	cmd.args[0x06] = 0x04;
634*9a0bf528SMauro Carvalho Chehab 	cmd.args[0x07] = 0x9d;
635*9a0bf528SMauro Carvalho Chehab 	cmd.args[0x08] = 0xfc;
636*9a0bf528SMauro Carvalho Chehab 	cmd.args[0x09] = 0x06;
637*9a0bf528SMauro Carvalho Chehab 	cmd.len = 0x0a;
638*9a0bf528SMauro Carvalho Chehab 	ret = cx24116_cmd_execute(fe, &cmd);
639*9a0bf528SMauro Carvalho Chehab 	if (ret != 0)
640*9a0bf528SMauro Carvalho Chehab 		return ret;
641*9a0bf528SMauro Carvalho Chehab 
642*9a0bf528SMauro Carvalho Chehab 	cx24116_writereg(state, CX24116_REG_SSTATUS, 0x00);
643*9a0bf528SMauro Carvalho Chehab 
644*9a0bf528SMauro Carvalho Chehab 	/* Firmware CMD 14: Tuner config */
645*9a0bf528SMauro Carvalho Chehab 	cmd.args[0x00] = CMD_TUNERINIT;
646*9a0bf528SMauro Carvalho Chehab 	cmd.args[0x01] = 0x00;
647*9a0bf528SMauro Carvalho Chehab 	cmd.args[0x02] = 0x00;
648*9a0bf528SMauro Carvalho Chehab 	cmd.len = 0x03;
649*9a0bf528SMauro Carvalho Chehab 	ret = cx24116_cmd_execute(fe, &cmd);
650*9a0bf528SMauro Carvalho Chehab 	if (ret != 0)
651*9a0bf528SMauro Carvalho Chehab 		return ret;
652*9a0bf528SMauro Carvalho Chehab 
653*9a0bf528SMauro Carvalho Chehab 	cx24116_writereg(state, 0xe5, 0x00);
654*9a0bf528SMauro Carvalho Chehab 
655*9a0bf528SMauro Carvalho Chehab 	/* Firmware CMD 13: MPEG config */
656*9a0bf528SMauro Carvalho Chehab 	cmd.args[0x00] = CMD_MPEGCONFIG;
657*9a0bf528SMauro Carvalho Chehab 	cmd.args[0x01] = 0x01;
658*9a0bf528SMauro Carvalho Chehab 	cmd.args[0x02] = 0x75;
659*9a0bf528SMauro Carvalho Chehab 	cmd.args[0x03] = 0x00;
660*9a0bf528SMauro Carvalho Chehab 	if (state->config->mpg_clk_pos_pol)
661*9a0bf528SMauro Carvalho Chehab 		cmd.args[0x04] = state->config->mpg_clk_pos_pol;
662*9a0bf528SMauro Carvalho Chehab 	else
663*9a0bf528SMauro Carvalho Chehab 		cmd.args[0x04] = 0x02;
664*9a0bf528SMauro Carvalho Chehab 	cmd.args[0x05] = 0x00;
665*9a0bf528SMauro Carvalho Chehab 	cmd.len = 0x06;
666*9a0bf528SMauro Carvalho Chehab 	ret = cx24116_cmd_execute(fe, &cmd);
667*9a0bf528SMauro Carvalho Chehab 	if (ret != 0)
668*9a0bf528SMauro Carvalho Chehab 		return ret;
669*9a0bf528SMauro Carvalho Chehab 
670*9a0bf528SMauro Carvalho Chehab 	/* Firmware CMD 35: Get firmware version */
671*9a0bf528SMauro Carvalho Chehab 	cmd.args[0x00] = CMD_UPDFWVERS;
672*9a0bf528SMauro Carvalho Chehab 	cmd.len = 0x02;
673*9a0bf528SMauro Carvalho Chehab 	for (i = 0; i < 4; i++) {
674*9a0bf528SMauro Carvalho Chehab 		cmd.args[0x01] = i;
675*9a0bf528SMauro Carvalho Chehab 		ret = cx24116_cmd_execute(fe, &cmd);
676*9a0bf528SMauro Carvalho Chehab 		if (ret != 0)
677*9a0bf528SMauro Carvalho Chehab 			return ret;
678*9a0bf528SMauro Carvalho Chehab 		vers[i] = cx24116_readreg(state, CX24116_REG_MAILBOX);
679*9a0bf528SMauro Carvalho Chehab 	}
680*9a0bf528SMauro Carvalho Chehab 	printk(KERN_INFO "%s: FW version %i.%i.%i.%i\n", __func__,
681*9a0bf528SMauro Carvalho Chehab 		vers[0], vers[1], vers[2], vers[3]);
682*9a0bf528SMauro Carvalho Chehab 
683*9a0bf528SMauro Carvalho Chehab 	return 0;
684*9a0bf528SMauro Carvalho Chehab }
685*9a0bf528SMauro Carvalho Chehab 
686*9a0bf528SMauro Carvalho Chehab static int cx24116_read_status(struct dvb_frontend *fe, fe_status_t *status)
687*9a0bf528SMauro Carvalho Chehab {
688*9a0bf528SMauro Carvalho Chehab 	struct cx24116_state *state = fe->demodulator_priv;
689*9a0bf528SMauro Carvalho Chehab 
690*9a0bf528SMauro Carvalho Chehab 	int lock = cx24116_readreg(state, CX24116_REG_SSTATUS) &
691*9a0bf528SMauro Carvalho Chehab 		CX24116_STATUS_MASK;
692*9a0bf528SMauro Carvalho Chehab 
693*9a0bf528SMauro Carvalho Chehab 	dprintk("%s: status = 0x%02x\n", __func__, lock);
694*9a0bf528SMauro Carvalho Chehab 
695*9a0bf528SMauro Carvalho Chehab 	*status = 0;
696*9a0bf528SMauro Carvalho Chehab 
697*9a0bf528SMauro Carvalho Chehab 	if (lock & CX24116_HAS_SIGNAL)
698*9a0bf528SMauro Carvalho Chehab 		*status |= FE_HAS_SIGNAL;
699*9a0bf528SMauro Carvalho Chehab 	if (lock & CX24116_HAS_CARRIER)
700*9a0bf528SMauro Carvalho Chehab 		*status |= FE_HAS_CARRIER;
701*9a0bf528SMauro Carvalho Chehab 	if (lock & CX24116_HAS_VITERBI)
702*9a0bf528SMauro Carvalho Chehab 		*status |= FE_HAS_VITERBI;
703*9a0bf528SMauro Carvalho Chehab 	if (lock & CX24116_HAS_SYNCLOCK)
704*9a0bf528SMauro Carvalho Chehab 		*status |= FE_HAS_SYNC | FE_HAS_LOCK;
705*9a0bf528SMauro Carvalho Chehab 
706*9a0bf528SMauro Carvalho Chehab 	return 0;
707*9a0bf528SMauro Carvalho Chehab }
708*9a0bf528SMauro Carvalho Chehab 
709*9a0bf528SMauro Carvalho Chehab static int cx24116_read_ber(struct dvb_frontend *fe, u32 *ber)
710*9a0bf528SMauro Carvalho Chehab {
711*9a0bf528SMauro Carvalho Chehab 	struct cx24116_state *state = fe->demodulator_priv;
712*9a0bf528SMauro Carvalho Chehab 
713*9a0bf528SMauro Carvalho Chehab 	dprintk("%s()\n", __func__);
714*9a0bf528SMauro Carvalho Chehab 
715*9a0bf528SMauro Carvalho Chehab 	*ber =  (cx24116_readreg(state, CX24116_REG_BER24) << 24) |
716*9a0bf528SMauro Carvalho Chehab 		(cx24116_readreg(state, CX24116_REG_BER16) << 16) |
717*9a0bf528SMauro Carvalho Chehab 		(cx24116_readreg(state, CX24116_REG_BER8)  << 8)  |
718*9a0bf528SMauro Carvalho Chehab 		 cx24116_readreg(state, CX24116_REG_BER0);
719*9a0bf528SMauro Carvalho Chehab 
720*9a0bf528SMauro Carvalho Chehab 	return 0;
721*9a0bf528SMauro Carvalho Chehab }
722*9a0bf528SMauro Carvalho Chehab 
723*9a0bf528SMauro Carvalho Chehab /* TODO Determine function and scale appropriately */
724*9a0bf528SMauro Carvalho Chehab static int cx24116_read_signal_strength(struct dvb_frontend *fe,
725*9a0bf528SMauro Carvalho Chehab 	u16 *signal_strength)
726*9a0bf528SMauro Carvalho Chehab {
727*9a0bf528SMauro Carvalho Chehab 	struct cx24116_state *state = fe->demodulator_priv;
728*9a0bf528SMauro Carvalho Chehab 	struct cx24116_cmd cmd;
729*9a0bf528SMauro Carvalho Chehab 	int ret;
730*9a0bf528SMauro Carvalho Chehab 	u16 sig_reading;
731*9a0bf528SMauro Carvalho Chehab 
732*9a0bf528SMauro Carvalho Chehab 	dprintk("%s()\n", __func__);
733*9a0bf528SMauro Carvalho Chehab 
734*9a0bf528SMauro Carvalho Chehab 	/* Firmware CMD 19: Get AGC */
735*9a0bf528SMauro Carvalho Chehab 	cmd.args[0x00] = CMD_GETAGC;
736*9a0bf528SMauro Carvalho Chehab 	cmd.len = 0x01;
737*9a0bf528SMauro Carvalho Chehab 	ret = cx24116_cmd_execute(fe, &cmd);
738*9a0bf528SMauro Carvalho Chehab 	if (ret != 0)
739*9a0bf528SMauro Carvalho Chehab 		return ret;
740*9a0bf528SMauro Carvalho Chehab 
741*9a0bf528SMauro Carvalho Chehab 	sig_reading =
742*9a0bf528SMauro Carvalho Chehab 		(cx24116_readreg(state,
743*9a0bf528SMauro Carvalho Chehab 			CX24116_REG_SSTATUS) & CX24116_SIGNAL_MASK) |
744*9a0bf528SMauro Carvalho Chehab 		(cx24116_readreg(state, CX24116_REG_SIGNAL) << 6);
745*9a0bf528SMauro Carvalho Chehab 	*signal_strength = 0 - sig_reading;
746*9a0bf528SMauro Carvalho Chehab 
747*9a0bf528SMauro Carvalho Chehab 	dprintk("%s: raw / cooked = 0x%04x / 0x%04x\n",
748*9a0bf528SMauro Carvalho Chehab 		__func__, sig_reading, *signal_strength);
749*9a0bf528SMauro Carvalho Chehab 
750*9a0bf528SMauro Carvalho Chehab 	return 0;
751*9a0bf528SMauro Carvalho Chehab }
752*9a0bf528SMauro Carvalho Chehab 
753*9a0bf528SMauro Carvalho Chehab /* SNR (0..100)% = (sig & 0xf0) * 10 + (sig & 0x0f) * 10 / 16 */
754*9a0bf528SMauro Carvalho Chehab static int cx24116_read_snr_pct(struct dvb_frontend *fe, u16 *snr)
755*9a0bf528SMauro Carvalho Chehab {
756*9a0bf528SMauro Carvalho Chehab 	struct cx24116_state *state = fe->demodulator_priv;
757*9a0bf528SMauro Carvalho Chehab 	u8 snr_reading;
758*9a0bf528SMauro Carvalho Chehab 	static const u32 snr_tab[] = { /* 10 x Table (rounded up) */
759*9a0bf528SMauro Carvalho Chehab 		0x00000, 0x0199A, 0x03333, 0x04ccD, 0x06667,
760*9a0bf528SMauro Carvalho Chehab 		0x08000, 0x0999A, 0x0b333, 0x0cccD, 0x0e667,
761*9a0bf528SMauro Carvalho Chehab 		0x10000, 0x1199A, 0x13333, 0x14ccD, 0x16667,
762*9a0bf528SMauro Carvalho Chehab 		0x18000 };
763*9a0bf528SMauro Carvalho Chehab 
764*9a0bf528SMauro Carvalho Chehab 	dprintk("%s()\n", __func__);
765*9a0bf528SMauro Carvalho Chehab 
766*9a0bf528SMauro Carvalho Chehab 	snr_reading = cx24116_readreg(state, CX24116_REG_QUALITY0);
767*9a0bf528SMauro Carvalho Chehab 
768*9a0bf528SMauro Carvalho Chehab 	if (snr_reading >= 0xa0 /* 100% */)
769*9a0bf528SMauro Carvalho Chehab 		*snr = 0xffff;
770*9a0bf528SMauro Carvalho Chehab 	else
771*9a0bf528SMauro Carvalho Chehab 		*snr = snr_tab[(snr_reading & 0xf0) >> 4] +
772*9a0bf528SMauro Carvalho Chehab 			(snr_tab[(snr_reading & 0x0f)] >> 4);
773*9a0bf528SMauro Carvalho Chehab 
774*9a0bf528SMauro Carvalho Chehab 	dprintk("%s: raw / cooked = 0x%02x / 0x%04x\n", __func__,
775*9a0bf528SMauro Carvalho Chehab 		snr_reading, *snr);
776*9a0bf528SMauro Carvalho Chehab 
777*9a0bf528SMauro Carvalho Chehab 	return 0;
778*9a0bf528SMauro Carvalho Chehab }
779*9a0bf528SMauro Carvalho Chehab 
780*9a0bf528SMauro Carvalho Chehab /* The reelbox patches show the value in the registers represents
781*9a0bf528SMauro Carvalho Chehab  * ESNO, from 0->30db (values 0->300). We provide this value by
782*9a0bf528SMauro Carvalho Chehab  * default.
783*9a0bf528SMauro Carvalho Chehab  */
784*9a0bf528SMauro Carvalho Chehab static int cx24116_read_snr_esno(struct dvb_frontend *fe, u16 *snr)
785*9a0bf528SMauro Carvalho Chehab {
786*9a0bf528SMauro Carvalho Chehab 	struct cx24116_state *state = fe->demodulator_priv;
787*9a0bf528SMauro Carvalho Chehab 
788*9a0bf528SMauro Carvalho Chehab 	dprintk("%s()\n", __func__);
789*9a0bf528SMauro Carvalho Chehab 
790*9a0bf528SMauro Carvalho Chehab 	*snr = cx24116_readreg(state, CX24116_REG_QUALITY8) << 8 |
791*9a0bf528SMauro Carvalho Chehab 		cx24116_readreg(state, CX24116_REG_QUALITY0);
792*9a0bf528SMauro Carvalho Chehab 
793*9a0bf528SMauro Carvalho Chehab 	dprintk("%s: raw 0x%04x\n", __func__, *snr);
794*9a0bf528SMauro Carvalho Chehab 
795*9a0bf528SMauro Carvalho Chehab 	return 0;
796*9a0bf528SMauro Carvalho Chehab }
797*9a0bf528SMauro Carvalho Chehab 
798*9a0bf528SMauro Carvalho Chehab static int cx24116_read_snr(struct dvb_frontend *fe, u16 *snr)
799*9a0bf528SMauro Carvalho Chehab {
800*9a0bf528SMauro Carvalho Chehab 	if (esno_snr == 1)
801*9a0bf528SMauro Carvalho Chehab 		return cx24116_read_snr_esno(fe, snr);
802*9a0bf528SMauro Carvalho Chehab 	else
803*9a0bf528SMauro Carvalho Chehab 		return cx24116_read_snr_pct(fe, snr);
804*9a0bf528SMauro Carvalho Chehab }
805*9a0bf528SMauro Carvalho Chehab 
806*9a0bf528SMauro Carvalho Chehab static int cx24116_read_ucblocks(struct dvb_frontend *fe, u32 *ucblocks)
807*9a0bf528SMauro Carvalho Chehab {
808*9a0bf528SMauro Carvalho Chehab 	struct cx24116_state *state = fe->demodulator_priv;
809*9a0bf528SMauro Carvalho Chehab 
810*9a0bf528SMauro Carvalho Chehab 	dprintk("%s()\n", __func__);
811*9a0bf528SMauro Carvalho Chehab 
812*9a0bf528SMauro Carvalho Chehab 	*ucblocks = (cx24116_readreg(state, CX24116_REG_UCB8) << 8) |
813*9a0bf528SMauro Carvalho Chehab 		cx24116_readreg(state, CX24116_REG_UCB0);
814*9a0bf528SMauro Carvalho Chehab 
815*9a0bf528SMauro Carvalho Chehab 	return 0;
816*9a0bf528SMauro Carvalho Chehab }
817*9a0bf528SMauro Carvalho Chehab 
818*9a0bf528SMauro Carvalho Chehab /* Overwrite the current tuning params, we are about to tune */
819*9a0bf528SMauro Carvalho Chehab static void cx24116_clone_params(struct dvb_frontend *fe)
820*9a0bf528SMauro Carvalho Chehab {
821*9a0bf528SMauro Carvalho Chehab 	struct cx24116_state *state = fe->demodulator_priv;
822*9a0bf528SMauro Carvalho Chehab 	memcpy(&state->dcur, &state->dnxt, sizeof(state->dcur));
823*9a0bf528SMauro Carvalho Chehab }
824*9a0bf528SMauro Carvalho Chehab 
825*9a0bf528SMauro Carvalho Chehab /* Wait for LNB */
826*9a0bf528SMauro Carvalho Chehab static int cx24116_wait_for_lnb(struct dvb_frontend *fe)
827*9a0bf528SMauro Carvalho Chehab {
828*9a0bf528SMauro Carvalho Chehab 	struct cx24116_state *state = fe->demodulator_priv;
829*9a0bf528SMauro Carvalho Chehab 	int i;
830*9a0bf528SMauro Carvalho Chehab 
831*9a0bf528SMauro Carvalho Chehab 	dprintk("%s() qstatus = 0x%02x\n", __func__,
832*9a0bf528SMauro Carvalho Chehab 		cx24116_readreg(state, CX24116_REG_QSTATUS));
833*9a0bf528SMauro Carvalho Chehab 
834*9a0bf528SMauro Carvalho Chehab 	/* Wait for up to 300 ms */
835*9a0bf528SMauro Carvalho Chehab 	for (i = 0; i < 30 ; i++) {
836*9a0bf528SMauro Carvalho Chehab 		if (cx24116_readreg(state, CX24116_REG_QSTATUS) & 0x20)
837*9a0bf528SMauro Carvalho Chehab 			return 0;
838*9a0bf528SMauro Carvalho Chehab 		msleep(10);
839*9a0bf528SMauro Carvalho Chehab 	}
840*9a0bf528SMauro Carvalho Chehab 
841*9a0bf528SMauro Carvalho Chehab 	dprintk("%s(): LNB not ready\n", __func__);
842*9a0bf528SMauro Carvalho Chehab 
843*9a0bf528SMauro Carvalho Chehab 	return -ETIMEDOUT; /* -EBUSY ? */
844*9a0bf528SMauro Carvalho Chehab }
845*9a0bf528SMauro Carvalho Chehab 
846*9a0bf528SMauro Carvalho Chehab static int cx24116_set_voltage(struct dvb_frontend *fe,
847*9a0bf528SMauro Carvalho Chehab 	fe_sec_voltage_t voltage)
848*9a0bf528SMauro Carvalho Chehab {
849*9a0bf528SMauro Carvalho Chehab 	struct cx24116_cmd cmd;
850*9a0bf528SMauro Carvalho Chehab 	int ret;
851*9a0bf528SMauro Carvalho Chehab 
852*9a0bf528SMauro Carvalho Chehab 	dprintk("%s: %s\n", __func__,
853*9a0bf528SMauro Carvalho Chehab 		voltage == SEC_VOLTAGE_13 ? "SEC_VOLTAGE_13" :
854*9a0bf528SMauro Carvalho Chehab 		voltage == SEC_VOLTAGE_18 ? "SEC_VOLTAGE_18" : "??");
855*9a0bf528SMauro Carvalho Chehab 
856*9a0bf528SMauro Carvalho Chehab 	/* Wait for LNB ready */
857*9a0bf528SMauro Carvalho Chehab 	ret = cx24116_wait_for_lnb(fe);
858*9a0bf528SMauro Carvalho Chehab 	if (ret != 0)
859*9a0bf528SMauro Carvalho Chehab 		return ret;
860*9a0bf528SMauro Carvalho Chehab 
861*9a0bf528SMauro Carvalho Chehab 	/* Wait for voltage/min repeat delay */
862*9a0bf528SMauro Carvalho Chehab 	msleep(100);
863*9a0bf528SMauro Carvalho Chehab 
864*9a0bf528SMauro Carvalho Chehab 	cmd.args[0x00] = CMD_LNBDCLEVEL;
865*9a0bf528SMauro Carvalho Chehab 	cmd.args[0x01] = (voltage == SEC_VOLTAGE_18 ? 0x01 : 0x00);
866*9a0bf528SMauro Carvalho Chehab 	cmd.len = 0x02;
867*9a0bf528SMauro Carvalho Chehab 
868*9a0bf528SMauro Carvalho Chehab 	/* Min delay time before DiSEqC send */
869*9a0bf528SMauro Carvalho Chehab 	msleep(15);
870*9a0bf528SMauro Carvalho Chehab 
871*9a0bf528SMauro Carvalho Chehab 	return cx24116_cmd_execute(fe, &cmd);
872*9a0bf528SMauro Carvalho Chehab }
873*9a0bf528SMauro Carvalho Chehab 
874*9a0bf528SMauro Carvalho Chehab static int cx24116_set_tone(struct dvb_frontend *fe,
875*9a0bf528SMauro Carvalho Chehab 	fe_sec_tone_mode_t tone)
876*9a0bf528SMauro Carvalho Chehab {
877*9a0bf528SMauro Carvalho Chehab 	struct cx24116_cmd cmd;
878*9a0bf528SMauro Carvalho Chehab 	int ret;
879*9a0bf528SMauro Carvalho Chehab 
880*9a0bf528SMauro Carvalho Chehab 	dprintk("%s(%d)\n", __func__, tone);
881*9a0bf528SMauro Carvalho Chehab 	if ((tone != SEC_TONE_ON) && (tone != SEC_TONE_OFF)) {
882*9a0bf528SMauro Carvalho Chehab 		printk(KERN_ERR "%s: Invalid, tone=%d\n", __func__, tone);
883*9a0bf528SMauro Carvalho Chehab 		return -EINVAL;
884*9a0bf528SMauro Carvalho Chehab 	}
885*9a0bf528SMauro Carvalho Chehab 
886*9a0bf528SMauro Carvalho Chehab 	/* Wait for LNB ready */
887*9a0bf528SMauro Carvalho Chehab 	ret = cx24116_wait_for_lnb(fe);
888*9a0bf528SMauro Carvalho Chehab 	if (ret != 0)
889*9a0bf528SMauro Carvalho Chehab 		return ret;
890*9a0bf528SMauro Carvalho Chehab 
891*9a0bf528SMauro Carvalho Chehab 	/* Min delay time after DiSEqC send */
892*9a0bf528SMauro Carvalho Chehab 	msleep(15); /* XXX determine is FW does this, see send_diseqc/burst */
893*9a0bf528SMauro Carvalho Chehab 
894*9a0bf528SMauro Carvalho Chehab 	/* Now we set the tone */
895*9a0bf528SMauro Carvalho Chehab 	cmd.args[0x00] = CMD_SET_TONE;
896*9a0bf528SMauro Carvalho Chehab 	cmd.args[0x01] = 0x00;
897*9a0bf528SMauro Carvalho Chehab 	cmd.args[0x02] = 0x00;
898*9a0bf528SMauro Carvalho Chehab 
899*9a0bf528SMauro Carvalho Chehab 	switch (tone) {
900*9a0bf528SMauro Carvalho Chehab 	case SEC_TONE_ON:
901*9a0bf528SMauro Carvalho Chehab 		dprintk("%s: setting tone on\n", __func__);
902*9a0bf528SMauro Carvalho Chehab 		cmd.args[0x03] = 0x01;
903*9a0bf528SMauro Carvalho Chehab 		break;
904*9a0bf528SMauro Carvalho Chehab 	case SEC_TONE_OFF:
905*9a0bf528SMauro Carvalho Chehab 		dprintk("%s: setting tone off\n", __func__);
906*9a0bf528SMauro Carvalho Chehab 		cmd.args[0x03] = 0x00;
907*9a0bf528SMauro Carvalho Chehab 		break;
908*9a0bf528SMauro Carvalho Chehab 	}
909*9a0bf528SMauro Carvalho Chehab 	cmd.len = 0x04;
910*9a0bf528SMauro Carvalho Chehab 
911*9a0bf528SMauro Carvalho Chehab 	/* Min delay time before DiSEqC send */
912*9a0bf528SMauro Carvalho Chehab 	msleep(15); /* XXX determine is FW does this, see send_diseqc/burst */
913*9a0bf528SMauro Carvalho Chehab 
914*9a0bf528SMauro Carvalho Chehab 	return cx24116_cmd_execute(fe, &cmd);
915*9a0bf528SMauro Carvalho Chehab }
916*9a0bf528SMauro Carvalho Chehab 
917*9a0bf528SMauro Carvalho Chehab /* Initialise DiSEqC */
918*9a0bf528SMauro Carvalho Chehab static int cx24116_diseqc_init(struct dvb_frontend *fe)
919*9a0bf528SMauro Carvalho Chehab {
920*9a0bf528SMauro Carvalho Chehab 	struct cx24116_state *state = fe->demodulator_priv;
921*9a0bf528SMauro Carvalho Chehab 	struct cx24116_cmd cmd;
922*9a0bf528SMauro Carvalho Chehab 	int ret;
923*9a0bf528SMauro Carvalho Chehab 
924*9a0bf528SMauro Carvalho Chehab 	/* Firmware CMD 20: LNB/DiSEqC config */
925*9a0bf528SMauro Carvalho Chehab 	cmd.args[0x00] = CMD_LNBCONFIG;
926*9a0bf528SMauro Carvalho Chehab 	cmd.args[0x01] = 0x00;
927*9a0bf528SMauro Carvalho Chehab 	cmd.args[0x02] = 0x10;
928*9a0bf528SMauro Carvalho Chehab 	cmd.args[0x03] = 0x00;
929*9a0bf528SMauro Carvalho Chehab 	cmd.args[0x04] = 0x8f;
930*9a0bf528SMauro Carvalho Chehab 	cmd.args[0x05] = 0x28;
931*9a0bf528SMauro Carvalho Chehab 	cmd.args[0x06] = (toneburst == CX24116_DISEQC_TONEOFF) ? 0x00 : 0x01;
932*9a0bf528SMauro Carvalho Chehab 	cmd.args[0x07] = 0x01;
933*9a0bf528SMauro Carvalho Chehab 	cmd.len = 0x08;
934*9a0bf528SMauro Carvalho Chehab 	ret = cx24116_cmd_execute(fe, &cmd);
935*9a0bf528SMauro Carvalho Chehab 	if (ret != 0)
936*9a0bf528SMauro Carvalho Chehab 		return ret;
937*9a0bf528SMauro Carvalho Chehab 
938*9a0bf528SMauro Carvalho Chehab 	/* Prepare a DiSEqC command */
939*9a0bf528SMauro Carvalho Chehab 	state->dsec_cmd.args[0x00] = CMD_LNBSEND;
940*9a0bf528SMauro Carvalho Chehab 
941*9a0bf528SMauro Carvalho Chehab 	/* DiSEqC burst */
942*9a0bf528SMauro Carvalho Chehab 	state->dsec_cmd.args[CX24116_DISEQC_BURST]  = CX24116_DISEQC_MINI_A;
943*9a0bf528SMauro Carvalho Chehab 
944*9a0bf528SMauro Carvalho Chehab 	/* Unknown */
945*9a0bf528SMauro Carvalho Chehab 	state->dsec_cmd.args[CX24116_DISEQC_ARG2_2] = 0x02;
946*9a0bf528SMauro Carvalho Chehab 	state->dsec_cmd.args[CX24116_DISEQC_ARG3_0] = 0x00;
947*9a0bf528SMauro Carvalho Chehab 	/* Continuation flag? */
948*9a0bf528SMauro Carvalho Chehab 	state->dsec_cmd.args[CX24116_DISEQC_ARG4_0] = 0x00;
949*9a0bf528SMauro Carvalho Chehab 
950*9a0bf528SMauro Carvalho Chehab 	/* DiSEqC message length */
951*9a0bf528SMauro Carvalho Chehab 	state->dsec_cmd.args[CX24116_DISEQC_MSGLEN] = 0x00;
952*9a0bf528SMauro Carvalho Chehab 
953*9a0bf528SMauro Carvalho Chehab 	/* Command length */
954*9a0bf528SMauro Carvalho Chehab 	state->dsec_cmd.len = CX24116_DISEQC_MSGOFS;
955*9a0bf528SMauro Carvalho Chehab 
956*9a0bf528SMauro Carvalho Chehab 	return 0;
957*9a0bf528SMauro Carvalho Chehab }
958*9a0bf528SMauro Carvalho Chehab 
959*9a0bf528SMauro Carvalho Chehab /* Send DiSEqC message with derived burst (hack) || previous burst */
960*9a0bf528SMauro Carvalho Chehab static int cx24116_send_diseqc_msg(struct dvb_frontend *fe,
961*9a0bf528SMauro Carvalho Chehab 	struct dvb_diseqc_master_cmd *d)
962*9a0bf528SMauro Carvalho Chehab {
963*9a0bf528SMauro Carvalho Chehab 	struct cx24116_state *state = fe->demodulator_priv;
964*9a0bf528SMauro Carvalho Chehab 	int i, ret;
965*9a0bf528SMauro Carvalho Chehab 
966*9a0bf528SMauro Carvalho Chehab 	/* Dump DiSEqC message */
967*9a0bf528SMauro Carvalho Chehab 	if (debug) {
968*9a0bf528SMauro Carvalho Chehab 		printk(KERN_INFO "cx24116: %s(", __func__);
969*9a0bf528SMauro Carvalho Chehab 		for (i = 0 ; i < d->msg_len ;) {
970*9a0bf528SMauro Carvalho Chehab 			printk(KERN_INFO "0x%02x", d->msg[i]);
971*9a0bf528SMauro Carvalho Chehab 			if (++i < d->msg_len)
972*9a0bf528SMauro Carvalho Chehab 				printk(KERN_INFO ", ");
973*9a0bf528SMauro Carvalho Chehab 		}
974*9a0bf528SMauro Carvalho Chehab 		printk(") toneburst=%d\n", toneburst);
975*9a0bf528SMauro Carvalho Chehab 	}
976*9a0bf528SMauro Carvalho Chehab 
977*9a0bf528SMauro Carvalho Chehab 	/* Validate length */
978*9a0bf528SMauro Carvalho Chehab 	if (d->msg_len > (CX24116_ARGLEN - CX24116_DISEQC_MSGOFS))
979*9a0bf528SMauro Carvalho Chehab 		return -EINVAL;
980*9a0bf528SMauro Carvalho Chehab 
981*9a0bf528SMauro Carvalho Chehab 	/* DiSEqC message */
982*9a0bf528SMauro Carvalho Chehab 	for (i = 0; i < d->msg_len; i++)
983*9a0bf528SMauro Carvalho Chehab 		state->dsec_cmd.args[CX24116_DISEQC_MSGOFS + i] = d->msg[i];
984*9a0bf528SMauro Carvalho Chehab 
985*9a0bf528SMauro Carvalho Chehab 	/* DiSEqC message length */
986*9a0bf528SMauro Carvalho Chehab 	state->dsec_cmd.args[CX24116_DISEQC_MSGLEN] = d->msg_len;
987*9a0bf528SMauro Carvalho Chehab 
988*9a0bf528SMauro Carvalho Chehab 	/* Command length */
989*9a0bf528SMauro Carvalho Chehab 	state->dsec_cmd.len = CX24116_DISEQC_MSGOFS +
990*9a0bf528SMauro Carvalho Chehab 		state->dsec_cmd.args[CX24116_DISEQC_MSGLEN];
991*9a0bf528SMauro Carvalho Chehab 
992*9a0bf528SMauro Carvalho Chehab 	/* DiSEqC toneburst */
993*9a0bf528SMauro Carvalho Chehab 	if (toneburst == CX24116_DISEQC_MESGCACHE)
994*9a0bf528SMauro Carvalho Chehab 		/* Message is cached */
995*9a0bf528SMauro Carvalho Chehab 		return 0;
996*9a0bf528SMauro Carvalho Chehab 
997*9a0bf528SMauro Carvalho Chehab 	else if (toneburst == CX24116_DISEQC_TONEOFF)
998*9a0bf528SMauro Carvalho Chehab 		/* Message is sent without burst */
999*9a0bf528SMauro Carvalho Chehab 		state->dsec_cmd.args[CX24116_DISEQC_BURST] = 0;
1000*9a0bf528SMauro Carvalho Chehab 
1001*9a0bf528SMauro Carvalho Chehab 	else if (toneburst == CX24116_DISEQC_TONECACHE) {
1002*9a0bf528SMauro Carvalho Chehab 		/*
1003*9a0bf528SMauro Carvalho Chehab 		 * Message is sent with derived else cached burst
1004*9a0bf528SMauro Carvalho Chehab 		 *
1005*9a0bf528SMauro Carvalho Chehab 		 * WRITE PORT GROUP COMMAND 38
1006*9a0bf528SMauro Carvalho Chehab 		 *
1007*9a0bf528SMauro Carvalho Chehab 		 * 0/A/A: E0 10 38 F0..F3
1008*9a0bf528SMauro Carvalho Chehab 		 * 1/B/B: E0 10 38 F4..F7
1009*9a0bf528SMauro Carvalho Chehab 		 * 2/C/A: E0 10 38 F8..FB
1010*9a0bf528SMauro Carvalho Chehab 		 * 3/D/B: E0 10 38 FC..FF
1011*9a0bf528SMauro Carvalho Chehab 		 *
1012*9a0bf528SMauro Carvalho Chehab 		 * databyte[3]= 8421:8421
1013*9a0bf528SMauro Carvalho Chehab 		 *              ABCD:WXYZ
1014*9a0bf528SMauro Carvalho Chehab 		 *              CLR :SET
1015*9a0bf528SMauro Carvalho Chehab 		 *
1016*9a0bf528SMauro Carvalho Chehab 		 *              WX= PORT SELECT 0..3    (X=TONEBURST)
1017*9a0bf528SMauro Carvalho Chehab 		 *              Y = VOLTAGE             (0=13V, 1=18V)
1018*9a0bf528SMauro Carvalho Chehab 		 *              Z = BAND                (0=LOW, 1=HIGH(22K))
1019*9a0bf528SMauro Carvalho Chehab 		 */
1020*9a0bf528SMauro Carvalho Chehab 		if (d->msg_len >= 4 && d->msg[2] == 0x38)
1021*9a0bf528SMauro Carvalho Chehab 			state->dsec_cmd.args[CX24116_DISEQC_BURST] =
1022*9a0bf528SMauro Carvalho Chehab 				((d->msg[3] & 4) >> 2);
1023*9a0bf528SMauro Carvalho Chehab 		if (debug)
1024*9a0bf528SMauro Carvalho Chehab 			dprintk("%s burst=%d\n", __func__,
1025*9a0bf528SMauro Carvalho Chehab 				state->dsec_cmd.args[CX24116_DISEQC_BURST]);
1026*9a0bf528SMauro Carvalho Chehab 	}
1027*9a0bf528SMauro Carvalho Chehab 
1028*9a0bf528SMauro Carvalho Chehab 	/* Wait for LNB ready */
1029*9a0bf528SMauro Carvalho Chehab 	ret = cx24116_wait_for_lnb(fe);
1030*9a0bf528SMauro Carvalho Chehab 	if (ret != 0)
1031*9a0bf528SMauro Carvalho Chehab 		return ret;
1032*9a0bf528SMauro Carvalho Chehab 
1033*9a0bf528SMauro Carvalho Chehab 	/* Wait for voltage/min repeat delay */
1034*9a0bf528SMauro Carvalho Chehab 	msleep(100);
1035*9a0bf528SMauro Carvalho Chehab 
1036*9a0bf528SMauro Carvalho Chehab 	/* Command */
1037*9a0bf528SMauro Carvalho Chehab 	ret = cx24116_cmd_execute(fe, &state->dsec_cmd);
1038*9a0bf528SMauro Carvalho Chehab 	if (ret != 0)
1039*9a0bf528SMauro Carvalho Chehab 		return ret;
1040*9a0bf528SMauro Carvalho Chehab 	/*
1041*9a0bf528SMauro Carvalho Chehab 	 * Wait for send
1042*9a0bf528SMauro Carvalho Chehab 	 *
1043*9a0bf528SMauro Carvalho Chehab 	 * Eutelsat spec:
1044*9a0bf528SMauro Carvalho Chehab 	 * >15ms delay          + (XXX determine if FW does this, see set_tone)
1045*9a0bf528SMauro Carvalho Chehab 	 *  13.5ms per byte     +
1046*9a0bf528SMauro Carvalho Chehab 	 * >15ms delay          +
1047*9a0bf528SMauro Carvalho Chehab 	 *  12.5ms burst        +
1048*9a0bf528SMauro Carvalho Chehab 	 * >15ms delay            (XXX determine if FW does this, see set_tone)
1049*9a0bf528SMauro Carvalho Chehab 	 */
1050*9a0bf528SMauro Carvalho Chehab 	msleep((state->dsec_cmd.args[CX24116_DISEQC_MSGLEN] << 4) +
1051*9a0bf528SMauro Carvalho Chehab 		((toneburst == CX24116_DISEQC_TONEOFF) ? 30 : 60));
1052*9a0bf528SMauro Carvalho Chehab 
1053*9a0bf528SMauro Carvalho Chehab 	return 0;
1054*9a0bf528SMauro Carvalho Chehab }
1055*9a0bf528SMauro Carvalho Chehab 
1056*9a0bf528SMauro Carvalho Chehab /* Send DiSEqC burst */
1057*9a0bf528SMauro Carvalho Chehab static int cx24116_diseqc_send_burst(struct dvb_frontend *fe,
1058*9a0bf528SMauro Carvalho Chehab 	fe_sec_mini_cmd_t burst)
1059*9a0bf528SMauro Carvalho Chehab {
1060*9a0bf528SMauro Carvalho Chehab 	struct cx24116_state *state = fe->demodulator_priv;
1061*9a0bf528SMauro Carvalho Chehab 	int ret;
1062*9a0bf528SMauro Carvalho Chehab 
1063*9a0bf528SMauro Carvalho Chehab 	dprintk("%s(%d) toneburst=%d\n", __func__, burst, toneburst);
1064*9a0bf528SMauro Carvalho Chehab 
1065*9a0bf528SMauro Carvalho Chehab 	/* DiSEqC burst */
1066*9a0bf528SMauro Carvalho Chehab 	if (burst == SEC_MINI_A)
1067*9a0bf528SMauro Carvalho Chehab 		state->dsec_cmd.args[CX24116_DISEQC_BURST] =
1068*9a0bf528SMauro Carvalho Chehab 			CX24116_DISEQC_MINI_A;
1069*9a0bf528SMauro Carvalho Chehab 	else if (burst == SEC_MINI_B)
1070*9a0bf528SMauro Carvalho Chehab 		state->dsec_cmd.args[CX24116_DISEQC_BURST] =
1071*9a0bf528SMauro Carvalho Chehab 			CX24116_DISEQC_MINI_B;
1072*9a0bf528SMauro Carvalho Chehab 	else
1073*9a0bf528SMauro Carvalho Chehab 		return -EINVAL;
1074*9a0bf528SMauro Carvalho Chehab 
1075*9a0bf528SMauro Carvalho Chehab 	/* DiSEqC toneburst */
1076*9a0bf528SMauro Carvalho Chehab 	if (toneburst != CX24116_DISEQC_MESGCACHE)
1077*9a0bf528SMauro Carvalho Chehab 		/* Burst is cached */
1078*9a0bf528SMauro Carvalho Chehab 		return 0;
1079*9a0bf528SMauro Carvalho Chehab 
1080*9a0bf528SMauro Carvalho Chehab 	/* Burst is to be sent with cached message */
1081*9a0bf528SMauro Carvalho Chehab 
1082*9a0bf528SMauro Carvalho Chehab 	/* Wait for LNB ready */
1083*9a0bf528SMauro Carvalho Chehab 	ret = cx24116_wait_for_lnb(fe);
1084*9a0bf528SMauro Carvalho Chehab 	if (ret != 0)
1085*9a0bf528SMauro Carvalho Chehab 		return ret;
1086*9a0bf528SMauro Carvalho Chehab 
1087*9a0bf528SMauro Carvalho Chehab 	/* Wait for voltage/min repeat delay */
1088*9a0bf528SMauro Carvalho Chehab 	msleep(100);
1089*9a0bf528SMauro Carvalho Chehab 
1090*9a0bf528SMauro Carvalho Chehab 	/* Command */
1091*9a0bf528SMauro Carvalho Chehab 	ret = cx24116_cmd_execute(fe, &state->dsec_cmd);
1092*9a0bf528SMauro Carvalho Chehab 	if (ret != 0)
1093*9a0bf528SMauro Carvalho Chehab 		return ret;
1094*9a0bf528SMauro Carvalho Chehab 
1095*9a0bf528SMauro Carvalho Chehab 	/*
1096*9a0bf528SMauro Carvalho Chehab 	 * Wait for send
1097*9a0bf528SMauro Carvalho Chehab 	 *
1098*9a0bf528SMauro Carvalho Chehab 	 * Eutelsat spec:
1099*9a0bf528SMauro Carvalho Chehab 	 * >15ms delay          + (XXX determine if FW does this, see set_tone)
1100*9a0bf528SMauro Carvalho Chehab 	 *  13.5ms per byte     +
1101*9a0bf528SMauro Carvalho Chehab 	 * >15ms delay          +
1102*9a0bf528SMauro Carvalho Chehab 	 *  12.5ms burst        +
1103*9a0bf528SMauro Carvalho Chehab 	 * >15ms delay            (XXX determine if FW does this, see set_tone)
1104*9a0bf528SMauro Carvalho Chehab 	 */
1105*9a0bf528SMauro Carvalho Chehab 	msleep((state->dsec_cmd.args[CX24116_DISEQC_MSGLEN] << 4) + 60);
1106*9a0bf528SMauro Carvalho Chehab 
1107*9a0bf528SMauro Carvalho Chehab 	return 0;
1108*9a0bf528SMauro Carvalho Chehab }
1109*9a0bf528SMauro Carvalho Chehab 
1110*9a0bf528SMauro Carvalho Chehab static void cx24116_release(struct dvb_frontend *fe)
1111*9a0bf528SMauro Carvalho Chehab {
1112*9a0bf528SMauro Carvalho Chehab 	struct cx24116_state *state = fe->demodulator_priv;
1113*9a0bf528SMauro Carvalho Chehab 	dprintk("%s\n", __func__);
1114*9a0bf528SMauro Carvalho Chehab 	kfree(state);
1115*9a0bf528SMauro Carvalho Chehab }
1116*9a0bf528SMauro Carvalho Chehab 
1117*9a0bf528SMauro Carvalho Chehab static struct dvb_frontend_ops cx24116_ops;
1118*9a0bf528SMauro Carvalho Chehab 
1119*9a0bf528SMauro Carvalho Chehab struct dvb_frontend *cx24116_attach(const struct cx24116_config *config,
1120*9a0bf528SMauro Carvalho Chehab 	struct i2c_adapter *i2c)
1121*9a0bf528SMauro Carvalho Chehab {
1122*9a0bf528SMauro Carvalho Chehab 	struct cx24116_state *state = NULL;
1123*9a0bf528SMauro Carvalho Chehab 	int ret;
1124*9a0bf528SMauro Carvalho Chehab 
1125*9a0bf528SMauro Carvalho Chehab 	dprintk("%s\n", __func__);
1126*9a0bf528SMauro Carvalho Chehab 
1127*9a0bf528SMauro Carvalho Chehab 	/* allocate memory for the internal state */
1128*9a0bf528SMauro Carvalho Chehab 	state = kzalloc(sizeof(struct cx24116_state), GFP_KERNEL);
1129*9a0bf528SMauro Carvalho Chehab 	if (state == NULL)
1130*9a0bf528SMauro Carvalho Chehab 		goto error1;
1131*9a0bf528SMauro Carvalho Chehab 
1132*9a0bf528SMauro Carvalho Chehab 	state->config = config;
1133*9a0bf528SMauro Carvalho Chehab 	state->i2c = i2c;
1134*9a0bf528SMauro Carvalho Chehab 
1135*9a0bf528SMauro Carvalho Chehab 	/* check if the demod is present */
1136*9a0bf528SMauro Carvalho Chehab 	ret = (cx24116_readreg(state, 0xFF) << 8) |
1137*9a0bf528SMauro Carvalho Chehab 		cx24116_readreg(state, 0xFE);
1138*9a0bf528SMauro Carvalho Chehab 	if (ret != 0x0501) {
1139*9a0bf528SMauro Carvalho Chehab 		printk(KERN_INFO "Invalid probe, probably not a CX24116 device\n");
1140*9a0bf528SMauro Carvalho Chehab 		goto error2;
1141*9a0bf528SMauro Carvalho Chehab 	}
1142*9a0bf528SMauro Carvalho Chehab 
1143*9a0bf528SMauro Carvalho Chehab 	/* create dvb_frontend */
1144*9a0bf528SMauro Carvalho Chehab 	memcpy(&state->frontend.ops, &cx24116_ops,
1145*9a0bf528SMauro Carvalho Chehab 		sizeof(struct dvb_frontend_ops));
1146*9a0bf528SMauro Carvalho Chehab 	state->frontend.demodulator_priv = state;
1147*9a0bf528SMauro Carvalho Chehab 	return &state->frontend;
1148*9a0bf528SMauro Carvalho Chehab 
1149*9a0bf528SMauro Carvalho Chehab error2: kfree(state);
1150*9a0bf528SMauro Carvalho Chehab error1: return NULL;
1151*9a0bf528SMauro Carvalho Chehab }
1152*9a0bf528SMauro Carvalho Chehab EXPORT_SYMBOL(cx24116_attach);
1153*9a0bf528SMauro Carvalho Chehab 
1154*9a0bf528SMauro Carvalho Chehab /*
1155*9a0bf528SMauro Carvalho Chehab  * Initialise or wake up device
1156*9a0bf528SMauro Carvalho Chehab  *
1157*9a0bf528SMauro Carvalho Chehab  * Power config will reset and load initial firmware if required
1158*9a0bf528SMauro Carvalho Chehab  */
1159*9a0bf528SMauro Carvalho Chehab static int cx24116_initfe(struct dvb_frontend *fe)
1160*9a0bf528SMauro Carvalho Chehab {
1161*9a0bf528SMauro Carvalho Chehab 	struct cx24116_state *state = fe->demodulator_priv;
1162*9a0bf528SMauro Carvalho Chehab 	struct cx24116_cmd cmd;
1163*9a0bf528SMauro Carvalho Chehab 	int ret;
1164*9a0bf528SMauro Carvalho Chehab 
1165*9a0bf528SMauro Carvalho Chehab 	dprintk("%s()\n", __func__);
1166*9a0bf528SMauro Carvalho Chehab 
1167*9a0bf528SMauro Carvalho Chehab 	/* Power on */
1168*9a0bf528SMauro Carvalho Chehab 	cx24116_writereg(state, 0xe0, 0);
1169*9a0bf528SMauro Carvalho Chehab 	cx24116_writereg(state, 0xe1, 0);
1170*9a0bf528SMauro Carvalho Chehab 	cx24116_writereg(state, 0xea, 0);
1171*9a0bf528SMauro Carvalho Chehab 
1172*9a0bf528SMauro Carvalho Chehab 	/* Firmware CMD 36: Power config */
1173*9a0bf528SMauro Carvalho Chehab 	cmd.args[0x00] = CMD_TUNERSLEEP;
1174*9a0bf528SMauro Carvalho Chehab 	cmd.args[0x01] = 0;
1175*9a0bf528SMauro Carvalho Chehab 	cmd.len = 0x02;
1176*9a0bf528SMauro Carvalho Chehab 	ret = cx24116_cmd_execute(fe, &cmd);
1177*9a0bf528SMauro Carvalho Chehab 	if (ret != 0)
1178*9a0bf528SMauro Carvalho Chehab 		return ret;
1179*9a0bf528SMauro Carvalho Chehab 
1180*9a0bf528SMauro Carvalho Chehab 	ret = cx24116_diseqc_init(fe);
1181*9a0bf528SMauro Carvalho Chehab 	if (ret != 0)
1182*9a0bf528SMauro Carvalho Chehab 		return ret;
1183*9a0bf528SMauro Carvalho Chehab 
1184*9a0bf528SMauro Carvalho Chehab 	/* HVR-4000 needs this */
1185*9a0bf528SMauro Carvalho Chehab 	return cx24116_set_voltage(fe, SEC_VOLTAGE_13);
1186*9a0bf528SMauro Carvalho Chehab }
1187*9a0bf528SMauro Carvalho Chehab 
1188*9a0bf528SMauro Carvalho Chehab /*
1189*9a0bf528SMauro Carvalho Chehab  * Put device to sleep
1190*9a0bf528SMauro Carvalho Chehab  */
1191*9a0bf528SMauro Carvalho Chehab static int cx24116_sleep(struct dvb_frontend *fe)
1192*9a0bf528SMauro Carvalho Chehab {
1193*9a0bf528SMauro Carvalho Chehab 	struct cx24116_state *state = fe->demodulator_priv;
1194*9a0bf528SMauro Carvalho Chehab 	struct cx24116_cmd cmd;
1195*9a0bf528SMauro Carvalho Chehab 	int ret;
1196*9a0bf528SMauro Carvalho Chehab 
1197*9a0bf528SMauro Carvalho Chehab 	dprintk("%s()\n", __func__);
1198*9a0bf528SMauro Carvalho Chehab 
1199*9a0bf528SMauro Carvalho Chehab 	/* Firmware CMD 36: Power config */
1200*9a0bf528SMauro Carvalho Chehab 	cmd.args[0x00] = CMD_TUNERSLEEP;
1201*9a0bf528SMauro Carvalho Chehab 	cmd.args[0x01] = 1;
1202*9a0bf528SMauro Carvalho Chehab 	cmd.len = 0x02;
1203*9a0bf528SMauro Carvalho Chehab 	ret = cx24116_cmd_execute(fe, &cmd);
1204*9a0bf528SMauro Carvalho Chehab 	if (ret != 0)
1205*9a0bf528SMauro Carvalho Chehab 		return ret;
1206*9a0bf528SMauro Carvalho Chehab 
1207*9a0bf528SMauro Carvalho Chehab 	/* Power off (Shutdown clocks) */
1208*9a0bf528SMauro Carvalho Chehab 	cx24116_writereg(state, 0xea, 0xff);
1209*9a0bf528SMauro Carvalho Chehab 	cx24116_writereg(state, 0xe1, 1);
1210*9a0bf528SMauro Carvalho Chehab 	cx24116_writereg(state, 0xe0, 1);
1211*9a0bf528SMauro Carvalho Chehab 
1212*9a0bf528SMauro Carvalho Chehab 	return 0;
1213*9a0bf528SMauro Carvalho Chehab }
1214*9a0bf528SMauro Carvalho Chehab 
1215*9a0bf528SMauro Carvalho Chehab /* dvb-core told us to tune, the tv property cache will be complete,
1216*9a0bf528SMauro Carvalho Chehab  * it's safe for is to pull values and use them for tuning purposes.
1217*9a0bf528SMauro Carvalho Chehab  */
1218*9a0bf528SMauro Carvalho Chehab static int cx24116_set_frontend(struct dvb_frontend *fe)
1219*9a0bf528SMauro Carvalho Chehab {
1220*9a0bf528SMauro Carvalho Chehab 	struct cx24116_state *state = fe->demodulator_priv;
1221*9a0bf528SMauro Carvalho Chehab 	struct dtv_frontend_properties *c = &fe->dtv_property_cache;
1222*9a0bf528SMauro Carvalho Chehab 	struct cx24116_cmd cmd;
1223*9a0bf528SMauro Carvalho Chehab 	fe_status_t tunerstat;
1224*9a0bf528SMauro Carvalho Chehab 	int i, status, ret, retune = 1;
1225*9a0bf528SMauro Carvalho Chehab 
1226*9a0bf528SMauro Carvalho Chehab 	dprintk("%s()\n", __func__);
1227*9a0bf528SMauro Carvalho Chehab 
1228*9a0bf528SMauro Carvalho Chehab 	switch (c->delivery_system) {
1229*9a0bf528SMauro Carvalho Chehab 	case SYS_DVBS:
1230*9a0bf528SMauro Carvalho Chehab 		dprintk("%s: DVB-S delivery system selected\n", __func__);
1231*9a0bf528SMauro Carvalho Chehab 
1232*9a0bf528SMauro Carvalho Chehab 		/* Only QPSK is supported for DVB-S */
1233*9a0bf528SMauro Carvalho Chehab 		if (c->modulation != QPSK) {
1234*9a0bf528SMauro Carvalho Chehab 			dprintk("%s: unsupported modulation selected (%d)\n",
1235*9a0bf528SMauro Carvalho Chehab 				__func__, c->modulation);
1236*9a0bf528SMauro Carvalho Chehab 			return -EOPNOTSUPP;
1237*9a0bf528SMauro Carvalho Chehab 		}
1238*9a0bf528SMauro Carvalho Chehab 
1239*9a0bf528SMauro Carvalho Chehab 		/* Pilot doesn't exist in DVB-S, turn bit off */
1240*9a0bf528SMauro Carvalho Chehab 		state->dnxt.pilot_val = CX24116_PILOT_OFF;
1241*9a0bf528SMauro Carvalho Chehab 
1242*9a0bf528SMauro Carvalho Chehab 		/* DVB-S only supports 0.35 */
1243*9a0bf528SMauro Carvalho Chehab 		if (c->rolloff != ROLLOFF_35) {
1244*9a0bf528SMauro Carvalho Chehab 			dprintk("%s: unsupported rolloff selected (%d)\n",
1245*9a0bf528SMauro Carvalho Chehab 				__func__, c->rolloff);
1246*9a0bf528SMauro Carvalho Chehab 			return -EOPNOTSUPP;
1247*9a0bf528SMauro Carvalho Chehab 		}
1248*9a0bf528SMauro Carvalho Chehab 		state->dnxt.rolloff_val = CX24116_ROLLOFF_035;
1249*9a0bf528SMauro Carvalho Chehab 		break;
1250*9a0bf528SMauro Carvalho Chehab 
1251*9a0bf528SMauro Carvalho Chehab 	case SYS_DVBS2:
1252*9a0bf528SMauro Carvalho Chehab 		dprintk("%s: DVB-S2 delivery system selected\n", __func__);
1253*9a0bf528SMauro Carvalho Chehab 
1254*9a0bf528SMauro Carvalho Chehab 		/*
1255*9a0bf528SMauro Carvalho Chehab 		 * NBC 8PSK/QPSK with DVB-S is supported for DVB-S2,
1256*9a0bf528SMauro Carvalho Chehab 		 * but not hardware auto detection
1257*9a0bf528SMauro Carvalho Chehab 		 */
1258*9a0bf528SMauro Carvalho Chehab 		if (c->modulation != PSK_8 && c->modulation != QPSK) {
1259*9a0bf528SMauro Carvalho Chehab 			dprintk("%s: unsupported modulation selected (%d)\n",
1260*9a0bf528SMauro Carvalho Chehab 				__func__, c->modulation);
1261*9a0bf528SMauro Carvalho Chehab 			return -EOPNOTSUPP;
1262*9a0bf528SMauro Carvalho Chehab 		}
1263*9a0bf528SMauro Carvalho Chehab 
1264*9a0bf528SMauro Carvalho Chehab 		switch (c->pilot) {
1265*9a0bf528SMauro Carvalho Chehab 		case PILOT_AUTO:	/* Not supported but emulated */
1266*9a0bf528SMauro Carvalho Chehab 			state->dnxt.pilot_val = (c->modulation == QPSK)
1267*9a0bf528SMauro Carvalho Chehab 				? CX24116_PILOT_OFF : CX24116_PILOT_ON;
1268*9a0bf528SMauro Carvalho Chehab 			retune++;
1269*9a0bf528SMauro Carvalho Chehab 			break;
1270*9a0bf528SMauro Carvalho Chehab 		case PILOT_OFF:
1271*9a0bf528SMauro Carvalho Chehab 			state->dnxt.pilot_val = CX24116_PILOT_OFF;
1272*9a0bf528SMauro Carvalho Chehab 			break;
1273*9a0bf528SMauro Carvalho Chehab 		case PILOT_ON:
1274*9a0bf528SMauro Carvalho Chehab 			state->dnxt.pilot_val = CX24116_PILOT_ON;
1275*9a0bf528SMauro Carvalho Chehab 			break;
1276*9a0bf528SMauro Carvalho Chehab 		default:
1277*9a0bf528SMauro Carvalho Chehab 			dprintk("%s: unsupported pilot mode selected (%d)\n",
1278*9a0bf528SMauro Carvalho Chehab 				__func__, c->pilot);
1279*9a0bf528SMauro Carvalho Chehab 			return -EOPNOTSUPP;
1280*9a0bf528SMauro Carvalho Chehab 		}
1281*9a0bf528SMauro Carvalho Chehab 
1282*9a0bf528SMauro Carvalho Chehab 		switch (c->rolloff) {
1283*9a0bf528SMauro Carvalho Chehab 		case ROLLOFF_20:
1284*9a0bf528SMauro Carvalho Chehab 			state->dnxt.rolloff_val = CX24116_ROLLOFF_020;
1285*9a0bf528SMauro Carvalho Chehab 			break;
1286*9a0bf528SMauro Carvalho Chehab 		case ROLLOFF_25:
1287*9a0bf528SMauro Carvalho Chehab 			state->dnxt.rolloff_val = CX24116_ROLLOFF_025;
1288*9a0bf528SMauro Carvalho Chehab 			break;
1289*9a0bf528SMauro Carvalho Chehab 		case ROLLOFF_35:
1290*9a0bf528SMauro Carvalho Chehab 			state->dnxt.rolloff_val = CX24116_ROLLOFF_035;
1291*9a0bf528SMauro Carvalho Chehab 			break;
1292*9a0bf528SMauro Carvalho Chehab 		case ROLLOFF_AUTO:	/* Rolloff must be explicit */
1293*9a0bf528SMauro Carvalho Chehab 		default:
1294*9a0bf528SMauro Carvalho Chehab 			dprintk("%s: unsupported rolloff selected (%d)\n",
1295*9a0bf528SMauro Carvalho Chehab 				__func__, c->rolloff);
1296*9a0bf528SMauro Carvalho Chehab 			return -EOPNOTSUPP;
1297*9a0bf528SMauro Carvalho Chehab 		}
1298*9a0bf528SMauro Carvalho Chehab 		break;
1299*9a0bf528SMauro Carvalho Chehab 
1300*9a0bf528SMauro Carvalho Chehab 	default:
1301*9a0bf528SMauro Carvalho Chehab 		dprintk("%s: unsupported delivery system selected (%d)\n",
1302*9a0bf528SMauro Carvalho Chehab 			__func__, c->delivery_system);
1303*9a0bf528SMauro Carvalho Chehab 		return -EOPNOTSUPP;
1304*9a0bf528SMauro Carvalho Chehab 	}
1305*9a0bf528SMauro Carvalho Chehab 	state->dnxt.delsys = c->delivery_system;
1306*9a0bf528SMauro Carvalho Chehab 	state->dnxt.modulation = c->modulation;
1307*9a0bf528SMauro Carvalho Chehab 	state->dnxt.frequency = c->frequency;
1308*9a0bf528SMauro Carvalho Chehab 	state->dnxt.pilot = c->pilot;
1309*9a0bf528SMauro Carvalho Chehab 	state->dnxt.rolloff = c->rolloff;
1310*9a0bf528SMauro Carvalho Chehab 
1311*9a0bf528SMauro Carvalho Chehab 	ret = cx24116_set_inversion(state, c->inversion);
1312*9a0bf528SMauro Carvalho Chehab 	if (ret !=  0)
1313*9a0bf528SMauro Carvalho Chehab 		return ret;
1314*9a0bf528SMauro Carvalho Chehab 
1315*9a0bf528SMauro Carvalho Chehab 	/* FEC_NONE/AUTO for DVB-S2 is not supported and detected here */
1316*9a0bf528SMauro Carvalho Chehab 	ret = cx24116_set_fec(state, c->delivery_system, c->modulation, c->fec_inner);
1317*9a0bf528SMauro Carvalho Chehab 	if (ret !=  0)
1318*9a0bf528SMauro Carvalho Chehab 		return ret;
1319*9a0bf528SMauro Carvalho Chehab 
1320*9a0bf528SMauro Carvalho Chehab 	ret = cx24116_set_symbolrate(state, c->symbol_rate);
1321*9a0bf528SMauro Carvalho Chehab 	if (ret !=  0)
1322*9a0bf528SMauro Carvalho Chehab 		return ret;
1323*9a0bf528SMauro Carvalho Chehab 
1324*9a0bf528SMauro Carvalho Chehab 	/* discard the 'current' tuning parameters and prepare to tune */
1325*9a0bf528SMauro Carvalho Chehab 	cx24116_clone_params(fe);
1326*9a0bf528SMauro Carvalho Chehab 
1327*9a0bf528SMauro Carvalho Chehab 	dprintk("%s:   delsys      = %d\n", __func__, state->dcur.delsys);
1328*9a0bf528SMauro Carvalho Chehab 	dprintk("%s:   modulation  = %d\n", __func__, state->dcur.modulation);
1329*9a0bf528SMauro Carvalho Chehab 	dprintk("%s:   frequency   = %d\n", __func__, state->dcur.frequency);
1330*9a0bf528SMauro Carvalho Chehab 	dprintk("%s:   pilot       = %d (val = 0x%02x)\n", __func__,
1331*9a0bf528SMauro Carvalho Chehab 		state->dcur.pilot, state->dcur.pilot_val);
1332*9a0bf528SMauro Carvalho Chehab 	dprintk("%s:   retune      = %d\n", __func__, retune);
1333*9a0bf528SMauro Carvalho Chehab 	dprintk("%s:   rolloff     = %d (val = 0x%02x)\n", __func__,
1334*9a0bf528SMauro Carvalho Chehab 		state->dcur.rolloff, state->dcur.rolloff_val);
1335*9a0bf528SMauro Carvalho Chehab 	dprintk("%s:   symbol_rate = %d\n", __func__, state->dcur.symbol_rate);
1336*9a0bf528SMauro Carvalho Chehab 	dprintk("%s:   FEC         = %d (mask/val = 0x%02x/0x%02x)\n", __func__,
1337*9a0bf528SMauro Carvalho Chehab 		state->dcur.fec, state->dcur.fec_mask, state->dcur.fec_val);
1338*9a0bf528SMauro Carvalho Chehab 	dprintk("%s:   Inversion   = %d (val = 0x%02x)\n", __func__,
1339*9a0bf528SMauro Carvalho Chehab 		state->dcur.inversion, state->dcur.inversion_val);
1340*9a0bf528SMauro Carvalho Chehab 
1341*9a0bf528SMauro Carvalho Chehab 	/* This is also done in advise/acquire on HVR4000 but not on LITE */
1342*9a0bf528SMauro Carvalho Chehab 	if (state->config->set_ts_params)
1343*9a0bf528SMauro Carvalho Chehab 		state->config->set_ts_params(fe, 0);
1344*9a0bf528SMauro Carvalho Chehab 
1345*9a0bf528SMauro Carvalho Chehab 	/* Set/Reset B/W */
1346*9a0bf528SMauro Carvalho Chehab 	cmd.args[0x00] = CMD_BANDWIDTH;
1347*9a0bf528SMauro Carvalho Chehab 	cmd.args[0x01] = 0x01;
1348*9a0bf528SMauro Carvalho Chehab 	cmd.len = 0x02;
1349*9a0bf528SMauro Carvalho Chehab 	ret = cx24116_cmd_execute(fe, &cmd);
1350*9a0bf528SMauro Carvalho Chehab 	if (ret != 0)
1351*9a0bf528SMauro Carvalho Chehab 		return ret;
1352*9a0bf528SMauro Carvalho Chehab 
1353*9a0bf528SMauro Carvalho Chehab 	/* Prepare a tune request */
1354*9a0bf528SMauro Carvalho Chehab 	cmd.args[0x00] = CMD_TUNEREQUEST;
1355*9a0bf528SMauro Carvalho Chehab 
1356*9a0bf528SMauro Carvalho Chehab 	/* Frequency */
1357*9a0bf528SMauro Carvalho Chehab 	cmd.args[0x01] = (state->dcur.frequency & 0xff0000) >> 16;
1358*9a0bf528SMauro Carvalho Chehab 	cmd.args[0x02] = (state->dcur.frequency & 0x00ff00) >> 8;
1359*9a0bf528SMauro Carvalho Chehab 	cmd.args[0x03] = (state->dcur.frequency & 0x0000ff);
1360*9a0bf528SMauro Carvalho Chehab 
1361*9a0bf528SMauro Carvalho Chehab 	/* Symbol Rate */
1362*9a0bf528SMauro Carvalho Chehab 	cmd.args[0x04] = ((state->dcur.symbol_rate / 1000) & 0xff00) >> 8;
1363*9a0bf528SMauro Carvalho Chehab 	cmd.args[0x05] = ((state->dcur.symbol_rate / 1000) & 0x00ff);
1364*9a0bf528SMauro Carvalho Chehab 
1365*9a0bf528SMauro Carvalho Chehab 	/* Automatic Inversion */
1366*9a0bf528SMauro Carvalho Chehab 	cmd.args[0x06] = state->dcur.inversion_val;
1367*9a0bf528SMauro Carvalho Chehab 
1368*9a0bf528SMauro Carvalho Chehab 	/* Modulation / FEC / Pilot */
1369*9a0bf528SMauro Carvalho Chehab 	cmd.args[0x07] = state->dcur.fec_val | state->dcur.pilot_val;
1370*9a0bf528SMauro Carvalho Chehab 
1371*9a0bf528SMauro Carvalho Chehab 	cmd.args[0x08] = CX24116_SEARCH_RANGE_KHZ >> 8;
1372*9a0bf528SMauro Carvalho Chehab 	cmd.args[0x09] = CX24116_SEARCH_RANGE_KHZ & 0xff;
1373*9a0bf528SMauro Carvalho Chehab 	cmd.args[0x0a] = 0x00;
1374*9a0bf528SMauro Carvalho Chehab 	cmd.args[0x0b] = 0x00;
1375*9a0bf528SMauro Carvalho Chehab 	cmd.args[0x0c] = state->dcur.rolloff_val;
1376*9a0bf528SMauro Carvalho Chehab 	cmd.args[0x0d] = state->dcur.fec_mask;
1377*9a0bf528SMauro Carvalho Chehab 
1378*9a0bf528SMauro Carvalho Chehab 	if (state->dcur.symbol_rate > 30000000) {
1379*9a0bf528SMauro Carvalho Chehab 		cmd.args[0x0e] = 0x04;
1380*9a0bf528SMauro Carvalho Chehab 		cmd.args[0x0f] = 0x00;
1381*9a0bf528SMauro Carvalho Chehab 		cmd.args[0x10] = 0x01;
1382*9a0bf528SMauro Carvalho Chehab 		cmd.args[0x11] = 0x77;
1383*9a0bf528SMauro Carvalho Chehab 		cmd.args[0x12] = 0x36;
1384*9a0bf528SMauro Carvalho Chehab 		cx24116_writereg(state, CX24116_REG_CLKDIV, 0x44);
1385*9a0bf528SMauro Carvalho Chehab 		cx24116_writereg(state, CX24116_REG_RATEDIV, 0x01);
1386*9a0bf528SMauro Carvalho Chehab 	} else {
1387*9a0bf528SMauro Carvalho Chehab 		cmd.args[0x0e] = 0x06;
1388*9a0bf528SMauro Carvalho Chehab 		cmd.args[0x0f] = 0x00;
1389*9a0bf528SMauro Carvalho Chehab 		cmd.args[0x10] = 0x00;
1390*9a0bf528SMauro Carvalho Chehab 		cmd.args[0x11] = 0xFA;
1391*9a0bf528SMauro Carvalho Chehab 		cmd.args[0x12] = 0x24;
1392*9a0bf528SMauro Carvalho Chehab 		cx24116_writereg(state, CX24116_REG_CLKDIV, 0x46);
1393*9a0bf528SMauro Carvalho Chehab 		cx24116_writereg(state, CX24116_REG_RATEDIV, 0x00);
1394*9a0bf528SMauro Carvalho Chehab 	}
1395*9a0bf528SMauro Carvalho Chehab 
1396*9a0bf528SMauro Carvalho Chehab 	cmd.len = 0x13;
1397*9a0bf528SMauro Carvalho Chehab 
1398*9a0bf528SMauro Carvalho Chehab 	/* We need to support pilot and non-pilot tuning in the
1399*9a0bf528SMauro Carvalho Chehab 	 * driver automatically. This is a workaround for because
1400*9a0bf528SMauro Carvalho Chehab 	 * the demod does not support autodetect.
1401*9a0bf528SMauro Carvalho Chehab 	 */
1402*9a0bf528SMauro Carvalho Chehab 	do {
1403*9a0bf528SMauro Carvalho Chehab 		/* Reset status register */
1404*9a0bf528SMauro Carvalho Chehab 		status = cx24116_readreg(state, CX24116_REG_SSTATUS)
1405*9a0bf528SMauro Carvalho Chehab 			& CX24116_SIGNAL_MASK;
1406*9a0bf528SMauro Carvalho Chehab 		cx24116_writereg(state, CX24116_REG_SSTATUS, status);
1407*9a0bf528SMauro Carvalho Chehab 
1408*9a0bf528SMauro Carvalho Chehab 		/* Tune */
1409*9a0bf528SMauro Carvalho Chehab 		ret = cx24116_cmd_execute(fe, &cmd);
1410*9a0bf528SMauro Carvalho Chehab 		if (ret != 0)
1411*9a0bf528SMauro Carvalho Chehab 			break;
1412*9a0bf528SMauro Carvalho Chehab 
1413*9a0bf528SMauro Carvalho Chehab 		/*
1414*9a0bf528SMauro Carvalho Chehab 		 * Wait for up to 500 ms before retrying
1415*9a0bf528SMauro Carvalho Chehab 		 *
1416*9a0bf528SMauro Carvalho Chehab 		 * If we are able to tune then generally it occurs within 100ms.
1417*9a0bf528SMauro Carvalho Chehab 		 * If it takes longer, try a different toneburst setting.
1418*9a0bf528SMauro Carvalho Chehab 		 */
1419*9a0bf528SMauro Carvalho Chehab 		for (i = 0; i < 50 ; i++) {
1420*9a0bf528SMauro Carvalho Chehab 			cx24116_read_status(fe, &tunerstat);
1421*9a0bf528SMauro Carvalho Chehab 			status = tunerstat & (FE_HAS_SIGNAL | FE_HAS_SYNC);
1422*9a0bf528SMauro Carvalho Chehab 			if (status == (FE_HAS_SIGNAL | FE_HAS_SYNC)) {
1423*9a0bf528SMauro Carvalho Chehab 				dprintk("%s: Tuned\n", __func__);
1424*9a0bf528SMauro Carvalho Chehab 				goto tuned;
1425*9a0bf528SMauro Carvalho Chehab 			}
1426*9a0bf528SMauro Carvalho Chehab 			msleep(10);
1427*9a0bf528SMauro Carvalho Chehab 		}
1428*9a0bf528SMauro Carvalho Chehab 
1429*9a0bf528SMauro Carvalho Chehab 		dprintk("%s: Not tuned\n", __func__);
1430*9a0bf528SMauro Carvalho Chehab 
1431*9a0bf528SMauro Carvalho Chehab 		/* Toggle pilot bit when in auto-pilot */
1432*9a0bf528SMauro Carvalho Chehab 		if (state->dcur.pilot == PILOT_AUTO)
1433*9a0bf528SMauro Carvalho Chehab 			cmd.args[0x07] ^= CX24116_PILOT_ON;
1434*9a0bf528SMauro Carvalho Chehab 	} while (--retune);
1435*9a0bf528SMauro Carvalho Chehab 
1436*9a0bf528SMauro Carvalho Chehab tuned:  /* Set/Reset B/W */
1437*9a0bf528SMauro Carvalho Chehab 	cmd.args[0x00] = CMD_BANDWIDTH;
1438*9a0bf528SMauro Carvalho Chehab 	cmd.args[0x01] = 0x00;
1439*9a0bf528SMauro Carvalho Chehab 	cmd.len = 0x02;
1440*9a0bf528SMauro Carvalho Chehab 	return cx24116_cmd_execute(fe, &cmd);
1441*9a0bf528SMauro Carvalho Chehab }
1442*9a0bf528SMauro Carvalho Chehab 
1443*9a0bf528SMauro Carvalho Chehab static int cx24116_tune(struct dvb_frontend *fe, bool re_tune,
1444*9a0bf528SMauro Carvalho Chehab 	unsigned int mode_flags, unsigned int *delay, fe_status_t *status)
1445*9a0bf528SMauro Carvalho Chehab {
1446*9a0bf528SMauro Carvalho Chehab 	/*
1447*9a0bf528SMauro Carvalho Chehab 	 * It is safe to discard "params" here, as the DVB core will sync
1448*9a0bf528SMauro Carvalho Chehab 	 * fe->dtv_property_cache with fepriv->parameters_in, where the
1449*9a0bf528SMauro Carvalho Chehab 	 * DVBv3 params are stored. The only practical usage for it indicate
1450*9a0bf528SMauro Carvalho Chehab 	 * that re-tuning is needed, e. g. (fepriv->state & FESTATE_RETUNE) is
1451*9a0bf528SMauro Carvalho Chehab 	 * true.
1452*9a0bf528SMauro Carvalho Chehab 	 */
1453*9a0bf528SMauro Carvalho Chehab 
1454*9a0bf528SMauro Carvalho Chehab 	*delay = HZ / 5;
1455*9a0bf528SMauro Carvalho Chehab 	if (re_tune) {
1456*9a0bf528SMauro Carvalho Chehab 		int ret = cx24116_set_frontend(fe);
1457*9a0bf528SMauro Carvalho Chehab 		if (ret)
1458*9a0bf528SMauro Carvalho Chehab 			return ret;
1459*9a0bf528SMauro Carvalho Chehab 	}
1460*9a0bf528SMauro Carvalho Chehab 	return cx24116_read_status(fe, status);
1461*9a0bf528SMauro Carvalho Chehab }
1462*9a0bf528SMauro Carvalho Chehab 
1463*9a0bf528SMauro Carvalho Chehab static int cx24116_get_algo(struct dvb_frontend *fe)
1464*9a0bf528SMauro Carvalho Chehab {
1465*9a0bf528SMauro Carvalho Chehab 	return DVBFE_ALGO_HW;
1466*9a0bf528SMauro Carvalho Chehab }
1467*9a0bf528SMauro Carvalho Chehab 
1468*9a0bf528SMauro Carvalho Chehab static struct dvb_frontend_ops cx24116_ops = {
1469*9a0bf528SMauro Carvalho Chehab 	.delsys = { SYS_DVBS, SYS_DVBS2 },
1470*9a0bf528SMauro Carvalho Chehab 	.info = {
1471*9a0bf528SMauro Carvalho Chehab 		.name = "Conexant CX24116/CX24118",
1472*9a0bf528SMauro Carvalho Chehab 		.frequency_min = 950000,
1473*9a0bf528SMauro Carvalho Chehab 		.frequency_max = 2150000,
1474*9a0bf528SMauro Carvalho Chehab 		.frequency_stepsize = 1011, /* kHz for QPSK frontends */
1475*9a0bf528SMauro Carvalho Chehab 		.frequency_tolerance = 5000,
1476*9a0bf528SMauro Carvalho Chehab 		.symbol_rate_min = 1000000,
1477*9a0bf528SMauro Carvalho Chehab 		.symbol_rate_max = 45000000,
1478*9a0bf528SMauro Carvalho Chehab 		.caps = FE_CAN_INVERSION_AUTO |
1479*9a0bf528SMauro Carvalho Chehab 			FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 | FE_CAN_FEC_3_4 |
1480*9a0bf528SMauro Carvalho Chehab 			FE_CAN_FEC_4_5 | FE_CAN_FEC_5_6 | FE_CAN_FEC_6_7 |
1481*9a0bf528SMauro Carvalho Chehab 			FE_CAN_FEC_7_8 | FE_CAN_FEC_AUTO |
1482*9a0bf528SMauro Carvalho Chehab 			FE_CAN_2G_MODULATION |
1483*9a0bf528SMauro Carvalho Chehab 			FE_CAN_QPSK | FE_CAN_RECOVER
1484*9a0bf528SMauro Carvalho Chehab 	},
1485*9a0bf528SMauro Carvalho Chehab 
1486*9a0bf528SMauro Carvalho Chehab 	.release = cx24116_release,
1487*9a0bf528SMauro Carvalho Chehab 
1488*9a0bf528SMauro Carvalho Chehab 	.init = cx24116_initfe,
1489*9a0bf528SMauro Carvalho Chehab 	.sleep = cx24116_sleep,
1490*9a0bf528SMauro Carvalho Chehab 	.read_status = cx24116_read_status,
1491*9a0bf528SMauro Carvalho Chehab 	.read_ber = cx24116_read_ber,
1492*9a0bf528SMauro Carvalho Chehab 	.read_signal_strength = cx24116_read_signal_strength,
1493*9a0bf528SMauro Carvalho Chehab 	.read_snr = cx24116_read_snr,
1494*9a0bf528SMauro Carvalho Chehab 	.read_ucblocks = cx24116_read_ucblocks,
1495*9a0bf528SMauro Carvalho Chehab 	.set_tone = cx24116_set_tone,
1496*9a0bf528SMauro Carvalho Chehab 	.set_voltage = cx24116_set_voltage,
1497*9a0bf528SMauro Carvalho Chehab 	.diseqc_send_master_cmd = cx24116_send_diseqc_msg,
1498*9a0bf528SMauro Carvalho Chehab 	.diseqc_send_burst = cx24116_diseqc_send_burst,
1499*9a0bf528SMauro Carvalho Chehab 	.get_frontend_algo = cx24116_get_algo,
1500*9a0bf528SMauro Carvalho Chehab 	.tune = cx24116_tune,
1501*9a0bf528SMauro Carvalho Chehab 
1502*9a0bf528SMauro Carvalho Chehab 	.set_frontend = cx24116_set_frontend,
1503*9a0bf528SMauro Carvalho Chehab };
1504*9a0bf528SMauro Carvalho Chehab 
1505*9a0bf528SMauro Carvalho Chehab MODULE_DESCRIPTION("DVB Frontend module for Conexant cx24116/cx24118 hardware");
1506*9a0bf528SMauro Carvalho Chehab MODULE_AUTHOR("Steven Toth");
1507*9a0bf528SMauro Carvalho Chehab MODULE_LICENSE("GPL");
1508*9a0bf528SMauro Carvalho Chehab 
1509