1 /* 2 * Afatech AF9033 demodulator driver 3 * 4 * Copyright (C) 2009 Antti Palosaari <crope@iki.fi> 5 * Copyright (C) 2012 Antti Palosaari <crope@iki.fi> 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License as published by 9 * the Free Software Foundation; either version 2 of the License, or 10 * (at your option) any later version. 11 * 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 * 17 * You should have received a copy of the GNU General Public License along 18 * with this program; if not, write to the Free Software Foundation, Inc., 19 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. 20 */ 21 22 #include "af9033_priv.h" 23 24 struct af9033_state { 25 struct i2c_adapter *i2c; 26 struct dvb_frontend fe; 27 struct af9033_config cfg; 28 29 u32 bandwidth_hz; 30 bool ts_mode_parallel; 31 bool ts_mode_serial; 32 33 u32 ber; 34 u32 ucb; 35 unsigned long last_stat_check; 36 }; 37 38 /* write multiple registers */ 39 static int af9033_wr_regs(struct af9033_state *state, u32 reg, const u8 *val, 40 int len) 41 { 42 int ret; 43 u8 buf[3 + len]; 44 struct i2c_msg msg[1] = { 45 { 46 .addr = state->cfg.i2c_addr, 47 .flags = 0, 48 .len = sizeof(buf), 49 .buf = buf, 50 } 51 }; 52 53 buf[0] = (reg >> 16) & 0xff; 54 buf[1] = (reg >> 8) & 0xff; 55 buf[2] = (reg >> 0) & 0xff; 56 memcpy(&buf[3], val, len); 57 58 ret = i2c_transfer(state->i2c, msg, 1); 59 if (ret == 1) { 60 ret = 0; 61 } else { 62 dev_warn(&state->i2c->dev, "%s: i2c wr failed=%d reg=%06x " \ 63 "len=%d\n", KBUILD_MODNAME, ret, reg, len); 64 ret = -EREMOTEIO; 65 } 66 67 return ret; 68 } 69 70 /* read multiple registers */ 71 static int af9033_rd_regs(struct af9033_state *state, u32 reg, u8 *val, int len) 72 { 73 int ret; 74 u8 buf[3] = { (reg >> 16) & 0xff, (reg >> 8) & 0xff, 75 (reg >> 0) & 0xff }; 76 struct i2c_msg msg[2] = { 77 { 78 .addr = state->cfg.i2c_addr, 79 .flags = 0, 80 .len = sizeof(buf), 81 .buf = buf 82 }, { 83 .addr = state->cfg.i2c_addr, 84 .flags = I2C_M_RD, 85 .len = len, 86 .buf = val 87 } 88 }; 89 90 ret = i2c_transfer(state->i2c, msg, 2); 91 if (ret == 2) { 92 ret = 0; 93 } else { 94 dev_warn(&state->i2c->dev, "%s: i2c rd failed=%d reg=%06x " \ 95 "len=%d\n", KBUILD_MODNAME, ret, reg, len); 96 ret = -EREMOTEIO; 97 } 98 99 return ret; 100 } 101 102 103 /* write single register */ 104 static int af9033_wr_reg(struct af9033_state *state, u32 reg, u8 val) 105 { 106 return af9033_wr_regs(state, reg, &val, 1); 107 } 108 109 /* read single register */ 110 static int af9033_rd_reg(struct af9033_state *state, u32 reg, u8 *val) 111 { 112 return af9033_rd_regs(state, reg, val, 1); 113 } 114 115 /* write single register with mask */ 116 static int af9033_wr_reg_mask(struct af9033_state *state, u32 reg, u8 val, 117 u8 mask) 118 { 119 int ret; 120 u8 tmp; 121 122 /* no need for read if whole reg is written */ 123 if (mask != 0xff) { 124 ret = af9033_rd_regs(state, reg, &tmp, 1); 125 if (ret) 126 return ret; 127 128 val &= mask; 129 tmp &= ~mask; 130 val |= tmp; 131 } 132 133 return af9033_wr_regs(state, reg, &val, 1); 134 } 135 136 /* read single register with mask */ 137 static int af9033_rd_reg_mask(struct af9033_state *state, u32 reg, u8 *val, 138 u8 mask) 139 { 140 int ret, i; 141 u8 tmp; 142 143 ret = af9033_rd_regs(state, reg, &tmp, 1); 144 if (ret) 145 return ret; 146 147 tmp &= mask; 148 149 /* find position of the first bit */ 150 for (i = 0; i < 8; i++) { 151 if ((mask >> i) & 0x01) 152 break; 153 } 154 *val = tmp >> i; 155 156 return 0; 157 } 158 159 static u32 af9033_div(struct af9033_state *state, u32 a, u32 b, u32 x) 160 { 161 u32 r = 0, c = 0, i; 162 163 dev_dbg(&state->i2c->dev, "%s: a=%d b=%d x=%d\n", __func__, a, b, x); 164 165 if (a > b) { 166 c = a / b; 167 a = a - c * b; 168 } 169 170 for (i = 0; i < x; i++) { 171 if (a >= b) { 172 r += 1; 173 a -= b; 174 } 175 a <<= 1; 176 r <<= 1; 177 } 178 r = (c << (u32)x) + r; 179 180 dev_dbg(&state->i2c->dev, "%s: a=%d b=%d x=%d r=%d r=%x\n", 181 __func__, a, b, x, r, r); 182 183 return r; 184 } 185 186 static void af9033_release(struct dvb_frontend *fe) 187 { 188 struct af9033_state *state = fe->demodulator_priv; 189 190 kfree(state); 191 } 192 193 static int af9033_init(struct dvb_frontend *fe) 194 { 195 struct af9033_state *state = fe->demodulator_priv; 196 int ret, i, len; 197 const struct reg_val *init; 198 u8 buf[4]; 199 u32 adc_cw, clock_cw; 200 struct reg_val_mask tab[] = { 201 { 0x80fb24, 0x00, 0x08 }, 202 { 0x80004c, 0x00, 0xff }, 203 { 0x00f641, state->cfg.tuner, 0xff }, 204 { 0x80f5ca, 0x01, 0x01 }, 205 { 0x80f715, 0x01, 0x01 }, 206 { 0x00f41f, 0x04, 0x04 }, 207 { 0x00f41a, 0x01, 0x01 }, 208 { 0x80f731, 0x00, 0x01 }, 209 { 0x00d91e, 0x00, 0x01 }, 210 { 0x00d919, 0x00, 0x01 }, 211 { 0x80f732, 0x00, 0x01 }, 212 { 0x00d91f, 0x00, 0x01 }, 213 { 0x00d91a, 0x00, 0x01 }, 214 { 0x80f730, 0x00, 0x01 }, 215 { 0x80f778, 0x00, 0xff }, 216 { 0x80f73c, 0x01, 0x01 }, 217 { 0x80f776, 0x00, 0x01 }, 218 { 0x00d8fd, 0x01, 0xff }, 219 { 0x00d830, 0x01, 0xff }, 220 { 0x00d831, 0x00, 0xff }, 221 { 0x00d832, 0x00, 0xff }, 222 { 0x80f985, state->ts_mode_serial, 0x01 }, 223 { 0x80f986, state->ts_mode_parallel, 0x01 }, 224 { 0x00d827, 0x00, 0xff }, 225 { 0x00d829, 0x00, 0xff }, 226 }; 227 228 /* program clock control */ 229 clock_cw = af9033_div(state, state->cfg.clock, 1000000ul, 19ul); 230 buf[0] = (clock_cw >> 0) & 0xff; 231 buf[1] = (clock_cw >> 8) & 0xff; 232 buf[2] = (clock_cw >> 16) & 0xff; 233 buf[3] = (clock_cw >> 24) & 0xff; 234 235 dev_dbg(&state->i2c->dev, "%s: clock=%d clock_cw=%08x\n", 236 __func__, state->cfg.clock, clock_cw); 237 238 ret = af9033_wr_regs(state, 0x800025, buf, 4); 239 if (ret < 0) 240 goto err; 241 242 /* program ADC control */ 243 for (i = 0; i < ARRAY_SIZE(clock_adc_lut); i++) { 244 if (clock_adc_lut[i].clock == state->cfg.clock) 245 break; 246 } 247 248 adc_cw = af9033_div(state, clock_adc_lut[i].adc, 1000000ul, 19ul); 249 buf[0] = (adc_cw >> 0) & 0xff; 250 buf[1] = (adc_cw >> 8) & 0xff; 251 buf[2] = (adc_cw >> 16) & 0xff; 252 253 dev_dbg(&state->i2c->dev, "%s: adc=%d adc_cw=%06x\n", 254 __func__, clock_adc_lut[i].adc, adc_cw); 255 256 ret = af9033_wr_regs(state, 0x80f1cd, buf, 3); 257 if (ret < 0) 258 goto err; 259 260 /* program register table */ 261 for (i = 0; i < ARRAY_SIZE(tab); i++) { 262 ret = af9033_wr_reg_mask(state, tab[i].reg, tab[i].val, 263 tab[i].mask); 264 if (ret < 0) 265 goto err; 266 } 267 268 /* settings for TS interface */ 269 if (state->cfg.ts_mode == AF9033_TS_MODE_USB) { 270 ret = af9033_wr_reg_mask(state, 0x80f9a5, 0x00, 0x01); 271 if (ret < 0) 272 goto err; 273 274 ret = af9033_wr_reg_mask(state, 0x80f9b5, 0x01, 0x01); 275 if (ret < 0) 276 goto err; 277 } else { 278 ret = af9033_wr_reg_mask(state, 0x80f990, 0x00, 0x01); 279 if (ret < 0) 280 goto err; 281 282 ret = af9033_wr_reg_mask(state, 0x80f9b5, 0x00, 0x01); 283 if (ret < 0) 284 goto err; 285 } 286 287 /* load OFSM settings */ 288 dev_dbg(&state->i2c->dev, "%s: load ofsm settings\n", __func__); 289 len = ARRAY_SIZE(ofsm_init); 290 init = ofsm_init; 291 for (i = 0; i < len; i++) { 292 ret = af9033_wr_reg(state, init[i].reg, init[i].val); 293 if (ret < 0) 294 goto err; 295 } 296 297 /* load tuner specific settings */ 298 dev_dbg(&state->i2c->dev, "%s: load tuner specific settings\n", 299 __func__); 300 switch (state->cfg.tuner) { 301 case AF9033_TUNER_TUA9001: 302 len = ARRAY_SIZE(tuner_init_tua9001); 303 init = tuner_init_tua9001; 304 break; 305 case AF9033_TUNER_FC0011: 306 len = ARRAY_SIZE(tuner_init_fc0011); 307 init = tuner_init_fc0011; 308 break; 309 case AF9033_TUNER_MXL5007T: 310 len = ARRAY_SIZE(tuner_init_mxl5007t); 311 init = tuner_init_mxl5007t; 312 break; 313 case AF9033_TUNER_TDA18218: 314 len = ARRAY_SIZE(tuner_init_tda18218); 315 init = tuner_init_tda18218; 316 break; 317 case AF9033_TUNER_FC2580: 318 len = ARRAY_SIZE(tuner_init_fc2580); 319 init = tuner_init_fc2580; 320 break; 321 case AF9033_TUNER_FC0012: 322 len = ARRAY_SIZE(tuner_init_fc0012); 323 init = tuner_init_fc0012; 324 break; 325 default: 326 dev_dbg(&state->i2c->dev, "%s: unsupported tuner ID=%d\n", 327 __func__, state->cfg.tuner); 328 ret = -ENODEV; 329 goto err; 330 } 331 332 for (i = 0; i < len; i++) { 333 ret = af9033_wr_reg(state, init[i].reg, init[i].val); 334 if (ret < 0) 335 goto err; 336 } 337 338 if (state->cfg.ts_mode == AF9033_TS_MODE_SERIAL) { 339 ret = af9033_wr_reg_mask(state, 0x00d91c, 0x01, 0x01); 340 if (ret < 0) 341 goto err; 342 343 ret = af9033_wr_reg_mask(state, 0x00d917, 0x00, 0x01); 344 if (ret < 0) 345 goto err; 346 347 ret = af9033_wr_reg_mask(state, 0x00d916, 0x00, 0x01); 348 if (ret < 0) 349 goto err; 350 } 351 352 state->bandwidth_hz = 0; /* force to program all parameters */ 353 354 return 0; 355 356 err: 357 dev_dbg(&state->i2c->dev, "%s: failed=%d\n", __func__, ret); 358 359 return ret; 360 } 361 362 static int af9033_sleep(struct dvb_frontend *fe) 363 { 364 struct af9033_state *state = fe->demodulator_priv; 365 int ret, i; 366 u8 tmp; 367 368 ret = af9033_wr_reg(state, 0x80004c, 1); 369 if (ret < 0) 370 goto err; 371 372 ret = af9033_wr_reg(state, 0x800000, 0); 373 if (ret < 0) 374 goto err; 375 376 for (i = 100, tmp = 1; i && tmp; i--) { 377 ret = af9033_rd_reg(state, 0x80004c, &tmp); 378 if (ret < 0) 379 goto err; 380 381 usleep_range(200, 10000); 382 } 383 384 dev_dbg(&state->i2c->dev, "%s: loop=%d\n", __func__, i); 385 386 if (i == 0) { 387 ret = -ETIMEDOUT; 388 goto err; 389 } 390 391 ret = af9033_wr_reg_mask(state, 0x80fb24, 0x08, 0x08); 392 if (ret < 0) 393 goto err; 394 395 /* prevent current leak (?) */ 396 if (state->cfg.ts_mode == AF9033_TS_MODE_SERIAL) { 397 /* enable parallel TS */ 398 ret = af9033_wr_reg_mask(state, 0x00d917, 0x00, 0x01); 399 if (ret < 0) 400 goto err; 401 402 ret = af9033_wr_reg_mask(state, 0x00d916, 0x01, 0x01); 403 if (ret < 0) 404 goto err; 405 } 406 407 return 0; 408 409 err: 410 dev_dbg(&state->i2c->dev, "%s: failed=%d\n", __func__, ret); 411 412 return ret; 413 } 414 415 static int af9033_get_tune_settings(struct dvb_frontend *fe, 416 struct dvb_frontend_tune_settings *fesettings) 417 { 418 fesettings->min_delay_ms = 800; 419 fesettings->step_size = 0; 420 fesettings->max_drift = 0; 421 422 return 0; 423 } 424 425 static int af9033_set_frontend(struct dvb_frontend *fe) 426 { 427 struct af9033_state *state = fe->demodulator_priv; 428 struct dtv_frontend_properties *c = &fe->dtv_property_cache; 429 int ret, i, spec_inv, sampling_freq; 430 u8 tmp, buf[3], bandwidth_reg_val; 431 u32 if_frequency, freq_cw, adc_freq; 432 433 dev_dbg(&state->i2c->dev, "%s: frequency=%d bandwidth_hz=%d\n", 434 __func__, c->frequency, c->bandwidth_hz); 435 436 /* check bandwidth */ 437 switch (c->bandwidth_hz) { 438 case 6000000: 439 bandwidth_reg_val = 0x00; 440 break; 441 case 7000000: 442 bandwidth_reg_val = 0x01; 443 break; 444 case 8000000: 445 bandwidth_reg_val = 0x02; 446 break; 447 default: 448 dev_dbg(&state->i2c->dev, "%s: invalid bandwidth_hz\n", 449 __func__); 450 ret = -EINVAL; 451 goto err; 452 } 453 454 /* program tuner */ 455 if (fe->ops.tuner_ops.set_params) 456 fe->ops.tuner_ops.set_params(fe); 457 458 /* program CFOE coefficients */ 459 if (c->bandwidth_hz != state->bandwidth_hz) { 460 for (i = 0; i < ARRAY_SIZE(coeff_lut); i++) { 461 if (coeff_lut[i].clock == state->cfg.clock && 462 coeff_lut[i].bandwidth_hz == c->bandwidth_hz) { 463 break; 464 } 465 } 466 ret = af9033_wr_regs(state, 0x800001, 467 coeff_lut[i].val, sizeof(coeff_lut[i].val)); 468 } 469 470 /* program frequency control */ 471 if (c->bandwidth_hz != state->bandwidth_hz) { 472 spec_inv = state->cfg.spec_inv ? -1 : 1; 473 474 for (i = 0; i < ARRAY_SIZE(clock_adc_lut); i++) { 475 if (clock_adc_lut[i].clock == state->cfg.clock) 476 break; 477 } 478 adc_freq = clock_adc_lut[i].adc; 479 480 /* get used IF frequency */ 481 if (fe->ops.tuner_ops.get_if_frequency) 482 fe->ops.tuner_ops.get_if_frequency(fe, &if_frequency); 483 else 484 if_frequency = 0; 485 486 sampling_freq = if_frequency; 487 488 while (sampling_freq > (adc_freq / 2)) 489 sampling_freq -= adc_freq; 490 491 if (sampling_freq >= 0) 492 spec_inv *= -1; 493 else 494 sampling_freq *= -1; 495 496 freq_cw = af9033_div(state, sampling_freq, adc_freq, 23ul); 497 498 if (spec_inv == -1) 499 freq_cw = 0x800000 - freq_cw; 500 501 /* get adc multiplies */ 502 ret = af9033_rd_reg(state, 0x800045, &tmp); 503 if (ret < 0) 504 goto err; 505 506 if (tmp == 1) 507 freq_cw /= 2; 508 509 buf[0] = (freq_cw >> 0) & 0xff; 510 buf[1] = (freq_cw >> 8) & 0xff; 511 buf[2] = (freq_cw >> 16) & 0x7f; 512 ret = af9033_wr_regs(state, 0x800029, buf, 3); 513 if (ret < 0) 514 goto err; 515 516 state->bandwidth_hz = c->bandwidth_hz; 517 } 518 519 ret = af9033_wr_reg_mask(state, 0x80f904, bandwidth_reg_val, 0x03); 520 if (ret < 0) 521 goto err; 522 523 ret = af9033_wr_reg(state, 0x800040, 0x00); 524 if (ret < 0) 525 goto err; 526 527 ret = af9033_wr_reg(state, 0x800047, 0x00); 528 if (ret < 0) 529 goto err; 530 531 ret = af9033_wr_reg_mask(state, 0x80f999, 0x00, 0x01); 532 if (ret < 0) 533 goto err; 534 535 if (c->frequency <= 230000000) 536 tmp = 0x00; /* VHF */ 537 else 538 tmp = 0x01; /* UHF */ 539 540 ret = af9033_wr_reg(state, 0x80004b, tmp); 541 if (ret < 0) 542 goto err; 543 544 ret = af9033_wr_reg(state, 0x800000, 0x00); 545 if (ret < 0) 546 goto err; 547 548 return 0; 549 550 err: 551 dev_dbg(&state->i2c->dev, "%s: failed=%d\n", __func__, ret); 552 553 return ret; 554 } 555 556 static int af9033_get_frontend(struct dvb_frontend *fe) 557 { 558 struct af9033_state *state = fe->demodulator_priv; 559 struct dtv_frontend_properties *c = &fe->dtv_property_cache; 560 int ret; 561 u8 buf[8]; 562 563 dev_dbg(&state->i2c->dev, "%s:\n", __func__); 564 565 /* read all needed registers */ 566 ret = af9033_rd_regs(state, 0x80f900, buf, sizeof(buf)); 567 if (ret < 0) 568 goto err; 569 570 switch ((buf[0] >> 0) & 3) { 571 case 0: 572 c->transmission_mode = TRANSMISSION_MODE_2K; 573 break; 574 case 1: 575 c->transmission_mode = TRANSMISSION_MODE_8K; 576 break; 577 } 578 579 switch ((buf[1] >> 0) & 3) { 580 case 0: 581 c->guard_interval = GUARD_INTERVAL_1_32; 582 break; 583 case 1: 584 c->guard_interval = GUARD_INTERVAL_1_16; 585 break; 586 case 2: 587 c->guard_interval = GUARD_INTERVAL_1_8; 588 break; 589 case 3: 590 c->guard_interval = GUARD_INTERVAL_1_4; 591 break; 592 } 593 594 switch ((buf[2] >> 0) & 7) { 595 case 0: 596 c->hierarchy = HIERARCHY_NONE; 597 break; 598 case 1: 599 c->hierarchy = HIERARCHY_1; 600 break; 601 case 2: 602 c->hierarchy = HIERARCHY_2; 603 break; 604 case 3: 605 c->hierarchy = HIERARCHY_4; 606 break; 607 } 608 609 switch ((buf[3] >> 0) & 3) { 610 case 0: 611 c->modulation = QPSK; 612 break; 613 case 1: 614 c->modulation = QAM_16; 615 break; 616 case 2: 617 c->modulation = QAM_64; 618 break; 619 } 620 621 switch ((buf[4] >> 0) & 3) { 622 case 0: 623 c->bandwidth_hz = 6000000; 624 break; 625 case 1: 626 c->bandwidth_hz = 7000000; 627 break; 628 case 2: 629 c->bandwidth_hz = 8000000; 630 break; 631 } 632 633 switch ((buf[6] >> 0) & 7) { 634 case 0: 635 c->code_rate_HP = FEC_1_2; 636 break; 637 case 1: 638 c->code_rate_HP = FEC_2_3; 639 break; 640 case 2: 641 c->code_rate_HP = FEC_3_4; 642 break; 643 case 3: 644 c->code_rate_HP = FEC_5_6; 645 break; 646 case 4: 647 c->code_rate_HP = FEC_7_8; 648 break; 649 case 5: 650 c->code_rate_HP = FEC_NONE; 651 break; 652 } 653 654 switch ((buf[7] >> 0) & 7) { 655 case 0: 656 c->code_rate_LP = FEC_1_2; 657 break; 658 case 1: 659 c->code_rate_LP = FEC_2_3; 660 break; 661 case 2: 662 c->code_rate_LP = FEC_3_4; 663 break; 664 case 3: 665 c->code_rate_LP = FEC_5_6; 666 break; 667 case 4: 668 c->code_rate_LP = FEC_7_8; 669 break; 670 case 5: 671 c->code_rate_LP = FEC_NONE; 672 break; 673 } 674 675 return 0; 676 677 err: 678 dev_dbg(&state->i2c->dev, "%s: failed=%d\n", __func__, ret); 679 680 return ret; 681 } 682 683 static int af9033_read_status(struct dvb_frontend *fe, fe_status_t *status) 684 { 685 struct af9033_state *state = fe->demodulator_priv; 686 int ret; 687 u8 tmp; 688 689 *status = 0; 690 691 /* radio channel status, 0=no result, 1=has signal, 2=no signal */ 692 ret = af9033_rd_reg(state, 0x800047, &tmp); 693 if (ret < 0) 694 goto err; 695 696 /* has signal */ 697 if (tmp == 0x01) 698 *status |= FE_HAS_SIGNAL; 699 700 if (tmp != 0x02) { 701 /* TPS lock */ 702 ret = af9033_rd_reg_mask(state, 0x80f5a9, &tmp, 0x01); 703 if (ret < 0) 704 goto err; 705 706 if (tmp) 707 *status |= FE_HAS_SIGNAL | FE_HAS_CARRIER | 708 FE_HAS_VITERBI; 709 710 /* full lock */ 711 ret = af9033_rd_reg_mask(state, 0x80f999, &tmp, 0x01); 712 if (ret < 0) 713 goto err; 714 715 if (tmp) 716 *status |= FE_HAS_SIGNAL | FE_HAS_CARRIER | 717 FE_HAS_VITERBI | FE_HAS_SYNC | 718 FE_HAS_LOCK; 719 } 720 721 return 0; 722 723 err: 724 dev_dbg(&state->i2c->dev, "%s: failed=%d\n", __func__, ret); 725 726 return ret; 727 } 728 729 static int af9033_read_snr(struct dvb_frontend *fe, u16 *snr) 730 { 731 struct af9033_state *state = fe->demodulator_priv; 732 int ret, i, len; 733 u8 buf[3], tmp; 734 u32 snr_val; 735 const struct val_snr *uninitialized_var(snr_lut); 736 737 /* read value */ 738 ret = af9033_rd_regs(state, 0x80002c, buf, 3); 739 if (ret < 0) 740 goto err; 741 742 snr_val = (buf[2] << 16) | (buf[1] << 8) | buf[0]; 743 744 /* read current modulation */ 745 ret = af9033_rd_reg(state, 0x80f903, &tmp); 746 if (ret < 0) 747 goto err; 748 749 switch ((tmp >> 0) & 3) { 750 case 0: 751 len = ARRAY_SIZE(qpsk_snr_lut); 752 snr_lut = qpsk_snr_lut; 753 break; 754 case 1: 755 len = ARRAY_SIZE(qam16_snr_lut); 756 snr_lut = qam16_snr_lut; 757 break; 758 case 2: 759 len = ARRAY_SIZE(qam64_snr_lut); 760 snr_lut = qam64_snr_lut; 761 break; 762 default: 763 goto err; 764 } 765 766 for (i = 0; i < len; i++) { 767 tmp = snr_lut[i].snr; 768 769 if (snr_val < snr_lut[i].val) 770 break; 771 } 772 773 *snr = tmp * 10; /* dB/10 */ 774 775 return 0; 776 777 err: 778 dev_dbg(&state->i2c->dev, "%s: failed=%d\n", __func__, ret); 779 780 return ret; 781 } 782 783 static int af9033_read_signal_strength(struct dvb_frontend *fe, u16 *strength) 784 { 785 struct af9033_state *state = fe->demodulator_priv; 786 int ret; 787 u8 strength2; 788 789 /* read signal strength of 0-100 scale */ 790 ret = af9033_rd_reg(state, 0x800048, &strength2); 791 if (ret < 0) 792 goto err; 793 794 /* scale value to 0x0000-0xffff */ 795 *strength = strength2 * 0xffff / 100; 796 797 return 0; 798 799 err: 800 dev_dbg(&state->i2c->dev, "%s: failed=%d\n", __func__, ret); 801 802 return ret; 803 } 804 805 static int af9033_update_ch_stat(struct af9033_state *state) 806 { 807 int ret = 0; 808 u32 err_cnt, bit_cnt; 809 u16 abort_cnt; 810 u8 buf[7]; 811 812 /* only update data every half second */ 813 if (time_after(jiffies, state->last_stat_check + msecs_to_jiffies(500))) { 814 ret = af9033_rd_regs(state, 0x800032, buf, sizeof(buf)); 815 if (ret < 0) 816 goto err; 817 /* in 8 byte packets? */ 818 abort_cnt = (buf[1] << 8) + buf[0]; 819 /* in bits */ 820 err_cnt = (buf[4] << 16) + (buf[3] << 8) + buf[2]; 821 /* in 8 byte packets? always(?) 0x2710 = 10000 */ 822 bit_cnt = (buf[6] << 8) + buf[5]; 823 824 if (bit_cnt < abort_cnt) { 825 abort_cnt = 1000; 826 state->ber = 0xffffffff; 827 } else { 828 /* 8 byte packets, that have not been rejected already */ 829 bit_cnt -= (u32)abort_cnt; 830 if (bit_cnt == 0) { 831 state->ber = 0xffffffff; 832 } else { 833 err_cnt -= (u32)abort_cnt * 8 * 8; 834 bit_cnt *= 8 * 8; 835 state->ber = err_cnt * (0xffffffff / bit_cnt); 836 } 837 } 838 state->ucb += abort_cnt; 839 state->last_stat_check = jiffies; 840 } 841 842 return 0; 843 err: 844 dev_dbg(&state->i2c->dev, "%s: failed=%d\n", __func__, ret); 845 846 return ret; 847 } 848 849 static int af9033_read_ber(struct dvb_frontend *fe, u32 *ber) 850 { 851 struct af9033_state *state = fe->demodulator_priv; 852 int ret; 853 854 ret = af9033_update_ch_stat(state); 855 if (ret < 0) 856 return ret; 857 858 *ber = state->ber; 859 860 return 0; 861 } 862 863 static int af9033_read_ucblocks(struct dvb_frontend *fe, u32 *ucblocks) 864 { 865 struct af9033_state *state = fe->demodulator_priv; 866 int ret; 867 868 ret = af9033_update_ch_stat(state); 869 if (ret < 0) 870 return ret; 871 872 *ucblocks = state->ucb; 873 874 return 0; 875 } 876 877 static int af9033_i2c_gate_ctrl(struct dvb_frontend *fe, int enable) 878 { 879 struct af9033_state *state = fe->demodulator_priv; 880 int ret; 881 882 dev_dbg(&state->i2c->dev, "%s: enable=%d\n", __func__, enable); 883 884 ret = af9033_wr_reg_mask(state, 0x00fa04, enable, 0x01); 885 if (ret < 0) 886 goto err; 887 888 return 0; 889 890 err: 891 dev_dbg(&state->i2c->dev, "%s: failed=%d\n", __func__, ret); 892 893 return ret; 894 } 895 896 static struct dvb_frontend_ops af9033_ops; 897 898 struct dvb_frontend *af9033_attach(const struct af9033_config *config, 899 struct i2c_adapter *i2c) 900 { 901 int ret; 902 struct af9033_state *state; 903 u8 buf[8]; 904 905 dev_dbg(&i2c->dev, "%s:\n", __func__); 906 907 /* allocate memory for the internal state */ 908 state = kzalloc(sizeof(struct af9033_state), GFP_KERNEL); 909 if (state == NULL) 910 goto err; 911 912 /* setup the state */ 913 state->i2c = i2c; 914 memcpy(&state->cfg, config, sizeof(struct af9033_config)); 915 916 if (state->cfg.clock != 12000000) { 917 dev_err(&state->i2c->dev, "%s: af9033: unsupported clock=%d, " \ 918 "only 12000000 Hz is supported currently\n", 919 KBUILD_MODNAME, state->cfg.clock); 920 goto err; 921 } 922 923 /* firmware version */ 924 ret = af9033_rd_regs(state, 0x0083e9, &buf[0], 4); 925 if (ret < 0) 926 goto err; 927 928 ret = af9033_rd_regs(state, 0x804191, &buf[4], 4); 929 if (ret < 0) 930 goto err; 931 932 dev_info(&state->i2c->dev, "%s: firmware version: LINK=%d.%d.%d.%d " \ 933 "OFDM=%d.%d.%d.%d\n", KBUILD_MODNAME, buf[0], buf[1], 934 buf[2], buf[3], buf[4], buf[5], buf[6], buf[7]); 935 936 /* sleep */ 937 ret = af9033_wr_reg(state, 0x80004c, 1); 938 if (ret < 0) 939 goto err; 940 941 ret = af9033_wr_reg(state, 0x800000, 0); 942 if (ret < 0) 943 goto err; 944 945 /* configure internal TS mode */ 946 switch (state->cfg.ts_mode) { 947 case AF9033_TS_MODE_PARALLEL: 948 state->ts_mode_parallel = true; 949 break; 950 case AF9033_TS_MODE_SERIAL: 951 state->ts_mode_serial = true; 952 break; 953 case AF9033_TS_MODE_USB: 954 /* usb mode for AF9035 */ 955 default: 956 break; 957 } 958 959 /* create dvb_frontend */ 960 memcpy(&state->fe.ops, &af9033_ops, sizeof(struct dvb_frontend_ops)); 961 state->fe.demodulator_priv = state; 962 963 return &state->fe; 964 965 err: 966 kfree(state); 967 return NULL; 968 } 969 EXPORT_SYMBOL(af9033_attach); 970 971 static struct dvb_frontend_ops af9033_ops = { 972 .delsys = { SYS_DVBT }, 973 .info = { 974 .name = "Afatech AF9033 (DVB-T)", 975 .frequency_min = 174000000, 976 .frequency_max = 862000000, 977 .frequency_stepsize = 250000, 978 .frequency_tolerance = 0, 979 .caps = FE_CAN_FEC_1_2 | 980 FE_CAN_FEC_2_3 | 981 FE_CAN_FEC_3_4 | 982 FE_CAN_FEC_5_6 | 983 FE_CAN_FEC_7_8 | 984 FE_CAN_FEC_AUTO | 985 FE_CAN_QPSK | 986 FE_CAN_QAM_16 | 987 FE_CAN_QAM_64 | 988 FE_CAN_QAM_AUTO | 989 FE_CAN_TRANSMISSION_MODE_AUTO | 990 FE_CAN_GUARD_INTERVAL_AUTO | 991 FE_CAN_HIERARCHY_AUTO | 992 FE_CAN_RECOVER | 993 FE_CAN_MUTE_TS 994 }, 995 996 .release = af9033_release, 997 998 .init = af9033_init, 999 .sleep = af9033_sleep, 1000 1001 .get_tune_settings = af9033_get_tune_settings, 1002 .set_frontend = af9033_set_frontend, 1003 .get_frontend = af9033_get_frontend, 1004 1005 .read_status = af9033_read_status, 1006 .read_snr = af9033_read_snr, 1007 .read_signal_strength = af9033_read_signal_strength, 1008 .read_ber = af9033_read_ber, 1009 .read_ucblocks = af9033_read_ucblocks, 1010 1011 .i2c_gate_ctrl = af9033_i2c_gate_ctrl, 1012 }; 1013 1014 MODULE_AUTHOR("Antti Palosaari <crope@iki.fi>"); 1015 MODULE_DESCRIPTION("Afatech AF9033 DVB-T demodulator driver"); 1016 MODULE_LICENSE("GPL"); 1017