1 /* 2 * Afatech AF9033 demodulator driver 3 * 4 * Copyright (C) 2009 Antti Palosaari <crope@iki.fi> 5 * Copyright (C) 2012 Antti Palosaari <crope@iki.fi> 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License as published by 9 * the Free Software Foundation; either version 2 of the License, or 10 * (at your option) any later version. 11 * 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 * 17 * You should have received a copy of the GNU General Public License along 18 * with this program; if not, write to the Free Software Foundation, Inc., 19 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. 20 */ 21 22 #include "af9033_priv.h" 23 24 struct af9033_state { 25 struct i2c_adapter *i2c; 26 struct dvb_frontend fe; 27 struct af9033_config cfg; 28 29 u32 bandwidth_hz; 30 bool ts_mode_parallel; 31 bool ts_mode_serial; 32 33 u32 ber; 34 u32 ucb; 35 unsigned long last_stat_check; 36 }; 37 38 /* write multiple registers */ 39 static int af9033_wr_regs(struct af9033_state *state, u32 reg, const u8 *val, 40 int len) 41 { 42 int ret; 43 u8 buf[3 + len]; 44 struct i2c_msg msg[1] = { 45 { 46 .addr = state->cfg.i2c_addr, 47 .flags = 0, 48 .len = sizeof(buf), 49 .buf = buf, 50 } 51 }; 52 53 buf[0] = (reg >> 16) & 0xff; 54 buf[1] = (reg >> 8) & 0xff; 55 buf[2] = (reg >> 0) & 0xff; 56 memcpy(&buf[3], val, len); 57 58 ret = i2c_transfer(state->i2c, msg, 1); 59 if (ret == 1) { 60 ret = 0; 61 } else { 62 dev_warn(&state->i2c->dev, "%s: i2c wr failed=%d reg=%06x " \ 63 "len=%d\n", KBUILD_MODNAME, ret, reg, len); 64 ret = -EREMOTEIO; 65 } 66 67 return ret; 68 } 69 70 /* read multiple registers */ 71 static int af9033_rd_regs(struct af9033_state *state, u32 reg, u8 *val, int len) 72 { 73 int ret; 74 u8 buf[3] = { (reg >> 16) & 0xff, (reg >> 8) & 0xff, 75 (reg >> 0) & 0xff }; 76 struct i2c_msg msg[2] = { 77 { 78 .addr = state->cfg.i2c_addr, 79 .flags = 0, 80 .len = sizeof(buf), 81 .buf = buf 82 }, { 83 .addr = state->cfg.i2c_addr, 84 .flags = I2C_M_RD, 85 .len = len, 86 .buf = val 87 } 88 }; 89 90 ret = i2c_transfer(state->i2c, msg, 2); 91 if (ret == 2) { 92 ret = 0; 93 } else { 94 dev_warn(&state->i2c->dev, "%s: i2c rd failed=%d reg=%06x " \ 95 "len=%d\n", KBUILD_MODNAME, ret, reg, len); 96 ret = -EREMOTEIO; 97 } 98 99 return ret; 100 } 101 102 103 /* write single register */ 104 static int af9033_wr_reg(struct af9033_state *state, u32 reg, u8 val) 105 { 106 return af9033_wr_regs(state, reg, &val, 1); 107 } 108 109 /* read single register */ 110 static int af9033_rd_reg(struct af9033_state *state, u32 reg, u8 *val) 111 { 112 return af9033_rd_regs(state, reg, val, 1); 113 } 114 115 /* write single register with mask */ 116 static int af9033_wr_reg_mask(struct af9033_state *state, u32 reg, u8 val, 117 u8 mask) 118 { 119 int ret; 120 u8 tmp; 121 122 /* no need for read if whole reg is written */ 123 if (mask != 0xff) { 124 ret = af9033_rd_regs(state, reg, &tmp, 1); 125 if (ret) 126 return ret; 127 128 val &= mask; 129 tmp &= ~mask; 130 val |= tmp; 131 } 132 133 return af9033_wr_regs(state, reg, &val, 1); 134 } 135 136 /* read single register with mask */ 137 static int af9033_rd_reg_mask(struct af9033_state *state, u32 reg, u8 *val, 138 u8 mask) 139 { 140 int ret, i; 141 u8 tmp; 142 143 ret = af9033_rd_regs(state, reg, &tmp, 1); 144 if (ret) 145 return ret; 146 147 tmp &= mask; 148 149 /* find position of the first bit */ 150 for (i = 0; i < 8; i++) { 151 if ((mask >> i) & 0x01) 152 break; 153 } 154 *val = tmp >> i; 155 156 return 0; 157 } 158 159 static u32 af9033_div(struct af9033_state *state, u32 a, u32 b, u32 x) 160 { 161 u32 r = 0, c = 0, i; 162 163 dev_dbg(&state->i2c->dev, "%s: a=%d b=%d x=%d\n", __func__, a, b, x); 164 165 if (a > b) { 166 c = a / b; 167 a = a - c * b; 168 } 169 170 for (i = 0; i < x; i++) { 171 if (a >= b) { 172 r += 1; 173 a -= b; 174 } 175 a <<= 1; 176 r <<= 1; 177 } 178 r = (c << (u32)x) + r; 179 180 dev_dbg(&state->i2c->dev, "%s: a=%d b=%d x=%d r=%d r=%x\n", 181 __func__, a, b, x, r, r); 182 183 return r; 184 } 185 186 static void af9033_release(struct dvb_frontend *fe) 187 { 188 struct af9033_state *state = fe->demodulator_priv; 189 190 kfree(state); 191 } 192 193 static int af9033_init(struct dvb_frontend *fe) 194 { 195 struct af9033_state *state = fe->demodulator_priv; 196 int ret, i, len; 197 const struct reg_val *init; 198 u8 buf[4]; 199 u32 adc_cw, clock_cw; 200 struct reg_val_mask tab[] = { 201 { 0x80fb24, 0x00, 0x08 }, 202 { 0x80004c, 0x00, 0xff }, 203 { 0x00f641, state->cfg.tuner, 0xff }, 204 { 0x80f5ca, 0x01, 0x01 }, 205 { 0x80f715, 0x01, 0x01 }, 206 { 0x00f41f, 0x04, 0x04 }, 207 { 0x00f41a, 0x01, 0x01 }, 208 { 0x80f731, 0x00, 0x01 }, 209 { 0x00d91e, 0x00, 0x01 }, 210 { 0x00d919, 0x00, 0x01 }, 211 { 0x80f732, 0x00, 0x01 }, 212 { 0x00d91f, 0x00, 0x01 }, 213 { 0x00d91a, 0x00, 0x01 }, 214 { 0x80f730, 0x00, 0x01 }, 215 { 0x80f778, 0x00, 0xff }, 216 { 0x80f73c, 0x01, 0x01 }, 217 { 0x80f776, 0x00, 0x01 }, 218 { 0x00d8fd, 0x01, 0xff }, 219 { 0x00d830, 0x01, 0xff }, 220 { 0x00d831, 0x00, 0xff }, 221 { 0x00d832, 0x00, 0xff }, 222 { 0x80f985, state->ts_mode_serial, 0x01 }, 223 { 0x80f986, state->ts_mode_parallel, 0x01 }, 224 { 0x00d827, 0x00, 0xff }, 225 { 0x00d829, 0x00, 0xff }, 226 }; 227 228 /* program clock control */ 229 clock_cw = af9033_div(state, state->cfg.clock, 1000000ul, 19ul); 230 buf[0] = (clock_cw >> 0) & 0xff; 231 buf[1] = (clock_cw >> 8) & 0xff; 232 buf[2] = (clock_cw >> 16) & 0xff; 233 buf[3] = (clock_cw >> 24) & 0xff; 234 235 dev_dbg(&state->i2c->dev, "%s: clock=%d clock_cw=%08x\n", 236 __func__, state->cfg.clock, clock_cw); 237 238 ret = af9033_wr_regs(state, 0x800025, buf, 4); 239 if (ret < 0) 240 goto err; 241 242 /* program ADC control */ 243 for (i = 0; i < ARRAY_SIZE(clock_adc_lut); i++) { 244 if (clock_adc_lut[i].clock == state->cfg.clock) 245 break; 246 } 247 248 adc_cw = af9033_div(state, clock_adc_lut[i].adc, 1000000ul, 19ul); 249 buf[0] = (adc_cw >> 0) & 0xff; 250 buf[1] = (adc_cw >> 8) & 0xff; 251 buf[2] = (adc_cw >> 16) & 0xff; 252 253 dev_dbg(&state->i2c->dev, "%s: adc=%d adc_cw=%06x\n", 254 __func__, clock_adc_lut[i].adc, adc_cw); 255 256 ret = af9033_wr_regs(state, 0x80f1cd, buf, 3); 257 if (ret < 0) 258 goto err; 259 260 /* program register table */ 261 for (i = 0; i < ARRAY_SIZE(tab); i++) { 262 ret = af9033_wr_reg_mask(state, tab[i].reg, tab[i].val, 263 tab[i].mask); 264 if (ret < 0) 265 goto err; 266 } 267 268 /* settings for TS interface */ 269 if (state->cfg.ts_mode == AF9033_TS_MODE_USB) { 270 ret = af9033_wr_reg_mask(state, 0x80f9a5, 0x00, 0x01); 271 if (ret < 0) 272 goto err; 273 274 ret = af9033_wr_reg_mask(state, 0x80f9b5, 0x01, 0x01); 275 if (ret < 0) 276 goto err; 277 } else { 278 ret = af9033_wr_reg_mask(state, 0x80f990, 0x00, 0x01); 279 if (ret < 0) 280 goto err; 281 282 ret = af9033_wr_reg_mask(state, 0x80f9b5, 0x00, 0x01); 283 if (ret < 0) 284 goto err; 285 } 286 287 /* load OFSM settings */ 288 dev_dbg(&state->i2c->dev, "%s: load ofsm settings\n", __func__); 289 len = ARRAY_SIZE(ofsm_init); 290 init = ofsm_init; 291 for (i = 0; i < len; i++) { 292 ret = af9033_wr_reg(state, init[i].reg, init[i].val); 293 if (ret < 0) 294 goto err; 295 } 296 297 /* load tuner specific settings */ 298 dev_dbg(&state->i2c->dev, "%s: load tuner specific settings\n", 299 __func__); 300 switch (state->cfg.tuner) { 301 case AF9033_TUNER_TUA9001: 302 len = ARRAY_SIZE(tuner_init_tua9001); 303 init = tuner_init_tua9001; 304 break; 305 case AF9033_TUNER_FC0011: 306 len = ARRAY_SIZE(tuner_init_fc0011); 307 init = tuner_init_fc0011; 308 break; 309 case AF9033_TUNER_MXL5007T: 310 len = ARRAY_SIZE(tuner_init_mxl5007t); 311 init = tuner_init_mxl5007t; 312 break; 313 case AF9033_TUNER_TDA18218: 314 len = ARRAY_SIZE(tuner_init_tda18218); 315 init = tuner_init_tda18218; 316 break; 317 case AF9033_TUNER_FC2580: 318 len = ARRAY_SIZE(tuner_init_fc2580); 319 init = tuner_init_fc2580; 320 break; 321 default: 322 dev_dbg(&state->i2c->dev, "%s: unsupported tuner ID=%d\n", 323 __func__, state->cfg.tuner); 324 ret = -ENODEV; 325 goto err; 326 } 327 328 for (i = 0; i < len; i++) { 329 ret = af9033_wr_reg(state, init[i].reg, init[i].val); 330 if (ret < 0) 331 goto err; 332 } 333 334 state->bandwidth_hz = 0; /* force to program all parameters */ 335 336 return 0; 337 338 err: 339 dev_dbg(&state->i2c->dev, "%s: failed=%d\n", __func__, ret); 340 341 return ret; 342 } 343 344 static int af9033_sleep(struct dvb_frontend *fe) 345 { 346 struct af9033_state *state = fe->demodulator_priv; 347 int ret, i; 348 u8 tmp; 349 350 ret = af9033_wr_reg(state, 0x80004c, 1); 351 if (ret < 0) 352 goto err; 353 354 ret = af9033_wr_reg(state, 0x800000, 0); 355 if (ret < 0) 356 goto err; 357 358 for (i = 100, tmp = 1; i && tmp; i--) { 359 ret = af9033_rd_reg(state, 0x80004c, &tmp); 360 if (ret < 0) 361 goto err; 362 363 usleep_range(200, 10000); 364 } 365 366 dev_dbg(&state->i2c->dev, "%s: loop=%d\n", __func__, i); 367 368 if (i == 0) { 369 ret = -ETIMEDOUT; 370 goto err; 371 } 372 373 ret = af9033_wr_reg_mask(state, 0x80fb24, 0x08, 0x08); 374 if (ret < 0) 375 goto err; 376 377 /* prevent current leak (?) */ 378 if (state->cfg.ts_mode == AF9033_TS_MODE_SERIAL) { 379 /* enable parallel TS */ 380 ret = af9033_wr_reg_mask(state, 0x00d917, 0x00, 0x01); 381 if (ret < 0) 382 goto err; 383 384 ret = af9033_wr_reg_mask(state, 0x00d916, 0x01, 0x01); 385 if (ret < 0) 386 goto err; 387 } 388 389 return 0; 390 391 err: 392 dev_dbg(&state->i2c->dev, "%s: failed=%d\n", __func__, ret); 393 394 return ret; 395 } 396 397 static int af9033_get_tune_settings(struct dvb_frontend *fe, 398 struct dvb_frontend_tune_settings *fesettings) 399 { 400 fesettings->min_delay_ms = 800; 401 fesettings->step_size = 0; 402 fesettings->max_drift = 0; 403 404 return 0; 405 } 406 407 static int af9033_set_frontend(struct dvb_frontend *fe) 408 { 409 struct af9033_state *state = fe->demodulator_priv; 410 struct dtv_frontend_properties *c = &fe->dtv_property_cache; 411 int ret, i, spec_inv, sampling_freq; 412 u8 tmp, buf[3], bandwidth_reg_val; 413 u32 if_frequency, freq_cw, adc_freq; 414 415 dev_dbg(&state->i2c->dev, "%s: frequency=%d bandwidth_hz=%d\n", 416 __func__, c->frequency, c->bandwidth_hz); 417 418 /* check bandwidth */ 419 switch (c->bandwidth_hz) { 420 case 6000000: 421 bandwidth_reg_val = 0x00; 422 break; 423 case 7000000: 424 bandwidth_reg_val = 0x01; 425 break; 426 case 8000000: 427 bandwidth_reg_val = 0x02; 428 break; 429 default: 430 dev_dbg(&state->i2c->dev, "%s: invalid bandwidth_hz\n", 431 __func__); 432 ret = -EINVAL; 433 goto err; 434 } 435 436 /* program tuner */ 437 if (fe->ops.tuner_ops.set_params) 438 fe->ops.tuner_ops.set_params(fe); 439 440 /* program CFOE coefficients */ 441 if (c->bandwidth_hz != state->bandwidth_hz) { 442 for (i = 0; i < ARRAY_SIZE(coeff_lut); i++) { 443 if (coeff_lut[i].clock == state->cfg.clock && 444 coeff_lut[i].bandwidth_hz == c->bandwidth_hz) { 445 break; 446 } 447 } 448 ret = af9033_wr_regs(state, 0x800001, 449 coeff_lut[i].val, sizeof(coeff_lut[i].val)); 450 } 451 452 /* program frequency control */ 453 if (c->bandwidth_hz != state->bandwidth_hz) { 454 spec_inv = state->cfg.spec_inv ? -1 : 1; 455 456 for (i = 0; i < ARRAY_SIZE(clock_adc_lut); i++) { 457 if (clock_adc_lut[i].clock == state->cfg.clock) 458 break; 459 } 460 adc_freq = clock_adc_lut[i].adc; 461 462 /* get used IF frequency */ 463 if (fe->ops.tuner_ops.get_if_frequency) 464 fe->ops.tuner_ops.get_if_frequency(fe, &if_frequency); 465 else 466 if_frequency = 0; 467 468 sampling_freq = if_frequency; 469 470 while (sampling_freq > (adc_freq / 2)) 471 sampling_freq -= adc_freq; 472 473 if (sampling_freq >= 0) 474 spec_inv *= -1; 475 else 476 sampling_freq *= -1; 477 478 freq_cw = af9033_div(state, sampling_freq, adc_freq, 23ul); 479 480 if (spec_inv == -1) 481 freq_cw = 0x800000 - freq_cw; 482 483 /* get adc multiplies */ 484 ret = af9033_rd_reg(state, 0x800045, &tmp); 485 if (ret < 0) 486 goto err; 487 488 if (tmp == 1) 489 freq_cw /= 2; 490 491 buf[0] = (freq_cw >> 0) & 0xff; 492 buf[1] = (freq_cw >> 8) & 0xff; 493 buf[2] = (freq_cw >> 16) & 0x7f; 494 ret = af9033_wr_regs(state, 0x800029, buf, 3); 495 if (ret < 0) 496 goto err; 497 498 state->bandwidth_hz = c->bandwidth_hz; 499 } 500 501 ret = af9033_wr_reg_mask(state, 0x80f904, bandwidth_reg_val, 0x03); 502 if (ret < 0) 503 goto err; 504 505 ret = af9033_wr_reg(state, 0x800040, 0x00); 506 if (ret < 0) 507 goto err; 508 509 ret = af9033_wr_reg(state, 0x800047, 0x00); 510 if (ret < 0) 511 goto err; 512 513 ret = af9033_wr_reg_mask(state, 0x80f999, 0x00, 0x01); 514 if (ret < 0) 515 goto err; 516 517 if (c->frequency <= 230000000) 518 tmp = 0x00; /* VHF */ 519 else 520 tmp = 0x01; /* UHF */ 521 522 ret = af9033_wr_reg(state, 0x80004b, tmp); 523 if (ret < 0) 524 goto err; 525 526 ret = af9033_wr_reg(state, 0x800000, 0x00); 527 if (ret < 0) 528 goto err; 529 530 return 0; 531 532 err: 533 dev_dbg(&state->i2c->dev, "%s: failed=%d\n", __func__, ret); 534 535 return ret; 536 } 537 538 static int af9033_get_frontend(struct dvb_frontend *fe) 539 { 540 struct af9033_state *state = fe->demodulator_priv; 541 struct dtv_frontend_properties *c = &fe->dtv_property_cache; 542 int ret; 543 u8 buf[8]; 544 545 dev_dbg(&state->i2c->dev, "%s:\n", __func__); 546 547 /* read all needed registers */ 548 ret = af9033_rd_regs(state, 0x80f900, buf, sizeof(buf)); 549 if (ret < 0) 550 goto err; 551 552 switch ((buf[0] >> 0) & 3) { 553 case 0: 554 c->transmission_mode = TRANSMISSION_MODE_2K; 555 break; 556 case 1: 557 c->transmission_mode = TRANSMISSION_MODE_8K; 558 break; 559 } 560 561 switch ((buf[1] >> 0) & 3) { 562 case 0: 563 c->guard_interval = GUARD_INTERVAL_1_32; 564 break; 565 case 1: 566 c->guard_interval = GUARD_INTERVAL_1_16; 567 break; 568 case 2: 569 c->guard_interval = GUARD_INTERVAL_1_8; 570 break; 571 case 3: 572 c->guard_interval = GUARD_INTERVAL_1_4; 573 break; 574 } 575 576 switch ((buf[2] >> 0) & 7) { 577 case 0: 578 c->hierarchy = HIERARCHY_NONE; 579 break; 580 case 1: 581 c->hierarchy = HIERARCHY_1; 582 break; 583 case 2: 584 c->hierarchy = HIERARCHY_2; 585 break; 586 case 3: 587 c->hierarchy = HIERARCHY_4; 588 break; 589 } 590 591 switch ((buf[3] >> 0) & 3) { 592 case 0: 593 c->modulation = QPSK; 594 break; 595 case 1: 596 c->modulation = QAM_16; 597 break; 598 case 2: 599 c->modulation = QAM_64; 600 break; 601 } 602 603 switch ((buf[4] >> 0) & 3) { 604 case 0: 605 c->bandwidth_hz = 6000000; 606 break; 607 case 1: 608 c->bandwidth_hz = 7000000; 609 break; 610 case 2: 611 c->bandwidth_hz = 8000000; 612 break; 613 } 614 615 switch ((buf[6] >> 0) & 7) { 616 case 0: 617 c->code_rate_HP = FEC_1_2; 618 break; 619 case 1: 620 c->code_rate_HP = FEC_2_3; 621 break; 622 case 2: 623 c->code_rate_HP = FEC_3_4; 624 break; 625 case 3: 626 c->code_rate_HP = FEC_5_6; 627 break; 628 case 4: 629 c->code_rate_HP = FEC_7_8; 630 break; 631 case 5: 632 c->code_rate_HP = FEC_NONE; 633 break; 634 } 635 636 switch ((buf[7] >> 0) & 7) { 637 case 0: 638 c->code_rate_LP = FEC_1_2; 639 break; 640 case 1: 641 c->code_rate_LP = FEC_2_3; 642 break; 643 case 2: 644 c->code_rate_LP = FEC_3_4; 645 break; 646 case 3: 647 c->code_rate_LP = FEC_5_6; 648 break; 649 case 4: 650 c->code_rate_LP = FEC_7_8; 651 break; 652 case 5: 653 c->code_rate_LP = FEC_NONE; 654 break; 655 } 656 657 return 0; 658 659 err: 660 dev_dbg(&state->i2c->dev, "%s: failed=%d\n", __func__, ret); 661 662 return ret; 663 } 664 665 static int af9033_read_status(struct dvb_frontend *fe, fe_status_t *status) 666 { 667 struct af9033_state *state = fe->demodulator_priv; 668 int ret; 669 u8 tmp; 670 671 *status = 0; 672 673 /* radio channel status, 0=no result, 1=has signal, 2=no signal */ 674 ret = af9033_rd_reg(state, 0x800047, &tmp); 675 if (ret < 0) 676 goto err; 677 678 /* has signal */ 679 if (tmp == 0x01) 680 *status |= FE_HAS_SIGNAL; 681 682 if (tmp != 0x02) { 683 /* TPS lock */ 684 ret = af9033_rd_reg_mask(state, 0x80f5a9, &tmp, 0x01); 685 if (ret < 0) 686 goto err; 687 688 if (tmp) 689 *status |= FE_HAS_SIGNAL | FE_HAS_CARRIER | 690 FE_HAS_VITERBI; 691 692 /* full lock */ 693 ret = af9033_rd_reg_mask(state, 0x80f999, &tmp, 0x01); 694 if (ret < 0) 695 goto err; 696 697 if (tmp) 698 *status |= FE_HAS_SIGNAL | FE_HAS_CARRIER | 699 FE_HAS_VITERBI | FE_HAS_SYNC | 700 FE_HAS_LOCK; 701 } 702 703 return 0; 704 705 err: 706 dev_dbg(&state->i2c->dev, "%s: failed=%d\n", __func__, ret); 707 708 return ret; 709 } 710 711 static int af9033_read_snr(struct dvb_frontend *fe, u16 *snr) 712 { 713 struct af9033_state *state = fe->demodulator_priv; 714 int ret, i, len; 715 u8 buf[3], tmp; 716 u32 snr_val; 717 const struct val_snr *uninitialized_var(snr_lut); 718 719 /* read value */ 720 ret = af9033_rd_regs(state, 0x80002c, buf, 3); 721 if (ret < 0) 722 goto err; 723 724 snr_val = (buf[2] << 16) | (buf[1] << 8) | buf[0]; 725 726 /* read current modulation */ 727 ret = af9033_rd_reg(state, 0x80f903, &tmp); 728 if (ret < 0) 729 goto err; 730 731 switch ((tmp >> 0) & 3) { 732 case 0: 733 len = ARRAY_SIZE(qpsk_snr_lut); 734 snr_lut = qpsk_snr_lut; 735 break; 736 case 1: 737 len = ARRAY_SIZE(qam16_snr_lut); 738 snr_lut = qam16_snr_lut; 739 break; 740 case 2: 741 len = ARRAY_SIZE(qam64_snr_lut); 742 snr_lut = qam64_snr_lut; 743 break; 744 default: 745 goto err; 746 } 747 748 for (i = 0; i < len; i++) { 749 tmp = snr_lut[i].snr; 750 751 if (snr_val < snr_lut[i].val) 752 break; 753 } 754 755 *snr = tmp * 10; /* dB/10 */ 756 757 return 0; 758 759 err: 760 dev_dbg(&state->i2c->dev, "%s: failed=%d\n", __func__, ret); 761 762 return ret; 763 } 764 765 static int af9033_read_signal_strength(struct dvb_frontend *fe, u16 *strength) 766 { 767 struct af9033_state *state = fe->demodulator_priv; 768 int ret; 769 u8 strength2; 770 771 /* read signal strength of 0-100 scale */ 772 ret = af9033_rd_reg(state, 0x800048, &strength2); 773 if (ret < 0) 774 goto err; 775 776 /* scale value to 0x0000-0xffff */ 777 *strength = strength2 * 0xffff / 100; 778 779 return 0; 780 781 err: 782 dev_dbg(&state->i2c->dev, "%s: failed=%d\n", __func__, ret); 783 784 return ret; 785 } 786 787 static int af9033_update_ch_stat(struct af9033_state *state) 788 { 789 int ret = 0; 790 u32 err_cnt, bit_cnt; 791 u16 abort_cnt; 792 u8 buf[7]; 793 794 /* only update data every half second */ 795 if (time_after(jiffies, state->last_stat_check + msecs_to_jiffies(500))) { 796 ret = af9033_rd_regs(state, 0x800032, buf, sizeof(buf)); 797 if (ret < 0) 798 goto err; 799 /* in 8 byte packets? */ 800 abort_cnt = (buf[1] << 8) + buf[0]; 801 /* in bits */ 802 err_cnt = (buf[4] << 16) + (buf[3] << 8) + buf[2]; 803 /* in 8 byte packets? always(?) 0x2710 = 10000 */ 804 bit_cnt = (buf[6] << 8) + buf[5]; 805 806 if (bit_cnt < abort_cnt) { 807 abort_cnt = 1000; 808 state->ber = 0xffffffff; 809 } else { 810 /* 8 byte packets, that have not been rejected already */ 811 bit_cnt -= (u32)abort_cnt; 812 if (bit_cnt == 0) { 813 state->ber = 0xffffffff; 814 } else { 815 err_cnt -= (u32)abort_cnt * 8 * 8; 816 bit_cnt *= 8 * 8; 817 state->ber = err_cnt * (0xffffffff / bit_cnt); 818 } 819 } 820 state->ucb += abort_cnt; 821 state->last_stat_check = jiffies; 822 } 823 824 return 0; 825 err: 826 dev_dbg(&state->i2c->dev, "%s: failed=%d\n", __func__, ret); 827 828 return ret; 829 } 830 831 static int af9033_read_ber(struct dvb_frontend *fe, u32 *ber) 832 { 833 struct af9033_state *state = fe->demodulator_priv; 834 int ret; 835 836 ret = af9033_update_ch_stat(state); 837 if (ret < 0) 838 return ret; 839 840 *ber = state->ber; 841 842 return 0; 843 } 844 845 static int af9033_read_ucblocks(struct dvb_frontend *fe, u32 *ucblocks) 846 { 847 struct af9033_state *state = fe->demodulator_priv; 848 int ret; 849 850 ret = af9033_update_ch_stat(state); 851 if (ret < 0) 852 return ret; 853 854 *ucblocks = state->ucb; 855 856 return 0; 857 } 858 859 static int af9033_i2c_gate_ctrl(struct dvb_frontend *fe, int enable) 860 { 861 struct af9033_state *state = fe->demodulator_priv; 862 int ret; 863 864 dev_dbg(&state->i2c->dev, "%s: enable=%d\n", __func__, enable); 865 866 ret = af9033_wr_reg_mask(state, 0x00fa04, enable, 0x01); 867 if (ret < 0) 868 goto err; 869 870 return 0; 871 872 err: 873 dev_dbg(&state->i2c->dev, "%s: failed=%d\n", __func__, ret); 874 875 return ret; 876 } 877 878 static struct dvb_frontend_ops af9033_ops; 879 880 struct dvb_frontend *af9033_attach(const struct af9033_config *config, 881 struct i2c_adapter *i2c) 882 { 883 int ret; 884 struct af9033_state *state; 885 u8 buf[8]; 886 887 dev_dbg(&i2c->dev, "%s:\n", __func__); 888 889 /* allocate memory for the internal state */ 890 state = kzalloc(sizeof(struct af9033_state), GFP_KERNEL); 891 if (state == NULL) 892 goto err; 893 894 /* setup the state */ 895 state->i2c = i2c; 896 memcpy(&state->cfg, config, sizeof(struct af9033_config)); 897 898 if (state->cfg.clock != 12000000) { 899 dev_err(&state->i2c->dev, "%s: af9033: unsupported clock=%d, " \ 900 "only 12000000 Hz is supported currently\n", 901 KBUILD_MODNAME, state->cfg.clock); 902 goto err; 903 } 904 905 /* firmware version */ 906 ret = af9033_rd_regs(state, 0x0083e9, &buf[0], 4); 907 if (ret < 0) 908 goto err; 909 910 ret = af9033_rd_regs(state, 0x804191, &buf[4], 4); 911 if (ret < 0) 912 goto err; 913 914 dev_info(&state->i2c->dev, "%s: firmware version: LINK=%d.%d.%d.%d " \ 915 "OFDM=%d.%d.%d.%d\n", KBUILD_MODNAME, buf[0], buf[1], 916 buf[2], buf[3], buf[4], buf[5], buf[6], buf[7]); 917 918 /* sleep */ 919 ret = af9033_wr_reg(state, 0x80004c, 1); 920 if (ret < 0) 921 goto err; 922 923 ret = af9033_wr_reg(state, 0x800000, 0); 924 if (ret < 0) 925 goto err; 926 927 /* configure internal TS mode */ 928 switch (state->cfg.ts_mode) { 929 case AF9033_TS_MODE_PARALLEL: 930 state->ts_mode_parallel = true; 931 break; 932 case AF9033_TS_MODE_SERIAL: 933 state->ts_mode_serial = true; 934 break; 935 case AF9033_TS_MODE_USB: 936 /* usb mode for AF9035 */ 937 default: 938 break; 939 } 940 941 /* create dvb_frontend */ 942 memcpy(&state->fe.ops, &af9033_ops, sizeof(struct dvb_frontend_ops)); 943 state->fe.demodulator_priv = state; 944 945 return &state->fe; 946 947 err: 948 kfree(state); 949 return NULL; 950 } 951 EXPORT_SYMBOL(af9033_attach); 952 953 static struct dvb_frontend_ops af9033_ops = { 954 .delsys = { SYS_DVBT }, 955 .info = { 956 .name = "Afatech AF9033 (DVB-T)", 957 .frequency_min = 174000000, 958 .frequency_max = 862000000, 959 .frequency_stepsize = 250000, 960 .frequency_tolerance = 0, 961 .caps = FE_CAN_FEC_1_2 | 962 FE_CAN_FEC_2_3 | 963 FE_CAN_FEC_3_4 | 964 FE_CAN_FEC_5_6 | 965 FE_CAN_FEC_7_8 | 966 FE_CAN_FEC_AUTO | 967 FE_CAN_QPSK | 968 FE_CAN_QAM_16 | 969 FE_CAN_QAM_64 | 970 FE_CAN_QAM_AUTO | 971 FE_CAN_TRANSMISSION_MODE_AUTO | 972 FE_CAN_GUARD_INTERVAL_AUTO | 973 FE_CAN_HIERARCHY_AUTO | 974 FE_CAN_RECOVER | 975 FE_CAN_MUTE_TS 976 }, 977 978 .release = af9033_release, 979 980 .init = af9033_init, 981 .sleep = af9033_sleep, 982 983 .get_tune_settings = af9033_get_tune_settings, 984 .set_frontend = af9033_set_frontend, 985 .get_frontend = af9033_get_frontend, 986 987 .read_status = af9033_read_status, 988 .read_snr = af9033_read_snr, 989 .read_signal_strength = af9033_read_signal_strength, 990 .read_ber = af9033_read_ber, 991 .read_ucblocks = af9033_read_ucblocks, 992 993 .i2c_gate_ctrl = af9033_i2c_gate_ctrl, 994 }; 995 996 MODULE_AUTHOR("Antti Palosaari <crope@iki.fi>"); 997 MODULE_DESCRIPTION("Afatech AF9033 DVB-T demodulator driver"); 998 MODULE_LICENSE("GPL"); 999