1 /* 2 * Afatech AF9033 demodulator driver 3 * 4 * Copyright (C) 2009 Antti Palosaari <crope@iki.fi> 5 * Copyright (C) 2012 Antti Palosaari <crope@iki.fi> 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License as published by 9 * the Free Software Foundation; either version 2 of the License, or 10 * (at your option) any later version. 11 * 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 * 17 * You should have received a copy of the GNU General Public License along 18 * with this program; if not, write to the Free Software Foundation, Inc., 19 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. 20 */ 21 22 #include "af9033_priv.h" 23 24 /* Max transfer size done by I2C transfer functions */ 25 #define MAX_XFER_SIZE 64 26 27 struct af9033_state { 28 struct i2c_adapter *i2c; 29 struct dvb_frontend fe; 30 struct af9033_config cfg; 31 32 u32 bandwidth_hz; 33 bool ts_mode_parallel; 34 bool ts_mode_serial; 35 36 u32 ber; 37 u32 ucb; 38 unsigned long last_stat_check; 39 }; 40 41 /* write multiple registers */ 42 static int af9033_wr_regs(struct af9033_state *state, u32 reg, const u8 *val, 43 int len) 44 { 45 int ret; 46 u8 buf[MAX_XFER_SIZE]; 47 struct i2c_msg msg[1] = { 48 { 49 .addr = state->cfg.i2c_addr, 50 .flags = 0, 51 .len = 3 + len, 52 .buf = buf, 53 } 54 }; 55 56 if (3 + len > sizeof(buf)) { 57 dev_warn(&state->i2c->dev, 58 "%s: i2c wr reg=%04x: len=%d is too big!\n", 59 KBUILD_MODNAME, reg, len); 60 return -EINVAL; 61 } 62 63 buf[0] = (reg >> 16) & 0xff; 64 buf[1] = (reg >> 8) & 0xff; 65 buf[2] = (reg >> 0) & 0xff; 66 memcpy(&buf[3], val, len); 67 68 ret = i2c_transfer(state->i2c, msg, 1); 69 if (ret == 1) { 70 ret = 0; 71 } else { 72 dev_warn(&state->i2c->dev, "%s: i2c wr failed=%d reg=%06x " \ 73 "len=%d\n", KBUILD_MODNAME, ret, reg, len); 74 ret = -EREMOTEIO; 75 } 76 77 return ret; 78 } 79 80 /* read multiple registers */ 81 static int af9033_rd_regs(struct af9033_state *state, u32 reg, u8 *val, int len) 82 { 83 int ret; 84 u8 buf[3] = { (reg >> 16) & 0xff, (reg >> 8) & 0xff, 85 (reg >> 0) & 0xff }; 86 struct i2c_msg msg[2] = { 87 { 88 .addr = state->cfg.i2c_addr, 89 .flags = 0, 90 .len = sizeof(buf), 91 .buf = buf 92 }, { 93 .addr = state->cfg.i2c_addr, 94 .flags = I2C_M_RD, 95 .len = len, 96 .buf = val 97 } 98 }; 99 100 ret = i2c_transfer(state->i2c, msg, 2); 101 if (ret == 2) { 102 ret = 0; 103 } else { 104 dev_warn(&state->i2c->dev, "%s: i2c rd failed=%d reg=%06x " \ 105 "len=%d\n", KBUILD_MODNAME, ret, reg, len); 106 ret = -EREMOTEIO; 107 } 108 109 return ret; 110 } 111 112 113 /* write single register */ 114 static int af9033_wr_reg(struct af9033_state *state, u32 reg, u8 val) 115 { 116 return af9033_wr_regs(state, reg, &val, 1); 117 } 118 119 /* read single register */ 120 static int af9033_rd_reg(struct af9033_state *state, u32 reg, u8 *val) 121 { 122 return af9033_rd_regs(state, reg, val, 1); 123 } 124 125 /* write single register with mask */ 126 static int af9033_wr_reg_mask(struct af9033_state *state, u32 reg, u8 val, 127 u8 mask) 128 { 129 int ret; 130 u8 tmp; 131 132 /* no need for read if whole reg is written */ 133 if (mask != 0xff) { 134 ret = af9033_rd_regs(state, reg, &tmp, 1); 135 if (ret) 136 return ret; 137 138 val &= mask; 139 tmp &= ~mask; 140 val |= tmp; 141 } 142 143 return af9033_wr_regs(state, reg, &val, 1); 144 } 145 146 /* read single register with mask */ 147 static int af9033_rd_reg_mask(struct af9033_state *state, u32 reg, u8 *val, 148 u8 mask) 149 { 150 int ret, i; 151 u8 tmp; 152 153 ret = af9033_rd_regs(state, reg, &tmp, 1); 154 if (ret) 155 return ret; 156 157 tmp &= mask; 158 159 /* find position of the first bit */ 160 for (i = 0; i < 8; i++) { 161 if ((mask >> i) & 0x01) 162 break; 163 } 164 *val = tmp >> i; 165 166 return 0; 167 } 168 169 /* write reg val table using reg addr auto increment */ 170 static int af9033_wr_reg_val_tab(struct af9033_state *state, 171 const struct reg_val *tab, int tab_len) 172 { 173 #define MAX_TAB_LEN 212 174 int ret, i, j; 175 u8 buf[1 + MAX_TAB_LEN]; 176 177 dev_dbg(&state->i2c->dev, "%s: tab_len=%d\n", __func__, tab_len); 178 179 if (tab_len > sizeof(buf)) { 180 dev_warn(&state->i2c->dev, "%s: tab len %d is too big\n", 181 KBUILD_MODNAME, tab_len); 182 return -EINVAL; 183 } 184 185 for (i = 0, j = 0; i < tab_len; i++) { 186 buf[j] = tab[i].val; 187 188 if (i == tab_len - 1 || tab[i].reg != tab[i + 1].reg - 1) { 189 ret = af9033_wr_regs(state, tab[i].reg - j, buf, j + 1); 190 if (ret < 0) 191 goto err; 192 193 j = 0; 194 } else { 195 j++; 196 } 197 } 198 199 return 0; 200 201 err: 202 dev_dbg(&state->i2c->dev, "%s: failed=%d\n", __func__, ret); 203 204 return ret; 205 } 206 207 static u32 af9033_div(struct af9033_state *state, u32 a, u32 b, u32 x) 208 { 209 u32 r = 0, c = 0, i; 210 211 dev_dbg(&state->i2c->dev, "%s: a=%d b=%d x=%d\n", __func__, a, b, x); 212 213 if (a > b) { 214 c = a / b; 215 a = a - c * b; 216 } 217 218 for (i = 0; i < x; i++) { 219 if (a >= b) { 220 r += 1; 221 a -= b; 222 } 223 a <<= 1; 224 r <<= 1; 225 } 226 r = (c << (u32)x) + r; 227 228 dev_dbg(&state->i2c->dev, "%s: a=%d b=%d x=%d r=%d r=%x\n", 229 __func__, a, b, x, r, r); 230 231 return r; 232 } 233 234 static void af9033_release(struct dvb_frontend *fe) 235 { 236 struct af9033_state *state = fe->demodulator_priv; 237 238 kfree(state); 239 } 240 241 static int af9033_init(struct dvb_frontend *fe) 242 { 243 struct af9033_state *state = fe->demodulator_priv; 244 int ret, i, len; 245 const struct reg_val *init; 246 u8 buf[4]; 247 u32 adc_cw, clock_cw; 248 struct reg_val_mask tab[] = { 249 { 0x80fb24, 0x00, 0x08 }, 250 { 0x80004c, 0x00, 0xff }, 251 { 0x00f641, state->cfg.tuner, 0xff }, 252 { 0x80f5ca, 0x01, 0x01 }, 253 { 0x80f715, 0x01, 0x01 }, 254 { 0x00f41f, 0x04, 0x04 }, 255 { 0x00f41a, 0x01, 0x01 }, 256 { 0x80f731, 0x00, 0x01 }, 257 { 0x00d91e, 0x00, 0x01 }, 258 { 0x00d919, 0x00, 0x01 }, 259 { 0x80f732, 0x00, 0x01 }, 260 { 0x00d91f, 0x00, 0x01 }, 261 { 0x00d91a, 0x00, 0x01 }, 262 { 0x80f730, 0x00, 0x01 }, 263 { 0x80f778, 0x00, 0xff }, 264 { 0x80f73c, 0x01, 0x01 }, 265 { 0x80f776, 0x00, 0x01 }, 266 { 0x00d8fd, 0x01, 0xff }, 267 { 0x00d830, 0x01, 0xff }, 268 { 0x00d831, 0x00, 0xff }, 269 { 0x00d832, 0x00, 0xff }, 270 { 0x80f985, state->ts_mode_serial, 0x01 }, 271 { 0x80f986, state->ts_mode_parallel, 0x01 }, 272 { 0x00d827, 0x00, 0xff }, 273 { 0x00d829, 0x00, 0xff }, 274 { 0x800045, state->cfg.adc_multiplier, 0xff }, 275 }; 276 277 /* program clock control */ 278 clock_cw = af9033_div(state, state->cfg.clock, 1000000ul, 19ul); 279 buf[0] = (clock_cw >> 0) & 0xff; 280 buf[1] = (clock_cw >> 8) & 0xff; 281 buf[2] = (clock_cw >> 16) & 0xff; 282 buf[3] = (clock_cw >> 24) & 0xff; 283 284 dev_dbg(&state->i2c->dev, "%s: clock=%d clock_cw=%08x\n", 285 __func__, state->cfg.clock, clock_cw); 286 287 ret = af9033_wr_regs(state, 0x800025, buf, 4); 288 if (ret < 0) 289 goto err; 290 291 /* program ADC control */ 292 for (i = 0; i < ARRAY_SIZE(clock_adc_lut); i++) { 293 if (clock_adc_lut[i].clock == state->cfg.clock) 294 break; 295 } 296 297 adc_cw = af9033_div(state, clock_adc_lut[i].adc, 1000000ul, 19ul); 298 buf[0] = (adc_cw >> 0) & 0xff; 299 buf[1] = (adc_cw >> 8) & 0xff; 300 buf[2] = (adc_cw >> 16) & 0xff; 301 302 dev_dbg(&state->i2c->dev, "%s: adc=%d adc_cw=%06x\n", 303 __func__, clock_adc_lut[i].adc, adc_cw); 304 305 ret = af9033_wr_regs(state, 0x80f1cd, buf, 3); 306 if (ret < 0) 307 goto err; 308 309 /* program register table */ 310 for (i = 0; i < ARRAY_SIZE(tab); i++) { 311 ret = af9033_wr_reg_mask(state, tab[i].reg, tab[i].val, 312 tab[i].mask); 313 if (ret < 0) 314 goto err; 315 } 316 317 /* feed clock to RF tuner */ 318 switch (state->cfg.tuner) { 319 case AF9033_TUNER_IT9135_38: 320 case AF9033_TUNER_IT9135_51: 321 case AF9033_TUNER_IT9135_52: 322 case AF9033_TUNER_IT9135_60: 323 case AF9033_TUNER_IT9135_61: 324 case AF9033_TUNER_IT9135_62: 325 ret = af9033_wr_reg(state, 0x80fba8, 0x00); 326 if (ret < 0) 327 goto err; 328 } 329 330 /* settings for TS interface */ 331 if (state->cfg.ts_mode == AF9033_TS_MODE_USB) { 332 ret = af9033_wr_reg_mask(state, 0x80f9a5, 0x00, 0x01); 333 if (ret < 0) 334 goto err; 335 336 ret = af9033_wr_reg_mask(state, 0x80f9b5, 0x01, 0x01); 337 if (ret < 0) 338 goto err; 339 } else { 340 ret = af9033_wr_reg_mask(state, 0x80f990, 0x00, 0x01); 341 if (ret < 0) 342 goto err; 343 344 ret = af9033_wr_reg_mask(state, 0x80f9b5, 0x00, 0x01); 345 if (ret < 0) 346 goto err; 347 } 348 349 /* load OFSM settings */ 350 dev_dbg(&state->i2c->dev, "%s: load ofsm settings\n", __func__); 351 switch (state->cfg.tuner) { 352 case AF9033_TUNER_IT9135_38: 353 case AF9033_TUNER_IT9135_51: 354 case AF9033_TUNER_IT9135_52: 355 len = ARRAY_SIZE(ofsm_init_it9135_v1); 356 init = ofsm_init_it9135_v1; 357 break; 358 case AF9033_TUNER_IT9135_60: 359 case AF9033_TUNER_IT9135_61: 360 case AF9033_TUNER_IT9135_62: 361 len = ARRAY_SIZE(ofsm_init_it9135_v2); 362 init = ofsm_init_it9135_v2; 363 break; 364 default: 365 len = ARRAY_SIZE(ofsm_init); 366 init = ofsm_init; 367 break; 368 } 369 370 ret = af9033_wr_reg_val_tab(state, init, len); 371 if (ret < 0) 372 goto err; 373 374 /* load tuner specific settings */ 375 dev_dbg(&state->i2c->dev, "%s: load tuner specific settings\n", 376 __func__); 377 switch (state->cfg.tuner) { 378 case AF9033_TUNER_TUA9001: 379 len = ARRAY_SIZE(tuner_init_tua9001); 380 init = tuner_init_tua9001; 381 break; 382 case AF9033_TUNER_FC0011: 383 len = ARRAY_SIZE(tuner_init_fc0011); 384 init = tuner_init_fc0011; 385 break; 386 case AF9033_TUNER_MXL5007T: 387 len = ARRAY_SIZE(tuner_init_mxl5007t); 388 init = tuner_init_mxl5007t; 389 break; 390 case AF9033_TUNER_TDA18218: 391 len = ARRAY_SIZE(tuner_init_tda18218); 392 init = tuner_init_tda18218; 393 break; 394 case AF9033_TUNER_FC2580: 395 len = ARRAY_SIZE(tuner_init_fc2580); 396 init = tuner_init_fc2580; 397 break; 398 case AF9033_TUNER_FC0012: 399 len = ARRAY_SIZE(tuner_init_fc0012); 400 init = tuner_init_fc0012; 401 break; 402 case AF9033_TUNER_IT9135_38: 403 len = ARRAY_SIZE(tuner_init_it9135_38); 404 init = tuner_init_it9135_38; 405 break; 406 case AF9033_TUNER_IT9135_51: 407 len = ARRAY_SIZE(tuner_init_it9135_51); 408 init = tuner_init_it9135_51; 409 break; 410 case AF9033_TUNER_IT9135_52: 411 len = ARRAY_SIZE(tuner_init_it9135_52); 412 init = tuner_init_it9135_52; 413 break; 414 case AF9033_TUNER_IT9135_60: 415 len = ARRAY_SIZE(tuner_init_it9135_60); 416 init = tuner_init_it9135_60; 417 break; 418 case AF9033_TUNER_IT9135_61: 419 len = ARRAY_SIZE(tuner_init_it9135_61); 420 init = tuner_init_it9135_61; 421 break; 422 case AF9033_TUNER_IT9135_62: 423 len = ARRAY_SIZE(tuner_init_it9135_62); 424 init = tuner_init_it9135_62; 425 break; 426 default: 427 dev_dbg(&state->i2c->dev, "%s: unsupported tuner ID=%d\n", 428 __func__, state->cfg.tuner); 429 ret = -ENODEV; 430 goto err; 431 } 432 433 ret = af9033_wr_reg_val_tab(state, init, len); 434 if (ret < 0) 435 goto err; 436 437 if (state->cfg.ts_mode == AF9033_TS_MODE_SERIAL) { 438 ret = af9033_wr_reg_mask(state, 0x00d91c, 0x01, 0x01); 439 if (ret < 0) 440 goto err; 441 442 ret = af9033_wr_reg_mask(state, 0x00d917, 0x00, 0x01); 443 if (ret < 0) 444 goto err; 445 446 ret = af9033_wr_reg_mask(state, 0x00d916, 0x00, 0x01); 447 if (ret < 0) 448 goto err; 449 } 450 451 switch (state->cfg.tuner) { 452 case AF9033_TUNER_IT9135_60: 453 case AF9033_TUNER_IT9135_61: 454 case AF9033_TUNER_IT9135_62: 455 ret = af9033_wr_reg(state, 0x800000, 0x01); 456 if (ret < 0) 457 goto err; 458 } 459 460 state->bandwidth_hz = 0; /* force to program all parameters */ 461 462 return 0; 463 464 err: 465 dev_dbg(&state->i2c->dev, "%s: failed=%d\n", __func__, ret); 466 467 return ret; 468 } 469 470 static int af9033_sleep(struct dvb_frontend *fe) 471 { 472 struct af9033_state *state = fe->demodulator_priv; 473 int ret, i; 474 u8 tmp; 475 476 ret = af9033_wr_reg(state, 0x80004c, 1); 477 if (ret < 0) 478 goto err; 479 480 ret = af9033_wr_reg(state, 0x800000, 0); 481 if (ret < 0) 482 goto err; 483 484 for (i = 100, tmp = 1; i && tmp; i--) { 485 ret = af9033_rd_reg(state, 0x80004c, &tmp); 486 if (ret < 0) 487 goto err; 488 489 usleep_range(200, 10000); 490 } 491 492 dev_dbg(&state->i2c->dev, "%s: loop=%d\n", __func__, i); 493 494 if (i == 0) { 495 ret = -ETIMEDOUT; 496 goto err; 497 } 498 499 ret = af9033_wr_reg_mask(state, 0x80fb24, 0x08, 0x08); 500 if (ret < 0) 501 goto err; 502 503 /* prevent current leak (?) */ 504 if (state->cfg.ts_mode == AF9033_TS_MODE_SERIAL) { 505 /* enable parallel TS */ 506 ret = af9033_wr_reg_mask(state, 0x00d917, 0x00, 0x01); 507 if (ret < 0) 508 goto err; 509 510 ret = af9033_wr_reg_mask(state, 0x00d916, 0x01, 0x01); 511 if (ret < 0) 512 goto err; 513 } 514 515 return 0; 516 517 err: 518 dev_dbg(&state->i2c->dev, "%s: failed=%d\n", __func__, ret); 519 520 return ret; 521 } 522 523 static int af9033_get_tune_settings(struct dvb_frontend *fe, 524 struct dvb_frontend_tune_settings *fesettings) 525 { 526 /* 800 => 2000 because IT9135 v2 is slow to gain lock */ 527 fesettings->min_delay_ms = 2000; 528 fesettings->step_size = 0; 529 fesettings->max_drift = 0; 530 531 return 0; 532 } 533 534 static int af9033_set_frontend(struct dvb_frontend *fe) 535 { 536 struct af9033_state *state = fe->demodulator_priv; 537 struct dtv_frontend_properties *c = &fe->dtv_property_cache; 538 int ret, i, spec_inv, sampling_freq; 539 u8 tmp, buf[3], bandwidth_reg_val; 540 u32 if_frequency, freq_cw, adc_freq; 541 542 dev_dbg(&state->i2c->dev, "%s: frequency=%d bandwidth_hz=%d\n", 543 __func__, c->frequency, c->bandwidth_hz); 544 545 /* check bandwidth */ 546 switch (c->bandwidth_hz) { 547 case 6000000: 548 bandwidth_reg_val = 0x00; 549 break; 550 case 7000000: 551 bandwidth_reg_val = 0x01; 552 break; 553 case 8000000: 554 bandwidth_reg_val = 0x02; 555 break; 556 default: 557 dev_dbg(&state->i2c->dev, "%s: invalid bandwidth_hz\n", 558 __func__); 559 ret = -EINVAL; 560 goto err; 561 } 562 563 /* program tuner */ 564 if (fe->ops.tuner_ops.set_params) 565 fe->ops.tuner_ops.set_params(fe); 566 567 /* program CFOE coefficients */ 568 if (c->bandwidth_hz != state->bandwidth_hz) { 569 for (i = 0; i < ARRAY_SIZE(coeff_lut); i++) { 570 if (coeff_lut[i].clock == state->cfg.clock && 571 coeff_lut[i].bandwidth_hz == c->bandwidth_hz) { 572 break; 573 } 574 } 575 ret = af9033_wr_regs(state, 0x800001, 576 coeff_lut[i].val, sizeof(coeff_lut[i].val)); 577 } 578 579 /* program frequency control */ 580 if (c->bandwidth_hz != state->bandwidth_hz) { 581 spec_inv = state->cfg.spec_inv ? -1 : 1; 582 583 for (i = 0; i < ARRAY_SIZE(clock_adc_lut); i++) { 584 if (clock_adc_lut[i].clock == state->cfg.clock) 585 break; 586 } 587 adc_freq = clock_adc_lut[i].adc; 588 589 /* get used IF frequency */ 590 if (fe->ops.tuner_ops.get_if_frequency) 591 fe->ops.tuner_ops.get_if_frequency(fe, &if_frequency); 592 else 593 if_frequency = 0; 594 595 sampling_freq = if_frequency; 596 597 while (sampling_freq > (adc_freq / 2)) 598 sampling_freq -= adc_freq; 599 600 if (sampling_freq >= 0) 601 spec_inv *= -1; 602 else 603 sampling_freq *= -1; 604 605 freq_cw = af9033_div(state, sampling_freq, adc_freq, 23ul); 606 607 if (spec_inv == -1) 608 freq_cw = 0x800000 - freq_cw; 609 610 if (state->cfg.adc_multiplier == AF9033_ADC_MULTIPLIER_2X) 611 freq_cw /= 2; 612 613 buf[0] = (freq_cw >> 0) & 0xff; 614 buf[1] = (freq_cw >> 8) & 0xff; 615 buf[2] = (freq_cw >> 16) & 0x7f; 616 617 /* FIXME: there seems to be calculation error here... */ 618 if (if_frequency == 0) 619 buf[2] = 0; 620 621 ret = af9033_wr_regs(state, 0x800029, buf, 3); 622 if (ret < 0) 623 goto err; 624 625 state->bandwidth_hz = c->bandwidth_hz; 626 } 627 628 ret = af9033_wr_reg_mask(state, 0x80f904, bandwidth_reg_val, 0x03); 629 if (ret < 0) 630 goto err; 631 632 ret = af9033_wr_reg(state, 0x800040, 0x00); 633 if (ret < 0) 634 goto err; 635 636 ret = af9033_wr_reg(state, 0x800047, 0x00); 637 if (ret < 0) 638 goto err; 639 640 ret = af9033_wr_reg_mask(state, 0x80f999, 0x00, 0x01); 641 if (ret < 0) 642 goto err; 643 644 if (c->frequency <= 230000000) 645 tmp = 0x00; /* VHF */ 646 else 647 tmp = 0x01; /* UHF */ 648 649 ret = af9033_wr_reg(state, 0x80004b, tmp); 650 if (ret < 0) 651 goto err; 652 653 ret = af9033_wr_reg(state, 0x800000, 0x00); 654 if (ret < 0) 655 goto err; 656 657 return 0; 658 659 err: 660 dev_dbg(&state->i2c->dev, "%s: failed=%d\n", __func__, ret); 661 662 return ret; 663 } 664 665 static int af9033_get_frontend(struct dvb_frontend *fe) 666 { 667 struct af9033_state *state = fe->demodulator_priv; 668 struct dtv_frontend_properties *c = &fe->dtv_property_cache; 669 int ret; 670 u8 buf[8]; 671 672 dev_dbg(&state->i2c->dev, "%s:\n", __func__); 673 674 /* read all needed registers */ 675 ret = af9033_rd_regs(state, 0x80f900, buf, sizeof(buf)); 676 if (ret < 0) 677 goto err; 678 679 switch ((buf[0] >> 0) & 3) { 680 case 0: 681 c->transmission_mode = TRANSMISSION_MODE_2K; 682 break; 683 case 1: 684 c->transmission_mode = TRANSMISSION_MODE_8K; 685 break; 686 } 687 688 switch ((buf[1] >> 0) & 3) { 689 case 0: 690 c->guard_interval = GUARD_INTERVAL_1_32; 691 break; 692 case 1: 693 c->guard_interval = GUARD_INTERVAL_1_16; 694 break; 695 case 2: 696 c->guard_interval = GUARD_INTERVAL_1_8; 697 break; 698 case 3: 699 c->guard_interval = GUARD_INTERVAL_1_4; 700 break; 701 } 702 703 switch ((buf[2] >> 0) & 7) { 704 case 0: 705 c->hierarchy = HIERARCHY_NONE; 706 break; 707 case 1: 708 c->hierarchy = HIERARCHY_1; 709 break; 710 case 2: 711 c->hierarchy = HIERARCHY_2; 712 break; 713 case 3: 714 c->hierarchy = HIERARCHY_4; 715 break; 716 } 717 718 switch ((buf[3] >> 0) & 3) { 719 case 0: 720 c->modulation = QPSK; 721 break; 722 case 1: 723 c->modulation = QAM_16; 724 break; 725 case 2: 726 c->modulation = QAM_64; 727 break; 728 } 729 730 switch ((buf[4] >> 0) & 3) { 731 case 0: 732 c->bandwidth_hz = 6000000; 733 break; 734 case 1: 735 c->bandwidth_hz = 7000000; 736 break; 737 case 2: 738 c->bandwidth_hz = 8000000; 739 break; 740 } 741 742 switch ((buf[6] >> 0) & 7) { 743 case 0: 744 c->code_rate_HP = FEC_1_2; 745 break; 746 case 1: 747 c->code_rate_HP = FEC_2_3; 748 break; 749 case 2: 750 c->code_rate_HP = FEC_3_4; 751 break; 752 case 3: 753 c->code_rate_HP = FEC_5_6; 754 break; 755 case 4: 756 c->code_rate_HP = FEC_7_8; 757 break; 758 case 5: 759 c->code_rate_HP = FEC_NONE; 760 break; 761 } 762 763 switch ((buf[7] >> 0) & 7) { 764 case 0: 765 c->code_rate_LP = FEC_1_2; 766 break; 767 case 1: 768 c->code_rate_LP = FEC_2_3; 769 break; 770 case 2: 771 c->code_rate_LP = FEC_3_4; 772 break; 773 case 3: 774 c->code_rate_LP = FEC_5_6; 775 break; 776 case 4: 777 c->code_rate_LP = FEC_7_8; 778 break; 779 case 5: 780 c->code_rate_LP = FEC_NONE; 781 break; 782 } 783 784 return 0; 785 786 err: 787 dev_dbg(&state->i2c->dev, "%s: failed=%d\n", __func__, ret); 788 789 return ret; 790 } 791 792 static int af9033_read_status(struct dvb_frontend *fe, fe_status_t *status) 793 { 794 struct af9033_state *state = fe->demodulator_priv; 795 int ret; 796 u8 tmp; 797 798 *status = 0; 799 800 /* radio channel status, 0=no result, 1=has signal, 2=no signal */ 801 ret = af9033_rd_reg(state, 0x800047, &tmp); 802 if (ret < 0) 803 goto err; 804 805 /* has signal */ 806 if (tmp == 0x01) 807 *status |= FE_HAS_SIGNAL; 808 809 if (tmp != 0x02) { 810 /* TPS lock */ 811 ret = af9033_rd_reg_mask(state, 0x80f5a9, &tmp, 0x01); 812 if (ret < 0) 813 goto err; 814 815 if (tmp) 816 *status |= FE_HAS_SIGNAL | FE_HAS_CARRIER | 817 FE_HAS_VITERBI; 818 819 /* full lock */ 820 ret = af9033_rd_reg_mask(state, 0x80f999, &tmp, 0x01); 821 if (ret < 0) 822 goto err; 823 824 if (tmp) 825 *status |= FE_HAS_SIGNAL | FE_HAS_CARRIER | 826 FE_HAS_VITERBI | FE_HAS_SYNC | 827 FE_HAS_LOCK; 828 } 829 830 return 0; 831 832 err: 833 dev_dbg(&state->i2c->dev, "%s: failed=%d\n", __func__, ret); 834 835 return ret; 836 } 837 838 static int af9033_read_snr(struct dvb_frontend *fe, u16 *snr) 839 { 840 struct af9033_state *state = fe->demodulator_priv; 841 int ret, i, len; 842 u8 buf[3], tmp; 843 u32 snr_val; 844 const struct val_snr *uninitialized_var(snr_lut); 845 846 /* read value */ 847 ret = af9033_rd_regs(state, 0x80002c, buf, 3); 848 if (ret < 0) 849 goto err; 850 851 snr_val = (buf[2] << 16) | (buf[1] << 8) | buf[0]; 852 853 /* read current modulation */ 854 ret = af9033_rd_reg(state, 0x80f903, &tmp); 855 if (ret < 0) 856 goto err; 857 858 switch ((tmp >> 0) & 3) { 859 case 0: 860 len = ARRAY_SIZE(qpsk_snr_lut); 861 snr_lut = qpsk_snr_lut; 862 break; 863 case 1: 864 len = ARRAY_SIZE(qam16_snr_lut); 865 snr_lut = qam16_snr_lut; 866 break; 867 case 2: 868 len = ARRAY_SIZE(qam64_snr_lut); 869 snr_lut = qam64_snr_lut; 870 break; 871 default: 872 goto err; 873 } 874 875 for (i = 0; i < len; i++) { 876 tmp = snr_lut[i].snr; 877 878 if (snr_val < snr_lut[i].val) 879 break; 880 } 881 882 *snr = tmp * 10; /* dB/10 */ 883 884 return 0; 885 886 err: 887 dev_dbg(&state->i2c->dev, "%s: failed=%d\n", __func__, ret); 888 889 return ret; 890 } 891 892 static int af9033_read_signal_strength(struct dvb_frontend *fe, u16 *strength) 893 { 894 struct af9033_state *state = fe->demodulator_priv; 895 int ret; 896 u8 strength2; 897 898 /* read signal strength of 0-100 scale */ 899 ret = af9033_rd_reg(state, 0x800048, &strength2); 900 if (ret < 0) 901 goto err; 902 903 /* scale value to 0x0000-0xffff */ 904 *strength = strength2 * 0xffff / 100; 905 906 return 0; 907 908 err: 909 dev_dbg(&state->i2c->dev, "%s: failed=%d\n", __func__, ret); 910 911 return ret; 912 } 913 914 static int af9033_update_ch_stat(struct af9033_state *state) 915 { 916 int ret = 0; 917 u32 err_cnt, bit_cnt; 918 u16 abort_cnt; 919 u8 buf[7]; 920 921 /* only update data every half second */ 922 if (time_after(jiffies, state->last_stat_check + msecs_to_jiffies(500))) { 923 ret = af9033_rd_regs(state, 0x800032, buf, sizeof(buf)); 924 if (ret < 0) 925 goto err; 926 /* in 8 byte packets? */ 927 abort_cnt = (buf[1] << 8) + buf[0]; 928 /* in bits */ 929 err_cnt = (buf[4] << 16) + (buf[3] << 8) + buf[2]; 930 /* in 8 byte packets? always(?) 0x2710 = 10000 */ 931 bit_cnt = (buf[6] << 8) + buf[5]; 932 933 if (bit_cnt < abort_cnt) { 934 abort_cnt = 1000; 935 state->ber = 0xffffffff; 936 } else { 937 /* 8 byte packets, that have not been rejected already */ 938 bit_cnt -= (u32)abort_cnt; 939 if (bit_cnt == 0) { 940 state->ber = 0xffffffff; 941 } else { 942 err_cnt -= (u32)abort_cnt * 8 * 8; 943 bit_cnt *= 8 * 8; 944 state->ber = err_cnt * (0xffffffff / bit_cnt); 945 } 946 } 947 state->ucb += abort_cnt; 948 state->last_stat_check = jiffies; 949 } 950 951 return 0; 952 err: 953 dev_dbg(&state->i2c->dev, "%s: failed=%d\n", __func__, ret); 954 955 return ret; 956 } 957 958 static int af9033_read_ber(struct dvb_frontend *fe, u32 *ber) 959 { 960 struct af9033_state *state = fe->demodulator_priv; 961 int ret; 962 963 ret = af9033_update_ch_stat(state); 964 if (ret < 0) 965 return ret; 966 967 *ber = state->ber; 968 969 return 0; 970 } 971 972 static int af9033_read_ucblocks(struct dvb_frontend *fe, u32 *ucblocks) 973 { 974 struct af9033_state *state = fe->demodulator_priv; 975 int ret; 976 977 ret = af9033_update_ch_stat(state); 978 if (ret < 0) 979 return ret; 980 981 *ucblocks = state->ucb; 982 983 return 0; 984 } 985 986 static int af9033_i2c_gate_ctrl(struct dvb_frontend *fe, int enable) 987 { 988 struct af9033_state *state = fe->demodulator_priv; 989 int ret; 990 991 dev_dbg(&state->i2c->dev, "%s: enable=%d\n", __func__, enable); 992 993 ret = af9033_wr_reg_mask(state, 0x00fa04, enable, 0x01); 994 if (ret < 0) 995 goto err; 996 997 return 0; 998 999 err: 1000 dev_dbg(&state->i2c->dev, "%s: failed=%d\n", __func__, ret); 1001 1002 return ret; 1003 } 1004 1005 static int af9033_pid_filter_ctrl(struct dvb_frontend *fe, int onoff) 1006 { 1007 struct af9033_state *state = fe->demodulator_priv; 1008 int ret; 1009 1010 dev_dbg(&state->i2c->dev, "%s: onoff=%d\n", __func__, onoff); 1011 1012 ret = af9033_wr_reg_mask(state, 0x80f993, onoff, 0x01); 1013 if (ret < 0) 1014 goto err; 1015 1016 return 0; 1017 1018 err: 1019 dev_dbg(&state->i2c->dev, "%s: failed=%d\n", __func__, ret); 1020 1021 return ret; 1022 } 1023 1024 static int af9033_pid_filter(struct dvb_frontend *fe, int index, u16 pid, int onoff) 1025 { 1026 struct af9033_state *state = fe->demodulator_priv; 1027 int ret; 1028 u8 wbuf[2] = {(pid >> 0) & 0xff, (pid >> 8) & 0xff}; 1029 1030 dev_dbg(&state->i2c->dev, "%s: index=%d pid=%04x onoff=%d\n", 1031 __func__, index, pid, onoff); 1032 1033 if (pid > 0x1fff) 1034 return 0; 1035 1036 ret = af9033_wr_regs(state, 0x80f996, wbuf, 2); 1037 if (ret < 0) 1038 goto err; 1039 1040 ret = af9033_wr_reg(state, 0x80f994, onoff); 1041 if (ret < 0) 1042 goto err; 1043 1044 ret = af9033_wr_reg(state, 0x80f995, index); 1045 if (ret < 0) 1046 goto err; 1047 1048 return 0; 1049 1050 err: 1051 dev_dbg(&state->i2c->dev, "%s: failed=%d\n", __func__, ret); 1052 1053 return ret; 1054 } 1055 1056 static struct dvb_frontend_ops af9033_ops; 1057 1058 struct dvb_frontend *af9033_attach(const struct af9033_config *config, 1059 struct i2c_adapter *i2c, 1060 struct af9033_ops *ops) 1061 { 1062 int ret; 1063 struct af9033_state *state; 1064 u8 buf[8]; 1065 1066 dev_dbg(&i2c->dev, "%s:\n", __func__); 1067 1068 /* allocate memory for the internal state */ 1069 state = kzalloc(sizeof(struct af9033_state), GFP_KERNEL); 1070 if (state == NULL) 1071 goto err; 1072 1073 /* setup the state */ 1074 state->i2c = i2c; 1075 memcpy(&state->cfg, config, sizeof(struct af9033_config)); 1076 1077 if (state->cfg.clock != 12000000) { 1078 dev_err(&state->i2c->dev, "%s: af9033: unsupported clock=%d, " \ 1079 "only 12000000 Hz is supported currently\n", 1080 KBUILD_MODNAME, state->cfg.clock); 1081 goto err; 1082 } 1083 1084 /* firmware version */ 1085 ret = af9033_rd_regs(state, 0x0083e9, &buf[0], 4); 1086 if (ret < 0) 1087 goto err; 1088 1089 ret = af9033_rd_regs(state, 0x804191, &buf[4], 4); 1090 if (ret < 0) 1091 goto err; 1092 1093 dev_info(&state->i2c->dev, "%s: firmware version: LINK=%d.%d.%d.%d " \ 1094 "OFDM=%d.%d.%d.%d\n", KBUILD_MODNAME, buf[0], buf[1], 1095 buf[2], buf[3], buf[4], buf[5], buf[6], buf[7]); 1096 1097 /* sleep */ 1098 switch (state->cfg.tuner) { 1099 case AF9033_TUNER_IT9135_38: 1100 case AF9033_TUNER_IT9135_51: 1101 case AF9033_TUNER_IT9135_52: 1102 case AF9033_TUNER_IT9135_60: 1103 case AF9033_TUNER_IT9135_61: 1104 case AF9033_TUNER_IT9135_62: 1105 /* IT9135 did not like to sleep at that early */ 1106 break; 1107 default: 1108 ret = af9033_wr_reg(state, 0x80004c, 1); 1109 if (ret < 0) 1110 goto err; 1111 1112 ret = af9033_wr_reg(state, 0x800000, 0); 1113 if (ret < 0) 1114 goto err; 1115 } 1116 1117 /* configure internal TS mode */ 1118 switch (state->cfg.ts_mode) { 1119 case AF9033_TS_MODE_PARALLEL: 1120 state->ts_mode_parallel = true; 1121 break; 1122 case AF9033_TS_MODE_SERIAL: 1123 state->ts_mode_serial = true; 1124 break; 1125 case AF9033_TS_MODE_USB: 1126 /* usb mode for AF9035 */ 1127 default: 1128 break; 1129 } 1130 1131 /* create dvb_frontend */ 1132 memcpy(&state->fe.ops, &af9033_ops, sizeof(struct dvb_frontend_ops)); 1133 state->fe.demodulator_priv = state; 1134 1135 if (ops) { 1136 ops->pid_filter = af9033_pid_filter; 1137 ops->pid_filter_ctrl = af9033_pid_filter_ctrl; 1138 } 1139 1140 return &state->fe; 1141 1142 err: 1143 kfree(state); 1144 return NULL; 1145 } 1146 EXPORT_SYMBOL(af9033_attach); 1147 1148 static struct dvb_frontend_ops af9033_ops = { 1149 .delsys = { SYS_DVBT }, 1150 .info = { 1151 .name = "Afatech AF9033 (DVB-T)", 1152 .frequency_min = 174000000, 1153 .frequency_max = 862000000, 1154 .frequency_stepsize = 250000, 1155 .frequency_tolerance = 0, 1156 .caps = FE_CAN_FEC_1_2 | 1157 FE_CAN_FEC_2_3 | 1158 FE_CAN_FEC_3_4 | 1159 FE_CAN_FEC_5_6 | 1160 FE_CAN_FEC_7_8 | 1161 FE_CAN_FEC_AUTO | 1162 FE_CAN_QPSK | 1163 FE_CAN_QAM_16 | 1164 FE_CAN_QAM_64 | 1165 FE_CAN_QAM_AUTO | 1166 FE_CAN_TRANSMISSION_MODE_AUTO | 1167 FE_CAN_GUARD_INTERVAL_AUTO | 1168 FE_CAN_HIERARCHY_AUTO | 1169 FE_CAN_RECOVER | 1170 FE_CAN_MUTE_TS 1171 }, 1172 1173 .release = af9033_release, 1174 1175 .init = af9033_init, 1176 .sleep = af9033_sleep, 1177 1178 .get_tune_settings = af9033_get_tune_settings, 1179 .set_frontend = af9033_set_frontend, 1180 .get_frontend = af9033_get_frontend, 1181 1182 .read_status = af9033_read_status, 1183 .read_snr = af9033_read_snr, 1184 .read_signal_strength = af9033_read_signal_strength, 1185 .read_ber = af9033_read_ber, 1186 .read_ucblocks = af9033_read_ucblocks, 1187 1188 .i2c_gate_ctrl = af9033_i2c_gate_ctrl, 1189 }; 1190 1191 MODULE_AUTHOR("Antti Palosaari <crope@iki.fi>"); 1192 MODULE_DESCRIPTION("Afatech AF9033 DVB-T demodulator driver"); 1193 MODULE_LICENSE("GPL"); 1194