1*3785bc17SMauro Carvalho Chehab /* 2*3785bc17SMauro Carvalho Chehab * Linux driver for digital TV devices equipped with B2C2 FlexcopII(b)/III 3*3785bc17SMauro Carvalho Chehab * flexcop-reg.h - register abstraction for FlexCopII, FlexCopIIb and FlexCopIII 4*3785bc17SMauro Carvalho Chehab * see flexcop.c for copyright information 5*3785bc17SMauro Carvalho Chehab */ 6*3785bc17SMauro Carvalho Chehab #ifndef __FLEXCOP_REG_H__ 7*3785bc17SMauro Carvalho Chehab #define __FLEXCOP_REG_H__ 8*3785bc17SMauro Carvalho Chehab 9*3785bc17SMauro Carvalho Chehab typedef enum { 10*3785bc17SMauro Carvalho Chehab FLEXCOP_UNK = 0, 11*3785bc17SMauro Carvalho Chehab FLEXCOP_II, 12*3785bc17SMauro Carvalho Chehab FLEXCOP_IIB, 13*3785bc17SMauro Carvalho Chehab FLEXCOP_III, 14*3785bc17SMauro Carvalho Chehab } flexcop_revision_t; 15*3785bc17SMauro Carvalho Chehab 16*3785bc17SMauro Carvalho Chehab typedef enum { 17*3785bc17SMauro Carvalho Chehab FC_UNK = 0, 18*3785bc17SMauro Carvalho Chehab FC_CABLE, 19*3785bc17SMauro Carvalho Chehab FC_AIR_DVBT, 20*3785bc17SMauro Carvalho Chehab FC_AIR_ATSC1, 21*3785bc17SMauro Carvalho Chehab FC_AIR_ATSC2, 22*3785bc17SMauro Carvalho Chehab FC_AIR_ATSC3, 23*3785bc17SMauro Carvalho Chehab FC_SKY_REV23, 24*3785bc17SMauro Carvalho Chehab FC_SKY_REV26, 25*3785bc17SMauro Carvalho Chehab FC_SKY_REV27, 26*3785bc17SMauro Carvalho Chehab FC_SKY_REV28, 27*3785bc17SMauro Carvalho Chehab } flexcop_device_type_t; 28*3785bc17SMauro Carvalho Chehab 29*3785bc17SMauro Carvalho Chehab typedef enum { 30*3785bc17SMauro Carvalho Chehab FC_USB = 0, 31*3785bc17SMauro Carvalho Chehab FC_PCI, 32*3785bc17SMauro Carvalho Chehab } flexcop_bus_t; 33*3785bc17SMauro Carvalho Chehab 34*3785bc17SMauro Carvalho Chehab /* FlexCop IBI Registers */ 35*3785bc17SMauro Carvalho Chehab #if defined(__LITTLE_ENDIAN) 36*3785bc17SMauro Carvalho Chehab #include "flexcop_ibi_value_le.h" 37*3785bc17SMauro Carvalho Chehab #else 38*3785bc17SMauro Carvalho Chehab #if defined(__BIG_ENDIAN) 39*3785bc17SMauro Carvalho Chehab #include "flexcop_ibi_value_be.h" 40*3785bc17SMauro Carvalho Chehab #else 41*3785bc17SMauro Carvalho Chehab #error no endian defined 42*3785bc17SMauro Carvalho Chehab #endif 43*3785bc17SMauro Carvalho Chehab #endif 44*3785bc17SMauro Carvalho Chehab 45*3785bc17SMauro Carvalho Chehab #define fc_data_Tag_ID_DVB 0x3e 46*3785bc17SMauro Carvalho Chehab #define fc_data_Tag_ID_ATSC 0x3f 47*3785bc17SMauro Carvalho Chehab #define fc_data_Tag_ID_IDSB 0x8b 48*3785bc17SMauro Carvalho Chehab 49*3785bc17SMauro Carvalho Chehab #define fc_key_code_default 0x1 50*3785bc17SMauro Carvalho Chehab #define fc_key_code_even 0x2 51*3785bc17SMauro Carvalho Chehab #define fc_key_code_odd 0x3 52*3785bc17SMauro Carvalho Chehab 53*3785bc17SMauro Carvalho Chehab extern flexcop_ibi_value ibi_zero; 54*3785bc17SMauro Carvalho Chehab 55*3785bc17SMauro Carvalho Chehab typedef enum { 56*3785bc17SMauro Carvalho Chehab FC_I2C_PORT_DEMOD = 1, 57*3785bc17SMauro Carvalho Chehab FC_I2C_PORT_EEPROM = 2, 58*3785bc17SMauro Carvalho Chehab FC_I2C_PORT_TUNER = 3, 59*3785bc17SMauro Carvalho Chehab } flexcop_i2c_port_t; 60*3785bc17SMauro Carvalho Chehab 61*3785bc17SMauro Carvalho Chehab typedef enum { 62*3785bc17SMauro Carvalho Chehab FC_WRITE = 0, 63*3785bc17SMauro Carvalho Chehab FC_READ = 1, 64*3785bc17SMauro Carvalho Chehab } flexcop_access_op_t; 65*3785bc17SMauro Carvalho Chehab 66*3785bc17SMauro Carvalho Chehab typedef enum { 67*3785bc17SMauro Carvalho Chehab FC_SRAM_DEST_NET = 1, 68*3785bc17SMauro Carvalho Chehab FC_SRAM_DEST_CAI = 2, 69*3785bc17SMauro Carvalho Chehab FC_SRAM_DEST_CAO = 4, 70*3785bc17SMauro Carvalho Chehab FC_SRAM_DEST_MEDIA = 8 71*3785bc17SMauro Carvalho Chehab } flexcop_sram_dest_t; 72*3785bc17SMauro Carvalho Chehab 73*3785bc17SMauro Carvalho Chehab typedef enum { 74*3785bc17SMauro Carvalho Chehab FC_SRAM_DEST_TARGET_WAN_USB = 0, 75*3785bc17SMauro Carvalho Chehab FC_SRAM_DEST_TARGET_DMA1 = 1, 76*3785bc17SMauro Carvalho Chehab FC_SRAM_DEST_TARGET_DMA2 = 2, 77*3785bc17SMauro Carvalho Chehab FC_SRAM_DEST_TARGET_FC3_CA = 3 78*3785bc17SMauro Carvalho Chehab } flexcop_sram_dest_target_t; 79*3785bc17SMauro Carvalho Chehab 80*3785bc17SMauro Carvalho Chehab typedef enum { 81*3785bc17SMauro Carvalho Chehab FC_SRAM_2_32KB = 0, /* 64KB */ 82*3785bc17SMauro Carvalho Chehab FC_SRAM_1_32KB = 1, /* 32KB - default fow FCII */ 83*3785bc17SMauro Carvalho Chehab FC_SRAM_1_128KB = 2, /* 128KB */ 84*3785bc17SMauro Carvalho Chehab FC_SRAM_1_48KB = 3, /* 48KB - default for FCIII */ 85*3785bc17SMauro Carvalho Chehab } flexcop_sram_type_t; 86*3785bc17SMauro Carvalho Chehab 87*3785bc17SMauro Carvalho Chehab typedef enum { 88*3785bc17SMauro Carvalho Chehab FC_WAN_SPEED_4MBITS = 0, 89*3785bc17SMauro Carvalho Chehab FC_WAN_SPEED_8MBITS = 1, 90*3785bc17SMauro Carvalho Chehab FC_WAN_SPEED_12MBITS = 2, 91*3785bc17SMauro Carvalho Chehab FC_WAN_SPEED_16MBITS = 3, 92*3785bc17SMauro Carvalho Chehab } flexcop_wan_speed_t; 93*3785bc17SMauro Carvalho Chehab 94*3785bc17SMauro Carvalho Chehab typedef enum { 95*3785bc17SMauro Carvalho Chehab FC_DMA_1 = 1, 96*3785bc17SMauro Carvalho Chehab FC_DMA_2 = 2, 97*3785bc17SMauro Carvalho Chehab } flexcop_dma_index_t; 98*3785bc17SMauro Carvalho Chehab 99*3785bc17SMauro Carvalho Chehab typedef enum { 100*3785bc17SMauro Carvalho Chehab FC_DMA_SUBADDR_0 = 1, 101*3785bc17SMauro Carvalho Chehab FC_DMA_SUBADDR_1 = 2, 102*3785bc17SMauro Carvalho Chehab } flexcop_dma_addr_index_t; 103*3785bc17SMauro Carvalho Chehab 104*3785bc17SMauro Carvalho Chehab /* names of the particular registers */ 105*3785bc17SMauro Carvalho Chehab typedef enum { 106*3785bc17SMauro Carvalho Chehab dma1_000 = 0x000, 107*3785bc17SMauro Carvalho Chehab dma1_004 = 0x004, 108*3785bc17SMauro Carvalho Chehab dma1_008 = 0x008, 109*3785bc17SMauro Carvalho Chehab dma1_00c = 0x00c, 110*3785bc17SMauro Carvalho Chehab dma2_010 = 0x010, 111*3785bc17SMauro Carvalho Chehab dma2_014 = 0x014, 112*3785bc17SMauro Carvalho Chehab dma2_018 = 0x018, 113*3785bc17SMauro Carvalho Chehab dma2_01c = 0x01c, 114*3785bc17SMauro Carvalho Chehab 115*3785bc17SMauro Carvalho Chehab tw_sm_c_100 = 0x100, 116*3785bc17SMauro Carvalho Chehab tw_sm_c_104 = 0x104, 117*3785bc17SMauro Carvalho Chehab tw_sm_c_108 = 0x108, 118*3785bc17SMauro Carvalho Chehab tw_sm_c_10c = 0x10c, 119*3785bc17SMauro Carvalho Chehab tw_sm_c_110 = 0x110, 120*3785bc17SMauro Carvalho Chehab 121*3785bc17SMauro Carvalho Chehab lnb_switch_freq_200 = 0x200, 122*3785bc17SMauro Carvalho Chehab misc_204 = 0x204, 123*3785bc17SMauro Carvalho Chehab ctrl_208 = 0x208, 124*3785bc17SMauro Carvalho Chehab irq_20c = 0x20c, 125*3785bc17SMauro Carvalho Chehab sw_reset_210 = 0x210, 126*3785bc17SMauro Carvalho Chehab misc_214 = 0x214, 127*3785bc17SMauro Carvalho Chehab mbox_v8_to_host_218 = 0x218, 128*3785bc17SMauro Carvalho Chehab mbox_host_to_v8_21c = 0x21c, 129*3785bc17SMauro Carvalho Chehab 130*3785bc17SMauro Carvalho Chehab pid_filter_300 = 0x300, 131*3785bc17SMauro Carvalho Chehab pid_filter_304 = 0x304, 132*3785bc17SMauro Carvalho Chehab pid_filter_308 = 0x308, 133*3785bc17SMauro Carvalho Chehab pid_filter_30c = 0x30c, 134*3785bc17SMauro Carvalho Chehab index_reg_310 = 0x310, 135*3785bc17SMauro Carvalho Chehab pid_n_reg_314 = 0x314, 136*3785bc17SMauro Carvalho Chehab mac_low_reg_318 = 0x318, 137*3785bc17SMauro Carvalho Chehab mac_high_reg_31c = 0x31c, 138*3785bc17SMauro Carvalho Chehab 139*3785bc17SMauro Carvalho Chehab data_tag_400 = 0x400, 140*3785bc17SMauro Carvalho Chehab card_id_408 = 0x408, 141*3785bc17SMauro Carvalho Chehab card_id_40c = 0x40c, 142*3785bc17SMauro Carvalho Chehab mac_address_418 = 0x418, 143*3785bc17SMauro Carvalho Chehab mac_address_41c = 0x41c, 144*3785bc17SMauro Carvalho Chehab 145*3785bc17SMauro Carvalho Chehab ci_600 = 0x600, 146*3785bc17SMauro Carvalho Chehab pi_604 = 0x604, 147*3785bc17SMauro Carvalho Chehab pi_608 = 0x608, 148*3785bc17SMauro Carvalho Chehab dvb_reg_60c = 0x60c, 149*3785bc17SMauro Carvalho Chehab 150*3785bc17SMauro Carvalho Chehab sram_ctrl_reg_700 = 0x700, 151*3785bc17SMauro Carvalho Chehab net_buf_reg_704 = 0x704, 152*3785bc17SMauro Carvalho Chehab cai_buf_reg_708 = 0x708, 153*3785bc17SMauro Carvalho Chehab cao_buf_reg_70c = 0x70c, 154*3785bc17SMauro Carvalho Chehab media_buf_reg_710 = 0x710, 155*3785bc17SMauro Carvalho Chehab sram_dest_reg_714 = 0x714, 156*3785bc17SMauro Carvalho Chehab net_buf_reg_718 = 0x718, 157*3785bc17SMauro Carvalho Chehab wan_ctrl_reg_71c = 0x71c, 158*3785bc17SMauro Carvalho Chehab } flexcop_ibi_register; 159*3785bc17SMauro Carvalho Chehab 160*3785bc17SMauro Carvalho Chehab #define flexcop_set_ibi_value(reg,attr,val) { \ 161*3785bc17SMauro Carvalho Chehab flexcop_ibi_value v = fc->read_ibi_reg(fc,reg); \ 162*3785bc17SMauro Carvalho Chehab v.reg.attr = val; \ 163*3785bc17SMauro Carvalho Chehab fc->write_ibi_reg(fc,reg,v); \ 164*3785bc17SMauro Carvalho Chehab } 165*3785bc17SMauro Carvalho Chehab 166*3785bc17SMauro Carvalho Chehab #endif 167