1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Tegra CEC implementation 4 * 5 * The original 3.10 CEC driver using a custom API: 6 * 7 * Copyright (c) 2012-2015, NVIDIA CORPORATION. All rights reserved. 8 * 9 * Conversion to the CEC framework and to the mainline kernel: 10 * 11 * Copyright 2016-2017 Cisco Systems, Inc. and/or its affiliates. All rights reserved. 12 */ 13 14 #include <linux/module.h> 15 #include <linux/kernel.h> 16 #include <linux/err.h> 17 #include <linux/errno.h> 18 #include <linux/interrupt.h> 19 #include <linux/slab.h> 20 #include <linux/io.h> 21 #include <linux/clk.h> 22 #include <linux/delay.h> 23 #include <linux/pm.h> 24 #include <linux/of.h> 25 #include <linux/of_platform.h> 26 #include <linux/platform_device.h> 27 #include <linux/seq_file.h> 28 #include <linux/clk/tegra.h> 29 30 #include <media/cec-notifier.h> 31 32 #include "tegra_cec.h" 33 34 #define TEGRA_CEC_NAME "tegra-cec" 35 36 struct tegra_cec { 37 struct cec_adapter *adap; 38 struct device *dev; 39 struct clk *clk; 40 void __iomem *cec_base; 41 struct cec_notifier *notifier; 42 int tegra_cec_irq; 43 bool rx_done; 44 bool tx_done; 45 int tx_status; 46 u8 rx_buf[CEC_MAX_MSG_SIZE]; 47 u8 rx_buf_cnt; 48 u32 tx_buf[CEC_MAX_MSG_SIZE]; 49 u8 tx_buf_cur; 50 u8 tx_buf_cnt; 51 u32 rx_total_low_drives; 52 }; 53 54 static inline u32 cec_read(struct tegra_cec *cec, u32 reg) 55 { 56 return readl(cec->cec_base + reg); 57 } 58 59 static inline void cec_write(struct tegra_cec *cec, u32 reg, u32 val) 60 { 61 writel(val, cec->cec_base + reg); 62 } 63 64 static void tegra_cec_error_recovery(struct tegra_cec *cec) 65 { 66 u32 hw_ctrl; 67 68 hw_ctrl = cec_read(cec, TEGRA_CEC_HW_CONTROL); 69 cec_write(cec, TEGRA_CEC_HW_CONTROL, 0); 70 cec_write(cec, TEGRA_CEC_INT_STAT, 0xffffffff); 71 cec_write(cec, TEGRA_CEC_HW_CONTROL, hw_ctrl); 72 } 73 74 static irqreturn_t tegra_cec_irq_thread_handler(int irq, void *data) 75 { 76 struct device *dev = data; 77 struct tegra_cec *cec = dev_get_drvdata(dev); 78 79 if (cec->tx_done) { 80 cec_transmit_attempt_done(cec->adap, cec->tx_status); 81 cec->tx_done = false; 82 } 83 if (cec->rx_done) { 84 struct cec_msg msg = {}; 85 86 msg.len = cec->rx_buf_cnt; 87 memcpy(msg.msg, cec->rx_buf, msg.len); 88 cec_received_msg(cec->adap, &msg); 89 cec->rx_done = false; 90 cec->rx_buf_cnt = 0; 91 } 92 return IRQ_HANDLED; 93 } 94 95 static irqreturn_t tegra_cec_irq_handler(int irq, void *data) 96 { 97 struct device *dev = data; 98 struct tegra_cec *cec = dev_get_drvdata(dev); 99 u32 status, mask; 100 101 status = cec_read(cec, TEGRA_CEC_INT_STAT); 102 mask = cec_read(cec, TEGRA_CEC_INT_MASK); 103 104 status &= mask; 105 106 if (!status) 107 return IRQ_HANDLED; 108 109 if (status & TEGRA_CEC_INT_STAT_TX_REGISTER_UNDERRUN) { 110 dev_err(dev, "TX underrun, interrupt timing issue!\n"); 111 112 tegra_cec_error_recovery(cec); 113 cec_write(cec, TEGRA_CEC_INT_MASK, 114 mask & ~TEGRA_CEC_INT_MASK_TX_REGISTER_EMPTY); 115 116 cec->tx_done = true; 117 cec->tx_status = CEC_TX_STATUS_ERROR; 118 return IRQ_WAKE_THREAD; 119 } 120 121 if (status & TEGRA_CEC_INT_STAT_RX_BUS_ERROR_DETECTED) { 122 dev_warn_ratelimited(dev, "RX bus error detected, generated low drive\n"); 123 cec->rx_total_low_drives++; 124 cec_write(cec, TEGRA_CEC_INT_STAT, 125 TEGRA_CEC_INT_STAT_RX_BUS_ERROR_DETECTED); 126 } 127 128 if ((status & TEGRA_CEC_INT_STAT_TX_ARBITRATION_FAILED) || 129 (status & TEGRA_CEC_INT_STAT_TX_BUS_ANOMALY_DETECTED)) { 130 tegra_cec_error_recovery(cec); 131 cec_write(cec, TEGRA_CEC_INT_MASK, 132 mask & ~TEGRA_CEC_INT_MASK_TX_REGISTER_EMPTY); 133 134 cec->tx_done = true; 135 if (status & TEGRA_CEC_INT_STAT_TX_BUS_ANOMALY_DETECTED) 136 cec->tx_status = CEC_TX_STATUS_LOW_DRIVE; 137 else 138 cec->tx_status = CEC_TX_STATUS_ARB_LOST; 139 return IRQ_WAKE_THREAD; 140 } 141 142 if (status & TEGRA_CEC_INT_STAT_TX_FRAME_TRANSMITTED) { 143 cec_write(cec, TEGRA_CEC_INT_STAT, 144 TEGRA_CEC_INT_STAT_TX_FRAME_TRANSMITTED); 145 146 if (status & TEGRA_CEC_INT_STAT_TX_FRAME_OR_BLOCK_NAKD) { 147 tegra_cec_error_recovery(cec); 148 149 cec->tx_done = true; 150 cec->tx_status = CEC_TX_STATUS_NACK; 151 } else { 152 cec->tx_done = true; 153 cec->tx_status = CEC_TX_STATUS_OK; 154 } 155 return IRQ_WAKE_THREAD; 156 } 157 158 if (status & TEGRA_CEC_INT_STAT_TX_FRAME_OR_BLOCK_NAKD) 159 dev_warn(dev, "TX NAKed on the fly!\n"); 160 161 if (status & TEGRA_CEC_INT_STAT_TX_REGISTER_EMPTY) { 162 if (cec->tx_buf_cur == cec->tx_buf_cnt) { 163 cec_write(cec, TEGRA_CEC_INT_MASK, 164 mask & ~TEGRA_CEC_INT_MASK_TX_REGISTER_EMPTY); 165 } else { 166 cec_write(cec, TEGRA_CEC_TX_REGISTER, 167 cec->tx_buf[cec->tx_buf_cur++]); 168 cec_write(cec, TEGRA_CEC_INT_STAT, 169 TEGRA_CEC_INT_STAT_TX_REGISTER_EMPTY); 170 } 171 } 172 173 if (status & TEGRA_CEC_INT_STAT_RX_START_BIT_DETECTED) { 174 cec_write(cec, TEGRA_CEC_INT_STAT, 175 TEGRA_CEC_INT_STAT_RX_START_BIT_DETECTED); 176 cec->rx_done = false; 177 cec->rx_buf_cnt = 0; 178 } 179 if (status & TEGRA_CEC_INT_STAT_RX_REGISTER_FULL) { 180 u32 v; 181 182 cec_write(cec, TEGRA_CEC_INT_STAT, 183 TEGRA_CEC_INT_STAT_RX_REGISTER_FULL); 184 v = cec_read(cec, TEGRA_CEC_RX_REGISTER); 185 if (cec->rx_buf_cnt < CEC_MAX_MSG_SIZE) 186 cec->rx_buf[cec->rx_buf_cnt++] = v & 0xff; 187 if (v & TEGRA_CEC_RX_REGISTER_EOM) { 188 cec->rx_done = true; 189 return IRQ_WAKE_THREAD; 190 } 191 } 192 193 return IRQ_HANDLED; 194 } 195 196 static int tegra_cec_adap_enable(struct cec_adapter *adap, bool enable) 197 { 198 struct tegra_cec *cec = adap->priv; 199 200 cec->rx_buf_cnt = 0; 201 cec->tx_buf_cnt = 0; 202 cec->tx_buf_cur = 0; 203 204 cec_write(cec, TEGRA_CEC_HW_CONTROL, 0); 205 cec_write(cec, TEGRA_CEC_INT_MASK, 0); 206 cec_write(cec, TEGRA_CEC_INT_STAT, 0xffffffff); 207 cec_write(cec, TEGRA_CEC_SW_CONTROL, 0); 208 209 if (!enable) 210 return 0; 211 212 cec_write(cec, TEGRA_CEC_INPUT_FILTER, (1U << 31) | 0x20); 213 214 cec_write(cec, TEGRA_CEC_RX_TIMING_0, 215 (0x7a << TEGRA_CEC_RX_TIM0_START_BIT_MAX_LO_TIME_SHIFT) | 216 (0x6d << TEGRA_CEC_RX_TIM0_START_BIT_MIN_LO_TIME_SHIFT) | 217 (0x93 << TEGRA_CEC_RX_TIM0_START_BIT_MAX_DURATION_SHIFT) | 218 (0x86 << TEGRA_CEC_RX_TIM0_START_BIT_MIN_DURATION_SHIFT)); 219 220 cec_write(cec, TEGRA_CEC_RX_TIMING_1, 221 (0x35 << TEGRA_CEC_RX_TIM1_DATA_BIT_MAX_LO_TIME_SHIFT) | 222 (0x21 << TEGRA_CEC_RX_TIM1_DATA_BIT_SAMPLE_TIME_SHIFT) | 223 (0x56 << TEGRA_CEC_RX_TIM1_DATA_BIT_MAX_DURATION_SHIFT) | 224 (0x40 << TEGRA_CEC_RX_TIM1_DATA_BIT_MIN_DURATION_SHIFT)); 225 226 cec_write(cec, TEGRA_CEC_RX_TIMING_2, 227 (0x50 << TEGRA_CEC_RX_TIM2_END_OF_BLOCK_TIME_SHIFT)); 228 229 cec_write(cec, TEGRA_CEC_TX_TIMING_0, 230 (0x74 << TEGRA_CEC_TX_TIM0_START_BIT_LO_TIME_SHIFT) | 231 (0x8d << TEGRA_CEC_TX_TIM0_START_BIT_DURATION_SHIFT) | 232 (0x08 << TEGRA_CEC_TX_TIM0_BUS_XITION_TIME_SHIFT) | 233 (0x71 << TEGRA_CEC_TX_TIM0_BUS_ERROR_LO_TIME_SHIFT)); 234 235 cec_write(cec, TEGRA_CEC_TX_TIMING_1, 236 (0x2f << TEGRA_CEC_TX_TIM1_LO_DATA_BIT_LO_TIME_SHIFT) | 237 (0x13 << TEGRA_CEC_TX_TIM1_HI_DATA_BIT_LO_TIME_SHIFT) | 238 (0x4b << TEGRA_CEC_TX_TIM1_DATA_BIT_DURATION_SHIFT) | 239 (0x21 << TEGRA_CEC_TX_TIM1_ACK_NAK_BIT_SAMPLE_TIME_SHIFT)); 240 241 cec_write(cec, TEGRA_CEC_TX_TIMING_2, 242 (0x07 << TEGRA_CEC_TX_TIM2_BUS_IDLE_TIME_ADDITIONAL_FRAME_SHIFT) | 243 (0x05 << TEGRA_CEC_TX_TIM2_BUS_IDLE_TIME_NEW_FRAME_SHIFT) | 244 (0x03 << TEGRA_CEC_TX_TIM2_BUS_IDLE_TIME_RETRY_FRAME_SHIFT)); 245 246 cec_write(cec, TEGRA_CEC_INT_MASK, 247 TEGRA_CEC_INT_MASK_TX_REGISTER_UNDERRUN | 248 TEGRA_CEC_INT_MASK_TX_FRAME_OR_BLOCK_NAKD | 249 TEGRA_CEC_INT_MASK_TX_ARBITRATION_FAILED | 250 TEGRA_CEC_INT_MASK_TX_BUS_ANOMALY_DETECTED | 251 TEGRA_CEC_INT_MASK_TX_FRAME_TRANSMITTED | 252 TEGRA_CEC_INT_MASK_RX_REGISTER_FULL | 253 TEGRA_CEC_INT_MASK_RX_BUS_ERROR_DETECTED | 254 TEGRA_CEC_INT_MASK_RX_START_BIT_DETECTED); 255 256 /* 257 * TX_NAK_MODE ensures that the whole message is transmitted even 258 * if each byte is NACKed. Without this flag the retransmit of the 259 * messages after a NACK can be corrupt. This is a bug in the hardware. 260 * 261 * While less efficient, in practice you rarely transmit messages 262 * that can be NACKed, with the exception of POLL messages which 263 * are just one byte anyway. 264 */ 265 cec_write(cec, TEGRA_CEC_HW_CONTROL, 266 TEGRA_CEC_HWCTRL_TX_RX_MODE | 267 TEGRA_CEC_HWCTRL_TX_NAK_MODE); 268 return 0; 269 } 270 271 static int tegra_cec_adap_log_addr(struct cec_adapter *adap, u8 logical_addr) 272 { 273 struct tegra_cec *cec = adap->priv; 274 u32 state = cec_read(cec, TEGRA_CEC_HW_CONTROL); 275 276 if (logical_addr == CEC_LOG_ADDR_INVALID) 277 state &= ~TEGRA_CEC_HWCTRL_RX_LADDR_MASK; 278 else 279 state |= TEGRA_CEC_HWCTRL_RX_LADDR((1 << logical_addr)); 280 281 cec_write(cec, TEGRA_CEC_HW_CONTROL, state); 282 return 0; 283 } 284 285 static int tegra_cec_adap_monitor_all_enable(struct cec_adapter *adap, 286 bool enable) 287 { 288 struct tegra_cec *cec = adap->priv; 289 u32 reg = cec_read(cec, TEGRA_CEC_HW_CONTROL); 290 291 if (enable) 292 reg |= TEGRA_CEC_HWCTRL_RX_SNOOP; 293 else 294 reg &= ~TEGRA_CEC_HWCTRL_RX_SNOOP; 295 cec_write(cec, TEGRA_CEC_HW_CONTROL, reg); 296 return 0; 297 } 298 299 static int tegra_cec_adap_transmit(struct cec_adapter *adap, u8 attempts, 300 u32 signal_free_time_ms, struct cec_msg *msg) 301 { 302 bool retry_xfer = signal_free_time_ms == CEC_SIGNAL_FREE_TIME_RETRY; 303 struct tegra_cec *cec = adap->priv; 304 unsigned int i; 305 u32 mode = 0; 306 u32 mask; 307 308 if (cec_msg_is_broadcast(msg)) 309 mode = TEGRA_CEC_TX_REG_BCAST; 310 311 cec->tx_buf_cur = 0; 312 cec->tx_buf_cnt = msg->len; 313 314 for (i = 0; i < msg->len; i++) { 315 cec->tx_buf[i] = mode | msg->msg[i]; 316 if (i == 0) 317 cec->tx_buf[i] |= TEGRA_CEC_TX_REG_START_BIT; 318 if (i == msg->len - 1) 319 cec->tx_buf[i] |= TEGRA_CEC_TX_REG_EOM; 320 if (i == 0 && retry_xfer) 321 cec->tx_buf[i] |= TEGRA_CEC_TX_REG_RETRY; 322 } 323 324 mask = cec_read(cec, TEGRA_CEC_INT_MASK); 325 cec_write(cec, TEGRA_CEC_INT_MASK, 326 mask | TEGRA_CEC_INT_MASK_TX_REGISTER_EMPTY); 327 328 return 0; 329 } 330 331 static void tegra_cec_adap_status(struct cec_adapter *adap, struct seq_file *file) 332 { 333 struct tegra_cec *cec = adap->priv; 334 335 seq_printf(file, "receive low drive count: %u\n", 336 cec->rx_total_low_drives); 337 } 338 339 static const struct cec_adap_ops tegra_cec_ops = { 340 .adap_enable = tegra_cec_adap_enable, 341 .adap_log_addr = tegra_cec_adap_log_addr, 342 .adap_transmit = tegra_cec_adap_transmit, 343 .adap_monitor_all_enable = tegra_cec_adap_monitor_all_enable, 344 .adap_status = tegra_cec_adap_status, 345 }; 346 347 static int tegra_cec_probe(struct platform_device *pdev) 348 { 349 struct device *hdmi_dev; 350 struct tegra_cec *cec; 351 struct resource *res; 352 int ret = 0; 353 354 hdmi_dev = cec_notifier_parse_hdmi_phandle(&pdev->dev); 355 356 if (IS_ERR(hdmi_dev)) 357 return PTR_ERR(hdmi_dev); 358 359 cec = devm_kzalloc(&pdev->dev, sizeof(struct tegra_cec), GFP_KERNEL); 360 361 if (!cec) 362 return -ENOMEM; 363 364 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 365 366 if (!res) { 367 dev_err(&pdev->dev, 368 "Unable to allocate resources for device\n"); 369 return -EBUSY; 370 } 371 372 if (!devm_request_mem_region(&pdev->dev, res->start, resource_size(res), 373 pdev->name)) { 374 dev_err(&pdev->dev, 375 "Unable to request mem region for device\n"); 376 return -EBUSY; 377 } 378 379 cec->tegra_cec_irq = platform_get_irq(pdev, 0); 380 381 if (cec->tegra_cec_irq < 0) 382 return cec->tegra_cec_irq; 383 384 cec->cec_base = devm_ioremap(&pdev->dev, res->start, 385 resource_size(res)); 386 387 if (!cec->cec_base) { 388 dev_err(&pdev->dev, "Unable to grab IOs for device\n"); 389 return -EBUSY; 390 } 391 392 cec->clk = devm_clk_get(&pdev->dev, "cec"); 393 394 if (IS_ERR_OR_NULL(cec->clk)) { 395 dev_err(&pdev->dev, "Can't get clock for CEC\n"); 396 return -ENOENT; 397 } 398 399 ret = clk_prepare_enable(cec->clk); 400 if (ret) { 401 dev_err(&pdev->dev, "Unable to prepare clock for CEC\n"); 402 return ret; 403 } 404 405 /* set context info. */ 406 cec->dev = &pdev->dev; 407 408 platform_set_drvdata(pdev, cec); 409 410 ret = devm_request_threaded_irq(&pdev->dev, cec->tegra_cec_irq, 411 tegra_cec_irq_handler, tegra_cec_irq_thread_handler, 412 0, "cec_irq", &pdev->dev); 413 414 if (ret) 415 goto err_clk; 416 417 cec->adap = cec_allocate_adapter(&tegra_cec_ops, cec, TEGRA_CEC_NAME, 418 CEC_CAP_DEFAULTS | CEC_CAP_MONITOR_ALL | 419 CEC_CAP_CONNECTOR_INFO, 420 CEC_MAX_LOG_ADDRS); 421 if (IS_ERR(cec->adap)) { 422 ret = -ENOMEM; 423 dev_err(&pdev->dev, "Couldn't create cec adapter\n"); 424 goto err_clk; 425 } 426 427 cec->notifier = cec_notifier_cec_adap_register(hdmi_dev, NULL, 428 cec->adap); 429 if (!cec->notifier) { 430 ret = -ENOMEM; 431 goto err_adapter; 432 } 433 434 ret = cec_register_adapter(cec->adap, &pdev->dev); 435 if (ret) { 436 dev_err(&pdev->dev, "Couldn't register device\n"); 437 goto err_notifier; 438 } 439 440 return 0; 441 442 err_notifier: 443 cec_notifier_cec_adap_unregister(cec->notifier, cec->adap); 444 err_adapter: 445 cec_delete_adapter(cec->adap); 446 err_clk: 447 clk_disable_unprepare(cec->clk); 448 return ret; 449 } 450 451 static void tegra_cec_remove(struct platform_device *pdev) 452 { 453 struct tegra_cec *cec = platform_get_drvdata(pdev); 454 455 clk_disable_unprepare(cec->clk); 456 457 cec_notifier_cec_adap_unregister(cec->notifier, cec->adap); 458 cec_unregister_adapter(cec->adap); 459 } 460 461 #ifdef CONFIG_PM 462 static int tegra_cec_suspend(struct platform_device *pdev, pm_message_t state) 463 { 464 struct tegra_cec *cec = platform_get_drvdata(pdev); 465 466 clk_disable_unprepare(cec->clk); 467 468 dev_notice(&pdev->dev, "suspended\n"); 469 return 0; 470 } 471 472 static int tegra_cec_resume(struct platform_device *pdev) 473 { 474 struct tegra_cec *cec = platform_get_drvdata(pdev); 475 476 dev_notice(&pdev->dev, "Resuming\n"); 477 478 return clk_prepare_enable(cec->clk); 479 } 480 #endif 481 482 static const struct of_device_id tegra_cec_of_match[] = { 483 { .compatible = "nvidia,tegra114-cec", }, 484 { .compatible = "nvidia,tegra124-cec", }, 485 { .compatible = "nvidia,tegra210-cec", }, 486 {}, 487 }; 488 MODULE_DEVICE_TABLE(of, tegra_cec_of_match); 489 490 static struct platform_driver tegra_cec_driver = { 491 .driver = { 492 .name = TEGRA_CEC_NAME, 493 .of_match_table = tegra_cec_of_match, 494 }, 495 .probe = tegra_cec_probe, 496 .remove = tegra_cec_remove, 497 498 #ifdef CONFIG_PM 499 .suspend = tegra_cec_suspend, 500 .resume = tegra_cec_resume, 501 #endif 502 }; 503 504 module_platform_driver(tegra_cec_driver); 505 506 MODULE_DESCRIPTION("Tegra HDMI CEC driver"); 507 MODULE_AUTHOR("NVIDIA CORPORATION"); 508 MODULE_AUTHOR("Cisco Systems, Inc. and/or its affiliates"); 509 MODULE_LICENSE("GPL v2"); 510