1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* drivers/media/platform/s5p-cec/regs-cec.h 3 * 4 * Copyright (c) 2010 Samsung Electronics 5 * http://www.samsung.com/ 6 * 7 * register header file for Samsung TVOUT driver 8 */ 9 10 #ifndef __EXYNOS_REGS__H 11 #define __EXYNOS_REGS__H 12 13 /* 14 * Register part 15 */ 16 #define S5P_CEC_STATUS_0 (0x0000) 17 #define S5P_CEC_STATUS_1 (0x0004) 18 #define S5P_CEC_STATUS_2 (0x0008) 19 #define S5P_CEC_STATUS_3 (0x000C) 20 #define S5P_CEC_IRQ_MASK (0x0010) 21 #define S5P_CEC_IRQ_CLEAR (0x0014) 22 #define S5P_CEC_LOGIC_ADDR (0x0020) 23 #define S5P_CEC_DIVISOR_0 (0x0030) 24 #define S5P_CEC_DIVISOR_1 (0x0034) 25 #define S5P_CEC_DIVISOR_2 (0x0038) 26 #define S5P_CEC_DIVISOR_3 (0x003C) 27 28 #define S5P_CEC_TX_CTRL (0x0040) 29 #define S5P_CEC_TX_BYTES (0x0044) 30 #define S5P_CEC_TX_STAT0 (0x0060) 31 #define S5P_CEC_TX_STAT1 (0x0064) 32 #define S5P_CEC_TX_BUFF0 (0x0080) 33 #define S5P_CEC_TX_BUFF1 (0x0084) 34 #define S5P_CEC_TX_BUFF2 (0x0088) 35 #define S5P_CEC_TX_BUFF3 (0x008C) 36 #define S5P_CEC_TX_BUFF4 (0x0090) 37 #define S5P_CEC_TX_BUFF5 (0x0094) 38 #define S5P_CEC_TX_BUFF6 (0x0098) 39 #define S5P_CEC_TX_BUFF7 (0x009C) 40 #define S5P_CEC_TX_BUFF8 (0x00A0) 41 #define S5P_CEC_TX_BUFF9 (0x00A4) 42 #define S5P_CEC_TX_BUFF10 (0x00A8) 43 #define S5P_CEC_TX_BUFF11 (0x00AC) 44 #define S5P_CEC_TX_BUFF12 (0x00B0) 45 #define S5P_CEC_TX_BUFF13 (0x00B4) 46 #define S5P_CEC_TX_BUFF14 (0x00B8) 47 #define S5P_CEC_TX_BUFF15 (0x00BC) 48 49 #define S5P_CEC_RX_CTRL (0x00C0) 50 #define S5P_CEC_RX_STAT0 (0x00E0) 51 #define S5P_CEC_RX_STAT1 (0x00E4) 52 #define S5P_CEC_RX_BUFF0 (0x0100) 53 #define S5P_CEC_RX_BUFF1 (0x0104) 54 #define S5P_CEC_RX_BUFF2 (0x0108) 55 #define S5P_CEC_RX_BUFF3 (0x010C) 56 #define S5P_CEC_RX_BUFF4 (0x0110) 57 #define S5P_CEC_RX_BUFF5 (0x0114) 58 #define S5P_CEC_RX_BUFF6 (0x0118) 59 #define S5P_CEC_RX_BUFF7 (0x011C) 60 #define S5P_CEC_RX_BUFF8 (0x0120) 61 #define S5P_CEC_RX_BUFF9 (0x0124) 62 #define S5P_CEC_RX_BUFF10 (0x0128) 63 #define S5P_CEC_RX_BUFF11 (0x012C) 64 #define S5P_CEC_RX_BUFF12 (0x0130) 65 #define S5P_CEC_RX_BUFF13 (0x0134) 66 #define S5P_CEC_RX_BUFF14 (0x0138) 67 #define S5P_CEC_RX_BUFF15 (0x013C) 68 69 #define S5P_CEC_RX_FILTER_CTRL (0x0180) 70 #define S5P_CEC_RX_FILTER_TH (0x0184) 71 72 /* 73 * Bit definition part 74 */ 75 #define S5P_CEC_IRQ_TX_DONE (1<<0) 76 #define S5P_CEC_IRQ_TX_ERROR (1<<1) 77 #define S5P_CEC_IRQ_RX_DONE (1<<4) 78 #define S5P_CEC_IRQ_RX_ERROR (1<<5) 79 80 #define S5P_CEC_TX_CTRL_START (1<<0) 81 #define S5P_CEC_TX_CTRL_BCAST (1<<1) 82 #define S5P_CEC_TX_CTRL_RETRY (0x04<<4) 83 #define S5P_CEC_TX_CTRL_RESET (1<<7) 84 85 #define S5P_CEC_RX_CTRL_ENABLE (1<<0) 86 #define S5P_CEC_RX_CTRL_RESET (1<<7) 87 88 #define S5P_CEC_LOGIC_ADDR_MASK (0xF) 89 90 /* PMU Registers for PHY */ 91 #define EXYNOS_HDMI_PHY_CONTROL 0x700 92 93 #endif /* __EXYNOS_REGS__H */ 94