1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright 2017 Cisco Systems, Inc. and/or its affiliates. All rights reserved. 4 */ 5 6 #include <linux/delay.h> 7 #include <linux/sched/types.h> 8 #include <linux/seq_file.h> 9 #include <linux/slab.h> 10 11 #include <media/cec-pin.h> 12 #include "cec-pin-priv.h" 13 14 /* All timings are in microseconds */ 15 16 /* start bit timings */ 17 #define CEC_TIM_START_BIT_LOW 3700 18 #define CEC_TIM_START_BIT_LOW_MIN 3500 19 #define CEC_TIM_START_BIT_LOW_MAX 3900 20 #define CEC_TIM_START_BIT_TOTAL 4500 21 #define CEC_TIM_START_BIT_TOTAL_MIN 4300 22 #define CEC_TIM_START_BIT_TOTAL_MAX 4700 23 24 /* data bit timings */ 25 #define CEC_TIM_DATA_BIT_0_LOW 1500 26 #define CEC_TIM_DATA_BIT_0_LOW_MIN 1300 27 #define CEC_TIM_DATA_BIT_0_LOW_MAX 1700 28 #define CEC_TIM_DATA_BIT_1_LOW 600 29 #define CEC_TIM_DATA_BIT_1_LOW_MIN 400 30 #define CEC_TIM_DATA_BIT_1_LOW_MAX 800 31 #define CEC_TIM_DATA_BIT_TOTAL 2400 32 #define CEC_TIM_DATA_BIT_TOTAL_MIN 2050 33 #define CEC_TIM_DATA_BIT_TOTAL_MAX 2750 34 /* earliest safe time to sample the bit state */ 35 #define CEC_TIM_DATA_BIT_SAMPLE 850 36 /* earliest time the bit is back to 1 (T7 + 50) */ 37 #define CEC_TIM_DATA_BIT_HIGH 1750 38 39 /* when idle, sample once per millisecond */ 40 #define CEC_TIM_IDLE_SAMPLE 1000 41 /* when processing the start bit, sample twice per millisecond */ 42 #define CEC_TIM_START_BIT_SAMPLE 500 43 /* when polling for a state change, sample once every 50 microseconds */ 44 #define CEC_TIM_SAMPLE 50 45 46 #define CEC_TIM_LOW_DRIVE_ERROR (1.5 * CEC_TIM_DATA_BIT_TOTAL) 47 48 /* 49 * Total data bit time that is too short/long for a valid bit, 50 * used for error injection. 51 */ 52 #define CEC_TIM_DATA_BIT_TOTAL_SHORT 1800 53 #define CEC_TIM_DATA_BIT_TOTAL_LONG 2900 54 55 /* 56 * Total start bit time that is too short/long for a valid bit, 57 * used for error injection. 58 */ 59 #define CEC_TIM_START_BIT_TOTAL_SHORT 4100 60 #define CEC_TIM_START_BIT_TOTAL_LONG 5000 61 62 /* Data bits are 0-7, EOM is bit 8 and ACK is bit 9 */ 63 #define EOM_BIT 8 64 #define ACK_BIT 9 65 66 struct cec_state { 67 const char * const name; 68 unsigned int usecs; 69 }; 70 71 static const struct cec_state states[CEC_PIN_STATES] = { 72 { "Off", 0 }, 73 { "Idle", CEC_TIM_IDLE_SAMPLE }, 74 { "Tx Wait", CEC_TIM_SAMPLE }, 75 { "Tx Wait for High", CEC_TIM_IDLE_SAMPLE }, 76 { "Tx Start Bit Low", CEC_TIM_START_BIT_LOW }, 77 { "Tx Start Bit High", CEC_TIM_START_BIT_TOTAL - CEC_TIM_START_BIT_LOW }, 78 { "Tx Start Bit High Short", CEC_TIM_START_BIT_TOTAL_SHORT - CEC_TIM_START_BIT_LOW }, 79 { "Tx Start Bit High Long", CEC_TIM_START_BIT_TOTAL_LONG - CEC_TIM_START_BIT_LOW }, 80 { "Tx Start Bit Low Custom", 0 }, 81 { "Tx Start Bit High Custom", 0 }, 82 { "Tx Data 0 Low", CEC_TIM_DATA_BIT_0_LOW }, 83 { "Tx Data 0 High", CEC_TIM_DATA_BIT_TOTAL - CEC_TIM_DATA_BIT_0_LOW }, 84 { "Tx Data 0 High Short", CEC_TIM_DATA_BIT_TOTAL_SHORT - CEC_TIM_DATA_BIT_0_LOW }, 85 { "Tx Data 0 High Long", CEC_TIM_DATA_BIT_TOTAL_LONG - CEC_TIM_DATA_BIT_0_LOW }, 86 { "Tx Data 1 Low", CEC_TIM_DATA_BIT_1_LOW }, 87 { "Tx Data 1 High", CEC_TIM_DATA_BIT_TOTAL - CEC_TIM_DATA_BIT_1_LOW }, 88 { "Tx Data 1 High Short", CEC_TIM_DATA_BIT_TOTAL_SHORT - CEC_TIM_DATA_BIT_1_LOW }, 89 { "Tx Data 1 High Long", CEC_TIM_DATA_BIT_TOTAL_LONG - CEC_TIM_DATA_BIT_1_LOW }, 90 { "Tx Data 1 High Pre Sample", CEC_TIM_DATA_BIT_SAMPLE - CEC_TIM_DATA_BIT_1_LOW }, 91 { "Tx Data 1 High Post Sample", CEC_TIM_DATA_BIT_TOTAL - CEC_TIM_DATA_BIT_SAMPLE }, 92 { "Tx Data 1 High Post Sample Short", CEC_TIM_DATA_BIT_TOTAL_SHORT - CEC_TIM_DATA_BIT_SAMPLE }, 93 { "Tx Data 1 High Post Sample Long", CEC_TIM_DATA_BIT_TOTAL_LONG - CEC_TIM_DATA_BIT_SAMPLE }, 94 { "Tx Data Bit Low Custom", 0 }, 95 { "Tx Data Bit High Custom", 0 }, 96 { "Tx Pulse Low Custom", 0 }, 97 { "Tx Pulse High Custom", 0 }, 98 { "Tx Low Drive", CEC_TIM_LOW_DRIVE_ERROR }, 99 { "Rx Start Bit Low", CEC_TIM_SAMPLE }, 100 { "Rx Start Bit High", CEC_TIM_SAMPLE }, 101 { "Rx Data Sample", CEC_TIM_DATA_BIT_SAMPLE }, 102 { "Rx Data Post Sample", CEC_TIM_DATA_BIT_HIGH - CEC_TIM_DATA_BIT_SAMPLE }, 103 { "Rx Data Wait for Low", CEC_TIM_SAMPLE }, 104 { "Rx Ack Low", CEC_TIM_DATA_BIT_0_LOW }, 105 { "Rx Ack Low Post", CEC_TIM_DATA_BIT_HIGH - CEC_TIM_DATA_BIT_0_LOW }, 106 { "Rx Ack High Post", CEC_TIM_DATA_BIT_HIGH }, 107 { "Rx Ack Finish", CEC_TIM_DATA_BIT_TOTAL_MIN - CEC_TIM_DATA_BIT_HIGH }, 108 { "Rx Low Drive", CEC_TIM_LOW_DRIVE_ERROR }, 109 { "Rx Irq", 0 }, 110 }; 111 112 static void cec_pin_update(struct cec_pin *pin, bool v, bool force) 113 { 114 if (!force && v == pin->adap->cec_pin_is_high) 115 return; 116 117 pin->adap->cec_pin_is_high = v; 118 if (atomic_read_acquire(&pin->work_pin_num_events) < CEC_NUM_PIN_EVENTS) { 119 u8 ev = v; 120 121 if (pin->work_pin_events_dropped) { 122 pin->work_pin_events_dropped = false; 123 ev |= CEC_PIN_EVENT_FL_DROPPED; 124 } 125 pin->work_pin_events[pin->work_pin_events_wr] = ev; 126 pin->work_pin_ts[pin->work_pin_events_wr] = ktime_get(); 127 pin->work_pin_events_wr = 128 (pin->work_pin_events_wr + 1) % CEC_NUM_PIN_EVENTS; 129 atomic_inc_return_release(&pin->work_pin_num_events); 130 } else { 131 pin->work_pin_events_dropped = true; 132 pin->work_pin_events_dropped_cnt++; 133 } 134 wake_up_interruptible(&pin->kthread_waitq); 135 } 136 137 static bool cec_pin_read(struct cec_pin *pin) 138 { 139 bool v = call_pin_op(pin, read); 140 141 cec_pin_update(pin, v, false); 142 return v; 143 } 144 145 static void cec_pin_insert_glitch(struct cec_pin *pin, bool rising_edge) 146 { 147 /* 148 * Insert a short glitch after the falling or rising edge to 149 * simulate reflections on the CEC line. This can be used to 150 * test deglitch filters, which should be present in CEC devices 151 * to deal with noise on the line. 152 */ 153 if (!pin->tx_glitch_high_usecs || !pin->tx_glitch_low_usecs) 154 return; 155 if (rising_edge) { 156 udelay(pin->tx_glitch_high_usecs); 157 call_void_pin_op(pin, low); 158 udelay(pin->tx_glitch_low_usecs); 159 call_void_pin_op(pin, high); 160 } else { 161 udelay(pin->tx_glitch_low_usecs); 162 call_void_pin_op(pin, high); 163 udelay(pin->tx_glitch_high_usecs); 164 call_void_pin_op(pin, low); 165 } 166 } 167 168 static void cec_pin_low(struct cec_pin *pin) 169 { 170 call_void_pin_op(pin, low); 171 if (pin->tx_glitch_falling_edge && pin->adap->cec_pin_is_high) 172 cec_pin_insert_glitch(pin, false); 173 cec_pin_update(pin, false, false); 174 } 175 176 static bool cec_pin_high(struct cec_pin *pin) 177 { 178 call_void_pin_op(pin, high); 179 if (pin->tx_glitch_rising_edge && !pin->adap->cec_pin_is_high) 180 cec_pin_insert_glitch(pin, true); 181 return cec_pin_read(pin); 182 } 183 184 static bool rx_error_inj(struct cec_pin *pin, unsigned int mode_offset, 185 int arg_idx, u8 *arg) 186 { 187 #ifdef CONFIG_CEC_PIN_ERROR_INJ 188 u16 cmd = cec_pin_rx_error_inj(pin); 189 u64 e = pin->error_inj[cmd]; 190 unsigned int mode = (e >> mode_offset) & CEC_ERROR_INJ_MODE_MASK; 191 192 if (arg_idx >= 0) { 193 u8 pos = pin->error_inj_args[cmd][arg_idx]; 194 195 if (arg) 196 *arg = pos; 197 else if (pos != pin->rx_bit) 198 return false; 199 } 200 201 switch (mode) { 202 case CEC_ERROR_INJ_MODE_ONCE: 203 pin->error_inj[cmd] &= 204 ~(CEC_ERROR_INJ_MODE_MASK << mode_offset); 205 return true; 206 case CEC_ERROR_INJ_MODE_ALWAYS: 207 return true; 208 case CEC_ERROR_INJ_MODE_TOGGLE: 209 return pin->rx_toggle; 210 default: 211 return false; 212 } 213 #else 214 return false; 215 #endif 216 } 217 218 static bool rx_nack(struct cec_pin *pin) 219 { 220 return rx_error_inj(pin, CEC_ERROR_INJ_RX_NACK_OFFSET, -1, NULL); 221 } 222 223 static bool rx_low_drive(struct cec_pin *pin) 224 { 225 return rx_error_inj(pin, CEC_ERROR_INJ_RX_LOW_DRIVE_OFFSET, 226 CEC_ERROR_INJ_RX_LOW_DRIVE_ARG_IDX, NULL); 227 } 228 229 static bool rx_add_byte(struct cec_pin *pin) 230 { 231 return rx_error_inj(pin, CEC_ERROR_INJ_RX_ADD_BYTE_OFFSET, -1, NULL); 232 } 233 234 static bool rx_remove_byte(struct cec_pin *pin) 235 { 236 return rx_error_inj(pin, CEC_ERROR_INJ_RX_REMOVE_BYTE_OFFSET, -1, NULL); 237 } 238 239 static bool rx_arb_lost(struct cec_pin *pin, u8 *poll) 240 { 241 return pin->tx_msg.len == 0 && 242 rx_error_inj(pin, CEC_ERROR_INJ_RX_ARB_LOST_OFFSET, 243 CEC_ERROR_INJ_RX_ARB_LOST_ARG_IDX, poll); 244 } 245 246 static bool tx_error_inj(struct cec_pin *pin, unsigned int mode_offset, 247 int arg_idx, u8 *arg) 248 { 249 #ifdef CONFIG_CEC_PIN_ERROR_INJ 250 u16 cmd = cec_pin_tx_error_inj(pin); 251 u64 e = pin->error_inj[cmd]; 252 unsigned int mode = (e >> mode_offset) & CEC_ERROR_INJ_MODE_MASK; 253 254 if (arg_idx >= 0) { 255 u8 pos = pin->error_inj_args[cmd][arg_idx]; 256 257 if (arg) 258 *arg = pos; 259 else if (pos != pin->tx_bit) 260 return false; 261 } 262 263 switch (mode) { 264 case CEC_ERROR_INJ_MODE_ONCE: 265 pin->error_inj[cmd] &= 266 ~(CEC_ERROR_INJ_MODE_MASK << mode_offset); 267 return true; 268 case CEC_ERROR_INJ_MODE_ALWAYS: 269 return true; 270 case CEC_ERROR_INJ_MODE_TOGGLE: 271 return pin->tx_toggle; 272 default: 273 return false; 274 } 275 #else 276 return false; 277 #endif 278 } 279 280 static bool tx_no_eom(struct cec_pin *pin) 281 { 282 return tx_error_inj(pin, CEC_ERROR_INJ_TX_NO_EOM_OFFSET, -1, NULL); 283 } 284 285 static bool tx_early_eom(struct cec_pin *pin) 286 { 287 return tx_error_inj(pin, CEC_ERROR_INJ_TX_EARLY_EOM_OFFSET, -1, NULL); 288 } 289 290 static bool tx_short_bit(struct cec_pin *pin) 291 { 292 return tx_error_inj(pin, CEC_ERROR_INJ_TX_SHORT_BIT_OFFSET, 293 CEC_ERROR_INJ_TX_SHORT_BIT_ARG_IDX, NULL); 294 } 295 296 static bool tx_long_bit(struct cec_pin *pin) 297 { 298 return tx_error_inj(pin, CEC_ERROR_INJ_TX_LONG_BIT_OFFSET, 299 CEC_ERROR_INJ_TX_LONG_BIT_ARG_IDX, NULL); 300 } 301 302 static bool tx_custom_bit(struct cec_pin *pin) 303 { 304 return tx_error_inj(pin, CEC_ERROR_INJ_TX_CUSTOM_BIT_OFFSET, 305 CEC_ERROR_INJ_TX_CUSTOM_BIT_ARG_IDX, NULL); 306 } 307 308 static bool tx_short_start(struct cec_pin *pin) 309 { 310 return tx_error_inj(pin, CEC_ERROR_INJ_TX_SHORT_START_OFFSET, -1, NULL); 311 } 312 313 static bool tx_long_start(struct cec_pin *pin) 314 { 315 return tx_error_inj(pin, CEC_ERROR_INJ_TX_LONG_START_OFFSET, -1, NULL); 316 } 317 318 static bool tx_custom_start(struct cec_pin *pin) 319 { 320 return tx_error_inj(pin, CEC_ERROR_INJ_TX_CUSTOM_START_OFFSET, 321 -1, NULL); 322 } 323 324 static bool tx_last_bit(struct cec_pin *pin) 325 { 326 return tx_error_inj(pin, CEC_ERROR_INJ_TX_LAST_BIT_OFFSET, 327 CEC_ERROR_INJ_TX_LAST_BIT_ARG_IDX, NULL); 328 } 329 330 static u8 tx_add_bytes(struct cec_pin *pin) 331 { 332 u8 bytes; 333 334 if (tx_error_inj(pin, CEC_ERROR_INJ_TX_ADD_BYTES_OFFSET, 335 CEC_ERROR_INJ_TX_ADD_BYTES_ARG_IDX, &bytes)) 336 return bytes; 337 return 0; 338 } 339 340 static bool tx_remove_byte(struct cec_pin *pin) 341 { 342 return tx_error_inj(pin, CEC_ERROR_INJ_TX_REMOVE_BYTE_OFFSET, -1, NULL); 343 } 344 345 static bool tx_low_drive(struct cec_pin *pin) 346 { 347 return tx_error_inj(pin, CEC_ERROR_INJ_TX_LOW_DRIVE_OFFSET, 348 CEC_ERROR_INJ_TX_LOW_DRIVE_ARG_IDX, NULL); 349 } 350 351 static void cec_pin_to_idle(struct cec_pin *pin) 352 { 353 /* 354 * Reset all status fields, release the bus and 355 * go to idle state. 356 */ 357 pin->rx_bit = pin->tx_bit = 0; 358 pin->rx_msg.len = 0; 359 memset(pin->rx_msg.msg, 0, sizeof(pin->rx_msg.msg)); 360 pin->ts = ns_to_ktime(0); 361 pin->tx_generated_poll = false; 362 pin->tx_post_eom = false; 363 if (pin->state >= CEC_ST_TX_WAIT && 364 pin->state <= CEC_ST_TX_LOW_DRIVE) 365 pin->tx_toggle ^= 1; 366 if (pin->state >= CEC_ST_RX_START_BIT_LOW && 367 pin->state <= CEC_ST_RX_LOW_DRIVE) 368 pin->rx_toggle ^= 1; 369 pin->state = CEC_ST_IDLE; 370 } 371 372 /* 373 * Handle Transmit-related states 374 * 375 * Basic state changes when transmitting: 376 * 377 * Idle -> Tx Wait (waiting for the end of signal free time) -> 378 * Tx Start Bit Low -> Tx Start Bit High -> 379 * 380 * Regular data bits + EOM: 381 * Tx Data 0 Low -> Tx Data 0 High -> 382 * or: 383 * Tx Data 1 Low -> Tx Data 1 High -> 384 * 385 * First 4 data bits or Ack bit: 386 * Tx Data 0 Low -> Tx Data 0 High -> 387 * or: 388 * Tx Data 1 Low -> Tx Data 1 High -> Tx Data 1 Pre Sample -> 389 * Tx Data 1 Post Sample -> 390 * 391 * After the last Ack go to Idle. 392 * 393 * If it detects a Low Drive condition then: 394 * Tx Wait For High -> Idle 395 * 396 * If it loses arbitration, then it switches to state Rx Data Post Sample. 397 */ 398 static void cec_pin_tx_states(struct cec_pin *pin, ktime_t ts) 399 { 400 bool v; 401 bool is_ack_bit, ack; 402 403 switch (pin->state) { 404 case CEC_ST_TX_WAIT_FOR_HIGH: 405 if (cec_pin_read(pin)) 406 cec_pin_to_idle(pin); 407 break; 408 409 case CEC_ST_TX_START_BIT_LOW: 410 if (tx_short_start(pin)) { 411 /* 412 * Error Injection: send an invalid (too short) 413 * start pulse. 414 */ 415 pin->state = CEC_ST_TX_START_BIT_HIGH_SHORT; 416 } else if (tx_long_start(pin)) { 417 /* 418 * Error Injection: send an invalid (too long) 419 * start pulse. 420 */ 421 pin->state = CEC_ST_TX_START_BIT_HIGH_LONG; 422 } else { 423 pin->state = CEC_ST_TX_START_BIT_HIGH; 424 } 425 /* Generate start bit */ 426 cec_pin_high(pin); 427 break; 428 429 case CEC_ST_TX_START_BIT_LOW_CUSTOM: 430 pin->state = CEC_ST_TX_START_BIT_HIGH_CUSTOM; 431 /* Generate start bit */ 432 cec_pin_high(pin); 433 break; 434 435 case CEC_ST_TX_DATA_BIT_1_HIGH_POST_SAMPLE: 436 case CEC_ST_TX_DATA_BIT_1_HIGH_POST_SAMPLE_SHORT: 437 case CEC_ST_TX_DATA_BIT_1_HIGH_POST_SAMPLE_LONG: 438 if (pin->tx_nacked) { 439 cec_pin_to_idle(pin); 440 pin->tx_msg.len = 0; 441 if (pin->tx_generated_poll) 442 break; 443 pin->work_tx_ts = ts; 444 pin->work_tx_status = CEC_TX_STATUS_NACK; 445 wake_up_interruptible(&pin->kthread_waitq); 446 break; 447 } 448 fallthrough; 449 case CEC_ST_TX_DATA_BIT_0_HIGH: 450 case CEC_ST_TX_DATA_BIT_0_HIGH_SHORT: 451 case CEC_ST_TX_DATA_BIT_0_HIGH_LONG: 452 case CEC_ST_TX_DATA_BIT_1_HIGH: 453 case CEC_ST_TX_DATA_BIT_1_HIGH_SHORT: 454 case CEC_ST_TX_DATA_BIT_1_HIGH_LONG: 455 /* 456 * If the read value is 1, then all is OK, otherwise we have a 457 * low drive condition. 458 * 459 * Special case: when we generate a poll message due to an 460 * Arbitration Lost error injection, then ignore this since 461 * the pin can actually be low in that case. 462 */ 463 if (!cec_pin_read(pin) && !pin->tx_generated_poll) { 464 /* 465 * It's 0, so someone detected an error and pulled the 466 * line low for 1.5 times the nominal bit period. 467 */ 468 pin->tx_msg.len = 0; 469 pin->state = CEC_ST_TX_WAIT_FOR_HIGH; 470 pin->work_tx_ts = ts; 471 pin->work_tx_status = CEC_TX_STATUS_LOW_DRIVE; 472 pin->tx_low_drive_cnt++; 473 wake_up_interruptible(&pin->kthread_waitq); 474 break; 475 } 476 fallthrough; 477 case CEC_ST_TX_DATA_BIT_HIGH_CUSTOM: 478 if (tx_last_bit(pin)) { 479 /* Error Injection: just stop sending after this bit */ 480 cec_pin_to_idle(pin); 481 pin->tx_msg.len = 0; 482 if (pin->tx_generated_poll) 483 break; 484 pin->work_tx_ts = ts; 485 pin->work_tx_status = CEC_TX_STATUS_OK; 486 wake_up_interruptible(&pin->kthread_waitq); 487 break; 488 } 489 pin->tx_bit++; 490 fallthrough; 491 case CEC_ST_TX_START_BIT_HIGH: 492 case CEC_ST_TX_START_BIT_HIGH_SHORT: 493 case CEC_ST_TX_START_BIT_HIGH_LONG: 494 case CEC_ST_TX_START_BIT_HIGH_CUSTOM: 495 if (tx_low_drive(pin)) { 496 /* Error injection: go to low drive */ 497 cec_pin_low(pin); 498 pin->state = CEC_ST_TX_LOW_DRIVE; 499 pin->tx_msg.len = 0; 500 if (pin->tx_generated_poll) 501 break; 502 pin->work_tx_ts = ts; 503 pin->work_tx_status = CEC_TX_STATUS_LOW_DRIVE; 504 pin->tx_low_drive_cnt++; 505 wake_up_interruptible(&pin->kthread_waitq); 506 break; 507 } 508 if (pin->tx_bit / 10 >= pin->tx_msg.len + pin->tx_extra_bytes) { 509 cec_pin_to_idle(pin); 510 pin->tx_msg.len = 0; 511 if (pin->tx_generated_poll) 512 break; 513 pin->work_tx_ts = ts; 514 pin->work_tx_status = CEC_TX_STATUS_OK; 515 wake_up_interruptible(&pin->kthread_waitq); 516 break; 517 } 518 519 switch (pin->tx_bit % 10) { 520 default: { 521 /* 522 * In the CEC_ERROR_INJ_TX_ADD_BYTES case we transmit 523 * extra bytes, so pin->tx_bit / 10 can become >= 16. 524 * Generate bit values for those extra bytes instead 525 * of reading them from the transmit buffer. 526 */ 527 unsigned int idx = (pin->tx_bit / 10); 528 u8 val = idx; 529 530 if (idx < pin->tx_msg.len) 531 val = pin->tx_msg.msg[idx]; 532 v = val & (1 << (7 - (pin->tx_bit % 10))); 533 534 pin->state = v ? CEC_ST_TX_DATA_BIT_1_LOW : 535 CEC_ST_TX_DATA_BIT_0_LOW; 536 break; 537 } 538 case EOM_BIT: { 539 unsigned int tot_len = pin->tx_msg.len + 540 pin->tx_extra_bytes; 541 unsigned int tx_byte_idx = pin->tx_bit / 10; 542 543 v = !pin->tx_post_eom && tx_byte_idx == tot_len - 1; 544 if (tot_len > 1 && tx_byte_idx == tot_len - 2 && 545 tx_early_eom(pin)) { 546 /* Error injection: set EOM one byte early */ 547 v = true; 548 pin->tx_post_eom = true; 549 } else if (v && tx_no_eom(pin)) { 550 /* Error injection: no EOM */ 551 v = false; 552 } 553 pin->state = v ? CEC_ST_TX_DATA_BIT_1_LOW : 554 CEC_ST_TX_DATA_BIT_0_LOW; 555 break; 556 } 557 case ACK_BIT: 558 pin->state = CEC_ST_TX_DATA_BIT_1_LOW; 559 break; 560 } 561 if (tx_custom_bit(pin)) 562 pin->state = CEC_ST_TX_DATA_BIT_LOW_CUSTOM; 563 cec_pin_low(pin); 564 break; 565 566 case CEC_ST_TX_DATA_BIT_0_LOW: 567 case CEC_ST_TX_DATA_BIT_1_LOW: 568 v = pin->state == CEC_ST_TX_DATA_BIT_1_LOW; 569 is_ack_bit = pin->tx_bit % 10 == ACK_BIT; 570 if (v && (pin->tx_bit < 4 || is_ack_bit)) { 571 pin->state = CEC_ST_TX_DATA_BIT_1_HIGH_PRE_SAMPLE; 572 } else if (!is_ack_bit && tx_short_bit(pin)) { 573 /* Error Injection: send an invalid (too short) bit */ 574 pin->state = v ? CEC_ST_TX_DATA_BIT_1_HIGH_SHORT : 575 CEC_ST_TX_DATA_BIT_0_HIGH_SHORT; 576 } else if (!is_ack_bit && tx_long_bit(pin)) { 577 /* Error Injection: send an invalid (too long) bit */ 578 pin->state = v ? CEC_ST_TX_DATA_BIT_1_HIGH_LONG : 579 CEC_ST_TX_DATA_BIT_0_HIGH_LONG; 580 } else { 581 pin->state = v ? CEC_ST_TX_DATA_BIT_1_HIGH : 582 CEC_ST_TX_DATA_BIT_0_HIGH; 583 } 584 cec_pin_high(pin); 585 break; 586 587 case CEC_ST_TX_DATA_BIT_LOW_CUSTOM: 588 pin->state = CEC_ST_TX_DATA_BIT_HIGH_CUSTOM; 589 cec_pin_high(pin); 590 break; 591 592 case CEC_ST_TX_DATA_BIT_1_HIGH_PRE_SAMPLE: 593 /* Read the CEC value at the sample time */ 594 v = cec_pin_read(pin); 595 is_ack_bit = pin->tx_bit % 10 == ACK_BIT; 596 /* 597 * If v == 0 and we're within the first 4 bits 598 * of the initiator, then someone else started 599 * transmitting and we lost the arbitration 600 * (i.e. the logical address of the other 601 * transmitter has more leading 0 bits in the 602 * initiator). 603 */ 604 if (!v && !is_ack_bit && !pin->tx_generated_poll) { 605 pin->tx_msg.len = 0; 606 pin->work_tx_ts = ts; 607 pin->work_tx_status = CEC_TX_STATUS_ARB_LOST; 608 wake_up_interruptible(&pin->kthread_waitq); 609 pin->rx_bit = pin->tx_bit; 610 pin->tx_bit = 0; 611 memset(pin->rx_msg.msg, 0, sizeof(pin->rx_msg.msg)); 612 pin->rx_msg.msg[0] = pin->tx_msg.msg[0]; 613 pin->rx_msg.msg[0] &= (0xff << (8 - pin->rx_bit)); 614 pin->rx_msg.len = 0; 615 pin->ts = ktime_sub_us(ts, CEC_TIM_DATA_BIT_SAMPLE); 616 pin->state = CEC_ST_RX_DATA_POST_SAMPLE; 617 pin->rx_bit++; 618 break; 619 } 620 pin->state = CEC_ST_TX_DATA_BIT_1_HIGH_POST_SAMPLE; 621 if (!is_ack_bit && tx_short_bit(pin)) { 622 /* Error Injection: send an invalid (too short) bit */ 623 pin->state = CEC_ST_TX_DATA_BIT_1_HIGH_POST_SAMPLE_SHORT; 624 } else if (!is_ack_bit && tx_long_bit(pin)) { 625 /* Error Injection: send an invalid (too long) bit */ 626 pin->state = CEC_ST_TX_DATA_BIT_1_HIGH_POST_SAMPLE_LONG; 627 } 628 if (!is_ack_bit) 629 break; 630 /* Was the message ACKed? */ 631 ack = cec_msg_is_broadcast(&pin->tx_msg) ? v : !v; 632 if (!ack && (!pin->tx_ignore_nack_until_eom || 633 pin->tx_bit / 10 == pin->tx_msg.len - 1) && 634 !pin->tx_post_eom) { 635 /* 636 * Note: the CEC spec is ambiguous regarding 637 * what action to take when a NACK appears 638 * before the last byte of the payload was 639 * transmitted: either stop transmitting 640 * immediately, or wait until the last byte 641 * was transmitted. 642 * 643 * Most CEC implementations appear to stop 644 * immediately, and that's what we do here 645 * as well. 646 */ 647 pin->tx_nacked = true; 648 } 649 break; 650 651 case CEC_ST_TX_PULSE_LOW_CUSTOM: 652 cec_pin_high(pin); 653 pin->state = CEC_ST_TX_PULSE_HIGH_CUSTOM; 654 break; 655 656 case CEC_ST_TX_PULSE_HIGH_CUSTOM: 657 cec_pin_to_idle(pin); 658 break; 659 660 default: 661 break; 662 } 663 } 664 665 /* 666 * Handle Receive-related states 667 * 668 * Basic state changes when receiving: 669 * 670 * Rx Start Bit Low -> Rx Start Bit High -> 671 * Regular data bits + EOM: 672 * Rx Data Sample -> Rx Data Post Sample -> Rx Data High -> 673 * Ack bit 0: 674 * Rx Ack Low -> Rx Ack Low Post -> Rx Data High -> 675 * Ack bit 1: 676 * Rx Ack High Post -> Rx Data High -> 677 * Ack bit 0 && EOM: 678 * Rx Ack Low -> Rx Ack Low Post -> Rx Ack Finish -> Idle 679 */ 680 static void cec_pin_rx_states(struct cec_pin *pin, ktime_t ts) 681 { 682 s32 delta; 683 bool v; 684 bool ack; 685 bool bcast, for_us; 686 u8 dest; 687 u8 poll; 688 689 switch (pin->state) { 690 /* Receive states */ 691 case CEC_ST_RX_START_BIT_LOW: 692 v = cec_pin_read(pin); 693 if (!v) 694 break; 695 delta = ktime_us_delta(ts, pin->ts); 696 /* Start bit low is too short, go back to idle */ 697 if (delta < CEC_TIM_START_BIT_LOW_MIN - CEC_TIM_IDLE_SAMPLE) { 698 if (!pin->rx_start_bit_low_too_short_cnt++) { 699 pin->rx_start_bit_low_too_short_ts = ktime_to_ns(pin->ts); 700 pin->rx_start_bit_low_too_short_delta = delta; 701 } 702 cec_pin_to_idle(pin); 703 break; 704 } 705 pin->state = CEC_ST_RX_START_BIT_HIGH; 706 if (rx_arb_lost(pin, &poll)) { 707 /* 708 * Normally rx_toggle is toggled in cec_pin_to_idle() 709 * when we're in an RX state, but here we switch to TX 710 * mode, so cec_pin_to_idle() sees a TX mode and never 711 * toggles rx_toggle. So toggle it here as a special 712 * corner case. 713 */ 714 pin->rx_toggle ^= 1; 715 cec_msg_init(&pin->tx_msg, poll >> 4, poll & 0xf); 716 pin->tx_generated_poll = true; 717 pin->tx_extra_bytes = 0; 718 pin->state = CEC_ST_TX_START_BIT_HIGH; 719 pin->ts = ts; 720 } 721 break; 722 723 case CEC_ST_RX_START_BIT_HIGH: 724 v = cec_pin_read(pin); 725 delta = ktime_us_delta(ts, pin->ts); 726 /* 727 * Unfortunately the spec does not specify when to give up 728 * and go to idle. We just pick TOTAL_LONG. 729 */ 730 if (v && delta > CEC_TIM_START_BIT_TOTAL_LONG) { 731 pin->rx_start_bit_too_long_cnt++; 732 cec_pin_to_idle(pin); 733 break; 734 } 735 if (v) 736 break; 737 /* Start bit is too short, go back to idle */ 738 if (delta < CEC_TIM_START_BIT_TOTAL_MIN - CEC_TIM_IDLE_SAMPLE) { 739 if (!pin->rx_start_bit_too_short_cnt++) { 740 pin->rx_start_bit_too_short_ts = ktime_to_ns(pin->ts); 741 pin->rx_start_bit_too_short_delta = delta; 742 } 743 cec_pin_to_idle(pin); 744 break; 745 } 746 if (rx_low_drive(pin)) { 747 /* Error injection: go to low drive */ 748 cec_pin_low(pin); 749 pin->state = CEC_ST_RX_LOW_DRIVE; 750 pin->rx_low_drive_cnt++; 751 break; 752 } 753 pin->state = CEC_ST_RX_DATA_SAMPLE; 754 pin->ts = ts; 755 pin->rx_eom = false; 756 break; 757 758 case CEC_ST_RX_DATA_SAMPLE: 759 v = cec_pin_read(pin); 760 pin->state = CEC_ST_RX_DATA_POST_SAMPLE; 761 switch (pin->rx_bit % 10) { 762 default: 763 if (pin->rx_bit / 10 < CEC_MAX_MSG_SIZE) 764 pin->rx_msg.msg[pin->rx_bit / 10] |= 765 v << (7 - (pin->rx_bit % 10)); 766 break; 767 case EOM_BIT: 768 pin->rx_eom = v; 769 pin->rx_msg.len = pin->rx_bit / 10 + 1; 770 break; 771 case ACK_BIT: 772 break; 773 } 774 pin->rx_bit++; 775 break; 776 777 case CEC_ST_RX_DATA_POST_SAMPLE: 778 pin->state = CEC_ST_RX_DATA_WAIT_FOR_LOW; 779 break; 780 781 case CEC_ST_RX_DATA_WAIT_FOR_LOW: 782 v = cec_pin_read(pin); 783 delta = ktime_us_delta(ts, pin->ts); 784 /* 785 * Unfortunately the spec does not specify when to give up 786 * and go to idle. We just pick TOTAL_LONG. 787 */ 788 if (v && delta > CEC_TIM_DATA_BIT_TOTAL_LONG) { 789 pin->rx_data_bit_too_long_cnt++; 790 cec_pin_to_idle(pin); 791 break; 792 } 793 if (v) 794 break; 795 796 if (rx_low_drive(pin)) { 797 /* Error injection: go to low drive */ 798 cec_pin_low(pin); 799 pin->state = CEC_ST_RX_LOW_DRIVE; 800 pin->rx_low_drive_cnt++; 801 break; 802 } 803 804 /* 805 * Go to low drive state when the total bit time is 806 * too short. 807 */ 808 if (delta < CEC_TIM_DATA_BIT_TOTAL_MIN && !pin->rx_no_low_drive) { 809 if (!pin->rx_data_bit_too_short_cnt++) { 810 pin->rx_data_bit_too_short_ts = ktime_to_ns(pin->ts); 811 pin->rx_data_bit_too_short_delta = delta; 812 } 813 cec_pin_low(pin); 814 pin->state = CEC_ST_RX_LOW_DRIVE; 815 pin->rx_low_drive_cnt++; 816 break; 817 } 818 pin->ts = ts; 819 if (pin->rx_bit % 10 != 9) { 820 pin->state = CEC_ST_RX_DATA_SAMPLE; 821 break; 822 } 823 824 dest = cec_msg_destination(&pin->rx_msg); 825 bcast = dest == CEC_LOG_ADDR_BROADCAST; 826 /* for_us == broadcast or directed to us */ 827 for_us = bcast || (pin->la_mask & (1 << dest)); 828 /* ACK bit value */ 829 ack = bcast ? 1 : !for_us; 830 831 if (for_us && rx_nack(pin)) { 832 /* Error injection: toggle the ACK bit */ 833 ack = !ack; 834 } 835 836 if (ack) { 837 /* No need to write to the bus, just wait */ 838 pin->state = CEC_ST_RX_ACK_HIGH_POST; 839 break; 840 } 841 cec_pin_low(pin); 842 pin->state = CEC_ST_RX_ACK_LOW; 843 break; 844 845 case CEC_ST_RX_ACK_LOW: 846 cec_pin_high(pin); 847 pin->state = CEC_ST_RX_ACK_LOW_POST; 848 break; 849 850 case CEC_ST_RX_ACK_LOW_POST: 851 case CEC_ST_RX_ACK_HIGH_POST: 852 v = cec_pin_read(pin); 853 if (v && pin->rx_eom) { 854 pin->work_rx_msg = pin->rx_msg; 855 pin->work_rx_msg.rx_ts = ktime_to_ns(ts); 856 wake_up_interruptible(&pin->kthread_waitq); 857 pin->ts = ts; 858 pin->state = CEC_ST_RX_ACK_FINISH; 859 break; 860 } 861 pin->rx_bit++; 862 pin->state = CEC_ST_RX_DATA_WAIT_FOR_LOW; 863 break; 864 865 case CEC_ST_RX_ACK_FINISH: 866 cec_pin_to_idle(pin); 867 break; 868 869 default: 870 break; 871 } 872 } 873 874 /* 875 * Main timer function 876 * 877 */ 878 static enum hrtimer_restart cec_pin_timer(struct hrtimer *timer) 879 { 880 struct cec_pin *pin = container_of(timer, struct cec_pin, timer); 881 struct cec_adapter *adap = pin->adap; 882 ktime_t ts; 883 s32 delta; 884 u32 usecs; 885 886 ts = ktime_get(); 887 if (ktime_to_ns(pin->timer_ts)) { 888 delta = ktime_us_delta(ts, pin->timer_ts); 889 pin->timer_cnt++; 890 if (delta > 100 && pin->state != CEC_ST_IDLE) { 891 /* Keep track of timer overruns */ 892 pin->timer_sum_overrun += delta; 893 pin->timer_100us_overruns++; 894 if (delta > 300) 895 pin->timer_300us_overruns++; 896 if (delta > pin->timer_max_overrun) 897 pin->timer_max_overrun = delta; 898 } 899 } 900 if (adap->monitor_pin_cnt) 901 cec_pin_read(pin); 902 903 if (pin->wait_usecs) { 904 /* 905 * If we are monitoring the pin, then we have to 906 * sample at regular intervals. 907 */ 908 if (pin->wait_usecs > 150) { 909 pin->wait_usecs -= 100; 910 pin->timer_ts = ktime_add_us(ts, 100); 911 hrtimer_forward_now(timer, us_to_ktime(100)); 912 return HRTIMER_RESTART; 913 } 914 if (pin->wait_usecs > 100) { 915 pin->wait_usecs /= 2; 916 pin->timer_ts = ktime_add_us(ts, pin->wait_usecs); 917 hrtimer_forward_now(timer, 918 us_to_ktime(pin->wait_usecs)); 919 return HRTIMER_RESTART; 920 } 921 pin->timer_ts = ktime_add_us(ts, pin->wait_usecs); 922 hrtimer_forward_now(timer, 923 us_to_ktime(pin->wait_usecs)); 924 pin->wait_usecs = 0; 925 return HRTIMER_RESTART; 926 } 927 928 switch (pin->state) { 929 /* Transmit states */ 930 case CEC_ST_TX_WAIT_FOR_HIGH: 931 case CEC_ST_TX_START_BIT_LOW: 932 case CEC_ST_TX_START_BIT_HIGH: 933 case CEC_ST_TX_START_BIT_HIGH_SHORT: 934 case CEC_ST_TX_START_BIT_HIGH_LONG: 935 case CEC_ST_TX_START_BIT_LOW_CUSTOM: 936 case CEC_ST_TX_START_BIT_HIGH_CUSTOM: 937 case CEC_ST_TX_DATA_BIT_0_LOW: 938 case CEC_ST_TX_DATA_BIT_0_HIGH: 939 case CEC_ST_TX_DATA_BIT_0_HIGH_SHORT: 940 case CEC_ST_TX_DATA_BIT_0_HIGH_LONG: 941 case CEC_ST_TX_DATA_BIT_1_LOW: 942 case CEC_ST_TX_DATA_BIT_1_HIGH: 943 case CEC_ST_TX_DATA_BIT_1_HIGH_SHORT: 944 case CEC_ST_TX_DATA_BIT_1_HIGH_LONG: 945 case CEC_ST_TX_DATA_BIT_1_HIGH_PRE_SAMPLE: 946 case CEC_ST_TX_DATA_BIT_1_HIGH_POST_SAMPLE: 947 case CEC_ST_TX_DATA_BIT_1_HIGH_POST_SAMPLE_SHORT: 948 case CEC_ST_TX_DATA_BIT_1_HIGH_POST_SAMPLE_LONG: 949 case CEC_ST_TX_DATA_BIT_LOW_CUSTOM: 950 case CEC_ST_TX_DATA_BIT_HIGH_CUSTOM: 951 case CEC_ST_TX_PULSE_LOW_CUSTOM: 952 case CEC_ST_TX_PULSE_HIGH_CUSTOM: 953 cec_pin_tx_states(pin, ts); 954 break; 955 956 /* Receive states */ 957 case CEC_ST_RX_START_BIT_LOW: 958 case CEC_ST_RX_START_BIT_HIGH: 959 case CEC_ST_RX_DATA_SAMPLE: 960 case CEC_ST_RX_DATA_POST_SAMPLE: 961 case CEC_ST_RX_DATA_WAIT_FOR_LOW: 962 case CEC_ST_RX_ACK_LOW: 963 case CEC_ST_RX_ACK_LOW_POST: 964 case CEC_ST_RX_ACK_HIGH_POST: 965 case CEC_ST_RX_ACK_FINISH: 966 cec_pin_rx_states(pin, ts); 967 break; 968 969 case CEC_ST_IDLE: 970 case CEC_ST_TX_WAIT: 971 if (!cec_pin_high(pin)) { 972 /* Start bit, switch to receive state */ 973 pin->ts = ts; 974 pin->state = CEC_ST_RX_START_BIT_LOW; 975 /* 976 * If a transmit is pending, then that transmit should 977 * use a signal free time of no more than 978 * CEC_SIGNAL_FREE_TIME_NEW_INITIATOR since it will 979 * have a new initiator due to the receive that is now 980 * starting. 981 */ 982 if (pin->tx_msg.len && pin->tx_signal_free_time > 983 CEC_SIGNAL_FREE_TIME_NEW_INITIATOR) 984 pin->tx_signal_free_time = 985 CEC_SIGNAL_FREE_TIME_NEW_INITIATOR; 986 break; 987 } 988 if (ktime_to_ns(pin->ts) == 0) 989 pin->ts = ts; 990 if (pin->tx_msg.len) { 991 /* 992 * Check if the bus has been free for long enough 993 * so we can kick off the pending transmit. 994 */ 995 delta = ktime_us_delta(ts, pin->ts); 996 if (delta / CEC_TIM_DATA_BIT_TOTAL >= 997 pin->tx_signal_free_time) { 998 pin->tx_nacked = false; 999 if (tx_custom_start(pin)) 1000 pin->state = CEC_ST_TX_START_BIT_LOW_CUSTOM; 1001 else 1002 pin->state = CEC_ST_TX_START_BIT_LOW; 1003 /* Generate start bit */ 1004 cec_pin_low(pin); 1005 break; 1006 } 1007 if (delta / CEC_TIM_DATA_BIT_TOTAL >= 1008 pin->tx_signal_free_time - 1) 1009 pin->state = CEC_ST_TX_WAIT; 1010 break; 1011 } 1012 if (pin->tx_custom_pulse && pin->state == CEC_ST_IDLE) { 1013 pin->tx_custom_pulse = false; 1014 /* Generate custom pulse */ 1015 cec_pin_low(pin); 1016 pin->state = CEC_ST_TX_PULSE_LOW_CUSTOM; 1017 break; 1018 } 1019 if (pin->state != CEC_ST_IDLE || pin->ops->enable_irq == NULL || 1020 pin->enable_irq_failed || adap->is_configuring || 1021 adap->is_configured || adap->monitor_all_cnt || !adap->monitor_pin_cnt) 1022 break; 1023 /* Switch to interrupt mode */ 1024 atomic_set(&pin->work_irq_change, CEC_PIN_IRQ_ENABLE); 1025 pin->state = CEC_ST_RX_IRQ; 1026 wake_up_interruptible(&pin->kthread_waitq); 1027 return HRTIMER_NORESTART; 1028 1029 case CEC_ST_TX_LOW_DRIVE: 1030 case CEC_ST_RX_LOW_DRIVE: 1031 cec_pin_high(pin); 1032 cec_pin_to_idle(pin); 1033 break; 1034 1035 default: 1036 break; 1037 } 1038 1039 switch (pin->state) { 1040 case CEC_ST_TX_START_BIT_LOW_CUSTOM: 1041 case CEC_ST_TX_DATA_BIT_LOW_CUSTOM: 1042 case CEC_ST_TX_PULSE_LOW_CUSTOM: 1043 usecs = pin->tx_custom_low_usecs; 1044 break; 1045 case CEC_ST_TX_START_BIT_HIGH_CUSTOM: 1046 case CEC_ST_TX_DATA_BIT_HIGH_CUSTOM: 1047 case CEC_ST_TX_PULSE_HIGH_CUSTOM: 1048 usecs = pin->tx_custom_high_usecs; 1049 break; 1050 default: 1051 usecs = states[pin->state].usecs; 1052 break; 1053 } 1054 1055 if (!adap->monitor_pin_cnt || usecs <= 150) { 1056 pin->wait_usecs = 0; 1057 pin->timer_ts = ktime_add_us(ts, usecs); 1058 hrtimer_forward_now(timer, us_to_ktime(usecs)); 1059 return HRTIMER_RESTART; 1060 } 1061 pin->wait_usecs = usecs - 100; 1062 pin->timer_ts = ktime_add_us(ts, 100); 1063 hrtimer_forward_now(timer, us_to_ktime(100)); 1064 return HRTIMER_RESTART; 1065 } 1066 1067 static int cec_pin_thread_func(void *_adap) 1068 { 1069 struct cec_adapter *adap = _adap; 1070 struct cec_pin *pin = adap->pin; 1071 1072 pin->enabled_irq = false; 1073 pin->enable_irq_failed = false; 1074 for (;;) { 1075 wait_event_interruptible(pin->kthread_waitq, 1076 kthread_should_stop() || 1077 pin->work_rx_msg.len || 1078 pin->work_tx_status || 1079 atomic_read(&pin->work_irq_change) || 1080 atomic_read(&pin->work_pin_num_events)); 1081 1082 if (kthread_should_stop()) 1083 break; 1084 1085 if (pin->work_rx_msg.len) { 1086 struct cec_msg *msg = &pin->work_rx_msg; 1087 1088 if (msg->len > 1 && msg->len < CEC_MAX_MSG_SIZE && 1089 rx_add_byte(pin)) { 1090 /* Error injection: add byte to the message */ 1091 msg->msg[msg->len++] = 0x55; 1092 } 1093 if (msg->len > 2 && rx_remove_byte(pin)) { 1094 /* Error injection: remove byte from message */ 1095 msg->len--; 1096 } 1097 if (msg->len > CEC_MAX_MSG_SIZE) 1098 msg->len = CEC_MAX_MSG_SIZE; 1099 cec_received_msg_ts(adap, msg, 1100 ns_to_ktime(pin->work_rx_msg.rx_ts)); 1101 msg->len = 0; 1102 } 1103 1104 if (pin->work_tx_status) { 1105 unsigned int tx_status = pin->work_tx_status; 1106 1107 pin->work_tx_status = 0; 1108 cec_transmit_attempt_done_ts(adap, tx_status, 1109 pin->work_tx_ts); 1110 } 1111 1112 while (atomic_read_acquire(&pin->work_pin_num_events)) { 1113 unsigned int idx = pin->work_pin_events_rd; 1114 u8 v = pin->work_pin_events[idx]; 1115 1116 cec_queue_pin_cec_event(adap, 1117 v & CEC_PIN_EVENT_FL_IS_HIGH, 1118 v & CEC_PIN_EVENT_FL_DROPPED, 1119 pin->work_pin_ts[idx]); 1120 pin->work_pin_events_rd = (idx + 1) % CEC_NUM_PIN_EVENTS; 1121 atomic_dec_return_release(&pin->work_pin_num_events); 1122 } 1123 1124 switch (atomic_xchg(&pin->work_irq_change, 1125 CEC_PIN_IRQ_UNCHANGED)) { 1126 case CEC_PIN_IRQ_DISABLE: 1127 if (pin->enabled_irq) { 1128 pin->ops->disable_irq(adap); 1129 pin->enabled_irq = false; 1130 pin->enable_irq_failed = false; 1131 } 1132 cec_pin_high(pin); 1133 if (pin->state == CEC_ST_OFF) 1134 break; 1135 cec_pin_to_idle(pin); 1136 hrtimer_start(&pin->timer, ns_to_ktime(0), 1137 HRTIMER_MODE_REL); 1138 break; 1139 case CEC_PIN_IRQ_ENABLE: 1140 if (pin->enabled_irq || !pin->ops->enable_irq || 1141 pin->adap->devnode.unregistered) 1142 break; 1143 pin->enable_irq_failed = !pin->ops->enable_irq(adap); 1144 if (pin->enable_irq_failed) { 1145 cec_pin_to_idle(pin); 1146 hrtimer_start(&pin->timer, ns_to_ktime(0), 1147 HRTIMER_MODE_REL); 1148 } else { 1149 pin->enabled_irq = true; 1150 } 1151 break; 1152 default: 1153 break; 1154 } 1155 } 1156 1157 if (pin->enabled_irq) { 1158 pin->ops->disable_irq(pin->adap); 1159 pin->enabled_irq = false; 1160 pin->enable_irq_failed = false; 1161 cec_pin_high(pin); 1162 } 1163 return 0; 1164 } 1165 1166 static int cec_pin_adap_enable(struct cec_adapter *adap, bool enable) 1167 { 1168 struct cec_pin *pin = adap->pin; 1169 1170 if (enable) { 1171 cec_pin_read(pin); 1172 cec_pin_to_idle(pin); 1173 pin->tx_msg.len = 0; 1174 pin->timer_ts = ns_to_ktime(0); 1175 atomic_set(&pin->work_irq_change, CEC_PIN_IRQ_UNCHANGED); 1176 if (!pin->kthread) { 1177 pin->kthread = kthread_run(cec_pin_thread_func, adap, 1178 "cec-pin"); 1179 if (IS_ERR(pin->kthread)) { 1180 int err = PTR_ERR(pin->kthread); 1181 1182 pr_err("cec-pin: kernel_thread() failed\n"); 1183 pin->kthread = NULL; 1184 return err; 1185 } 1186 } 1187 hrtimer_start(&pin->timer, ns_to_ktime(0), 1188 HRTIMER_MODE_REL); 1189 } else if (pin->kthread) { 1190 hrtimer_cancel(&pin->timer); 1191 cec_pin_high(pin); 1192 cec_pin_to_idle(pin); 1193 pin->state = CEC_ST_OFF; 1194 pin->work_tx_status = 0; 1195 atomic_set(&pin->work_irq_change, CEC_PIN_IRQ_DISABLE); 1196 wake_up_interruptible(&pin->kthread_waitq); 1197 } 1198 return 0; 1199 } 1200 1201 static int cec_pin_adap_log_addr(struct cec_adapter *adap, u8 log_addr) 1202 { 1203 struct cec_pin *pin = adap->pin; 1204 1205 if (log_addr == CEC_LOG_ADDR_INVALID) 1206 pin->la_mask = 0; 1207 else 1208 pin->la_mask |= (1 << log_addr); 1209 return 0; 1210 } 1211 1212 void cec_pin_start_timer(struct cec_pin *pin) 1213 { 1214 if (pin->state != CEC_ST_RX_IRQ) 1215 return; 1216 1217 atomic_set(&pin->work_irq_change, CEC_PIN_IRQ_DISABLE); 1218 wake_up_interruptible(&pin->kthread_waitq); 1219 } 1220 1221 static int cec_pin_adap_transmit(struct cec_adapter *adap, u8 attempts, 1222 u32 signal_free_time, struct cec_msg *msg) 1223 { 1224 struct cec_pin *pin = adap->pin; 1225 1226 /* 1227 * If a receive is in progress, then this transmit should use 1228 * a signal free time of max CEC_SIGNAL_FREE_TIME_NEW_INITIATOR 1229 * since when it starts transmitting it will have a new initiator. 1230 */ 1231 if (pin->state != CEC_ST_IDLE && 1232 signal_free_time > CEC_SIGNAL_FREE_TIME_NEW_INITIATOR) 1233 signal_free_time = CEC_SIGNAL_FREE_TIME_NEW_INITIATOR; 1234 1235 pin->tx_signal_free_time = signal_free_time; 1236 pin->tx_extra_bytes = 0; 1237 pin->tx_msg = *msg; 1238 if (msg->len > 1) { 1239 /* Error injection: add byte to the message */ 1240 pin->tx_extra_bytes = tx_add_bytes(pin); 1241 } 1242 if (msg->len > 2 && tx_remove_byte(pin)) { 1243 /* Error injection: remove byte from the message */ 1244 pin->tx_msg.len--; 1245 } 1246 pin->work_tx_status = 0; 1247 pin->tx_bit = 0; 1248 cec_pin_start_timer(pin); 1249 return 0; 1250 } 1251 1252 static void cec_pin_adap_status(struct cec_adapter *adap, 1253 struct seq_file *file) 1254 { 1255 struct cec_pin *pin = adap->pin; 1256 1257 seq_printf(file, "state: %s\n", states[pin->state].name); 1258 seq_printf(file, "tx_bit: %d\n", pin->tx_bit); 1259 seq_printf(file, "rx_bit: %d\n", pin->rx_bit); 1260 seq_printf(file, "cec pin: %d\n", call_pin_op(pin, read)); 1261 seq_printf(file, "cec pin events dropped: %u\n", 1262 pin->work_pin_events_dropped_cnt); 1263 if (pin->ops->enable_irq) 1264 seq_printf(file, "irq %s\n", pin->enabled_irq ? "enabled" : 1265 (pin->enable_irq_failed ? "failed" : "disabled")); 1266 if (pin->timer_100us_overruns) { 1267 seq_printf(file, "timer overruns > 100us: %u of %u\n", 1268 pin->timer_100us_overruns, pin->timer_cnt); 1269 seq_printf(file, "timer overruns > 300us: %u of %u\n", 1270 pin->timer_300us_overruns, pin->timer_cnt); 1271 seq_printf(file, "max timer overrun: %u usecs\n", 1272 pin->timer_max_overrun); 1273 seq_printf(file, "avg timer overrun: %u usecs\n", 1274 pin->timer_sum_overrun / pin->timer_100us_overruns); 1275 } 1276 if (pin->rx_start_bit_low_too_short_cnt) 1277 seq_printf(file, 1278 "rx start bit low too short: %u (delta %u, ts %llu)\n", 1279 pin->rx_start_bit_low_too_short_cnt, 1280 pin->rx_start_bit_low_too_short_delta, 1281 pin->rx_start_bit_low_too_short_ts); 1282 if (pin->rx_start_bit_too_short_cnt) 1283 seq_printf(file, 1284 "rx start bit too short: %u (delta %u, ts %llu)\n", 1285 pin->rx_start_bit_too_short_cnt, 1286 pin->rx_start_bit_too_short_delta, 1287 pin->rx_start_bit_too_short_ts); 1288 if (pin->rx_start_bit_too_long_cnt) 1289 seq_printf(file, "rx start bit too long: %u\n", 1290 pin->rx_start_bit_too_long_cnt); 1291 if (pin->rx_data_bit_too_short_cnt) 1292 seq_printf(file, 1293 "rx data bit too short: %u (delta %u, ts %llu)\n", 1294 pin->rx_data_bit_too_short_cnt, 1295 pin->rx_data_bit_too_short_delta, 1296 pin->rx_data_bit_too_short_ts); 1297 if (pin->rx_data_bit_too_long_cnt) 1298 seq_printf(file, "rx data bit too long: %u\n", 1299 pin->rx_data_bit_too_long_cnt); 1300 seq_printf(file, "rx initiated low drive: %u\n", pin->rx_low_drive_cnt); 1301 seq_printf(file, "tx detected low drive: %u\n", pin->tx_low_drive_cnt); 1302 pin->work_pin_events_dropped_cnt = 0; 1303 pin->timer_cnt = 0; 1304 pin->timer_100us_overruns = 0; 1305 pin->timer_300us_overruns = 0; 1306 pin->timer_max_overrun = 0; 1307 pin->timer_sum_overrun = 0; 1308 pin->rx_start_bit_low_too_short_cnt = 0; 1309 pin->rx_start_bit_too_short_cnt = 0; 1310 pin->rx_start_bit_too_long_cnt = 0; 1311 pin->rx_data_bit_too_short_cnt = 0; 1312 pin->rx_data_bit_too_long_cnt = 0; 1313 pin->rx_low_drive_cnt = 0; 1314 pin->tx_low_drive_cnt = 0; 1315 call_void_pin_op(pin, status, file); 1316 } 1317 1318 static int cec_pin_adap_monitor_all_enable(struct cec_adapter *adap, 1319 bool enable) 1320 { 1321 struct cec_pin *pin = adap->pin; 1322 1323 pin->monitor_all = enable; 1324 return 0; 1325 } 1326 1327 static void cec_pin_adap_free(struct cec_adapter *adap) 1328 { 1329 struct cec_pin *pin = adap->pin; 1330 1331 if (pin->kthread) 1332 kthread_stop(pin->kthread); 1333 pin->kthread = NULL; 1334 if (pin->ops->free) 1335 pin->ops->free(adap); 1336 adap->pin = NULL; 1337 kfree(pin); 1338 } 1339 1340 static int cec_pin_received(struct cec_adapter *adap, struct cec_msg *msg) 1341 { 1342 struct cec_pin *pin = adap->pin; 1343 1344 if (pin->ops->received && !adap->devnode.unregistered) 1345 return pin->ops->received(adap, msg); 1346 return -ENOMSG; 1347 } 1348 1349 void cec_pin_changed(struct cec_adapter *adap, bool value) 1350 { 1351 struct cec_pin *pin = adap->pin; 1352 1353 cec_pin_update(pin, value, false); 1354 if (!value && (adap->is_configuring || adap->is_configured || 1355 adap->monitor_all_cnt || !adap->monitor_pin_cnt)) 1356 atomic_set(&pin->work_irq_change, CEC_PIN_IRQ_DISABLE); 1357 } 1358 EXPORT_SYMBOL_GPL(cec_pin_changed); 1359 1360 static const struct cec_adap_ops cec_pin_adap_ops = { 1361 .adap_enable = cec_pin_adap_enable, 1362 .adap_monitor_all_enable = cec_pin_adap_monitor_all_enable, 1363 .adap_log_addr = cec_pin_adap_log_addr, 1364 .adap_transmit = cec_pin_adap_transmit, 1365 .adap_status = cec_pin_adap_status, 1366 .adap_free = cec_pin_adap_free, 1367 #ifdef CONFIG_CEC_PIN_ERROR_INJ 1368 .error_inj_parse_line = cec_pin_error_inj_parse_line, 1369 .error_inj_show = cec_pin_error_inj_show, 1370 #endif 1371 .received = cec_pin_received, 1372 }; 1373 1374 struct cec_adapter *cec_pin_allocate_adapter(const struct cec_pin_ops *pin_ops, 1375 void *priv, const char *name, u32 caps) 1376 { 1377 struct cec_adapter *adap; 1378 struct cec_pin *pin = kzalloc_obj(*pin); 1379 1380 if (pin == NULL) 1381 return ERR_PTR(-ENOMEM); 1382 pin->ops = pin_ops; 1383 atomic_set(&pin->work_pin_num_events, 0); 1384 hrtimer_setup(&pin->timer, cec_pin_timer, CLOCK_MONOTONIC, HRTIMER_MODE_REL); 1385 init_waitqueue_head(&pin->kthread_waitq); 1386 pin->tx_custom_low_usecs = CEC_TIM_CUSTOM_DEFAULT; 1387 pin->tx_custom_high_usecs = CEC_TIM_CUSTOM_DEFAULT; 1388 pin->tx_glitch_low_usecs = CEC_TIM_GLITCH_DEFAULT; 1389 pin->tx_glitch_high_usecs = CEC_TIM_GLITCH_DEFAULT; 1390 1391 adap = cec_allocate_adapter(&cec_pin_adap_ops, priv, name, 1392 caps | CEC_CAP_MONITOR_ALL | CEC_CAP_MONITOR_PIN, 1393 CEC_MAX_LOG_ADDRS); 1394 1395 if (IS_ERR(adap)) { 1396 kfree(pin); 1397 return adap; 1398 } 1399 1400 adap->pin = pin; 1401 pin->adap = adap; 1402 cec_pin_update(pin, cec_pin_high(pin), true); 1403 return adap; 1404 } 1405 EXPORT_SYMBOL_GPL(cec_pin_allocate_adapter); 1406