1*3764e82eSJohannes Thumshirn #ifndef __MCB_INTERNAL 2*3764e82eSJohannes Thumshirn #define __MCB_INTERNAL 3*3764e82eSJohannes Thumshirn 4*3764e82eSJohannes Thumshirn #include <linux/types.h> 5*3764e82eSJohannes Thumshirn 6*3764e82eSJohannes Thumshirn #define CHAMELEON_FILENAME_LEN 12 7*3764e82eSJohannes Thumshirn #define CHAMELEONV2_MAGIC 0xabce 8*3764e82eSJohannes Thumshirn 9*3764e82eSJohannes Thumshirn enum chameleon_descriptor_type { 10*3764e82eSJohannes Thumshirn CHAMELEON_DTYPE_GENERAL = 0x0, 11*3764e82eSJohannes Thumshirn CHAMELEON_DTYPE_BRIDGE = 0x1, 12*3764e82eSJohannes Thumshirn CHAMELEON_DTYPE_CPU = 0x2, 13*3764e82eSJohannes Thumshirn CHAMELEON_DTYPE_BAR = 0x3, 14*3764e82eSJohannes Thumshirn CHAMELEON_DTYPE_END = 0xf, 15*3764e82eSJohannes Thumshirn }; 16*3764e82eSJohannes Thumshirn 17*3764e82eSJohannes Thumshirn enum chameleon_bus_type { 18*3764e82eSJohannes Thumshirn CHAMELEON_BUS_WISHBONE, 19*3764e82eSJohannes Thumshirn CHAMELEON_BUS_AVALON, 20*3764e82eSJohannes Thumshirn CHAMELEON_BUS_LPC, 21*3764e82eSJohannes Thumshirn CHAMELEON_BUS_ISA, 22*3764e82eSJohannes Thumshirn }; 23*3764e82eSJohannes Thumshirn 24*3764e82eSJohannes Thumshirn /** 25*3764e82eSJohannes Thumshirn * struct chameleon_fpga_header 26*3764e82eSJohannes Thumshirn * 27*3764e82eSJohannes Thumshirn * @revision: Revison of Chameleon table in FPGA 28*3764e82eSJohannes Thumshirn * @model: Chameleon table model ASCII char 29*3764e82eSJohannes Thumshirn * @minor: Revision minor 30*3764e82eSJohannes Thumshirn * @bus_type: Bus type (usually %CHAMELEON_BUS_WISHBONE) 31*3764e82eSJohannes Thumshirn * @magic: Chameleon header magic number (0xabce for version 2) 32*3764e82eSJohannes Thumshirn * @reserved: Reserved 33*3764e82eSJohannes Thumshirn * @filename: Filename of FPGA bitstream 34*3764e82eSJohannes Thumshirn */ 35*3764e82eSJohannes Thumshirn struct chameleon_fpga_header { 36*3764e82eSJohannes Thumshirn u8 revision; 37*3764e82eSJohannes Thumshirn char model; 38*3764e82eSJohannes Thumshirn u8 minor; 39*3764e82eSJohannes Thumshirn u8 bus_type; 40*3764e82eSJohannes Thumshirn u16 magic; 41*3764e82eSJohannes Thumshirn u16 reserved; 42*3764e82eSJohannes Thumshirn /* This one has no '\0' at the end!!! */ 43*3764e82eSJohannes Thumshirn char filename[CHAMELEON_FILENAME_LEN]; 44*3764e82eSJohannes Thumshirn } __packed; 45*3764e82eSJohannes Thumshirn #define HEADER_MAGIC_OFFSET 0x4 46*3764e82eSJohannes Thumshirn 47*3764e82eSJohannes Thumshirn /** 48*3764e82eSJohannes Thumshirn * struct chameleon_gdd - Chameleon General Device Descriptor 49*3764e82eSJohannes Thumshirn * 50*3764e82eSJohannes Thumshirn * @irq: the position in the FPGA's IRQ controller vector 51*3764e82eSJohannes Thumshirn * @rev: the revision of the variant's implementation 52*3764e82eSJohannes Thumshirn * @var: the variant of the IP core 53*3764e82eSJohannes Thumshirn * @dev: the device the IP core is 54*3764e82eSJohannes Thumshirn * @dtype: device descriptor type 55*3764e82eSJohannes Thumshirn * @bar: BAR offset that must be added to module offset 56*3764e82eSJohannes Thumshirn * @inst: the instance number of the device, 0 is first instance 57*3764e82eSJohannes Thumshirn * @group: the group the device belongs to (0 = no group) 58*3764e82eSJohannes Thumshirn * @reserved: reserved 59*3764e82eSJohannes Thumshirn * @offset: beginning of the address window of desired module 60*3764e82eSJohannes Thumshirn * @size: size of the module's address window 61*3764e82eSJohannes Thumshirn */ 62*3764e82eSJohannes Thumshirn struct chameleon_gdd { 63*3764e82eSJohannes Thumshirn __le32 reg1; 64*3764e82eSJohannes Thumshirn __le32 reg2; 65*3764e82eSJohannes Thumshirn __le32 offset; 66*3764e82eSJohannes Thumshirn __le32 size; 67*3764e82eSJohannes Thumshirn 68*3764e82eSJohannes Thumshirn } __packed; 69*3764e82eSJohannes Thumshirn 70*3764e82eSJohannes Thumshirn /* GDD Register 1 fields */ 71*3764e82eSJohannes Thumshirn #define GDD_IRQ(x) ((x) & 0x1f) 72*3764e82eSJohannes Thumshirn #define GDD_REV(x) (((x) >> 5) & 0x3f) 73*3764e82eSJohannes Thumshirn #define GDD_VAR(x) (((x) >> 11) & 0x3f) 74*3764e82eSJohannes Thumshirn #define GDD_DEV(x) (((x) >> 18) & 0x3ff) 75*3764e82eSJohannes Thumshirn #define GDD_DTY(x) (((x) >> 28) & 0xf) 76*3764e82eSJohannes Thumshirn 77*3764e82eSJohannes Thumshirn /* GDD Register 2 fields */ 78*3764e82eSJohannes Thumshirn #define GDD_BAR(x) ((x) & 0x7) 79*3764e82eSJohannes Thumshirn #define GDD_INS(x) (((x) >> 3) & 0x3f) 80*3764e82eSJohannes Thumshirn #define GDD_GRP(x) (((x) >> 9) & 0x3f) 81*3764e82eSJohannes Thumshirn 82*3764e82eSJohannes Thumshirn /** 83*3764e82eSJohannes Thumshirn * struct chameleon_bdd - Chameleon Bridge Device Descriptor 84*3764e82eSJohannes Thumshirn * 85*3764e82eSJohannes Thumshirn * @irq: the position in the FPGA's IRQ controller vector 86*3764e82eSJohannes Thumshirn * @rev: the revision of the variant's implementation 87*3764e82eSJohannes Thumshirn * @var: the variant of the IP core 88*3764e82eSJohannes Thumshirn * @dev: the device the IP core is 89*3764e82eSJohannes Thumshirn * @dtype: device descriptor type 90*3764e82eSJohannes Thumshirn * @bar: BAR offset that must be added to module offset 91*3764e82eSJohannes Thumshirn * @inst: the instance number of the device, 0 is first instance 92*3764e82eSJohannes Thumshirn * @dbar: destination bar from the bus _behind_ the bridge 93*3764e82eSJohannes Thumshirn * @chamoff: offset within the BAR of the source bus 94*3764e82eSJohannes Thumshirn * @offset: 95*3764e82eSJohannes Thumshirn * @size: 96*3764e82eSJohannes Thumshirn */ 97*3764e82eSJohannes Thumshirn struct chameleon_bdd { 98*3764e82eSJohannes Thumshirn unsigned int irq:6; 99*3764e82eSJohannes Thumshirn unsigned int rev:6; 100*3764e82eSJohannes Thumshirn unsigned int var:6; 101*3764e82eSJohannes Thumshirn unsigned int dev:10; 102*3764e82eSJohannes Thumshirn unsigned int dtype:4; 103*3764e82eSJohannes Thumshirn unsigned int bar:3; 104*3764e82eSJohannes Thumshirn unsigned int inst:6; 105*3764e82eSJohannes Thumshirn unsigned int dbar:3; 106*3764e82eSJohannes Thumshirn unsigned int group:6; 107*3764e82eSJohannes Thumshirn unsigned int reserved:14; 108*3764e82eSJohannes Thumshirn u32 chamoff; 109*3764e82eSJohannes Thumshirn u32 offset; 110*3764e82eSJohannes Thumshirn u32 size; 111*3764e82eSJohannes Thumshirn } __packed; 112*3764e82eSJohannes Thumshirn 113*3764e82eSJohannes Thumshirn int chameleon_parse_cells(struct mcb_bus *bus, phys_addr_t mapbase, 114*3764e82eSJohannes Thumshirn void __iomem *base); 115*3764e82eSJohannes Thumshirn 116*3764e82eSJohannes Thumshirn #endif 117