1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2016-2023, NVIDIA CORPORATION. All rights reserved. 4 */ 5 6 #include <linux/delay.h> 7 #include <linux/interrupt.h> 8 #include <linux/io.h> 9 #include <linux/mailbox_controller.h> 10 #include <linux/of.h> 11 #include <linux/of_device.h> 12 #include <linux/platform_device.h> 13 #include <linux/pm.h> 14 #include <linux/slab.h> 15 16 #include <soc/tegra/fuse.h> 17 18 #include <dt-bindings/mailbox/tegra186-hsp.h> 19 20 #include "mailbox.h" 21 22 #define HSP_INT_IE(x) (0x100 + ((x) * 4)) 23 #define HSP_INT_IV 0x300 24 #define HSP_INT_IR 0x304 25 26 #define HSP_INT_EMPTY_SHIFT 0 27 #define HSP_INT_EMPTY_MASK 0xff 28 #define HSP_INT_FULL_SHIFT 8 29 #define HSP_INT_FULL_MASK 0xff 30 31 #define HSP_INT_DIMENSIONING 0x380 32 #define HSP_nSM_SHIFT 0 33 #define HSP_nSS_SHIFT 4 34 #define HSP_nAS_SHIFT 8 35 #define HSP_nDB_SHIFT 12 36 #define HSP_nSI_SHIFT 16 37 #define HSP_nINT_MASK 0xf 38 39 #define HSP_DB_TRIGGER 0x0 40 #define HSP_DB_ENABLE 0x4 41 #define HSP_DB_RAW 0x8 42 #define HSP_DB_PENDING 0xc 43 44 #define HSP_SM_SHRD_MBOX 0x0 45 #define HSP_SM_SHRD_MBOX_FULL BIT(31) 46 #define HSP_SM_SHRD_MBOX_FULL_INT_IE 0x04 47 #define HSP_SM_SHRD_MBOX_EMPTY_INT_IE 0x08 48 49 #define HSP_SHRD_MBOX_TYPE1_TAG 0x40 50 #define HSP_SHRD_MBOX_TYPE1_DATA0 0x48 51 #define HSP_SHRD_MBOX_TYPE1_DATA1 0x4c 52 #define HSP_SHRD_MBOX_TYPE1_DATA2 0x50 53 #define HSP_SHRD_MBOX_TYPE1_DATA3 0x54 54 55 #define HSP_DB_CCPLEX 1 56 #define HSP_DB_BPMP 3 57 #define HSP_DB_MAX 7 58 59 #define HSP_MBOX_TYPE_MASK 0xff 60 61 struct tegra_hsp_channel; 62 struct tegra_hsp; 63 64 struct tegra_hsp_channel { 65 struct tegra_hsp *hsp; 66 struct mbox_chan *chan; 67 void __iomem *regs; 68 }; 69 70 struct tegra_hsp_doorbell { 71 struct tegra_hsp_channel channel; 72 struct list_head list; 73 const char *name; 74 unsigned int master; 75 unsigned int index; 76 }; 77 78 struct tegra_hsp_sm_ops { 79 void (*send)(struct tegra_hsp_channel *channel, void *data); 80 void (*recv)(struct tegra_hsp_channel *channel); 81 }; 82 83 struct tegra_hsp_mailbox { 84 struct tegra_hsp_channel channel; 85 const struct tegra_hsp_sm_ops *ops; 86 unsigned int index; 87 bool producer; 88 }; 89 90 struct tegra_hsp_db_map { 91 const char *name; 92 unsigned int master; 93 unsigned int index; 94 }; 95 96 struct tegra_hsp_soc { 97 const struct tegra_hsp_db_map *map; 98 bool has_per_mb_ie; 99 bool has_128_bit_mb; 100 unsigned int reg_stride; 101 }; 102 103 struct tegra_hsp { 104 struct device *dev; 105 const struct tegra_hsp_soc *soc; 106 struct mbox_controller mbox_db; 107 struct mbox_controller mbox_sm; 108 void __iomem *regs; 109 unsigned int doorbell_irq; 110 unsigned int *shared_irqs; 111 unsigned int shared_irq; 112 unsigned int num_sm; 113 unsigned int num_as; 114 unsigned int num_ss; 115 unsigned int num_db; 116 unsigned int num_si; 117 118 spinlock_t lock; 119 struct lock_class_key lock_key; 120 121 struct list_head doorbells; 122 struct tegra_hsp_mailbox *mailboxes; 123 124 unsigned long mask; 125 }; 126 127 static inline u32 tegra_hsp_readl(struct tegra_hsp *hsp, unsigned int offset) 128 { 129 return readl(hsp->regs + offset); 130 } 131 132 static inline void tegra_hsp_writel(struct tegra_hsp *hsp, u32 value, 133 unsigned int offset) 134 { 135 writel(value, hsp->regs + offset); 136 } 137 138 static inline u32 tegra_hsp_channel_readl(struct tegra_hsp_channel *channel, 139 unsigned int offset) 140 { 141 return readl(channel->regs + offset); 142 } 143 144 static inline void tegra_hsp_channel_writel(struct tegra_hsp_channel *channel, 145 u32 value, unsigned int offset) 146 { 147 writel(value, channel->regs + offset); 148 } 149 150 static bool tegra_hsp_doorbell_can_ring(struct tegra_hsp_doorbell *db) 151 { 152 u32 value; 153 154 value = tegra_hsp_channel_readl(&db->channel, HSP_DB_ENABLE); 155 156 return (value & BIT(TEGRA_HSP_DB_MASTER_CCPLEX)) != 0; 157 } 158 159 static struct tegra_hsp_doorbell * 160 __tegra_hsp_doorbell_get(struct tegra_hsp *hsp, unsigned int master) 161 { 162 struct tegra_hsp_doorbell *entry; 163 164 list_for_each_entry(entry, &hsp->doorbells, list) 165 if (entry->master == master) 166 return entry; 167 168 return NULL; 169 } 170 171 static struct tegra_hsp_doorbell * 172 tegra_hsp_doorbell_get(struct tegra_hsp *hsp, unsigned int master) 173 { 174 struct tegra_hsp_doorbell *db; 175 unsigned long flags; 176 177 spin_lock_irqsave(&hsp->lock, flags); 178 db = __tegra_hsp_doorbell_get(hsp, master); 179 spin_unlock_irqrestore(&hsp->lock, flags); 180 181 return db; 182 } 183 184 static irqreturn_t tegra_hsp_doorbell_irq(int irq, void *data) 185 { 186 struct tegra_hsp *hsp = data; 187 struct tegra_hsp_doorbell *db; 188 unsigned long master, value; 189 190 db = tegra_hsp_doorbell_get(hsp, TEGRA_HSP_DB_MASTER_CCPLEX); 191 if (!db) 192 return IRQ_NONE; 193 194 value = tegra_hsp_channel_readl(&db->channel, HSP_DB_PENDING); 195 tegra_hsp_channel_writel(&db->channel, value, HSP_DB_PENDING); 196 197 spin_lock(&hsp->lock); 198 199 for_each_set_bit(master, &value, hsp->mbox_db.num_chans) { 200 struct tegra_hsp_doorbell *db; 201 202 db = __tegra_hsp_doorbell_get(hsp, master); 203 /* 204 * Depending on the bootloader chain, the CCPLEX doorbell will 205 * have some doorbells enabled, which means that requesting an 206 * interrupt will immediately fire. 207 * 208 * In that case, db->channel.chan will still be NULL here and 209 * cause a crash if not properly guarded. 210 * 211 * It remains to be seen if ignoring the doorbell in that case 212 * is the correct solution. 213 */ 214 if (db && db->channel.chan) 215 mbox_chan_received_data(db->channel.chan, NULL); 216 } 217 218 spin_unlock(&hsp->lock); 219 220 return IRQ_HANDLED; 221 } 222 223 static irqreturn_t tegra_hsp_shared_irq(int irq, void *data) 224 { 225 struct tegra_hsp *hsp = data; 226 unsigned long bit, mask; 227 u32 status; 228 229 status = tegra_hsp_readl(hsp, HSP_INT_IR) & hsp->mask; 230 231 /* process EMPTY interrupts first */ 232 mask = (status >> HSP_INT_EMPTY_SHIFT) & HSP_INT_EMPTY_MASK; 233 234 for_each_set_bit(bit, &mask, hsp->num_sm) { 235 struct tegra_hsp_mailbox *mb = &hsp->mailboxes[bit]; 236 237 if (mb->producer) { 238 /* 239 * Disable EMPTY interrupts until data is sent with 240 * the next message. These interrupts are level- 241 * triggered, so if we kept them enabled they would 242 * constantly trigger until we next write data into 243 * the message. 244 */ 245 spin_lock(&hsp->lock); 246 247 hsp->mask &= ~BIT(HSP_INT_EMPTY_SHIFT + mb->index); 248 tegra_hsp_writel(hsp, hsp->mask, 249 HSP_INT_IE(hsp->shared_irq)); 250 251 spin_unlock(&hsp->lock); 252 253 mbox_chan_txdone(mb->channel.chan, 0); 254 } 255 } 256 257 /* process FULL interrupts */ 258 mask = (status >> HSP_INT_FULL_SHIFT) & HSP_INT_FULL_MASK; 259 260 for_each_set_bit(bit, &mask, hsp->num_sm) { 261 struct tegra_hsp_mailbox *mb = &hsp->mailboxes[bit]; 262 263 if (!mb->producer) 264 mb->ops->recv(&mb->channel); 265 } 266 267 return IRQ_HANDLED; 268 } 269 270 static struct tegra_hsp_channel * 271 tegra_hsp_doorbell_create(struct tegra_hsp *hsp, const char *name, 272 unsigned int master, unsigned int index) 273 { 274 struct tegra_hsp_doorbell *db; 275 unsigned int offset; 276 unsigned long flags; 277 278 db = devm_kzalloc(hsp->dev, sizeof(*db), GFP_KERNEL); 279 if (!db) 280 return ERR_PTR(-ENOMEM); 281 282 offset = (1 + (hsp->num_sm / 2) + hsp->num_ss + hsp->num_as) * SZ_64K; 283 offset += index * hsp->soc->reg_stride; 284 285 db->channel.regs = hsp->regs + offset; 286 db->channel.hsp = hsp; 287 288 db->name = devm_kstrdup_const(hsp->dev, name, GFP_KERNEL); 289 db->master = master; 290 db->index = index; 291 292 spin_lock_irqsave(&hsp->lock, flags); 293 list_add_tail(&db->list, &hsp->doorbells); 294 spin_unlock_irqrestore(&hsp->lock, flags); 295 296 return &db->channel; 297 } 298 299 static int tegra_hsp_doorbell_send_data(struct mbox_chan *chan, void *data) 300 { 301 struct tegra_hsp_doorbell *db = chan->con_priv; 302 303 tegra_hsp_channel_writel(&db->channel, 1, HSP_DB_TRIGGER); 304 305 return 0; 306 } 307 308 static int tegra_hsp_doorbell_startup(struct mbox_chan *chan) 309 { 310 struct tegra_hsp_doorbell *db = chan->con_priv; 311 struct tegra_hsp *hsp = db->channel.hsp; 312 struct tegra_hsp_doorbell *ccplex; 313 unsigned long flags; 314 u32 value; 315 316 if (db->master >= chan->mbox->num_chans) { 317 dev_err(chan->mbox->dev, 318 "invalid master ID %u for HSP channel\n", 319 db->master); 320 return -EINVAL; 321 } 322 323 ccplex = tegra_hsp_doorbell_get(hsp, TEGRA_HSP_DB_MASTER_CCPLEX); 324 if (!ccplex) 325 return -ENODEV; 326 327 /* 328 * On simulation platforms the BPMP hasn't had a chance yet to mark 329 * the doorbell as ringable by the CCPLEX, so we want to skip extra 330 * checks here. 331 */ 332 if (tegra_is_silicon() && !tegra_hsp_doorbell_can_ring(db)) 333 return -ENODEV; 334 335 spin_lock_irqsave(&hsp->lock, flags); 336 337 value = tegra_hsp_channel_readl(&ccplex->channel, HSP_DB_ENABLE); 338 value |= BIT(db->master); 339 tegra_hsp_channel_writel(&ccplex->channel, value, HSP_DB_ENABLE); 340 341 spin_unlock_irqrestore(&hsp->lock, flags); 342 343 return 0; 344 } 345 346 static void tegra_hsp_doorbell_shutdown(struct mbox_chan *chan) 347 { 348 struct tegra_hsp_doorbell *db = chan->con_priv; 349 struct tegra_hsp *hsp = db->channel.hsp; 350 struct tegra_hsp_doorbell *ccplex; 351 unsigned long flags; 352 u32 value; 353 354 ccplex = tegra_hsp_doorbell_get(hsp, TEGRA_HSP_DB_MASTER_CCPLEX); 355 if (!ccplex) 356 return; 357 358 spin_lock_irqsave(&hsp->lock, flags); 359 360 value = tegra_hsp_channel_readl(&ccplex->channel, HSP_DB_ENABLE); 361 value &= ~BIT(db->master); 362 tegra_hsp_channel_writel(&ccplex->channel, value, HSP_DB_ENABLE); 363 364 spin_unlock_irqrestore(&hsp->lock, flags); 365 } 366 367 static const struct mbox_chan_ops tegra_hsp_db_ops = { 368 .send_data = tegra_hsp_doorbell_send_data, 369 .startup = tegra_hsp_doorbell_startup, 370 .shutdown = tegra_hsp_doorbell_shutdown, 371 }; 372 373 static void tegra_hsp_sm_send32(struct tegra_hsp_channel *channel, void *data) 374 { 375 u32 value; 376 377 /* copy data and mark mailbox full */ 378 value = (u32)(unsigned long)data; 379 value |= HSP_SM_SHRD_MBOX_FULL; 380 381 tegra_hsp_channel_writel(channel, value, HSP_SM_SHRD_MBOX); 382 } 383 384 static void tegra_hsp_sm_recv32(struct tegra_hsp_channel *channel) 385 { 386 u32 value; 387 void *msg; 388 389 value = tegra_hsp_channel_readl(channel, HSP_SM_SHRD_MBOX); 390 value &= ~HSP_SM_SHRD_MBOX_FULL; 391 msg = (void *)(unsigned long)value; 392 mbox_chan_received_data(channel->chan, msg); 393 394 /* 395 * Need to clear all bits here since some producers, such as TCU, depend 396 * on fields in the register getting cleared by the consumer. 397 * 398 * The mailbox API doesn't give the consumers a way of doing that 399 * explicitly, so we have to make sure we cover all possible cases. 400 */ 401 tegra_hsp_channel_writel(channel, 0x0, HSP_SM_SHRD_MBOX); 402 } 403 404 static const struct tegra_hsp_sm_ops tegra_hsp_sm_32bit_ops = { 405 .send = tegra_hsp_sm_send32, 406 .recv = tegra_hsp_sm_recv32, 407 }; 408 409 static void tegra_hsp_sm_send128(struct tegra_hsp_channel *channel, void *data) 410 { 411 u32 value[4]; 412 413 memcpy(value, data, sizeof(value)); 414 415 /* Copy data */ 416 tegra_hsp_channel_writel(channel, value[0], HSP_SHRD_MBOX_TYPE1_DATA0); 417 tegra_hsp_channel_writel(channel, value[1], HSP_SHRD_MBOX_TYPE1_DATA1); 418 tegra_hsp_channel_writel(channel, value[2], HSP_SHRD_MBOX_TYPE1_DATA2); 419 tegra_hsp_channel_writel(channel, value[3], HSP_SHRD_MBOX_TYPE1_DATA3); 420 421 /* Update tag to mark mailbox full */ 422 tegra_hsp_channel_writel(channel, HSP_SM_SHRD_MBOX_FULL, 423 HSP_SHRD_MBOX_TYPE1_TAG); 424 } 425 426 static void tegra_hsp_sm_recv128(struct tegra_hsp_channel *channel) 427 { 428 u32 value[4]; 429 void *msg; 430 431 value[0] = tegra_hsp_channel_readl(channel, HSP_SHRD_MBOX_TYPE1_DATA0); 432 value[1] = tegra_hsp_channel_readl(channel, HSP_SHRD_MBOX_TYPE1_DATA1); 433 value[2] = tegra_hsp_channel_readl(channel, HSP_SHRD_MBOX_TYPE1_DATA2); 434 value[3] = tegra_hsp_channel_readl(channel, HSP_SHRD_MBOX_TYPE1_DATA3); 435 436 msg = (void *)(unsigned long)value; 437 mbox_chan_received_data(channel->chan, msg); 438 439 /* 440 * Clear data registers and tag. 441 */ 442 tegra_hsp_channel_writel(channel, 0x0, HSP_SHRD_MBOX_TYPE1_DATA0); 443 tegra_hsp_channel_writel(channel, 0x0, HSP_SHRD_MBOX_TYPE1_DATA1); 444 tegra_hsp_channel_writel(channel, 0x0, HSP_SHRD_MBOX_TYPE1_DATA2); 445 tegra_hsp_channel_writel(channel, 0x0, HSP_SHRD_MBOX_TYPE1_DATA3); 446 tegra_hsp_channel_writel(channel, 0x0, HSP_SHRD_MBOX_TYPE1_TAG); 447 } 448 449 static const struct tegra_hsp_sm_ops tegra_hsp_sm_128bit_ops = { 450 .send = tegra_hsp_sm_send128, 451 .recv = tegra_hsp_sm_recv128, 452 }; 453 454 static int tegra_hsp_mailbox_send_data(struct mbox_chan *chan, void *data) 455 { 456 struct tegra_hsp_mailbox *mb = chan->con_priv; 457 struct tegra_hsp *hsp = mb->channel.hsp; 458 unsigned long flags; 459 460 if (WARN_ON(!mb->producer)) 461 return -EPERM; 462 463 mb->ops->send(&mb->channel, data); 464 465 /* enable EMPTY interrupt for the shared mailbox */ 466 spin_lock_irqsave(&hsp->lock, flags); 467 468 hsp->mask |= BIT(HSP_INT_EMPTY_SHIFT + mb->index); 469 tegra_hsp_writel(hsp, hsp->mask, HSP_INT_IE(hsp->shared_irq)); 470 471 spin_unlock_irqrestore(&hsp->lock, flags); 472 473 return 0; 474 } 475 476 static int tegra_hsp_mailbox_flush(struct mbox_chan *chan, 477 unsigned long timeout) 478 { 479 struct tegra_hsp_mailbox *mb = chan->con_priv; 480 struct tegra_hsp_channel *ch = &mb->channel; 481 u32 value; 482 483 timeout = jiffies + msecs_to_jiffies(timeout); 484 485 while (time_before(jiffies, timeout)) { 486 value = tegra_hsp_channel_readl(ch, HSP_SM_SHRD_MBOX); 487 if ((value & HSP_SM_SHRD_MBOX_FULL) == 0) { 488 mbox_chan_txdone(chan, 0); 489 490 /* Wait until channel is empty */ 491 if (chan->active_req != NULL) 492 continue; 493 494 return 0; 495 } 496 497 udelay(1); 498 } 499 500 return -ETIME; 501 } 502 503 static int tegra_hsp_mailbox_startup(struct mbox_chan *chan) 504 { 505 struct tegra_hsp_mailbox *mb = chan->con_priv; 506 struct tegra_hsp_channel *ch = &mb->channel; 507 struct tegra_hsp *hsp = mb->channel.hsp; 508 unsigned long flags; 509 510 chan->txdone_method = TXDONE_BY_IRQ; 511 512 /* 513 * Shared mailboxes start out as consumers by default. FULL and EMPTY 514 * interrupts are coalesced at the same shared interrupt. 515 * 516 * Keep EMPTY interrupts disabled at startup and only enable them when 517 * the mailbox is actually full. This is required because the FULL and 518 * EMPTY interrupts are level-triggered, so keeping EMPTY interrupts 519 * enabled all the time would cause an interrupt storm while mailboxes 520 * are idle. 521 */ 522 523 spin_lock_irqsave(&hsp->lock, flags); 524 525 if (mb->producer) 526 hsp->mask &= ~BIT(HSP_INT_EMPTY_SHIFT + mb->index); 527 else 528 hsp->mask |= BIT(HSP_INT_FULL_SHIFT + mb->index); 529 530 tegra_hsp_writel(hsp, hsp->mask, HSP_INT_IE(hsp->shared_irq)); 531 532 spin_unlock_irqrestore(&hsp->lock, flags); 533 534 if (hsp->soc->has_per_mb_ie) { 535 if (mb->producer) 536 tegra_hsp_channel_writel(ch, 0x0, 537 HSP_SM_SHRD_MBOX_EMPTY_INT_IE); 538 else 539 tegra_hsp_channel_writel(ch, 0x1, 540 HSP_SM_SHRD_MBOX_FULL_INT_IE); 541 } 542 543 return 0; 544 } 545 546 static void tegra_hsp_mailbox_shutdown(struct mbox_chan *chan) 547 { 548 struct tegra_hsp_mailbox *mb = chan->con_priv; 549 struct tegra_hsp_channel *ch = &mb->channel; 550 struct tegra_hsp *hsp = mb->channel.hsp; 551 unsigned long flags; 552 553 if (hsp->soc->has_per_mb_ie) { 554 if (mb->producer) 555 tegra_hsp_channel_writel(ch, 0x0, 556 HSP_SM_SHRD_MBOX_EMPTY_INT_IE); 557 else 558 tegra_hsp_channel_writel(ch, 0x0, 559 HSP_SM_SHRD_MBOX_FULL_INT_IE); 560 } 561 562 spin_lock_irqsave(&hsp->lock, flags); 563 564 if (mb->producer) 565 hsp->mask &= ~BIT(HSP_INT_EMPTY_SHIFT + mb->index); 566 else 567 hsp->mask &= ~BIT(HSP_INT_FULL_SHIFT + mb->index); 568 569 tegra_hsp_writel(hsp, hsp->mask, HSP_INT_IE(hsp->shared_irq)); 570 571 spin_unlock_irqrestore(&hsp->lock, flags); 572 } 573 574 static const struct mbox_chan_ops tegra_hsp_sm_ops = { 575 .send_data = tegra_hsp_mailbox_send_data, 576 .flush = tegra_hsp_mailbox_flush, 577 .startup = tegra_hsp_mailbox_startup, 578 .shutdown = tegra_hsp_mailbox_shutdown, 579 }; 580 581 static struct mbox_chan *tegra_hsp_db_xlate(struct mbox_controller *mbox, 582 const struct of_phandle_args *args) 583 { 584 struct tegra_hsp *hsp = container_of(mbox, struct tegra_hsp, mbox_db); 585 unsigned int type = args->args[0], master = args->args[1]; 586 struct tegra_hsp_channel *channel = ERR_PTR(-ENODEV); 587 struct tegra_hsp_doorbell *db; 588 struct mbox_chan *chan; 589 unsigned long flags; 590 unsigned int i; 591 592 if (type != TEGRA_HSP_MBOX_TYPE_DB || !hsp->doorbell_irq) 593 return ERR_PTR(-ENODEV); 594 595 db = tegra_hsp_doorbell_get(hsp, master); 596 if (db) 597 channel = &db->channel; 598 599 if (IS_ERR(channel)) 600 return ERR_CAST(channel); 601 602 spin_lock_irqsave(&hsp->lock, flags); 603 604 for (i = 0; i < mbox->num_chans; i++) { 605 chan = &mbox->chans[i]; 606 if (!chan->con_priv) { 607 channel->chan = chan; 608 chan->con_priv = db; 609 break; 610 } 611 612 chan = NULL; 613 } 614 615 spin_unlock_irqrestore(&hsp->lock, flags); 616 617 return chan ?: ERR_PTR(-EBUSY); 618 } 619 620 static struct mbox_chan *tegra_hsp_sm_xlate(struct mbox_controller *mbox, 621 const struct of_phandle_args *args) 622 { 623 struct tegra_hsp *hsp = container_of(mbox, struct tegra_hsp, mbox_sm); 624 unsigned int type = args->args[0], index; 625 struct tegra_hsp_mailbox *mb; 626 627 index = args->args[1] & TEGRA_HSP_SM_MASK; 628 629 if ((type & HSP_MBOX_TYPE_MASK) != TEGRA_HSP_MBOX_TYPE_SM || 630 !hsp->shared_irqs || index >= hsp->num_sm) 631 return ERR_PTR(-ENODEV); 632 633 mb = &hsp->mailboxes[index]; 634 635 if (type & TEGRA_HSP_MBOX_TYPE_SM_128BIT) { 636 if (!hsp->soc->has_128_bit_mb) 637 return ERR_PTR(-ENODEV); 638 639 mb->ops = &tegra_hsp_sm_128bit_ops; 640 } else { 641 mb->ops = &tegra_hsp_sm_32bit_ops; 642 } 643 644 if ((args->args[1] & TEGRA_HSP_SM_FLAG_TX) == 0) 645 mb->producer = false; 646 else 647 mb->producer = true; 648 649 return mb->channel.chan; 650 } 651 652 static int tegra_hsp_add_doorbells(struct tegra_hsp *hsp) 653 { 654 const struct tegra_hsp_db_map *map = hsp->soc->map; 655 struct tegra_hsp_channel *channel; 656 657 while (map->name) { 658 channel = tegra_hsp_doorbell_create(hsp, map->name, 659 map->master, map->index); 660 if (IS_ERR(channel)) 661 return PTR_ERR(channel); 662 663 map++; 664 } 665 666 return 0; 667 } 668 669 static int tegra_hsp_add_mailboxes(struct tegra_hsp *hsp, struct device *dev) 670 { 671 int i; 672 673 hsp->mailboxes = devm_kcalloc(dev, hsp->num_sm, sizeof(*hsp->mailboxes), 674 GFP_KERNEL); 675 if (!hsp->mailboxes) 676 return -ENOMEM; 677 678 for (i = 0; i < hsp->num_sm; i++) { 679 struct tegra_hsp_mailbox *mb = &hsp->mailboxes[i]; 680 681 mb->index = i; 682 683 mb->channel.hsp = hsp; 684 mb->channel.regs = hsp->regs + SZ_64K + i * SZ_32K; 685 mb->channel.chan = &hsp->mbox_sm.chans[i]; 686 mb->channel.chan->con_priv = mb; 687 } 688 689 return 0; 690 } 691 692 static int tegra_hsp_request_shared_irq(struct tegra_hsp *hsp) 693 { 694 unsigned int i, irq = 0; 695 int err; 696 697 for (i = 0; i < hsp->num_si; i++) { 698 irq = hsp->shared_irqs[i]; 699 if (irq <= 0) 700 continue; 701 702 err = devm_request_irq(hsp->dev, irq, tegra_hsp_shared_irq, 0, 703 dev_name(hsp->dev), hsp); 704 if (err < 0) { 705 dev_err(hsp->dev, "failed to request interrupt: %d\n", 706 err); 707 continue; 708 } 709 710 hsp->shared_irq = i; 711 712 /* disable all interrupts */ 713 tegra_hsp_writel(hsp, 0, HSP_INT_IE(hsp->shared_irq)); 714 715 dev_dbg(hsp->dev, "interrupt requested: %u\n", irq); 716 717 break; 718 } 719 720 if (i == hsp->num_si) { 721 dev_err(hsp->dev, "failed to find available interrupt\n"); 722 return -ENOENT; 723 } 724 725 return 0; 726 } 727 728 static int tegra_hsp_probe(struct platform_device *pdev) 729 { 730 struct tegra_hsp *hsp; 731 struct resource *res; 732 unsigned int i; 733 u32 value; 734 int err; 735 736 hsp = devm_kzalloc(&pdev->dev, sizeof(*hsp), GFP_KERNEL); 737 if (!hsp) 738 return -ENOMEM; 739 740 hsp->dev = &pdev->dev; 741 hsp->soc = of_device_get_match_data(&pdev->dev); 742 INIT_LIST_HEAD(&hsp->doorbells); 743 spin_lock_init(&hsp->lock); 744 745 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 746 hsp->regs = devm_ioremap_resource(&pdev->dev, res); 747 if (IS_ERR(hsp->regs)) 748 return PTR_ERR(hsp->regs); 749 750 value = tegra_hsp_readl(hsp, HSP_INT_DIMENSIONING); 751 hsp->num_sm = (value >> HSP_nSM_SHIFT) & HSP_nINT_MASK; 752 hsp->num_ss = (value >> HSP_nSS_SHIFT) & HSP_nINT_MASK; 753 hsp->num_as = (value >> HSP_nAS_SHIFT) & HSP_nINT_MASK; 754 hsp->num_db = (value >> HSP_nDB_SHIFT) & HSP_nINT_MASK; 755 hsp->num_si = (value >> HSP_nSI_SHIFT) & HSP_nINT_MASK; 756 757 err = platform_get_irq_byname_optional(pdev, "doorbell"); 758 if (err >= 0) 759 hsp->doorbell_irq = err; 760 761 if (hsp->num_si > 0) { 762 unsigned int count = 0; 763 764 hsp->shared_irqs = devm_kcalloc(&pdev->dev, hsp->num_si, 765 sizeof(*hsp->shared_irqs), 766 GFP_KERNEL); 767 if (!hsp->shared_irqs) 768 return -ENOMEM; 769 770 for (i = 0; i < hsp->num_si; i++) { 771 char *name; 772 773 name = kasprintf(GFP_KERNEL, "shared%u", i); 774 if (!name) 775 return -ENOMEM; 776 777 err = platform_get_irq_byname_optional(pdev, name); 778 if (err >= 0) { 779 hsp->shared_irqs[i] = err; 780 count++; 781 } 782 783 kfree(name); 784 } 785 786 if (count == 0) { 787 devm_kfree(&pdev->dev, hsp->shared_irqs); 788 hsp->shared_irqs = NULL; 789 } 790 } 791 792 /* setup the doorbell controller */ 793 hsp->mbox_db.of_xlate = tegra_hsp_db_xlate; 794 hsp->mbox_db.num_chans = 32; 795 hsp->mbox_db.dev = &pdev->dev; 796 hsp->mbox_db.ops = &tegra_hsp_db_ops; 797 798 hsp->mbox_db.chans = devm_kcalloc(&pdev->dev, hsp->mbox_db.num_chans, 799 sizeof(*hsp->mbox_db.chans), 800 GFP_KERNEL); 801 if (!hsp->mbox_db.chans) 802 return -ENOMEM; 803 804 if (hsp->doorbell_irq) { 805 err = tegra_hsp_add_doorbells(hsp); 806 if (err < 0) { 807 dev_err(&pdev->dev, "failed to add doorbells: %d\n", 808 err); 809 return err; 810 } 811 } 812 813 err = devm_mbox_controller_register(&pdev->dev, &hsp->mbox_db); 814 if (err < 0) { 815 dev_err(&pdev->dev, "failed to register doorbell mailbox: %d\n", 816 err); 817 return err; 818 } 819 820 /* setup the shared mailbox controller */ 821 hsp->mbox_sm.of_xlate = tegra_hsp_sm_xlate; 822 hsp->mbox_sm.num_chans = hsp->num_sm; 823 hsp->mbox_sm.dev = &pdev->dev; 824 hsp->mbox_sm.ops = &tegra_hsp_sm_ops; 825 826 hsp->mbox_sm.chans = devm_kcalloc(&pdev->dev, hsp->mbox_sm.num_chans, 827 sizeof(*hsp->mbox_sm.chans), 828 GFP_KERNEL); 829 if (!hsp->mbox_sm.chans) 830 return -ENOMEM; 831 832 if (hsp->shared_irqs) { 833 err = tegra_hsp_add_mailboxes(hsp, &pdev->dev); 834 if (err < 0) { 835 dev_err(&pdev->dev, "failed to add mailboxes: %d\n", 836 err); 837 return err; 838 } 839 } 840 841 err = devm_mbox_controller_register(&pdev->dev, &hsp->mbox_sm); 842 if (err < 0) { 843 dev_err(&pdev->dev, "failed to register shared mailbox: %d\n", 844 err); 845 return err; 846 } 847 848 platform_set_drvdata(pdev, hsp); 849 850 if (hsp->doorbell_irq) { 851 err = devm_request_irq(&pdev->dev, hsp->doorbell_irq, 852 tegra_hsp_doorbell_irq, IRQF_NO_SUSPEND, 853 dev_name(&pdev->dev), hsp); 854 if (err < 0) { 855 dev_err(&pdev->dev, 856 "failed to request doorbell IRQ#%u: %d\n", 857 hsp->doorbell_irq, err); 858 return err; 859 } 860 } 861 862 if (hsp->shared_irqs) { 863 err = tegra_hsp_request_shared_irq(hsp); 864 if (err < 0) 865 return err; 866 } 867 868 lockdep_register_key(&hsp->lock_key); 869 lockdep_set_class(&hsp->lock, &hsp->lock_key); 870 871 return 0; 872 } 873 874 static int tegra_hsp_remove(struct platform_device *pdev) 875 { 876 struct tegra_hsp *hsp = platform_get_drvdata(pdev); 877 878 lockdep_unregister_key(&hsp->lock_key); 879 880 return 0; 881 } 882 883 static int __maybe_unused tegra_hsp_resume(struct device *dev) 884 { 885 struct tegra_hsp *hsp = dev_get_drvdata(dev); 886 unsigned int i; 887 struct tegra_hsp_doorbell *db; 888 889 list_for_each_entry(db, &hsp->doorbells, list) { 890 if (db->channel.chan) 891 tegra_hsp_doorbell_startup(db->channel.chan); 892 } 893 894 if (hsp->mailboxes) { 895 for (i = 0; i < hsp->num_sm; i++) { 896 struct tegra_hsp_mailbox *mb = &hsp->mailboxes[i]; 897 898 if (mb->channel.chan->cl) 899 tegra_hsp_mailbox_startup(mb->channel.chan); 900 } 901 } 902 903 return 0; 904 } 905 906 static const struct dev_pm_ops tegra_hsp_pm_ops = { 907 .resume_noirq = tegra_hsp_resume, 908 }; 909 910 static const struct tegra_hsp_db_map tegra186_hsp_db_map[] = { 911 { "ccplex", TEGRA_HSP_DB_MASTER_CCPLEX, HSP_DB_CCPLEX, }, 912 { "bpmp", TEGRA_HSP_DB_MASTER_BPMP, HSP_DB_BPMP, }, 913 { /* sentinel */ } 914 }; 915 916 static const struct tegra_hsp_soc tegra186_hsp_soc = { 917 .map = tegra186_hsp_db_map, 918 .has_per_mb_ie = false, 919 .has_128_bit_mb = false, 920 .reg_stride = 0x100, 921 }; 922 923 static const struct tegra_hsp_soc tegra194_hsp_soc = { 924 .map = tegra186_hsp_db_map, 925 .has_per_mb_ie = true, 926 .has_128_bit_mb = false, 927 .reg_stride = 0x100, 928 }; 929 930 static const struct tegra_hsp_soc tegra234_hsp_soc = { 931 .map = tegra186_hsp_db_map, 932 .has_per_mb_ie = false, 933 .has_128_bit_mb = true, 934 .reg_stride = 0x100, 935 }; 936 937 static const struct tegra_hsp_soc tegra264_hsp_soc = { 938 .map = tegra186_hsp_db_map, 939 .has_per_mb_ie = false, 940 .has_128_bit_mb = true, 941 .reg_stride = 0x1000, 942 }; 943 944 static const struct of_device_id tegra_hsp_match[] = { 945 { .compatible = "nvidia,tegra186-hsp", .data = &tegra186_hsp_soc }, 946 { .compatible = "nvidia,tegra194-hsp", .data = &tegra194_hsp_soc }, 947 { .compatible = "nvidia,tegra234-hsp", .data = &tegra234_hsp_soc }, 948 { .compatible = "nvidia,tegra264-hsp", .data = &tegra264_hsp_soc }, 949 { } 950 }; 951 952 static struct platform_driver tegra_hsp_driver = { 953 .driver = { 954 .name = "tegra-hsp", 955 .of_match_table = tegra_hsp_match, 956 .pm = &tegra_hsp_pm_ops, 957 }, 958 .probe = tegra_hsp_probe, 959 .remove = tegra_hsp_remove, 960 }; 961 962 static int __init tegra_hsp_init(void) 963 { 964 return platform_driver_register(&tegra_hsp_driver); 965 } 966 core_initcall(tegra_hsp_init); 967