xref: /linux/drivers/mailbox/rockchip-mailbox.c (revision 7db28abbea0f7dc1ec4fdfdc149db5fbd9e4c994)
1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3  * Copyright (c) 2015, Fuzhou Rockchip Electronics Co., Ltd
4  */
5 
6 #include <linux/clk.h>
7 #include <linux/interrupt.h>
8 #include <linux/io.h>
9 #include <linux/kernel.h>
10 #include <linux/mailbox_controller.h>
11 #include <linux/of.h>
12 #include <linux/module.h>
13 #include <linux/platform_device.h>
14 
15 #define MAILBOX_A2B_INTEN		0x00
16 #define MAILBOX_A2B_STATUS		0x04
17 #define MAILBOX_A2B_CMD(x)		(0x08 + (x) * 8)
18 #define MAILBOX_A2B_DAT(x)		(0x0c + (x) * 8)
19 
20 #define MAILBOX_B2A_INTEN		0x28
21 #define MAILBOX_B2A_STATUS		0x2C
22 #define MAILBOX_B2A_CMD(x)		(0x30 + (x) * 8)
23 #define MAILBOX_B2A_DAT(x)		(0x34 + (x) * 8)
24 
25 struct rockchip_mbox_msg {
26 	u32 cmd;
27 	int rx_size;
28 };
29 
30 struct rockchip_mbox_data {
31 	int num_chans;
32 };
33 
34 struct rockchip_mbox_chan {
35 	int idx;
36 	int irq;
37 	struct rockchip_mbox_msg *msg;
38 	struct rockchip_mbox *mb;
39 };
40 
41 struct rockchip_mbox {
42 	struct mbox_controller mbox;
43 	void __iomem *mbox_base;
44 
45 	/* The maximum size of buf for each channel */
46 	u32 buf_size;
47 
48 	struct rockchip_mbox_chan chans[];
49 };
50 
51 static int rockchip_mbox_send_data(struct mbox_chan *chan, void *data)
52 {
53 	struct rockchip_mbox *mb = dev_get_drvdata(chan->mbox->dev);
54 	struct rockchip_mbox_msg *msg = data;
55 	struct rockchip_mbox_chan *chans = mb->chans;
56 
57 	if (!msg)
58 		return -EINVAL;
59 
60 	if (msg->rx_size > mb->buf_size) {
61 		dev_err(mb->mbox.dev, "Transmit size over buf size(%d)\n",
62 			mb->buf_size);
63 		return -EINVAL;
64 	}
65 
66 	dev_dbg(mb->mbox.dev, "Chan[%d]: A2B message, cmd 0x%08x\n",
67 		chans->idx, msg->cmd);
68 
69 	mb->chans[chans->idx].msg = msg;
70 
71 	writel_relaxed(msg->cmd, mb->mbox_base + MAILBOX_A2B_CMD(chans->idx));
72 	writel_relaxed(msg->rx_size, mb->mbox_base +
73 		       MAILBOX_A2B_DAT(chans->idx));
74 
75 	return 0;
76 }
77 
78 static int rockchip_mbox_startup(struct mbox_chan *chan)
79 {
80 	struct rockchip_mbox *mb = dev_get_drvdata(chan->mbox->dev);
81 
82 	/* Enable all B2A interrupts */
83 	writel_relaxed((1 << mb->mbox.num_chans) - 1,
84 		       mb->mbox_base + MAILBOX_B2A_INTEN);
85 
86 	return 0;
87 }
88 
89 static void rockchip_mbox_shutdown(struct mbox_chan *chan)
90 {
91 	struct rockchip_mbox *mb = dev_get_drvdata(chan->mbox->dev);
92 	struct rockchip_mbox_chan *chans = mb->chans;
93 
94 	/* Disable all B2A interrupts */
95 	writel_relaxed(0, mb->mbox_base + MAILBOX_B2A_INTEN);
96 
97 	mb->chans[chans->idx].msg = NULL;
98 }
99 
100 static const struct mbox_chan_ops rockchip_mbox_chan_ops = {
101 	.send_data	= rockchip_mbox_send_data,
102 	.startup	= rockchip_mbox_startup,
103 	.shutdown	= rockchip_mbox_shutdown,
104 };
105 
106 static irqreturn_t rockchip_mbox_irq(int irq, void *dev_id)
107 {
108 	int idx;
109 	struct rockchip_mbox *mb = (struct rockchip_mbox *)dev_id;
110 	u32 status = readl_relaxed(mb->mbox_base + MAILBOX_B2A_STATUS);
111 
112 	for (idx = 0; idx < mb->mbox.num_chans; idx++) {
113 		if ((status & (1 << idx)) && (irq == mb->chans[idx].irq)) {
114 			/* Clear mbox interrupt */
115 			writel_relaxed(1 << idx,
116 				       mb->mbox_base + MAILBOX_B2A_STATUS);
117 			return IRQ_WAKE_THREAD;
118 		}
119 	}
120 
121 	return IRQ_NONE;
122 }
123 
124 static irqreturn_t rockchip_mbox_isr(int irq, void *dev_id)
125 {
126 	int idx;
127 	struct rockchip_mbox_msg *msg = NULL;
128 	struct rockchip_mbox *mb = (struct rockchip_mbox *)dev_id;
129 
130 	for (idx = 0; idx < mb->mbox.num_chans; idx++) {
131 		if (irq != mb->chans[idx].irq)
132 			continue;
133 
134 		msg = mb->chans[idx].msg;
135 		if (!msg) {
136 			dev_err(mb->mbox.dev,
137 				"Chan[%d]: B2A message is NULL\n", idx);
138 			break; /* spurious */
139 		}
140 
141 		mbox_chan_received_data(&mb->mbox.chans[idx], msg);
142 		mb->chans[idx].msg = NULL;
143 
144 		dev_dbg(mb->mbox.dev, "Chan[%d]: B2A message, cmd 0x%08x\n",
145 			idx, msg->cmd);
146 
147 		break;
148 	}
149 
150 	return IRQ_HANDLED;
151 }
152 
153 static const struct rockchip_mbox_data rk3368_drv_data = {
154 	.num_chans = 4,
155 };
156 
157 static const struct of_device_id rockchip_mbox_of_match[] = {
158 	{ .compatible = "rockchip,rk3368-mailbox", .data = &rk3368_drv_data},
159 	{ },
160 };
161 MODULE_DEVICE_TABLE(of, rockchip_mbox_of_match);
162 
163 static int rockchip_mbox_probe(struct platform_device *pdev)
164 {
165 	struct rockchip_mbox *mb;
166 	const struct rockchip_mbox_data *drv_data;
167 	struct resource *res;
168 	struct clk *pclk;
169 	int ret, irq, i;
170 
171 	if (!pdev->dev.of_node)
172 		return -ENODEV;
173 
174 	drv_data = (const struct rockchip_mbox_data *) device_get_match_data(&pdev->dev);
175 
176 	mb = devm_kzalloc(&pdev->dev, struct_size(mb, chans, drv_data->num_chans), GFP_KERNEL);
177 	if (!mb)
178 		return -ENOMEM;
179 
180 	mb->mbox.chans = devm_kcalloc(&pdev->dev, drv_data->num_chans,
181 				      sizeof(*mb->mbox.chans), GFP_KERNEL);
182 	if (!mb->mbox.chans)
183 		return -ENOMEM;
184 
185 	platform_set_drvdata(pdev, mb);
186 
187 	mb->mbox.dev = &pdev->dev;
188 	mb->mbox.num_chans = drv_data->num_chans;
189 	mb->mbox.ops = &rockchip_mbox_chan_ops;
190 	mb->mbox.txdone_irq = true;
191 
192 	mb->mbox_base = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
193 	if (IS_ERR(mb->mbox_base))
194 		return PTR_ERR(mb->mbox_base);
195 
196 	/* Each channel has two buffers for A2B and B2A */
197 	mb->buf_size = (size_t)resource_size(res) / (drv_data->num_chans * 2);
198 
199 	pclk = devm_clk_get_enabled(&pdev->dev, "pclk_mailbox");
200 	if (IS_ERR(pclk))
201 		return dev_err_probe(&pdev->dev, PTR_ERR(pclk),
202 				     "failed to get and enable pclk_mailbox clock\n");
203 
204 	for (i = 0; i < mb->mbox.num_chans; i++) {
205 		irq = platform_get_irq(pdev, i);
206 		if (irq < 0)
207 			return irq;
208 
209 		ret = devm_request_threaded_irq(&pdev->dev, irq,
210 						rockchip_mbox_irq,
211 						rockchip_mbox_isr, IRQF_ONESHOT,
212 						dev_name(&pdev->dev), mb);
213 		if (ret < 0)
214 			return ret;
215 
216 		mb->chans[i].idx = i;
217 		mb->chans[i].irq = irq;
218 		mb->chans[i].mb = mb;
219 		mb->chans[i].msg = NULL;
220 	}
221 
222 	ret = devm_mbox_controller_register(&pdev->dev, &mb->mbox);
223 	if (ret < 0)
224 		dev_err(&pdev->dev, "Failed to register mailbox: %d\n", ret);
225 
226 	return ret;
227 }
228 
229 static struct platform_driver rockchip_mbox_driver = {
230 	.probe	= rockchip_mbox_probe,
231 	.driver = {
232 		.name = "rockchip-mailbox",
233 		.of_match_table = rockchip_mbox_of_match,
234 	},
235 };
236 
237 module_platform_driver(rockchip_mbox_driver);
238 
239 MODULE_DESCRIPTION("Rockchip mailbox: communicate between CPU cores and MCU");
240 MODULE_AUTHOR("Addy Ke <addy.ke@rock-chips.com>");
241 MODULE_AUTHOR("Caesar Wang <wxt@rock-chips.com>");
242