1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2018-2020, The Linux Foundation. All rights reserved. 4 */ 5 6 #include <linux/bitfield.h> 7 #include <linux/interrupt.h> 8 #include <linux/irq.h> 9 #include <linux/irqdomain.h> 10 #include <linux/mailbox_controller.h> 11 #include <linux/module.h> 12 #include <linux/platform_device.h> 13 14 #include <dt-bindings/mailbox/qcom-ipcc.h> 15 16 /* IPCC Register offsets */ 17 #define IPCC_REG_CONFIG 0x08 18 #define IPCC_REG_SEND_ID 0x0c 19 #define IPCC_REG_RECV_ID 0x10 20 #define IPCC_REG_RECV_SIGNAL_ENABLE 0x14 21 #define IPCC_REG_RECV_SIGNAL_DISABLE 0x18 22 #define IPCC_REG_RECV_SIGNAL_CLEAR 0x1c 23 #define IPCC_REG_CLIENT_CLEAR 0x38 24 25 #define IPCC_CLEAR_ON_RECV_RD BIT(0) 26 #define IPCC_SIGNAL_ID_MASK GENMASK(15, 0) 27 #define IPCC_CLIENT_ID_MASK GENMASK(31, 16) 28 29 #define IPCC_NO_PENDING_IRQ GENMASK(31, 0) 30 31 /** 32 * struct qcom_ipcc_chan_info - Per-mailbox-channel info 33 * @client_id: The client-id to which the interrupt has to be triggered 34 * @signal_id: The signal-id to which the interrupt has to be triggered 35 */ 36 struct qcom_ipcc_chan_info { 37 u16 client_id; 38 u16 signal_id; 39 }; 40 41 /** 42 * struct qcom_ipcc - Holder for the mailbox driver 43 * @dev: Device associated with this instance 44 * @base: Base address of the IPCC frame associated to APSS 45 * @irq_domain: The irq_domain associated with this instance 46 * @chans: The mailbox channels array 47 * @mchan: The per-mailbox channel info array 48 * @mbox: The mailbox controller 49 * @num_chans: Number of @chans elements 50 * @irq: Summary irq 51 */ 52 struct qcom_ipcc { 53 struct device *dev; 54 void __iomem *base; 55 struct irq_domain *irq_domain; 56 struct mbox_chan *chans; 57 struct qcom_ipcc_chan_info *mchan; 58 struct mbox_controller mbox; 59 int num_chans; 60 int irq; 61 }; 62 63 static inline struct qcom_ipcc *to_qcom_ipcc(struct mbox_controller *mbox) 64 { 65 return container_of(mbox, struct qcom_ipcc, mbox); 66 } 67 68 static inline u32 qcom_ipcc_get_hwirq(u16 client_id, u16 signal_id) 69 { 70 return FIELD_PREP(IPCC_CLIENT_ID_MASK, client_id) | 71 FIELD_PREP(IPCC_SIGNAL_ID_MASK, signal_id); 72 } 73 74 static irqreturn_t qcom_ipcc_irq_fn(int irq, void *data) 75 { 76 struct qcom_ipcc *ipcc = data; 77 u32 hwirq; 78 int virq; 79 80 for (;;) { 81 hwirq = readl(ipcc->base + IPCC_REG_RECV_ID); 82 if (hwirq == IPCC_NO_PENDING_IRQ) 83 break; 84 85 virq = irq_find_mapping(ipcc->irq_domain, hwirq); 86 writel(hwirq, ipcc->base + IPCC_REG_RECV_SIGNAL_CLEAR); 87 generic_handle_irq(virq); 88 } 89 90 return IRQ_HANDLED; 91 } 92 93 static void qcom_ipcc_mask_irq(struct irq_data *irqd) 94 { 95 struct qcom_ipcc *ipcc = irq_data_get_irq_chip_data(irqd); 96 irq_hw_number_t hwirq = irqd_to_hwirq(irqd); 97 98 writel(hwirq, ipcc->base + IPCC_REG_RECV_SIGNAL_DISABLE); 99 } 100 101 static void qcom_ipcc_unmask_irq(struct irq_data *irqd) 102 { 103 struct qcom_ipcc *ipcc = irq_data_get_irq_chip_data(irqd); 104 irq_hw_number_t hwirq = irqd_to_hwirq(irqd); 105 106 writel(hwirq, ipcc->base + IPCC_REG_RECV_SIGNAL_ENABLE); 107 } 108 109 static struct irq_chip qcom_ipcc_irq_chip = { 110 .name = "ipcc", 111 .irq_mask = qcom_ipcc_mask_irq, 112 .irq_unmask = qcom_ipcc_unmask_irq, 113 .flags = IRQCHIP_SKIP_SET_WAKE, 114 }; 115 116 static int qcom_ipcc_domain_map(struct irq_domain *d, unsigned int irq, 117 irq_hw_number_t hw) 118 { 119 struct qcom_ipcc *ipcc = d->host_data; 120 121 irq_set_chip_and_handler(irq, &qcom_ipcc_irq_chip, handle_level_irq); 122 irq_set_chip_data(irq, ipcc); 123 irq_set_noprobe(irq); 124 125 return 0; 126 } 127 128 static int qcom_ipcc_domain_xlate(struct irq_domain *d, 129 struct device_node *node, const u32 *intspec, 130 unsigned int intsize, 131 unsigned long *out_hwirq, 132 unsigned int *out_type) 133 { 134 if (intsize != 3) 135 return -EINVAL; 136 137 *out_hwirq = qcom_ipcc_get_hwirq(intspec[0], intspec[1]); 138 *out_type = intspec[2] & IRQ_TYPE_SENSE_MASK; 139 140 return 0; 141 } 142 143 static const struct irq_domain_ops qcom_ipcc_irq_ops = { 144 .map = qcom_ipcc_domain_map, 145 .xlate = qcom_ipcc_domain_xlate, 146 }; 147 148 static int qcom_ipcc_mbox_send_data(struct mbox_chan *chan, void *data) 149 { 150 struct qcom_ipcc *ipcc = to_qcom_ipcc(chan->mbox); 151 struct qcom_ipcc_chan_info *mchan = chan->con_priv; 152 u32 hwirq; 153 154 hwirq = qcom_ipcc_get_hwirq(mchan->client_id, mchan->signal_id); 155 writel(hwirq, ipcc->base + IPCC_REG_SEND_ID); 156 157 return 0; 158 } 159 160 static void qcom_ipcc_mbox_shutdown(struct mbox_chan *chan) 161 { 162 chan->con_priv = NULL; 163 } 164 165 static struct mbox_chan *qcom_ipcc_mbox_xlate(struct mbox_controller *mbox, 166 const struct of_phandle_args *ph) 167 { 168 struct qcom_ipcc *ipcc = to_qcom_ipcc(mbox); 169 struct qcom_ipcc_chan_info *mchan; 170 struct mbox_chan *chan, *free_chan = NULL; 171 struct device *dev; 172 int chan_id; 173 174 dev = ipcc->dev; 175 176 if (ph->args_count != 2) 177 return ERR_PTR(-EINVAL); 178 179 for (chan_id = 0; chan_id < mbox->num_chans; chan_id++) { 180 chan = &ipcc->chans[chan_id]; 181 mchan = chan->con_priv; 182 183 if (!mchan) { 184 /* Keep scanning past holes to reject duplicate channel requests. */ 185 if (!free_chan) 186 free_chan = chan; 187 } else if (mchan->client_id == ph->args[0] && 188 mchan->signal_id == ph->args[1]) { 189 return ERR_PTR(-EBUSY); 190 } 191 } 192 193 if (!free_chan) 194 return ERR_PTR(-EBUSY); 195 196 chan = free_chan; 197 198 mchan = devm_kzalloc(dev, sizeof(*mchan), GFP_KERNEL); 199 if (!mchan) 200 return ERR_PTR(-ENOMEM); 201 202 mchan->client_id = ph->args[0]; 203 mchan->signal_id = ph->args[1]; 204 chan->con_priv = mchan; 205 206 return chan; 207 } 208 209 static const struct mbox_chan_ops ipcc_mbox_chan_ops = { 210 .send_data = qcom_ipcc_mbox_send_data, 211 .shutdown = qcom_ipcc_mbox_shutdown, 212 }; 213 214 static int qcom_ipcc_setup_mbox(struct qcom_ipcc *ipcc, 215 struct device_node *controller_dn) 216 { 217 struct of_phandle_args curr_ph; 218 struct device_node *client_dn; 219 struct mbox_controller *mbox; 220 struct device *dev = ipcc->dev; 221 int i, j, ret; 222 223 /* 224 * Find out the number of clients interested in this mailbox 225 * and create channels accordingly. 226 */ 227 ipcc->num_chans = 0; 228 for_each_node_with_property(client_dn, "mboxes") { 229 if (!of_device_is_available(client_dn)) 230 continue; 231 i = of_count_phandle_with_args(client_dn, 232 "mboxes", "#mbox-cells"); 233 for (j = 0; j < i; j++) { 234 ret = of_parse_phandle_with_args(client_dn, "mboxes", 235 "#mbox-cells", j, &curr_ph); 236 of_node_put(curr_ph.np); 237 if (!ret && curr_ph.np == controller_dn) 238 ipcc->num_chans++; 239 } 240 } 241 242 /* If no clients are found, skip registering as a mbox controller */ 243 if (!ipcc->num_chans) 244 return 0; 245 246 ipcc->chans = devm_kcalloc(dev, ipcc->num_chans, 247 sizeof(struct mbox_chan), GFP_KERNEL); 248 if (!ipcc->chans) 249 return -ENOMEM; 250 251 mbox = &ipcc->mbox; 252 mbox->dev = dev; 253 mbox->num_chans = ipcc->num_chans; 254 mbox->chans = ipcc->chans; 255 mbox->ops = &ipcc_mbox_chan_ops; 256 mbox->of_xlate = qcom_ipcc_mbox_xlate; 257 mbox->txdone_irq = false; 258 mbox->txdone_poll = false; 259 260 return devm_mbox_controller_register(dev, mbox); 261 } 262 263 static int qcom_ipcc_pm_resume(struct device *dev) 264 { 265 struct qcom_ipcc *ipcc = dev_get_drvdata(dev); 266 u32 hwirq; 267 int virq; 268 269 hwirq = readl(ipcc->base + IPCC_REG_RECV_ID); 270 if (hwirq == IPCC_NO_PENDING_IRQ) 271 return 0; 272 273 virq = irq_find_mapping(ipcc->irq_domain, hwirq); 274 275 dev_dbg(dev, "virq: %d triggered client-id: %ld; signal-id: %ld\n", virq, 276 FIELD_GET(IPCC_CLIENT_ID_MASK, hwirq), FIELD_GET(IPCC_SIGNAL_ID_MASK, hwirq)); 277 278 return 0; 279 } 280 281 static int qcom_ipcc_probe(struct platform_device *pdev) 282 { 283 struct qcom_ipcc *ipcc; 284 u32 config_value; 285 static int id; 286 char *name; 287 int ret; 288 289 ipcc = devm_kzalloc(&pdev->dev, sizeof(*ipcc), GFP_KERNEL); 290 if (!ipcc) 291 return -ENOMEM; 292 293 ipcc->dev = &pdev->dev; 294 295 ipcc->base = devm_platform_ioremap_resource(pdev, 0); 296 if (IS_ERR(ipcc->base)) 297 return PTR_ERR(ipcc->base); 298 299 /* 300 * It is possible that boot firmware is using the same IPCC instance 301 * as of the HLOS and it has kept CLEAR_ON_RECV_RD set which basically 302 * means Interrupt pending registers are cleared when RECV_ID is read. 303 * The register automatically updates to the next pending interrupt/client 304 * status based on priority. 305 */ 306 config_value = readl(ipcc->base + IPCC_REG_CONFIG); 307 if (config_value & IPCC_CLEAR_ON_RECV_RD) { 308 config_value &= ~(IPCC_CLEAR_ON_RECV_RD); 309 writel(config_value, ipcc->base + IPCC_REG_CONFIG); 310 } 311 312 ipcc->irq = platform_get_irq(pdev, 0); 313 if (ipcc->irq < 0) 314 return ipcc->irq; 315 316 name = devm_kasprintf(&pdev->dev, GFP_KERNEL, "ipcc_%d", id++); 317 if (!name) 318 return -ENOMEM; 319 320 ipcc->irq_domain = irq_domain_create_tree(dev_fwnode(&pdev->dev), &qcom_ipcc_irq_ops, ipcc); 321 if (!ipcc->irq_domain) 322 return -ENOMEM; 323 324 ret = qcom_ipcc_setup_mbox(ipcc, pdev->dev.of_node); 325 if (ret) 326 goto err_mbox; 327 328 ret = devm_request_irq(&pdev->dev, ipcc->irq, qcom_ipcc_irq_fn, 329 IRQF_TRIGGER_HIGH | IRQF_NO_SUSPEND | 330 IRQF_NO_THREAD, name, ipcc); 331 if (ret < 0) 332 goto err_req_irq; 333 334 platform_set_drvdata(pdev, ipcc); 335 336 return 0; 337 338 err_req_irq: 339 if (ipcc->num_chans) 340 mbox_controller_unregister(&ipcc->mbox); 341 err_mbox: 342 irq_domain_remove(ipcc->irq_domain); 343 344 return ret; 345 } 346 347 static void qcom_ipcc_remove(struct platform_device *pdev) 348 { 349 struct qcom_ipcc *ipcc = platform_get_drvdata(pdev); 350 351 disable_irq_wake(ipcc->irq); 352 irq_domain_remove(ipcc->irq_domain); 353 } 354 355 static const struct of_device_id qcom_ipcc_of_match[] = { 356 { .compatible = "qcom,ipcc"}, 357 {} 358 }; 359 MODULE_DEVICE_TABLE(of, qcom_ipcc_of_match); 360 361 static const struct dev_pm_ops qcom_ipcc_dev_pm_ops = { 362 NOIRQ_SYSTEM_SLEEP_PM_OPS(NULL, qcom_ipcc_pm_resume) 363 }; 364 365 static struct platform_driver qcom_ipcc_driver = { 366 .probe = qcom_ipcc_probe, 367 .remove = qcom_ipcc_remove, 368 .driver = { 369 .name = "qcom-ipcc", 370 .of_match_table = qcom_ipcc_of_match, 371 .suppress_bind_attrs = true, 372 .pm = pm_sleep_ptr(&qcom_ipcc_dev_pm_ops), 373 }, 374 }; 375 376 static int __init qcom_ipcc_init(void) 377 { 378 return platform_driver_register(&qcom_ipcc_driver); 379 } 380 arch_initcall(qcom_ipcc_init); 381 382 MODULE_AUTHOR("Venkata Narendra Kumar Gutta <vnkgutta@codeaurora.org>"); 383 MODULE_AUTHOR("Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>"); 384 MODULE_DESCRIPTION("Qualcomm Technologies, Inc. IPCC driver"); 385 MODULE_LICENSE("GPL v2"); 386