1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2018-2020, The Linux Foundation. All rights reserved. 4 */ 5 6 #include <linux/bitfield.h> 7 #include <linux/interrupt.h> 8 #include <linux/irq.h> 9 #include <linux/irqdomain.h> 10 #include <linux/mailbox_controller.h> 11 #include <linux/module.h> 12 #include <linux/platform_device.h> 13 #include <linux/spinlock.h> 14 15 #include <dt-bindings/mailbox/qcom-ipcc.h> 16 17 /* IPCC Register offsets */ 18 #define IPCC_REG_CONFIG 0x08 19 #define IPCC_REG_SEND_ID 0x0c 20 #define IPCC_REG_RECV_ID 0x10 21 #define IPCC_REG_RECV_SIGNAL_ENABLE 0x14 22 #define IPCC_REG_RECV_SIGNAL_DISABLE 0x18 23 #define IPCC_REG_RECV_SIGNAL_CLEAR 0x1c 24 #define IPCC_REG_CLIENT_CLEAR 0x38 25 26 #define IPCC_CLEAR_ON_RECV_RD BIT(0) 27 #define IPCC_SIGNAL_ID_MASK GENMASK(15, 0) 28 #define IPCC_CLIENT_ID_MASK GENMASK(31, 16) 29 30 #define IPCC_NO_PENDING_IRQ GENMASK(31, 0) 31 32 /** 33 * struct qcom_ipcc_chan_info - Per-mailbox-channel info 34 * @client_id: The client-id to which the interrupt has to be triggered 35 * @signal_id: The signal-id to which the interrupt has to be triggered 36 */ 37 struct qcom_ipcc_chan_info { 38 u16 client_id; 39 u16 signal_id; 40 }; 41 42 /** 43 * struct qcom_ipcc - Holder for the mailbox driver 44 * @dev: Device associated with this instance 45 * @base: Base address of the IPCC frame associated to APSS 46 * @irq_domain: The irq_domain associated with this instance 47 * @chans: The mailbox channels array 48 * @mchan: The per-mailbox channel info array 49 * @mbox: The mailbox controller 50 * @num_chans: Number of @chans elements 51 * @irq: Summary irq 52 */ 53 struct qcom_ipcc { 54 struct device *dev; 55 void __iomem *base; 56 struct irq_domain *irq_domain; 57 struct mbox_chan *chans; 58 struct qcom_ipcc_chan_info *mchan; 59 struct mbox_controller mbox; 60 int num_chans; 61 int irq; 62 }; 63 64 static inline struct qcom_ipcc *to_qcom_ipcc(struct mbox_controller *mbox) 65 { 66 return container_of(mbox, struct qcom_ipcc, mbox); 67 } 68 69 static inline u32 qcom_ipcc_get_hwirq(u16 client_id, u16 signal_id) 70 { 71 return FIELD_PREP(IPCC_CLIENT_ID_MASK, client_id) | 72 FIELD_PREP(IPCC_SIGNAL_ID_MASK, signal_id); 73 } 74 75 static irqreturn_t qcom_ipcc_irq_fn(int irq, void *data) 76 { 77 struct qcom_ipcc *ipcc = data; 78 u32 hwirq; 79 int virq; 80 81 for (;;) { 82 hwirq = readl(ipcc->base + IPCC_REG_RECV_ID); 83 if (hwirq == IPCC_NO_PENDING_IRQ) 84 break; 85 86 virq = irq_find_mapping(ipcc->irq_domain, hwirq); 87 writel(hwirq, ipcc->base + IPCC_REG_RECV_SIGNAL_CLEAR); 88 generic_handle_irq(virq); 89 } 90 91 return IRQ_HANDLED; 92 } 93 94 static void qcom_ipcc_mask_irq(struct irq_data *irqd) 95 { 96 struct qcom_ipcc *ipcc = irq_data_get_irq_chip_data(irqd); 97 irq_hw_number_t hwirq = irqd_to_hwirq(irqd); 98 99 writel(hwirq, ipcc->base + IPCC_REG_RECV_SIGNAL_DISABLE); 100 } 101 102 static void qcom_ipcc_unmask_irq(struct irq_data *irqd) 103 { 104 struct qcom_ipcc *ipcc = irq_data_get_irq_chip_data(irqd); 105 irq_hw_number_t hwirq = irqd_to_hwirq(irqd); 106 107 writel(hwirq, ipcc->base + IPCC_REG_RECV_SIGNAL_ENABLE); 108 } 109 110 static struct irq_chip qcom_ipcc_irq_chip = { 111 .name = "ipcc", 112 .irq_mask = qcom_ipcc_mask_irq, 113 .irq_unmask = qcom_ipcc_unmask_irq, 114 .flags = IRQCHIP_SKIP_SET_WAKE, 115 }; 116 117 static int qcom_ipcc_domain_map(struct irq_domain *d, unsigned int irq, 118 irq_hw_number_t hw) 119 { 120 struct qcom_ipcc *ipcc = d->host_data; 121 122 irq_set_chip_and_handler(irq, &qcom_ipcc_irq_chip, handle_level_irq); 123 irq_set_chip_data(irq, ipcc); 124 irq_set_noprobe(irq); 125 126 return 0; 127 } 128 129 static int qcom_ipcc_domain_xlate(struct irq_domain *d, 130 struct device_node *node, const u32 *intspec, 131 unsigned int intsize, 132 unsigned long *out_hwirq, 133 unsigned int *out_type) 134 { 135 if (intsize != 3) 136 return -EINVAL; 137 138 *out_hwirq = qcom_ipcc_get_hwirq(intspec[0], intspec[1]); 139 *out_type = intspec[2] & IRQ_TYPE_SENSE_MASK; 140 141 return 0; 142 } 143 144 static const struct irq_domain_ops qcom_ipcc_irq_ops = { 145 .map = qcom_ipcc_domain_map, 146 .xlate = qcom_ipcc_domain_xlate, 147 }; 148 149 static int qcom_ipcc_mbox_send_data(struct mbox_chan *chan, void *data) 150 { 151 struct qcom_ipcc *ipcc = to_qcom_ipcc(chan->mbox); 152 struct qcom_ipcc_chan_info *mchan = chan->con_priv; 153 u32 hwirq; 154 155 if (!mchan) 156 return -EINVAL; 157 158 hwirq = qcom_ipcc_get_hwirq(mchan->client_id, mchan->signal_id); 159 writel(hwirq, ipcc->base + IPCC_REG_SEND_ID); 160 161 return 0; 162 } 163 164 static void qcom_ipcc_mbox_shutdown(struct mbox_chan *chan) 165 { 166 guard(spinlock_irqsave)(&chan->lock); 167 168 chan->con_priv = NULL; 169 } 170 171 static struct mbox_chan *qcom_ipcc_mbox_xlate(struct mbox_controller *mbox, 172 const struct of_phandle_args *ph) 173 { 174 struct qcom_ipcc *ipcc = to_qcom_ipcc(mbox); 175 struct qcom_ipcc_chan_info *mchan; 176 struct mbox_chan *chan, *free_chan = NULL; 177 struct device *dev; 178 int chan_id; 179 180 dev = ipcc->dev; 181 182 if (ph->args_count != 2) 183 return ERR_PTR(-EINVAL); 184 185 for (chan_id = 0; chan_id < mbox->num_chans; chan_id++) { 186 chan = &ipcc->chans[chan_id]; 187 mchan = chan->con_priv; 188 189 if (!mchan) { 190 /* Keep scanning past holes to reject duplicate channel requests. */ 191 if (!free_chan) 192 free_chan = chan; 193 } else if (mchan->client_id == ph->args[0] && 194 mchan->signal_id == ph->args[1]) { 195 return ERR_PTR(-EBUSY); 196 } 197 } 198 199 if (!free_chan) 200 return ERR_PTR(-EBUSY); 201 202 chan = free_chan; 203 204 mchan = devm_kzalloc(dev, sizeof(*mchan), GFP_KERNEL); 205 if (!mchan) 206 return ERR_PTR(-ENOMEM); 207 208 mchan->client_id = ph->args[0]; 209 mchan->signal_id = ph->args[1]; 210 chan->con_priv = mchan; 211 212 return chan; 213 } 214 215 static const struct mbox_chan_ops ipcc_mbox_chan_ops = { 216 .send_data = qcom_ipcc_mbox_send_data, 217 .shutdown = qcom_ipcc_mbox_shutdown, 218 }; 219 220 static int qcom_ipcc_setup_mbox(struct qcom_ipcc *ipcc, 221 struct device_node *controller_dn) 222 { 223 struct of_phandle_args curr_ph; 224 struct device_node *client_dn; 225 struct mbox_controller *mbox; 226 struct device *dev = ipcc->dev; 227 int i, j, ret; 228 229 /* 230 * Find out the number of clients interested in this mailbox 231 * and create channels accordingly. 232 */ 233 ipcc->num_chans = 0; 234 for_each_node_with_property(client_dn, "mboxes") { 235 if (!of_device_is_available(client_dn)) 236 continue; 237 i = of_count_phandle_with_args(client_dn, 238 "mboxes", "#mbox-cells"); 239 for (j = 0; j < i; j++) { 240 ret = of_parse_phandle_with_args(client_dn, "mboxes", 241 "#mbox-cells", j, &curr_ph); 242 of_node_put(curr_ph.np); 243 if (!ret && curr_ph.np == controller_dn) 244 ipcc->num_chans++; 245 } 246 } 247 248 /* If no clients are found, skip registering as a mbox controller */ 249 if (!ipcc->num_chans) 250 return 0; 251 252 ipcc->chans = devm_kcalloc(dev, ipcc->num_chans, 253 sizeof(struct mbox_chan), GFP_KERNEL); 254 if (!ipcc->chans) 255 return -ENOMEM; 256 257 mbox = &ipcc->mbox; 258 mbox->dev = dev; 259 mbox->num_chans = ipcc->num_chans; 260 mbox->chans = ipcc->chans; 261 mbox->ops = &ipcc_mbox_chan_ops; 262 mbox->of_xlate = qcom_ipcc_mbox_xlate; 263 mbox->txdone_irq = false; 264 mbox->txdone_poll = false; 265 266 return devm_mbox_controller_register(dev, mbox); 267 } 268 269 static int qcom_ipcc_pm_resume(struct device *dev) 270 { 271 struct qcom_ipcc *ipcc = dev_get_drvdata(dev); 272 u32 hwirq; 273 int virq; 274 275 hwirq = readl(ipcc->base + IPCC_REG_RECV_ID); 276 if (hwirq == IPCC_NO_PENDING_IRQ) 277 return 0; 278 279 virq = irq_find_mapping(ipcc->irq_domain, hwirq); 280 281 dev_dbg(dev, "virq: %d triggered client-id: %ld; signal-id: %ld\n", virq, 282 FIELD_GET(IPCC_CLIENT_ID_MASK, hwirq), FIELD_GET(IPCC_SIGNAL_ID_MASK, hwirq)); 283 284 return 0; 285 } 286 287 static int qcom_ipcc_probe(struct platform_device *pdev) 288 { 289 struct qcom_ipcc *ipcc; 290 u32 config_value; 291 int ret; 292 293 ipcc = devm_kzalloc(&pdev->dev, sizeof(*ipcc), GFP_KERNEL); 294 if (!ipcc) 295 return -ENOMEM; 296 297 ipcc->dev = &pdev->dev; 298 299 ipcc->base = devm_platform_ioremap_resource(pdev, 0); 300 if (IS_ERR(ipcc->base)) 301 return PTR_ERR(ipcc->base); 302 303 /* 304 * It is possible that boot firmware is using the same IPCC instance 305 * as of the HLOS and it has kept CLEAR_ON_RECV_RD set which basically 306 * means Interrupt pending registers are cleared when RECV_ID is read. 307 * The register automatically updates to the next pending interrupt/client 308 * status based on priority. 309 */ 310 config_value = readl(ipcc->base + IPCC_REG_CONFIG); 311 if (config_value & IPCC_CLEAR_ON_RECV_RD) { 312 config_value &= ~(IPCC_CLEAR_ON_RECV_RD); 313 writel(config_value, ipcc->base + IPCC_REG_CONFIG); 314 } 315 316 ipcc->irq = platform_get_irq(pdev, 0); 317 if (ipcc->irq < 0) 318 return ipcc->irq; 319 320 ipcc->irq_domain = irq_domain_create_tree(dev_fwnode(&pdev->dev), &qcom_ipcc_irq_ops, ipcc); 321 if (!ipcc->irq_domain) 322 return -ENOMEM; 323 324 ret = qcom_ipcc_setup_mbox(ipcc, pdev->dev.of_node); 325 if (ret) 326 goto err_mbox; 327 328 ret = devm_request_irq(&pdev->dev, ipcc->irq, qcom_ipcc_irq_fn, 329 IRQF_TRIGGER_HIGH | IRQF_NO_SUSPEND | 330 IRQF_NO_THREAD, dev_name(&pdev->dev), ipcc); 331 if (ret < 0) 332 goto err_mbox; 333 334 platform_set_drvdata(pdev, ipcc); 335 336 return 0; 337 338 err_mbox: 339 irq_domain_remove(ipcc->irq_domain); 340 341 return ret; 342 } 343 344 static void qcom_ipcc_remove(struct platform_device *pdev) 345 { 346 struct qcom_ipcc *ipcc = platform_get_drvdata(pdev); 347 348 irq_domain_remove(ipcc->irq_domain); 349 } 350 351 static const struct of_device_id qcom_ipcc_of_match[] = { 352 { .compatible = "qcom,ipcc"}, 353 {} 354 }; 355 MODULE_DEVICE_TABLE(of, qcom_ipcc_of_match); 356 357 static const struct dev_pm_ops qcom_ipcc_dev_pm_ops = { 358 NOIRQ_SYSTEM_SLEEP_PM_OPS(NULL, qcom_ipcc_pm_resume) 359 }; 360 361 static struct platform_driver qcom_ipcc_driver = { 362 .probe = qcom_ipcc_probe, 363 .remove = qcom_ipcc_remove, 364 .driver = { 365 .name = "qcom-ipcc", 366 .of_match_table = qcom_ipcc_of_match, 367 .suppress_bind_attrs = true, 368 .pm = pm_sleep_ptr(&qcom_ipcc_dev_pm_ops), 369 }, 370 }; 371 372 static int __init qcom_ipcc_init(void) 373 { 374 return platform_driver_register(&qcom_ipcc_driver); 375 } 376 arch_initcall(qcom_ipcc_init); 377 378 MODULE_AUTHOR("Venkata Narendra Kumar Gutta <vnkgutta@codeaurora.org>"); 379 MODULE_AUTHOR("Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>"); 380 MODULE_DESCRIPTION("Qualcomm Technologies, Inc. IPCC driver"); 381 MODULE_LICENSE("GPL v2"); 382