1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * OMAP mailbox driver 4 * 5 * Copyright (C) 2006-2009 Nokia Corporation. All rights reserved. 6 * Copyright (C) 2013-2021 Texas Instruments Incorporated - https://www.ti.com 7 * 8 * Contact: Hiroshi DOYU <Hiroshi.DOYU@nokia.com> 9 * Suman Anna <s-anna@ti.com> 10 */ 11 12 #include <linux/interrupt.h> 13 #include <linux/spinlock.h> 14 #include <linux/mutex.h> 15 #include <linux/slab.h> 16 #include <linux/kfifo.h> 17 #include <linux/err.h> 18 #include <linux/module.h> 19 #include <linux/of.h> 20 #include <linux/platform_device.h> 21 #include <linux/pm_runtime.h> 22 #include <linux/mailbox_controller.h> 23 #include <linux/mailbox_client.h> 24 25 #include "mailbox.h" 26 27 #define MAILBOX_REVISION 0x000 28 #define MAILBOX_MESSAGE(m) (0x040 + 4 * (m)) 29 #define MAILBOX_FIFOSTATUS(m) (0x080 + 4 * (m)) 30 #define MAILBOX_MSGSTATUS(m) (0x0c0 + 4 * (m)) 31 32 #define OMAP2_MAILBOX_IRQSTATUS(u) (0x100 + 8 * (u)) 33 #define OMAP2_MAILBOX_IRQENABLE(u) (0x104 + 8 * (u)) 34 35 #define OMAP4_MAILBOX_IRQSTATUS(u) (0x104 + 0x10 * (u)) 36 #define OMAP4_MAILBOX_IRQENABLE(u) (0x108 + 0x10 * (u)) 37 #define OMAP4_MAILBOX_IRQENABLE_CLR(u) (0x10c + 0x10 * (u)) 38 39 #define MAILBOX_IRQSTATUS(type, u) (type ? OMAP4_MAILBOX_IRQSTATUS(u) : \ 40 OMAP2_MAILBOX_IRQSTATUS(u)) 41 #define MAILBOX_IRQENABLE(type, u) (type ? OMAP4_MAILBOX_IRQENABLE(u) : \ 42 OMAP2_MAILBOX_IRQENABLE(u)) 43 #define MAILBOX_IRQDISABLE(type, u) (type ? OMAP4_MAILBOX_IRQENABLE_CLR(u) \ 44 : OMAP2_MAILBOX_IRQENABLE(u)) 45 46 #define MAILBOX_IRQ_NEWMSG(m) (1 << (2 * (m))) 47 #define MAILBOX_IRQ_NOTFULL(m) (1 << (2 * (m) + 1)) 48 49 /* Interrupt register configuration types */ 50 #define MBOX_INTR_CFG_TYPE1 0 51 #define MBOX_INTR_CFG_TYPE2 1 52 53 typedef enum { 54 IRQ_TX = 1, 55 IRQ_RX = 2, 56 } omap_mbox_irq_t; 57 58 struct omap_mbox_fifo { 59 unsigned long msg; 60 unsigned long fifo_stat; 61 unsigned long msg_stat; 62 unsigned long irqenable; 63 unsigned long irqstatus; 64 unsigned long irqdisable; 65 u32 intr_bit; 66 }; 67 68 struct omap_mbox_match_data { 69 u32 intr_type; 70 }; 71 72 struct omap_mbox_device { 73 struct device *dev; 74 struct mutex cfg_lock; 75 void __iomem *mbox_base; 76 u32 *irq_ctx; 77 u32 num_users; 78 u32 num_fifos; 79 u32 intr_type; 80 }; 81 82 struct omap_mbox { 83 const char *name; 84 int irq; 85 struct omap_mbox_device *parent; 86 struct omap_mbox_fifo tx_fifo; 87 struct omap_mbox_fifo rx_fifo; 88 u32 intr_type; 89 struct mbox_chan *chan; 90 bool send_no_irq; 91 }; 92 93 static inline 94 unsigned int mbox_read_reg(struct omap_mbox_device *mdev, size_t ofs) 95 { 96 return __raw_readl(mdev->mbox_base + ofs); 97 } 98 99 static inline 100 void mbox_write_reg(struct omap_mbox_device *mdev, u32 val, size_t ofs) 101 { 102 __raw_writel(val, mdev->mbox_base + ofs); 103 } 104 105 /* Mailbox FIFO handle functions */ 106 static u32 mbox_fifo_read(struct omap_mbox *mbox) 107 { 108 struct omap_mbox_fifo *fifo = &mbox->rx_fifo; 109 110 return mbox_read_reg(mbox->parent, fifo->msg); 111 } 112 113 static void mbox_fifo_write(struct omap_mbox *mbox, u32 msg) 114 { 115 struct omap_mbox_fifo *fifo = &mbox->tx_fifo; 116 117 mbox_write_reg(mbox->parent, msg, fifo->msg); 118 } 119 120 static int mbox_fifo_empty(struct omap_mbox *mbox) 121 { 122 struct omap_mbox_fifo *fifo = &mbox->rx_fifo; 123 124 return (mbox_read_reg(mbox->parent, fifo->msg_stat) == 0); 125 } 126 127 static int mbox_fifo_full(struct omap_mbox *mbox) 128 { 129 struct omap_mbox_fifo *fifo = &mbox->tx_fifo; 130 131 return mbox_read_reg(mbox->parent, fifo->fifo_stat); 132 } 133 134 /* Mailbox IRQ handle functions */ 135 static void ack_mbox_irq(struct omap_mbox *mbox, omap_mbox_irq_t irq) 136 { 137 struct omap_mbox_fifo *fifo = (irq == IRQ_TX) ? 138 &mbox->tx_fifo : &mbox->rx_fifo; 139 u32 bit = fifo->intr_bit; 140 u32 irqstatus = fifo->irqstatus; 141 142 mbox_write_reg(mbox->parent, bit, irqstatus); 143 144 /* Flush posted write for irq status to avoid spurious interrupts */ 145 mbox_read_reg(mbox->parent, irqstatus); 146 } 147 148 static int is_mbox_irq(struct omap_mbox *mbox, omap_mbox_irq_t irq) 149 { 150 struct omap_mbox_fifo *fifo = (irq == IRQ_TX) ? 151 &mbox->tx_fifo : &mbox->rx_fifo; 152 u32 bit = fifo->intr_bit; 153 u32 irqenable = fifo->irqenable; 154 u32 irqstatus = fifo->irqstatus; 155 156 u32 enable = mbox_read_reg(mbox->parent, irqenable); 157 u32 status = mbox_read_reg(mbox->parent, irqstatus); 158 159 return (int)(enable & status & bit); 160 } 161 162 static void omap_mbox_enable_irq(struct omap_mbox *mbox, omap_mbox_irq_t irq) 163 { 164 u32 l; 165 struct omap_mbox_fifo *fifo = (irq == IRQ_TX) ? 166 &mbox->tx_fifo : &mbox->rx_fifo; 167 u32 bit = fifo->intr_bit; 168 u32 irqenable = fifo->irqenable; 169 170 l = mbox_read_reg(mbox->parent, irqenable); 171 l |= bit; 172 mbox_write_reg(mbox->parent, l, irqenable); 173 } 174 175 static void omap_mbox_disable_irq(struct omap_mbox *mbox, omap_mbox_irq_t irq) 176 { 177 struct omap_mbox_fifo *fifo = (irq == IRQ_TX) ? 178 &mbox->tx_fifo : &mbox->rx_fifo; 179 u32 bit = fifo->intr_bit; 180 u32 irqdisable = fifo->irqdisable; 181 182 /* 183 * Read and update the interrupt configuration register for pre-OMAP4. 184 * OMAP4 and later SoCs have a dedicated interrupt disabling register. 185 */ 186 if (!mbox->intr_type) 187 bit = mbox_read_reg(mbox->parent, irqdisable) & ~bit; 188 189 mbox_write_reg(mbox->parent, bit, irqdisable); 190 } 191 192 /* 193 * Mailbox interrupt handler 194 */ 195 static void __mbox_tx_interrupt(struct omap_mbox *mbox) 196 { 197 omap_mbox_disable_irq(mbox, IRQ_TX); 198 ack_mbox_irq(mbox, IRQ_TX); 199 mbox_chan_txdone(mbox->chan, 0); 200 } 201 202 static void __mbox_rx_interrupt(struct omap_mbox *mbox) 203 { 204 u32 msg; 205 206 while (!mbox_fifo_empty(mbox)) { 207 msg = mbox_fifo_read(mbox); 208 mbox_chan_received_data(mbox->chan, (void *)(uintptr_t)msg); 209 } 210 211 /* clear IRQ source. */ 212 ack_mbox_irq(mbox, IRQ_RX); 213 } 214 215 static irqreturn_t mbox_interrupt(int irq, void *p) 216 { 217 struct omap_mbox *mbox = p; 218 219 if (is_mbox_irq(mbox, IRQ_TX)) 220 __mbox_tx_interrupt(mbox); 221 222 if (is_mbox_irq(mbox, IRQ_RX)) 223 __mbox_rx_interrupt(mbox); 224 225 return IRQ_HANDLED; 226 } 227 228 static int omap_mbox_startup(struct omap_mbox *mbox) 229 { 230 int ret = 0; 231 232 ret = request_threaded_irq(mbox->irq, NULL, mbox_interrupt, 233 IRQF_ONESHOT, mbox->name, mbox); 234 if (unlikely(ret)) { 235 pr_err("failed to register mailbox interrupt:%d\n", ret); 236 return ret; 237 } 238 239 if (mbox->send_no_irq) 240 mbox->chan->txdone_method = TXDONE_BY_ACK; 241 242 omap_mbox_enable_irq(mbox, IRQ_RX); 243 244 return 0; 245 } 246 247 static void omap_mbox_fini(struct omap_mbox *mbox) 248 { 249 omap_mbox_disable_irq(mbox, IRQ_RX); 250 free_irq(mbox->irq, mbox); 251 } 252 253 static int omap_mbox_chan_startup(struct mbox_chan *chan) 254 { 255 struct omap_mbox *mbox = chan->con_priv; 256 struct omap_mbox_device *mdev = mbox->parent; 257 int ret = 0; 258 259 mutex_lock(&mdev->cfg_lock); 260 pm_runtime_get_sync(mdev->dev); 261 ret = omap_mbox_startup(mbox); 262 if (ret) 263 pm_runtime_put_sync(mdev->dev); 264 mutex_unlock(&mdev->cfg_lock); 265 return ret; 266 } 267 268 static void omap_mbox_chan_shutdown(struct mbox_chan *chan) 269 { 270 struct omap_mbox *mbox = chan->con_priv; 271 struct omap_mbox_device *mdev = mbox->parent; 272 273 mutex_lock(&mdev->cfg_lock); 274 omap_mbox_fini(mbox); 275 pm_runtime_put_sync(mdev->dev); 276 mutex_unlock(&mdev->cfg_lock); 277 } 278 279 static int omap_mbox_chan_send_noirq(struct omap_mbox *mbox, u32 msg) 280 { 281 if (mbox_fifo_full(mbox)) 282 return -EBUSY; 283 284 omap_mbox_enable_irq(mbox, IRQ_RX); 285 mbox_fifo_write(mbox, msg); 286 omap_mbox_disable_irq(mbox, IRQ_RX); 287 288 /* we must read and ack the interrupt directly from here */ 289 mbox_fifo_read(mbox); 290 ack_mbox_irq(mbox, IRQ_RX); 291 292 return 0; 293 } 294 295 static int omap_mbox_chan_send(struct omap_mbox *mbox, u32 msg) 296 { 297 if (mbox_fifo_full(mbox)) { 298 /* always enable the interrupt */ 299 omap_mbox_enable_irq(mbox, IRQ_TX); 300 return -EBUSY; 301 } 302 303 mbox_fifo_write(mbox, msg); 304 305 /* always enable the interrupt */ 306 omap_mbox_enable_irq(mbox, IRQ_TX); 307 return 0; 308 } 309 310 static int omap_mbox_chan_send_data(struct mbox_chan *chan, void *data) 311 { 312 struct omap_mbox *mbox = chan->con_priv; 313 int ret; 314 u32 msg = (u32)(uintptr_t)(data); 315 316 if (!mbox) 317 return -EINVAL; 318 319 if (mbox->send_no_irq) 320 ret = omap_mbox_chan_send_noirq(mbox, msg); 321 else 322 ret = omap_mbox_chan_send(mbox, msg); 323 324 return ret; 325 } 326 327 static const struct mbox_chan_ops omap_mbox_chan_ops = { 328 .startup = omap_mbox_chan_startup, 329 .send_data = omap_mbox_chan_send_data, 330 .shutdown = omap_mbox_chan_shutdown, 331 }; 332 333 #ifdef CONFIG_PM_SLEEP 334 static int omap_mbox_suspend(struct device *dev) 335 { 336 struct omap_mbox_device *mdev = dev_get_drvdata(dev); 337 u32 usr, fifo, reg; 338 339 if (pm_runtime_status_suspended(dev)) 340 return 0; 341 342 for (fifo = 0; fifo < mdev->num_fifos; fifo++) { 343 if (mbox_read_reg(mdev, MAILBOX_MSGSTATUS(fifo))) { 344 dev_err(mdev->dev, "fifo %d has unexpected unread messages\n", 345 fifo); 346 return -EBUSY; 347 } 348 } 349 350 for (usr = 0; usr < mdev->num_users; usr++) { 351 reg = MAILBOX_IRQENABLE(mdev->intr_type, usr); 352 mdev->irq_ctx[usr] = mbox_read_reg(mdev, reg); 353 } 354 355 return 0; 356 } 357 358 static int omap_mbox_resume(struct device *dev) 359 { 360 struct omap_mbox_device *mdev = dev_get_drvdata(dev); 361 u32 usr, reg; 362 363 if (pm_runtime_status_suspended(dev)) 364 return 0; 365 366 for (usr = 0; usr < mdev->num_users; usr++) { 367 reg = MAILBOX_IRQENABLE(mdev->intr_type, usr); 368 mbox_write_reg(mdev, mdev->irq_ctx[usr], reg); 369 } 370 371 return 0; 372 } 373 #endif 374 375 static const struct dev_pm_ops omap_mbox_pm_ops = { 376 SET_SYSTEM_SLEEP_PM_OPS(omap_mbox_suspend, omap_mbox_resume) 377 }; 378 379 static const struct omap_mbox_match_data omap2_data = { MBOX_INTR_CFG_TYPE1 }; 380 static const struct omap_mbox_match_data omap4_data = { MBOX_INTR_CFG_TYPE2 }; 381 382 static const struct of_device_id omap_mailbox_of_match[] = { 383 { 384 .compatible = "ti,omap2-mailbox", 385 .data = &omap2_data, 386 }, 387 { 388 .compatible = "ti,omap3-mailbox", 389 .data = &omap2_data, 390 }, 391 { 392 .compatible = "ti,omap4-mailbox", 393 .data = &omap4_data, 394 }, 395 { 396 .compatible = "ti,am654-mailbox", 397 .data = &omap4_data, 398 }, 399 { 400 .compatible = "ti,am64-mailbox", 401 .data = &omap4_data, 402 }, 403 { 404 /* end */ 405 }, 406 }; 407 MODULE_DEVICE_TABLE(of, omap_mailbox_of_match); 408 409 static struct mbox_chan *omap_mbox_of_xlate(struct mbox_controller *controller, 410 const struct of_phandle_args *sp) 411 { 412 phandle phandle = sp->args[0]; 413 struct device_node *node; 414 struct omap_mbox_device *mdev; 415 struct omap_mbox *mbox; 416 int i; 417 418 mdev = dev_get_drvdata(controller->dev); 419 if (WARN_ON(!mdev)) 420 return ERR_PTR(-EINVAL); 421 422 node = of_find_node_by_phandle(phandle); 423 if (!node) { 424 pr_err("%s: could not find node phandle 0x%x\n", 425 __func__, phandle); 426 return ERR_PTR(-ENODEV); 427 } 428 429 for (i = 0; i < controller->num_chans; i++) { 430 mbox = controller->chans[i].con_priv; 431 if (!strcmp(mbox->name, node->name)) { 432 of_node_put(node); 433 return &controller->chans[i]; 434 } 435 } 436 437 of_node_put(node); 438 return ERR_PTR(-ENOENT); 439 } 440 441 static int omap_mbox_probe(struct platform_device *pdev) 442 { 443 int ret; 444 struct mbox_chan *chnls; 445 struct omap_mbox *mbox; 446 struct omap_mbox_device *mdev; 447 struct omap_mbox_fifo *fifo; 448 struct device_node *node = pdev->dev.of_node; 449 struct device_node *child; 450 const struct omap_mbox_match_data *match_data; 451 struct mbox_controller *controller; 452 u32 intr_type, info_count; 453 u32 num_users, num_fifos; 454 u32 tmp[3]; 455 u32 l; 456 int i; 457 458 if (!node) { 459 pr_err("%s: only DT-based devices are supported\n", __func__); 460 return -ENODEV; 461 } 462 463 match_data = of_device_get_match_data(&pdev->dev); 464 if (!match_data) 465 return -ENODEV; 466 intr_type = match_data->intr_type; 467 468 if (of_property_read_u32(node, "ti,mbox-num-users", &num_users)) 469 return -ENODEV; 470 471 if (of_property_read_u32(node, "ti,mbox-num-fifos", &num_fifos)) 472 return -ENODEV; 473 474 info_count = of_get_available_child_count(node); 475 if (!info_count) { 476 dev_err(&pdev->dev, "no available mbox devices found\n"); 477 return -ENODEV; 478 } 479 480 mdev = devm_kzalloc(&pdev->dev, sizeof(*mdev), GFP_KERNEL); 481 if (!mdev) 482 return -ENOMEM; 483 484 mdev->mbox_base = devm_platform_ioremap_resource(pdev, 0); 485 if (IS_ERR(mdev->mbox_base)) 486 return PTR_ERR(mdev->mbox_base); 487 488 mdev->irq_ctx = devm_kcalloc(&pdev->dev, num_users, sizeof(u32), 489 GFP_KERNEL); 490 if (!mdev->irq_ctx) 491 return -ENOMEM; 492 493 chnls = devm_kcalloc(&pdev->dev, info_count + 1, sizeof(*chnls), 494 GFP_KERNEL); 495 if (!chnls) 496 return -ENOMEM; 497 498 child = NULL; 499 for (i = 0; i < info_count; i++) { 500 int tx_id, tx_irq, tx_usr; 501 int rx_id, rx_usr; 502 503 mbox = devm_kzalloc(&pdev->dev, sizeof(*mbox), GFP_KERNEL); 504 if (!mbox) 505 return -ENOMEM; 506 507 child = of_get_next_available_child(node, child); 508 ret = of_property_read_u32_array(child, "ti,mbox-tx", tmp, 509 ARRAY_SIZE(tmp)); 510 if (ret) 511 return ret; 512 tx_id = tmp[0]; 513 tx_irq = tmp[1]; 514 tx_usr = tmp[2]; 515 516 ret = of_property_read_u32_array(child, "ti,mbox-rx", tmp, 517 ARRAY_SIZE(tmp)); 518 if (ret) 519 return ret; 520 rx_id = tmp[0]; 521 /* rx_irq = tmp[1]; */ 522 rx_usr = tmp[2]; 523 524 if (tx_id >= num_fifos || rx_id >= num_fifos || 525 tx_usr >= num_users || rx_usr >= num_users) 526 return -EINVAL; 527 528 fifo = &mbox->tx_fifo; 529 fifo->msg = MAILBOX_MESSAGE(tx_id); 530 fifo->fifo_stat = MAILBOX_FIFOSTATUS(tx_id); 531 fifo->intr_bit = MAILBOX_IRQ_NOTFULL(tx_id); 532 fifo->irqenable = MAILBOX_IRQENABLE(intr_type, tx_usr); 533 fifo->irqstatus = MAILBOX_IRQSTATUS(intr_type, tx_usr); 534 fifo->irqdisable = MAILBOX_IRQDISABLE(intr_type, tx_usr); 535 536 fifo = &mbox->rx_fifo; 537 fifo->msg = MAILBOX_MESSAGE(rx_id); 538 fifo->msg_stat = MAILBOX_MSGSTATUS(rx_id); 539 fifo->intr_bit = MAILBOX_IRQ_NEWMSG(rx_id); 540 fifo->irqenable = MAILBOX_IRQENABLE(intr_type, rx_usr); 541 fifo->irqstatus = MAILBOX_IRQSTATUS(intr_type, rx_usr); 542 fifo->irqdisable = MAILBOX_IRQDISABLE(intr_type, rx_usr); 543 544 mbox->send_no_irq = of_property_read_bool(child, "ti,mbox-send-noirq"); 545 mbox->intr_type = intr_type; 546 547 mbox->parent = mdev; 548 mbox->name = child->name; 549 mbox->irq = platform_get_irq(pdev, tx_irq); 550 if (mbox->irq < 0) 551 return mbox->irq; 552 mbox->chan = &chnls[i]; 553 chnls[i].con_priv = mbox; 554 } 555 556 mutex_init(&mdev->cfg_lock); 557 mdev->dev = &pdev->dev; 558 mdev->num_users = num_users; 559 mdev->num_fifos = num_fifos; 560 mdev->intr_type = intr_type; 561 562 controller = devm_kzalloc(&pdev->dev, sizeof(*controller), GFP_KERNEL); 563 if (!controller) 564 return -ENOMEM; 565 /* 566 * OMAP/K3 Mailbox IP does not have a Tx-Done IRQ, but rather a Tx-Ready 567 * IRQ and is needed to run the Tx state machine 568 */ 569 controller->txdone_irq = true; 570 controller->dev = mdev->dev; 571 controller->ops = &omap_mbox_chan_ops; 572 controller->chans = chnls; 573 controller->num_chans = info_count; 574 controller->of_xlate = omap_mbox_of_xlate; 575 ret = devm_mbox_controller_register(mdev->dev, controller); 576 if (ret) 577 return ret; 578 579 platform_set_drvdata(pdev, mdev); 580 devm_pm_runtime_enable(mdev->dev); 581 582 ret = pm_runtime_resume_and_get(mdev->dev); 583 if (ret < 0) 584 return ret; 585 586 /* 587 * just print the raw revision register, the format is not 588 * uniform across all SoCs 589 */ 590 l = mbox_read_reg(mdev, MAILBOX_REVISION); 591 dev_info(mdev->dev, "omap mailbox rev 0x%x\n", l); 592 593 ret = pm_runtime_put_sync(mdev->dev); 594 if (ret < 0 && ret != -ENOSYS) 595 return ret; 596 597 return 0; 598 } 599 600 static struct platform_driver omap_mbox_driver = { 601 .probe = omap_mbox_probe, 602 .driver = { 603 .name = "omap-mailbox", 604 .pm = &omap_mbox_pm_ops, 605 .of_match_table = of_match_ptr(omap_mailbox_of_match), 606 }, 607 }; 608 module_platform_driver(omap_mbox_driver); 609 610 MODULE_LICENSE("GPL v2"); 611 MODULE_DESCRIPTION("omap mailbox: interrupt driven messaging"); 612 MODULE_AUTHOR("Toshihiro Kobayashi"); 613 MODULE_AUTHOR("Hiroshi DOYU"); 614