1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (c) 2018 Pengutronix, Oleksij Rempel <o.rempel@pengutronix.de> 4 * Copyright 2022 NXP, Peng Fan <peng.fan@nxp.com> 5 */ 6 7 #include <linux/bitfield.h> 8 #include <linux/clk.h> 9 #include <linux/firmware/imx/ipc.h> 10 #include <linux/firmware/imx/s4.h> 11 #include <linux/interrupt.h> 12 #include <linux/io.h> 13 #include <linux/iopoll.h> 14 #include <linux/jiffies.h> 15 #include <linux/kernel.h> 16 #include <linux/mailbox_controller.h> 17 #include <linux/module.h> 18 #include <linux/of.h> 19 #include <linux/of_platform.h> 20 #include <linux/platform_device.h> 21 #include <linux/pm_runtime.h> 22 #include <linux/suspend.h> 23 #include <linux/slab.h> 24 #include <linux/workqueue.h> 25 26 #define IMX_MU_CHANS 24 27 /* TX0/RX0/RXDB[0-3] */ 28 #define IMX_MU_SCU_CHANS 6 29 /* TX0/RX0 */ 30 #define IMX_MU_S4_CHANS 2 31 #define IMX_MU_CHAN_NAME_SIZE 32 32 33 #define IMX_MU_V2_PAR_OFF 0x4 34 #define IMX_MU_V2_TR_MASK GENMASK(7, 0) 35 #define IMX_MU_V2_RR_MASK GENMASK(15, 8) 36 37 #define IMX_MU_SECO_TX_TOUT (msecs_to_jiffies(3000)) 38 #define IMX_MU_SECO_RX_TOUT (msecs_to_jiffies(3000)) 39 40 /* Please not change TX & RX */ 41 enum imx_mu_chan_type { 42 IMX_MU_TYPE_TX = 0, /* Tx */ 43 IMX_MU_TYPE_RX = 1, /* Rx */ 44 IMX_MU_TYPE_TXDB = 2, /* Tx doorbell */ 45 IMX_MU_TYPE_RXDB = 3, /* Rx doorbell */ 46 IMX_MU_TYPE_RST = 4, /* Reset */ 47 IMX_MU_TYPE_TXDB_V2 = 5, /* Tx doorbell with S/W ACK */ 48 }; 49 50 enum imx_mu_xcr { 51 IMX_MU_CR, 52 IMX_MU_GIER, 53 IMX_MU_GCR, 54 IMX_MU_TCR, 55 IMX_MU_RCR, 56 IMX_MU_xCR_MAX, 57 }; 58 59 enum imx_mu_xsr { 60 IMX_MU_SR, 61 IMX_MU_GSR, 62 IMX_MU_TSR, 63 IMX_MU_RSR, 64 IMX_MU_xSR_MAX, 65 }; 66 67 struct imx_sc_rpc_msg_max { 68 struct imx_sc_rpc_msg hdr; 69 u32 data[30]; 70 }; 71 72 struct imx_s4_rpc_msg_max { 73 struct imx_s4_rpc_msg hdr; 74 u32 data[254]; 75 }; 76 77 struct imx_mu_con_priv { 78 unsigned int idx; 79 char irq_desc[IMX_MU_CHAN_NAME_SIZE]; 80 enum imx_mu_chan_type type; 81 struct mbox_chan *chan; 82 struct work_struct txdb_work; 83 }; 84 85 struct imx_mu_priv { 86 struct device *dev; 87 void __iomem *base; 88 void *msg; 89 spinlock_t xcr_lock; /* control register lock */ 90 91 struct mbox_controller mbox; 92 struct mbox_chan mbox_chans[IMX_MU_CHANS]; 93 94 struct imx_mu_con_priv con_priv[IMX_MU_CHANS]; 95 const struct imx_mu_dcfg *dcfg; 96 struct clk *clk; 97 int irq[IMX_MU_CHANS]; 98 bool suspend; 99 bool side_b; 100 101 u32 xcr[IMX_MU_xCR_MAX]; 102 u32 num_tr; 103 u32 num_rr; 104 }; 105 106 enum imx_mu_type { 107 IMX_MU_V1, 108 IMX_MU_V2 = BIT(1), 109 IMX_MU_V2_S4 = BIT(15), 110 IMX_MU_V2_IRQ = BIT(16), 111 }; 112 113 struct imx_mu_dcfg { 114 int (*tx)(struct imx_mu_priv *priv, struct imx_mu_con_priv *cp, void *data); 115 int (*rx)(struct imx_mu_priv *priv, struct imx_mu_con_priv *cp); 116 int (*rxdb)(struct imx_mu_priv *priv, struct imx_mu_con_priv *cp); 117 int (*init)(struct imx_mu_priv *priv); 118 enum imx_mu_type type; 119 u32 xTR; /* Transmit Register0 */ 120 u32 xRR; /* Receive Register0 */ 121 u32 xSR[IMX_MU_xSR_MAX]; /* Status Registers */ 122 u32 xCR[IMX_MU_xCR_MAX]; /* Control Registers */ 123 bool skip_suspend_flag; 124 }; 125 126 #define IMX_MU_xSR_GIPn(type, x) (type & IMX_MU_V2 ? BIT(x) : BIT(28 + (3 - (x)))) 127 #define IMX_MU_xSR_RFn(type, x) (type & IMX_MU_V2 ? BIT(x) : BIT(24 + (3 - (x)))) 128 #define IMX_MU_xSR_TEn(type, x) (type & IMX_MU_V2 ? BIT(x) : BIT(20 + (3 - (x)))) 129 130 /* General Purpose Interrupt Enable */ 131 #define IMX_MU_xCR_GIEn(type, x) (type & IMX_MU_V2 ? BIT(x) : BIT(28 + (3 - (x)))) 132 /* Receive Interrupt Enable */ 133 #define IMX_MU_xCR_RIEn(type, x) (type & IMX_MU_V2 ? BIT(x) : BIT(24 + (3 - (x)))) 134 /* Transmit Interrupt Enable */ 135 #define IMX_MU_xCR_TIEn(type, x) (type & IMX_MU_V2 ? BIT(x) : BIT(20 + (3 - (x)))) 136 /* General Purpose Interrupt Request */ 137 #define IMX_MU_xCR_GIRn(type, x) (type & IMX_MU_V2 ? BIT(x) : BIT(16 + (3 - (x)))) 138 /* MU reset */ 139 #define IMX_MU_xCR_RST(type) (type & IMX_MU_V2 ? BIT(0) : BIT(5)) 140 #define IMX_MU_xSR_RST(type) (type & IMX_MU_V2 ? BIT(0) : BIT(7)) 141 142 143 static struct imx_mu_priv *to_imx_mu_priv(struct mbox_controller *mbox) 144 { 145 return container_of(mbox, struct imx_mu_priv, mbox); 146 } 147 148 static void imx_mu_write(struct imx_mu_priv *priv, u32 val, u32 offs) 149 { 150 iowrite32(val, priv->base + offs); 151 } 152 153 static u32 imx_mu_read(struct imx_mu_priv *priv, u32 offs) 154 { 155 return ioread32(priv->base + offs); 156 } 157 158 static int imx_mu_tx_waiting_write(struct imx_mu_priv *priv, u32 val, u32 idx) 159 { 160 u64 timeout_time = get_jiffies_64() + IMX_MU_SECO_TX_TOUT; 161 u32 status; 162 u32 can_write; 163 164 dev_dbg(priv->dev, "Trying to write %.8x to idx %d\n", val, idx); 165 166 do { 167 status = imx_mu_read(priv, priv->dcfg->xSR[IMX_MU_TSR]); 168 can_write = status & IMX_MU_xSR_TEn(priv->dcfg->type, idx % 4); 169 } while (!can_write && time_is_after_jiffies64(timeout_time)); 170 171 if (!can_write) { 172 dev_err(priv->dev, "timeout trying to write %.8x at %d(%.8x)\n", 173 val, idx, status); 174 return -ETIME; 175 } 176 177 imx_mu_write(priv, val, priv->dcfg->xTR + (idx % 4) * 4); 178 179 return 0; 180 } 181 182 static int imx_mu_rx_waiting_read(struct imx_mu_priv *priv, u32 *val, u32 idx) 183 { 184 u64 timeout_time = get_jiffies_64() + IMX_MU_SECO_RX_TOUT; 185 u32 status; 186 u32 can_read; 187 188 dev_dbg(priv->dev, "Trying to read from idx %d\n", idx); 189 190 do { 191 status = imx_mu_read(priv, priv->dcfg->xSR[IMX_MU_RSR]); 192 can_read = status & IMX_MU_xSR_RFn(priv->dcfg->type, idx % 4); 193 } while (!can_read && time_is_after_jiffies64(timeout_time)); 194 195 if (!can_read) { 196 dev_err(priv->dev, "timeout trying to read idx %d (%.8x)\n", 197 idx, status); 198 return -ETIME; 199 } 200 201 *val = imx_mu_read(priv, priv->dcfg->xRR + (idx % 4) * 4); 202 dev_dbg(priv->dev, "Read %.8x\n", *val); 203 204 return 0; 205 } 206 207 static u32 imx_mu_xcr_rmw(struct imx_mu_priv *priv, enum imx_mu_xcr type, u32 set, u32 clr) 208 { 209 unsigned long flags; 210 u32 val; 211 212 spin_lock_irqsave(&priv->xcr_lock, flags); 213 val = imx_mu_read(priv, priv->dcfg->xCR[type]); 214 val &= ~clr; 215 val |= set; 216 imx_mu_write(priv, val, priv->dcfg->xCR[type]); 217 spin_unlock_irqrestore(&priv->xcr_lock, flags); 218 219 return val; 220 } 221 222 static int imx_mu_generic_tx(struct imx_mu_priv *priv, 223 struct imx_mu_con_priv *cp, 224 void *data) 225 { 226 u32 *arg = data; 227 u32 val; 228 int ret, count; 229 230 switch (cp->type) { 231 case IMX_MU_TYPE_TX: 232 imx_mu_write(priv, *arg, priv->dcfg->xTR + cp->idx * 4); 233 imx_mu_xcr_rmw(priv, IMX_MU_TCR, IMX_MU_xCR_TIEn(priv->dcfg->type, cp->idx), 0); 234 break; 235 case IMX_MU_TYPE_TXDB: 236 imx_mu_xcr_rmw(priv, IMX_MU_GCR, IMX_MU_xCR_GIRn(priv->dcfg->type, cp->idx), 0); 237 queue_work(system_bh_wq, &cp->txdb_work); 238 break; 239 case IMX_MU_TYPE_TXDB_V2: 240 imx_mu_write(priv, IMX_MU_xCR_GIRn(priv->dcfg->type, cp->idx), 241 priv->dcfg->xCR[IMX_MU_GCR]); 242 ret = -ETIMEDOUT; 243 count = 0; 244 while (ret && (count < 10)) { 245 ret = 246 readl_poll_timeout(priv->base + priv->dcfg->xCR[IMX_MU_GCR], val, 247 !(val & IMX_MU_xCR_GIRn(priv->dcfg->type, cp->idx)), 248 0, 10000); 249 250 if (ret) { 251 dev_warn_ratelimited(priv->dev, 252 "channel type: %d timeout, %d times, retry\n", 253 cp->type, ++count); 254 } 255 } 256 break; 257 default: 258 dev_warn_ratelimited(priv->dev, "Send data on wrong channel type: %d\n", cp->type); 259 return -EINVAL; 260 } 261 262 return 0; 263 } 264 265 static int imx_mu_generic_rx(struct imx_mu_priv *priv, 266 struct imx_mu_con_priv *cp) 267 { 268 u32 dat; 269 270 dat = imx_mu_read(priv, priv->dcfg->xRR + (cp->idx) * 4); 271 mbox_chan_received_data(cp->chan, (void *)&dat); 272 273 return 0; 274 } 275 276 static int imx_mu_generic_rxdb(struct imx_mu_priv *priv, 277 struct imx_mu_con_priv *cp) 278 { 279 imx_mu_write(priv, IMX_MU_xSR_GIPn(priv->dcfg->type, cp->idx), 280 priv->dcfg->xSR[IMX_MU_GSR]); 281 mbox_chan_received_data(cp->chan, NULL); 282 283 return 0; 284 } 285 286 static int imx_mu_specific_tx(struct imx_mu_priv *priv, struct imx_mu_con_priv *cp, void *data) 287 { 288 u32 *arg = data; 289 u32 num_tr = priv->num_tr; 290 int i, ret; 291 u32 xsr; 292 u32 size, max_size; 293 294 if (priv->dcfg->type & IMX_MU_V2_S4) { 295 size = ((struct imx_s4_rpc_msg_max *)data)->hdr.size; 296 max_size = sizeof(struct imx_s4_rpc_msg_max); 297 } else { 298 size = ((struct imx_sc_rpc_msg_max *)data)->hdr.size; 299 max_size = sizeof(struct imx_sc_rpc_msg_max); 300 } 301 302 switch (cp->type) { 303 case IMX_MU_TYPE_TX: 304 /* 305 * msg->hdr.size specifies the number of u32 words while 306 * sizeof yields bytes. 307 */ 308 309 if (size > max_size / 4) { 310 /* 311 * The real message size can be different to 312 * struct imx_sc_rpc_msg_max/imx_s4_rpc_msg_max size 313 */ 314 dev_err(priv->dev, "Maximal message size (%u bytes) exceeded on TX; got: %i bytes\n", max_size, size << 2); 315 return -EINVAL; 316 } 317 318 for (i = 0; i < num_tr && i < size; i++) 319 imx_mu_write(priv, *arg++, priv->dcfg->xTR + (i % num_tr) * 4); 320 for (; i < size; i++) { 321 ret = readl_poll_timeout(priv->base + priv->dcfg->xSR[IMX_MU_TSR], 322 xsr, 323 xsr & IMX_MU_xSR_TEn(priv->dcfg->type, i % num_tr), 324 0, 5 * USEC_PER_SEC); 325 if (ret) { 326 dev_err(priv->dev, "Send data index: %d timeout\n", i); 327 return ret; 328 } 329 imx_mu_write(priv, *arg++, priv->dcfg->xTR + (i % num_tr) * 4); 330 } 331 332 imx_mu_xcr_rmw(priv, IMX_MU_TCR, IMX_MU_xCR_TIEn(priv->dcfg->type, cp->idx), 0); 333 break; 334 default: 335 dev_warn_ratelimited(priv->dev, "Send data on wrong channel type: %d\n", cp->type); 336 return -EINVAL; 337 } 338 339 return 0; 340 } 341 342 static int imx_mu_specific_rx(struct imx_mu_priv *priv, struct imx_mu_con_priv *cp) 343 { 344 u32 *data; 345 int i, ret; 346 u32 xsr; 347 u32 size, max_size; 348 u32 num_rr = priv->num_rr; 349 350 data = (u32 *)priv->msg; 351 352 imx_mu_xcr_rmw(priv, IMX_MU_RCR, 0, IMX_MU_xCR_RIEn(priv->dcfg->type, 0)); 353 *data++ = imx_mu_read(priv, priv->dcfg->xRR); 354 355 if (priv->dcfg->type & IMX_MU_V2_S4) { 356 size = ((struct imx_s4_rpc_msg_max *)priv->msg)->hdr.size; 357 max_size = sizeof(struct imx_s4_rpc_msg_max); 358 } else { 359 size = ((struct imx_sc_rpc_msg_max *)priv->msg)->hdr.size; 360 max_size = sizeof(struct imx_sc_rpc_msg_max); 361 } 362 363 if (size > max_size / 4) { 364 dev_err(priv->dev, "Maximal message size (%u bytes) exceeded on RX; got: %i bytes\n", max_size, size << 2); 365 return -EINVAL; 366 } 367 368 for (i = 1; i < size; i++) { 369 ret = readl_poll_timeout(priv->base + priv->dcfg->xSR[IMX_MU_RSR], xsr, 370 xsr & IMX_MU_xSR_RFn(priv->dcfg->type, i % num_rr), 0, 371 5 * USEC_PER_SEC); 372 if (ret) { 373 dev_err(priv->dev, "timeout read idx %d\n", i); 374 return ret; 375 } 376 *data++ = imx_mu_read(priv, priv->dcfg->xRR + (i % num_rr) * 4); 377 } 378 379 imx_mu_xcr_rmw(priv, IMX_MU_RCR, IMX_MU_xCR_RIEn(priv->dcfg->type, 0), 0); 380 mbox_chan_received_data(cp->chan, (void *)priv->msg); 381 382 return 0; 383 } 384 385 static int imx_mu_seco_tx(struct imx_mu_priv *priv, struct imx_mu_con_priv *cp, 386 void *data) 387 { 388 struct imx_sc_rpc_msg_max *msg = data; 389 u32 *arg = data; 390 u32 byte_size; 391 int err; 392 int i; 393 394 dev_dbg(priv->dev, "Sending message\n"); 395 396 switch (cp->type) { 397 case IMX_MU_TYPE_TXDB: 398 byte_size = msg->hdr.size * sizeof(u32); 399 if (byte_size > sizeof(*msg)) { 400 /* 401 * The real message size can be different to 402 * struct imx_sc_rpc_msg_max size 403 */ 404 dev_err(priv->dev, 405 "Exceed max msg size (%zu) on TX, got: %i\n", 406 sizeof(*msg), byte_size); 407 return -EINVAL; 408 } 409 410 print_hex_dump_debug("from client ", DUMP_PREFIX_OFFSET, 4, 4, 411 data, byte_size, false); 412 413 /* Send first word */ 414 dev_dbg(priv->dev, "Sending header\n"); 415 imx_mu_write(priv, *arg++, priv->dcfg->xTR); 416 417 /* Send signaling */ 418 dev_dbg(priv->dev, "Sending signaling\n"); 419 imx_mu_xcr_rmw(priv, IMX_MU_GCR, 420 IMX_MU_xCR_GIRn(priv->dcfg->type, cp->idx), 0); 421 422 /* Send words to fill the mailbox */ 423 for (i = 1; i < 4 && i < msg->hdr.size; i++) { 424 dev_dbg(priv->dev, "Sending word %d\n", i); 425 imx_mu_write(priv, *arg++, 426 priv->dcfg->xTR + (i % 4) * 4); 427 } 428 429 /* Send rest of message waiting for remote read */ 430 for (; i < msg->hdr.size; i++) { 431 dev_dbg(priv->dev, "Sending word %d\n", i); 432 err = imx_mu_tx_waiting_write(priv, *arg++, i); 433 if (err) { 434 dev_err(priv->dev, "Timeout tx %d\n", i); 435 return err; 436 } 437 } 438 439 /* Simulate hack for mbox framework */ 440 queue_work(system_bh_wq, &cp->txdb_work); 441 442 break; 443 default: 444 dev_warn_ratelimited(priv->dev, 445 "Send data on wrong channel type: %d\n", 446 cp->type); 447 return -EINVAL; 448 } 449 450 return 0; 451 } 452 453 static int imx_mu_seco_rxdb(struct imx_mu_priv *priv, struct imx_mu_con_priv *cp) 454 { 455 struct imx_sc_rpc_msg_max msg; 456 u32 *data = (u32 *)&msg; 457 u32 byte_size; 458 int err = 0; 459 int i; 460 461 dev_dbg(priv->dev, "Receiving message\n"); 462 463 /* Read header */ 464 dev_dbg(priv->dev, "Receiving header\n"); 465 *data++ = imx_mu_read(priv, priv->dcfg->xRR); 466 byte_size = msg.hdr.size * sizeof(u32); 467 if (byte_size > sizeof(msg)) { 468 dev_err(priv->dev, "Exceed max msg size (%zu) on RX, got: %i\n", 469 sizeof(msg), byte_size); 470 err = -EINVAL; 471 goto error; 472 } 473 474 /* Read message waiting they are written */ 475 for (i = 1; i < msg.hdr.size; i++) { 476 dev_dbg(priv->dev, "Receiving word %d\n", i); 477 err = imx_mu_rx_waiting_read(priv, data++, i); 478 if (err) { 479 dev_err(priv->dev, "Timeout rx %d\n", i); 480 goto error; 481 } 482 } 483 484 /* Clear GIP */ 485 imx_mu_write(priv, IMX_MU_xSR_GIPn(priv->dcfg->type, cp->idx), 486 priv->dcfg->xSR[IMX_MU_GSR]); 487 488 print_hex_dump_debug("to client ", DUMP_PREFIX_OFFSET, 4, 4, 489 &msg, byte_size, false); 490 491 /* send data to client */ 492 dev_dbg(priv->dev, "Sending message to client\n"); 493 mbox_chan_received_data(cp->chan, (void *)&msg); 494 495 goto exit; 496 497 error: 498 mbox_chan_received_data(cp->chan, ERR_PTR(err)); 499 500 exit: 501 return err; 502 } 503 504 static void imx_mu_txdb_work(struct work_struct *t) 505 { 506 struct imx_mu_con_priv *cp = from_work(cp, t, txdb_work); 507 508 mbox_chan_txdone(cp->chan, 0); 509 } 510 511 static irqreturn_t imx_mu_isr(int irq, void *p) 512 { 513 struct mbox_chan *chan = p; 514 struct imx_mu_priv *priv = to_imx_mu_priv(chan->mbox); 515 struct imx_mu_con_priv *cp = chan->con_priv; 516 u32 val, ctrl; 517 518 switch (cp->type) { 519 case IMX_MU_TYPE_TX: 520 ctrl = imx_mu_read(priv, priv->dcfg->xCR[IMX_MU_TCR]); 521 val = imx_mu_read(priv, priv->dcfg->xSR[IMX_MU_TSR]); 522 val &= IMX_MU_xSR_TEn(priv->dcfg->type, cp->idx) & 523 (ctrl & IMX_MU_xCR_TIEn(priv->dcfg->type, cp->idx)); 524 break; 525 case IMX_MU_TYPE_RX: 526 ctrl = imx_mu_read(priv, priv->dcfg->xCR[IMX_MU_RCR]); 527 val = imx_mu_read(priv, priv->dcfg->xSR[IMX_MU_RSR]); 528 val &= IMX_MU_xSR_RFn(priv->dcfg->type, cp->idx) & 529 (ctrl & IMX_MU_xCR_RIEn(priv->dcfg->type, cp->idx)); 530 break; 531 case IMX_MU_TYPE_RXDB: 532 ctrl = imx_mu_read(priv, priv->dcfg->xCR[IMX_MU_GIER]); 533 val = imx_mu_read(priv, priv->dcfg->xSR[IMX_MU_GSR]); 534 val &= IMX_MU_xSR_GIPn(priv->dcfg->type, cp->idx) & 535 (ctrl & IMX_MU_xCR_GIEn(priv->dcfg->type, cp->idx)); 536 break; 537 case IMX_MU_TYPE_RST: 538 return IRQ_NONE; 539 default: 540 dev_warn_ratelimited(priv->dev, "Unhandled channel type %d\n", 541 cp->type); 542 return IRQ_NONE; 543 } 544 545 if (!val) 546 return IRQ_NONE; 547 548 if ((val == IMX_MU_xSR_TEn(priv->dcfg->type, cp->idx)) && 549 (cp->type == IMX_MU_TYPE_TX)) { 550 imx_mu_xcr_rmw(priv, IMX_MU_TCR, 0, IMX_MU_xCR_TIEn(priv->dcfg->type, cp->idx)); 551 mbox_chan_txdone(chan, 0); 552 } else if ((val == IMX_MU_xSR_RFn(priv->dcfg->type, cp->idx)) && 553 (cp->type == IMX_MU_TYPE_RX)) { 554 priv->dcfg->rx(priv, cp); 555 } else if ((val == IMX_MU_xSR_GIPn(priv->dcfg->type, cp->idx)) && 556 (cp->type == IMX_MU_TYPE_RXDB)) { 557 priv->dcfg->rxdb(priv, cp); 558 } else { 559 dev_warn_ratelimited(priv->dev, "Not handled interrupt\n"); 560 return IRQ_NONE; 561 } 562 563 if (priv->suspend) 564 pm_system_wakeup(); 565 566 return IRQ_HANDLED; 567 } 568 569 static int imx_mu_send_data(struct mbox_chan *chan, void *data) 570 { 571 struct imx_mu_priv *priv = to_imx_mu_priv(chan->mbox); 572 struct imx_mu_con_priv *cp = chan->con_priv; 573 574 return priv->dcfg->tx(priv, cp, data); 575 } 576 577 static int imx_mu_startup(struct mbox_chan *chan) 578 { 579 struct imx_mu_priv *priv = to_imx_mu_priv(chan->mbox); 580 struct imx_mu_con_priv *cp = chan->con_priv; 581 unsigned long irq_flag = 0; 582 int ret; 583 584 pm_runtime_get_sync(priv->dev); 585 if (cp->type == IMX_MU_TYPE_TXDB_V2) 586 return 0; 587 588 if (cp->type == IMX_MU_TYPE_TXDB) { 589 /* Tx doorbell don't have ACK support */ 590 INIT_WORK(&cp->txdb_work, imx_mu_txdb_work); 591 return 0; 592 } 593 594 /* IPC MU should be with IRQF_NO_SUSPEND set */ 595 if (!priv->dev->pm_domain) 596 irq_flag |= IRQF_NO_SUSPEND; 597 598 if (!(priv->dcfg->type & IMX_MU_V2_IRQ)) 599 irq_flag |= IRQF_SHARED; 600 601 ret = request_irq(priv->irq[cp->type], imx_mu_isr, irq_flag, cp->irq_desc, chan); 602 if (ret) { 603 dev_err(priv->dev, "Unable to acquire IRQ %d\n", priv->irq[cp->type]); 604 return ret; 605 } 606 607 switch (cp->type) { 608 case IMX_MU_TYPE_RX: 609 imx_mu_xcr_rmw(priv, IMX_MU_RCR, IMX_MU_xCR_RIEn(priv->dcfg->type, cp->idx), 0); 610 break; 611 case IMX_MU_TYPE_RXDB: 612 imx_mu_xcr_rmw(priv, IMX_MU_GIER, IMX_MU_xCR_GIEn(priv->dcfg->type, cp->idx), 0); 613 break; 614 default: 615 break; 616 } 617 618 return 0; 619 } 620 621 static void imx_mu_shutdown(struct mbox_chan *chan) 622 { 623 struct imx_mu_priv *priv = to_imx_mu_priv(chan->mbox); 624 struct imx_mu_con_priv *cp = chan->con_priv; 625 int ret; 626 u32 sr; 627 628 if (cp->type == IMX_MU_TYPE_TXDB_V2) { 629 pm_runtime_put_sync(priv->dev); 630 return; 631 } 632 633 if (cp->type == IMX_MU_TYPE_TXDB) { 634 cancel_work_sync(&cp->txdb_work); 635 pm_runtime_put_sync(priv->dev); 636 return; 637 } 638 639 switch (cp->type) { 640 case IMX_MU_TYPE_TX: 641 imx_mu_xcr_rmw(priv, IMX_MU_TCR, 0, IMX_MU_xCR_TIEn(priv->dcfg->type, cp->idx)); 642 break; 643 case IMX_MU_TYPE_RX: 644 imx_mu_xcr_rmw(priv, IMX_MU_RCR, 0, IMX_MU_xCR_RIEn(priv->dcfg->type, cp->idx)); 645 break; 646 case IMX_MU_TYPE_RXDB: 647 imx_mu_xcr_rmw(priv, IMX_MU_GIER, 0, IMX_MU_xCR_GIEn(priv->dcfg->type, cp->idx)); 648 break; 649 case IMX_MU_TYPE_RST: 650 imx_mu_xcr_rmw(priv, IMX_MU_CR, IMX_MU_xCR_RST(priv->dcfg->type), 0); 651 ret = readl_poll_timeout(priv->base + priv->dcfg->xSR[IMX_MU_SR], sr, 652 !(sr & IMX_MU_xSR_RST(priv->dcfg->type)), 1, 5); 653 if (ret) 654 dev_warn(priv->dev, "RST channel timeout\n"); 655 break; 656 default: 657 break; 658 } 659 660 free_irq(priv->irq[cp->type], chan); 661 pm_runtime_put_sync(priv->dev); 662 } 663 664 static const struct mbox_chan_ops imx_mu_ops = { 665 .send_data = imx_mu_send_data, 666 .startup = imx_mu_startup, 667 .shutdown = imx_mu_shutdown, 668 }; 669 670 static struct mbox_chan *imx_mu_specific_xlate(struct mbox_controller *mbox, 671 const struct of_phandle_args *sp) 672 { 673 u32 type, idx, chan; 674 675 if (sp->args_count != 2) { 676 dev_err(mbox->dev, "Invalid argument count %d\n", sp->args_count); 677 return ERR_PTR(-EINVAL); 678 } 679 680 type = sp->args[0]; /* channel type */ 681 idx = sp->args[1]; /* index */ 682 683 switch (type) { 684 case IMX_MU_TYPE_TX: 685 case IMX_MU_TYPE_RX: 686 if (idx != 0) 687 dev_err(mbox->dev, "Invalid chan idx: %d\n", idx); 688 chan = type; 689 break; 690 case IMX_MU_TYPE_RXDB: 691 chan = 2 + idx; 692 break; 693 default: 694 dev_err(mbox->dev, "Invalid chan type: %d\n", type); 695 return ERR_PTR(-EINVAL); 696 } 697 698 if (chan >= mbox->num_chans) { 699 dev_err(mbox->dev, "Not supported channel number: %d. (type: %d, idx: %d)\n", chan, type, idx); 700 return ERR_PTR(-EINVAL); 701 } 702 703 return &mbox->chans[chan]; 704 } 705 706 static struct mbox_chan * imx_mu_xlate(struct mbox_controller *mbox, 707 const struct of_phandle_args *sp) 708 { 709 struct mbox_chan *p_chan; 710 u32 type, idx, chan; 711 712 if (sp->args_count != 2) { 713 dev_err(mbox->dev, "Invalid argument count %d\n", sp->args_count); 714 return ERR_PTR(-EINVAL); 715 } 716 717 type = sp->args[0]; /* channel type */ 718 idx = sp->args[1]; /* index */ 719 720 /* RST only supports 1 channel */ 721 if ((type == IMX_MU_TYPE_RST) && idx) { 722 dev_err(mbox->dev, "Invalid RST channel %d\n", idx); 723 return ERR_PTR(-EINVAL); 724 } 725 726 chan = type * 4 + idx; 727 if (chan >= mbox->num_chans) { 728 dev_err(mbox->dev, "Not supported channel number: %d. (type: %d, idx: %d)\n", chan, type, idx); 729 return ERR_PTR(-EINVAL); 730 } 731 732 p_chan = &mbox->chans[chan]; 733 734 if (type == IMX_MU_TYPE_TXDB_V2) 735 p_chan->txdone_method = MBOX_TXDONE_BY_ACK; 736 737 return p_chan; 738 } 739 740 static struct mbox_chan *imx_mu_seco_xlate(struct mbox_controller *mbox, 741 const struct of_phandle_args *sp) 742 { 743 u32 type; 744 745 if (sp->args_count < 1) { 746 dev_err(mbox->dev, "Invalid argument count %d\n", sp->args_count); 747 return ERR_PTR(-EINVAL); 748 } 749 750 type = sp->args[0]; /* channel type */ 751 752 /* Only supports TXDB and RXDB */ 753 if (type == IMX_MU_TYPE_TX || type == IMX_MU_TYPE_RX) { 754 dev_err(mbox->dev, "Invalid type: %d\n", type); 755 return ERR_PTR(-EINVAL); 756 } 757 758 return imx_mu_xlate(mbox, sp); 759 } 760 761 static void imx_mu_get_tr_rr(struct imx_mu_priv *priv) 762 { 763 u32 val; 764 765 if (priv->dcfg->type & IMX_MU_V2) { 766 val = imx_mu_read(priv, IMX_MU_V2_PAR_OFF); 767 priv->num_tr = FIELD_GET(IMX_MU_V2_TR_MASK, val); 768 priv->num_rr = FIELD_GET(IMX_MU_V2_RR_MASK, val); 769 } else { 770 priv->num_tr = 4; 771 priv->num_rr = 4; 772 } 773 } 774 775 static int imx_mu_init_generic(struct imx_mu_priv *priv) 776 { 777 unsigned int i; 778 unsigned int val; 779 780 if (priv->num_rr > 4 || priv->num_tr > 4) { 781 WARN_ONCE(true, "%s not support TR/RR larger than 4\n", __func__); 782 return -EOPNOTSUPP; 783 } 784 785 for (i = 0; i < IMX_MU_CHANS; i++) { 786 struct imx_mu_con_priv *cp = &priv->con_priv[i]; 787 788 cp->idx = i % 4; 789 cp->type = i >> 2; 790 cp->chan = &priv->mbox_chans[i]; 791 priv->mbox_chans[i].con_priv = cp; 792 snprintf(cp->irq_desc, sizeof(cp->irq_desc), 793 "%s[%i-%u]", dev_name(priv->dev), cp->type, cp->idx); 794 } 795 796 priv->mbox.num_chans = IMX_MU_CHANS; 797 priv->mbox.of_xlate = imx_mu_xlate; 798 799 if (priv->side_b) 800 return 0; 801 802 /* Set default MU configuration */ 803 for (i = 0; i < IMX_MU_xCR_MAX; i++) 804 imx_mu_write(priv, 0, priv->dcfg->xCR[i]); 805 806 /* Clear any pending GIP */ 807 val = imx_mu_read(priv, priv->dcfg->xSR[IMX_MU_GSR]); 808 imx_mu_write(priv, val, priv->dcfg->xSR[IMX_MU_GSR]); 809 810 /* Clear any pending RSR */ 811 for (i = 0; i < priv->num_rr; i++) 812 imx_mu_read(priv, priv->dcfg->xRR + i * 4); 813 814 return 0; 815 } 816 817 static int imx_mu_init_specific(struct imx_mu_priv *priv) 818 { 819 unsigned int i; 820 int num_chans = priv->dcfg->type & IMX_MU_V2_S4 ? IMX_MU_S4_CHANS : IMX_MU_SCU_CHANS; 821 822 for (i = 0; i < num_chans; i++) { 823 struct imx_mu_con_priv *cp = &priv->con_priv[i]; 824 825 cp->idx = i < 2 ? 0 : i - 2; 826 cp->type = i < 2 ? i : IMX_MU_TYPE_RXDB; 827 cp->chan = &priv->mbox_chans[i]; 828 priv->mbox_chans[i].con_priv = cp; 829 snprintf(cp->irq_desc, sizeof(cp->irq_desc), 830 "%s[%i-%u]", dev_name(priv->dev), cp->type, cp->idx); 831 } 832 833 priv->mbox.num_chans = num_chans; 834 priv->mbox.of_xlate = imx_mu_specific_xlate; 835 836 /* Set default MU configuration */ 837 for (i = 0; i < IMX_MU_xCR_MAX; i++) 838 imx_mu_write(priv, 0, priv->dcfg->xCR[i]); 839 840 return 0; 841 } 842 843 static int imx_mu_init_seco(struct imx_mu_priv *priv) 844 { 845 int ret; 846 847 ret = imx_mu_init_generic(priv); 848 if (ret) 849 return ret; 850 priv->mbox.of_xlate = imx_mu_seco_xlate; 851 852 return 0; 853 } 854 855 static int imx_mu_probe(struct platform_device *pdev) 856 { 857 struct device *dev = &pdev->dev; 858 struct device_node *np = dev->of_node; 859 struct imx_mu_priv *priv; 860 const struct imx_mu_dcfg *dcfg; 861 int i, ret; 862 u32 size; 863 864 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); 865 if (!priv) 866 return -ENOMEM; 867 868 priv->dev = dev; 869 870 priv->base = devm_platform_ioremap_resource(pdev, 0); 871 if (IS_ERR(priv->base)) 872 return PTR_ERR(priv->base); 873 874 dcfg = of_device_get_match_data(dev); 875 if (!dcfg) 876 return -EINVAL; 877 priv->dcfg = dcfg; 878 if (priv->dcfg->type & IMX_MU_V2_IRQ) { 879 priv->irq[IMX_MU_TYPE_TX] = platform_get_irq_byname(pdev, "tx"); 880 if (priv->irq[IMX_MU_TYPE_TX] < 0) 881 return priv->irq[IMX_MU_TYPE_TX]; 882 priv->irq[IMX_MU_TYPE_RX] = platform_get_irq_byname(pdev, "rx"); 883 if (priv->irq[IMX_MU_TYPE_RX] < 0) 884 return priv->irq[IMX_MU_TYPE_RX]; 885 } else { 886 ret = platform_get_irq(pdev, 0); 887 if (ret < 0) 888 return ret; 889 890 for (i = 0; i < IMX_MU_CHANS; i++) 891 priv->irq[i] = ret; 892 } 893 894 if (priv->dcfg->type & IMX_MU_V2_S4) 895 size = sizeof(struct imx_s4_rpc_msg_max); 896 else 897 size = sizeof(struct imx_sc_rpc_msg_max); 898 899 priv->msg = devm_kzalloc(dev, size, GFP_KERNEL); 900 if (!priv->msg) 901 return -ENOMEM; 902 903 priv->clk = devm_clk_get(dev, NULL); 904 if (IS_ERR(priv->clk)) { 905 if (PTR_ERR(priv->clk) != -ENOENT) 906 return PTR_ERR(priv->clk); 907 908 priv->clk = NULL; 909 } 910 911 ret = clk_prepare_enable(priv->clk); 912 if (ret) { 913 dev_err(dev, "Failed to enable clock\n"); 914 return ret; 915 } 916 917 imx_mu_get_tr_rr(priv); 918 919 priv->side_b = of_property_read_bool(np, "fsl,mu-side-b"); 920 921 ret = priv->dcfg->init(priv); 922 if (ret) { 923 dev_err(dev, "Failed to init MU\n"); 924 goto disable_clk; 925 } 926 927 spin_lock_init(&priv->xcr_lock); 928 929 priv->mbox.dev = dev; 930 priv->mbox.ops = &imx_mu_ops; 931 priv->mbox.chans = priv->mbox_chans; 932 priv->mbox.txdone_irq = true; 933 934 platform_set_drvdata(pdev, priv); 935 936 ret = devm_mbox_controller_register(dev, &priv->mbox); 937 if (ret) 938 goto disable_clk; 939 940 of_platform_populate(dev->of_node, NULL, NULL, dev); 941 942 pm_runtime_enable(dev); 943 944 ret = pm_runtime_resume_and_get(dev); 945 if (ret < 0) 946 goto disable_runtime_pm; 947 948 ret = pm_runtime_put_sync(dev); 949 if (ret < 0) 950 goto disable_runtime_pm; 951 952 clk_disable_unprepare(priv->clk); 953 954 return 0; 955 956 disable_runtime_pm: 957 pm_runtime_disable(dev); 958 disable_clk: 959 clk_disable_unprepare(priv->clk); 960 return ret; 961 } 962 963 static void imx_mu_remove(struct platform_device *pdev) 964 { 965 struct imx_mu_priv *priv = platform_get_drvdata(pdev); 966 967 pm_runtime_disable(priv->dev); 968 } 969 970 static const struct imx_mu_dcfg imx_mu_cfg_imx6sx = { 971 .tx = imx_mu_generic_tx, 972 .rx = imx_mu_generic_rx, 973 .rxdb = imx_mu_generic_rxdb, 974 .init = imx_mu_init_generic, 975 .xTR = 0x0, 976 .xRR = 0x10, 977 .xSR = {0x20, 0x20, 0x20, 0x20}, 978 .xCR = {0x24, 0x24, 0x24, 0x24, 0x24}, 979 }; 980 981 static const struct imx_mu_dcfg imx_mu_cfg_imx7ulp = { 982 .tx = imx_mu_generic_tx, 983 .rx = imx_mu_generic_rx, 984 .rxdb = imx_mu_generic_rxdb, 985 .init = imx_mu_init_generic, 986 .xTR = 0x20, 987 .xRR = 0x40, 988 .xSR = {0x60, 0x60, 0x60, 0x60}, 989 .xCR = {0x64, 0x64, 0x64, 0x64, 0x64}, 990 .skip_suspend_flag = true, 991 }; 992 993 static const struct imx_mu_dcfg imx_mu_cfg_imx8ulp = { 994 .tx = imx_mu_generic_tx, 995 .rx = imx_mu_generic_rx, 996 .rxdb = imx_mu_generic_rxdb, 997 .init = imx_mu_init_generic, 998 .type = IMX_MU_V2, 999 .xTR = 0x200, 1000 .xRR = 0x280, 1001 .xSR = {0xC, 0x118, 0x124, 0x12C}, 1002 .xCR = {0x8, 0x110, 0x114, 0x120, 0x128}, 1003 }; 1004 1005 static const struct imx_mu_dcfg imx_mu_cfg_imx8ulp_s4 = { 1006 .tx = imx_mu_specific_tx, 1007 .rx = imx_mu_specific_rx, 1008 .init = imx_mu_init_specific, 1009 .type = IMX_MU_V2 | IMX_MU_V2_S4, 1010 .xTR = 0x200, 1011 .xRR = 0x280, 1012 .xSR = {0xC, 0x118, 0x124, 0x12C}, 1013 .xCR = {0x8, 0x110, 0x114, 0x120, 0x128}, 1014 }; 1015 1016 static const struct imx_mu_dcfg imx_mu_cfg_imx93_s4 = { 1017 .tx = imx_mu_specific_tx, 1018 .rx = imx_mu_specific_rx, 1019 .init = imx_mu_init_specific, 1020 .type = IMX_MU_V2 | IMX_MU_V2_S4 | IMX_MU_V2_IRQ, 1021 .xTR = 0x200, 1022 .xRR = 0x280, 1023 .xSR = {0xC, 0x118, 0x124, 0x12C}, 1024 .xCR = {0x8, 0x110, 0x114, 0x120, 0x128}, 1025 }; 1026 1027 static const struct imx_mu_dcfg imx_mu_cfg_imx8_scu = { 1028 .tx = imx_mu_specific_tx, 1029 .rx = imx_mu_specific_rx, 1030 .init = imx_mu_init_specific, 1031 .rxdb = imx_mu_generic_rxdb, 1032 .xTR = 0x0, 1033 .xRR = 0x10, 1034 .xSR = {0x20, 0x20, 0x20, 0x20}, 1035 .xCR = {0x24, 0x24, 0x24, 0x24, 0x24}, 1036 }; 1037 1038 static const struct imx_mu_dcfg imx_mu_cfg_imx8_seco = { 1039 .tx = imx_mu_seco_tx, 1040 .rx = imx_mu_generic_rx, 1041 .rxdb = imx_mu_seco_rxdb, 1042 .init = imx_mu_init_seco, 1043 .xTR = 0x0, 1044 .xRR = 0x10, 1045 .xSR = {0x20, 0x20, 0x20, 0x20}, 1046 .xCR = {0x24, 0x24, 0x24, 0x24, 0x24}, 1047 }; 1048 1049 static const struct of_device_id imx_mu_dt_ids[] = { 1050 { .compatible = "fsl,imx7ulp-mu", .data = &imx_mu_cfg_imx7ulp }, 1051 { .compatible = "fsl,imx6sx-mu", .data = &imx_mu_cfg_imx6sx }, 1052 { .compatible = "fsl,imx8ulp-mu", .data = &imx_mu_cfg_imx8ulp }, 1053 { .compatible = "fsl,imx8ulp-mu-s4", .data = &imx_mu_cfg_imx8ulp_s4 }, 1054 { .compatible = "fsl,imx93-mu-s4", .data = &imx_mu_cfg_imx93_s4 }, 1055 { .compatible = "fsl,imx95-mu", .data = &imx_mu_cfg_imx8ulp }, 1056 { .compatible = "fsl,imx95-mu-ele", .data = &imx_mu_cfg_imx8ulp_s4 }, 1057 { .compatible = "fsl,imx95-mu-v2x", .data = &imx_mu_cfg_imx8ulp_s4 }, 1058 { .compatible = "fsl,imx8-mu-scu", .data = &imx_mu_cfg_imx8_scu }, 1059 { .compatible = "fsl,imx8-mu-seco", .data = &imx_mu_cfg_imx8_seco }, 1060 { }, 1061 }; 1062 MODULE_DEVICE_TABLE(of, imx_mu_dt_ids); 1063 1064 static int __maybe_unused imx_mu_suspend_noirq(struct device *dev) 1065 { 1066 struct imx_mu_priv *priv = dev_get_drvdata(dev); 1067 int i; 1068 1069 if (!priv->clk) { 1070 for (i = 0; i < IMX_MU_xCR_MAX; i++) 1071 priv->xcr[i] = imx_mu_read(priv, priv->dcfg->xCR[i]); 1072 } 1073 1074 if (!priv->dcfg->skip_suspend_flag) 1075 priv->suspend = true; 1076 1077 return 0; 1078 } 1079 1080 static int __maybe_unused imx_mu_resume_noirq(struct device *dev) 1081 { 1082 struct imx_mu_priv *priv = dev_get_drvdata(dev); 1083 int i; 1084 1085 /* 1086 * ONLY restore MU when context lost, the TIE could 1087 * be set during noirq resume as there is MU data 1088 * communication going on, and restore the saved 1089 * value will overwrite the TIE and cause MU data 1090 * send failed, may lead to system freeze. This issue 1091 * is observed by testing freeze mode suspend. 1092 */ 1093 if (!priv->clk && !imx_mu_read(priv, priv->dcfg->xCR[0])) { 1094 for (i = 0; i < IMX_MU_xCR_MAX; i++) 1095 imx_mu_write(priv, priv->xcr[i], priv->dcfg->xCR[i]); 1096 } 1097 1098 if (!priv->dcfg->skip_suspend_flag) 1099 priv->suspend = false; 1100 1101 return 0; 1102 } 1103 1104 static int __maybe_unused imx_mu_runtime_suspend(struct device *dev) 1105 { 1106 struct imx_mu_priv *priv = dev_get_drvdata(dev); 1107 1108 clk_disable_unprepare(priv->clk); 1109 1110 return 0; 1111 } 1112 1113 static int __maybe_unused imx_mu_runtime_resume(struct device *dev) 1114 { 1115 struct imx_mu_priv *priv = dev_get_drvdata(dev); 1116 int ret; 1117 1118 ret = clk_prepare_enable(priv->clk); 1119 if (ret) 1120 dev_err(dev, "failed to enable clock\n"); 1121 1122 return ret; 1123 } 1124 1125 static const struct dev_pm_ops imx_mu_pm_ops = { 1126 SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(imx_mu_suspend_noirq, 1127 imx_mu_resume_noirq) 1128 SET_RUNTIME_PM_OPS(imx_mu_runtime_suspend, 1129 imx_mu_runtime_resume, NULL) 1130 }; 1131 1132 static struct platform_driver imx_mu_driver = { 1133 .probe = imx_mu_probe, 1134 .remove = imx_mu_remove, 1135 .driver = { 1136 .name = "imx_mu", 1137 .of_match_table = imx_mu_dt_ids, 1138 .pm = &imx_mu_pm_ops, 1139 }, 1140 }; 1141 module_platform_driver(imx_mu_driver); 1142 1143 MODULE_AUTHOR("Oleksij Rempel <o.rempel@pengutronix.de>"); 1144 MODULE_DESCRIPTION("Message Unit driver for i.MX"); 1145 MODULE_LICENSE("GPL v2"); 1146