1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (c) 2018 Pengutronix, Oleksij Rempel <o.rempel@pengutronix.de> 4 * Copyright 2022 NXP, Peng Fan <peng.fan@nxp.com> 5 */ 6 7 #include <linux/bitfield.h> 8 #include <linux/clk.h> 9 #include <linux/firmware/imx/ipc.h> 10 #include <linux/firmware/imx/s4.h> 11 #include <linux/interrupt.h> 12 #include <linux/io.h> 13 #include <linux/iopoll.h> 14 #include <linux/jiffies.h> 15 #include <linux/kernel.h> 16 #include <linux/mailbox_controller.h> 17 #include <linux/module.h> 18 #include <linux/of.h> 19 #include <linux/of_platform.h> 20 #include <linux/platform_device.h> 21 #include <linux/pm_runtime.h> 22 #include <linux/suspend.h> 23 #include <linux/slab.h> 24 #include <linux/workqueue.h> 25 26 #include "mailbox.h" 27 28 #define IMX_MU_CHANS 24 29 /* TX0/RX0/RXDB[0-3] */ 30 #define IMX_MU_SCU_CHANS 6 31 /* TX0/RX0 */ 32 #define IMX_MU_S4_CHANS 2 33 #define IMX_MU_CHAN_NAME_SIZE 32 34 35 #define IMX_MU_V2_PAR_OFF 0x4 36 #define IMX_MU_V2_TR_MASK GENMASK(7, 0) 37 #define IMX_MU_V2_RR_MASK GENMASK(15, 8) 38 39 #define IMX_MU_SECO_TX_TOUT (msecs_to_jiffies(3000)) 40 #define IMX_MU_SECO_RX_TOUT (msecs_to_jiffies(3000)) 41 42 /* Please not change TX & RX */ 43 enum imx_mu_chan_type { 44 IMX_MU_TYPE_TX = 0, /* Tx */ 45 IMX_MU_TYPE_RX = 1, /* Rx */ 46 IMX_MU_TYPE_TXDB = 2, /* Tx doorbell */ 47 IMX_MU_TYPE_RXDB = 3, /* Rx doorbell */ 48 IMX_MU_TYPE_RST = 4, /* Reset */ 49 IMX_MU_TYPE_TXDB_V2 = 5, /* Tx doorbell with S/W ACK */ 50 }; 51 52 enum imx_mu_xcr { 53 IMX_MU_CR, 54 IMX_MU_GIER, 55 IMX_MU_GCR, 56 IMX_MU_TCR, 57 IMX_MU_RCR, 58 IMX_MU_xCR_MAX, 59 }; 60 61 enum imx_mu_xsr { 62 IMX_MU_SR, 63 IMX_MU_GSR, 64 IMX_MU_TSR, 65 IMX_MU_RSR, 66 IMX_MU_xSR_MAX, 67 }; 68 69 struct imx_sc_rpc_msg_max { 70 struct imx_sc_rpc_msg hdr; 71 u32 data[30]; 72 }; 73 74 struct imx_s4_rpc_msg_max { 75 struct imx_s4_rpc_msg hdr; 76 u32 data[254]; 77 }; 78 79 struct imx_mu_con_priv { 80 unsigned int idx; 81 char irq_desc[IMX_MU_CHAN_NAME_SIZE]; 82 enum imx_mu_chan_type type; 83 struct mbox_chan *chan; 84 struct work_struct txdb_work; 85 }; 86 87 struct imx_mu_priv { 88 struct device *dev; 89 void __iomem *base; 90 void *msg; 91 spinlock_t xcr_lock; /* control register lock */ 92 93 struct mbox_controller mbox; 94 struct mbox_chan mbox_chans[IMX_MU_CHANS]; 95 96 struct imx_mu_con_priv con_priv[IMX_MU_CHANS]; 97 const struct imx_mu_dcfg *dcfg; 98 struct clk *clk; 99 int irq[IMX_MU_CHANS]; 100 bool suspend; 101 bool side_b; 102 103 u32 xcr[IMX_MU_xCR_MAX]; 104 u32 num_tr; 105 u32 num_rr; 106 }; 107 108 enum imx_mu_type { 109 IMX_MU_V1, 110 IMX_MU_V2 = BIT(1), 111 IMX_MU_V2_S4 = BIT(15), 112 IMX_MU_V2_IRQ = BIT(16), 113 }; 114 115 struct imx_mu_dcfg { 116 int (*tx)(struct imx_mu_priv *priv, struct imx_mu_con_priv *cp, void *data); 117 int (*rx)(struct imx_mu_priv *priv, struct imx_mu_con_priv *cp); 118 int (*rxdb)(struct imx_mu_priv *priv, struct imx_mu_con_priv *cp); 119 int (*init)(struct imx_mu_priv *priv); 120 enum imx_mu_type type; 121 u32 xTR; /* Transmit Register0 */ 122 u32 xRR; /* Receive Register0 */ 123 u32 xSR[IMX_MU_xSR_MAX]; /* Status Registers */ 124 u32 xCR[IMX_MU_xCR_MAX]; /* Control Registers */ 125 }; 126 127 #define IMX_MU_xSR_GIPn(type, x) (type & IMX_MU_V2 ? BIT(x) : BIT(28 + (3 - (x)))) 128 #define IMX_MU_xSR_RFn(type, x) (type & IMX_MU_V2 ? BIT(x) : BIT(24 + (3 - (x)))) 129 #define IMX_MU_xSR_TEn(type, x) (type & IMX_MU_V2 ? BIT(x) : BIT(20 + (3 - (x)))) 130 131 /* General Purpose Interrupt Enable */ 132 #define IMX_MU_xCR_GIEn(type, x) (type & IMX_MU_V2 ? BIT(x) : BIT(28 + (3 - (x)))) 133 /* Receive Interrupt Enable */ 134 #define IMX_MU_xCR_RIEn(type, x) (type & IMX_MU_V2 ? BIT(x) : BIT(24 + (3 - (x)))) 135 /* Transmit Interrupt Enable */ 136 #define IMX_MU_xCR_TIEn(type, x) (type & IMX_MU_V2 ? BIT(x) : BIT(20 + (3 - (x)))) 137 /* General Purpose Interrupt Request */ 138 #define IMX_MU_xCR_GIRn(type, x) (type & IMX_MU_V2 ? BIT(x) : BIT(16 + (3 - (x)))) 139 /* MU reset */ 140 #define IMX_MU_xCR_RST(type) (type & IMX_MU_V2 ? BIT(0) : BIT(5)) 141 #define IMX_MU_xSR_RST(type) (type & IMX_MU_V2 ? BIT(0) : BIT(7)) 142 143 144 static struct imx_mu_priv *to_imx_mu_priv(struct mbox_controller *mbox) 145 { 146 return container_of(mbox, struct imx_mu_priv, mbox); 147 } 148 149 static void imx_mu_write(struct imx_mu_priv *priv, u32 val, u32 offs) 150 { 151 iowrite32(val, priv->base + offs); 152 } 153 154 static u32 imx_mu_read(struct imx_mu_priv *priv, u32 offs) 155 { 156 return ioread32(priv->base + offs); 157 } 158 159 static int imx_mu_tx_waiting_write(struct imx_mu_priv *priv, u32 val, u32 idx) 160 { 161 u64 timeout_time = get_jiffies_64() + IMX_MU_SECO_TX_TOUT; 162 u32 status; 163 u32 can_write; 164 165 dev_dbg(priv->dev, "Trying to write %.8x to idx %d\n", val, idx); 166 167 do { 168 status = imx_mu_read(priv, priv->dcfg->xSR[IMX_MU_TSR]); 169 can_write = status & IMX_MU_xSR_TEn(priv->dcfg->type, idx % 4); 170 } while (!can_write && time_is_after_jiffies64(timeout_time)); 171 172 if (!can_write) { 173 dev_err(priv->dev, "timeout trying to write %.8x at %d(%.8x)\n", 174 val, idx, status); 175 return -ETIME; 176 } 177 178 imx_mu_write(priv, val, priv->dcfg->xTR + (idx % 4) * 4); 179 180 return 0; 181 } 182 183 static int imx_mu_rx_waiting_read(struct imx_mu_priv *priv, u32 *val, u32 idx) 184 { 185 u64 timeout_time = get_jiffies_64() + IMX_MU_SECO_RX_TOUT; 186 u32 status; 187 u32 can_read; 188 189 dev_dbg(priv->dev, "Trying to read from idx %d\n", idx); 190 191 do { 192 status = imx_mu_read(priv, priv->dcfg->xSR[IMX_MU_RSR]); 193 can_read = status & IMX_MU_xSR_RFn(priv->dcfg->type, idx % 4); 194 } while (!can_read && time_is_after_jiffies64(timeout_time)); 195 196 if (!can_read) { 197 dev_err(priv->dev, "timeout trying to read idx %d (%.8x)\n", 198 idx, status); 199 return -ETIME; 200 } 201 202 *val = imx_mu_read(priv, priv->dcfg->xRR + (idx % 4) * 4); 203 dev_dbg(priv->dev, "Read %.8x\n", *val); 204 205 return 0; 206 } 207 208 static u32 imx_mu_xcr_rmw(struct imx_mu_priv *priv, enum imx_mu_xcr type, u32 set, u32 clr) 209 { 210 unsigned long flags; 211 u32 val; 212 213 spin_lock_irqsave(&priv->xcr_lock, flags); 214 val = imx_mu_read(priv, priv->dcfg->xCR[type]); 215 val &= ~clr; 216 val |= set; 217 imx_mu_write(priv, val, priv->dcfg->xCR[type]); 218 spin_unlock_irqrestore(&priv->xcr_lock, flags); 219 220 return val; 221 } 222 223 static int imx_mu_generic_tx(struct imx_mu_priv *priv, 224 struct imx_mu_con_priv *cp, 225 void *data) 226 { 227 u32 *arg = data; 228 u32 val; 229 int ret, count; 230 231 switch (cp->type) { 232 case IMX_MU_TYPE_TX: 233 imx_mu_write(priv, *arg, priv->dcfg->xTR + cp->idx * 4); 234 imx_mu_xcr_rmw(priv, IMX_MU_TCR, IMX_MU_xCR_TIEn(priv->dcfg->type, cp->idx), 0); 235 break; 236 case IMX_MU_TYPE_TXDB: 237 imx_mu_xcr_rmw(priv, IMX_MU_GCR, IMX_MU_xCR_GIRn(priv->dcfg->type, cp->idx), 0); 238 queue_work(system_bh_wq, &cp->txdb_work); 239 break; 240 case IMX_MU_TYPE_TXDB_V2: 241 imx_mu_write(priv, IMX_MU_xCR_GIRn(priv->dcfg->type, cp->idx), 242 priv->dcfg->xCR[IMX_MU_GCR]); 243 ret = -ETIMEDOUT; 244 count = 0; 245 while (ret && (count < 10)) { 246 ret = 247 readl_poll_timeout(priv->base + priv->dcfg->xCR[IMX_MU_GCR], val, 248 !(val & IMX_MU_xCR_GIRn(priv->dcfg->type, cp->idx)), 249 0, 10000); 250 251 if (ret) { 252 dev_warn_ratelimited(priv->dev, 253 "channel type: %d timeout, %d times, retry\n", 254 cp->type, ++count); 255 } 256 } 257 break; 258 default: 259 dev_warn_ratelimited(priv->dev, "Send data on wrong channel type: %d\n", cp->type); 260 return -EINVAL; 261 } 262 263 return 0; 264 } 265 266 static int imx_mu_generic_rx(struct imx_mu_priv *priv, 267 struct imx_mu_con_priv *cp) 268 { 269 u32 dat; 270 271 dat = imx_mu_read(priv, priv->dcfg->xRR + (cp->idx) * 4); 272 mbox_chan_received_data(cp->chan, (void *)&dat); 273 274 return 0; 275 } 276 277 static int imx_mu_generic_rxdb(struct imx_mu_priv *priv, 278 struct imx_mu_con_priv *cp) 279 { 280 imx_mu_write(priv, IMX_MU_xSR_GIPn(priv->dcfg->type, cp->idx), 281 priv->dcfg->xSR[IMX_MU_GSR]); 282 mbox_chan_received_data(cp->chan, NULL); 283 284 return 0; 285 } 286 287 static int imx_mu_specific_tx(struct imx_mu_priv *priv, struct imx_mu_con_priv *cp, void *data) 288 { 289 u32 *arg = data; 290 u32 num_tr = priv->num_tr; 291 int i, ret; 292 u32 xsr; 293 u32 size, max_size; 294 295 if (priv->dcfg->type & IMX_MU_V2_S4) { 296 size = ((struct imx_s4_rpc_msg_max *)data)->hdr.size; 297 max_size = sizeof(struct imx_s4_rpc_msg_max); 298 } else { 299 size = ((struct imx_sc_rpc_msg_max *)data)->hdr.size; 300 max_size = sizeof(struct imx_sc_rpc_msg_max); 301 } 302 303 switch (cp->type) { 304 case IMX_MU_TYPE_TX: 305 /* 306 * msg->hdr.size specifies the number of u32 words while 307 * sizeof yields bytes. 308 */ 309 310 if (size > max_size / 4) { 311 /* 312 * The real message size can be different to 313 * struct imx_sc_rpc_msg_max/imx_s4_rpc_msg_max size 314 */ 315 dev_err(priv->dev, "Maximal message size (%u bytes) exceeded on TX; got: %i bytes\n", max_size, size << 2); 316 return -EINVAL; 317 } 318 319 for (i = 0; i < num_tr && i < size; i++) 320 imx_mu_write(priv, *arg++, priv->dcfg->xTR + (i % num_tr) * 4); 321 for (; i < size; i++) { 322 ret = readl_poll_timeout(priv->base + priv->dcfg->xSR[IMX_MU_TSR], 323 xsr, 324 xsr & IMX_MU_xSR_TEn(priv->dcfg->type, i % num_tr), 325 0, 5 * USEC_PER_SEC); 326 if (ret) { 327 dev_err(priv->dev, "Send data index: %d timeout\n", i); 328 return ret; 329 } 330 imx_mu_write(priv, *arg++, priv->dcfg->xTR + (i % num_tr) * 4); 331 } 332 333 imx_mu_xcr_rmw(priv, IMX_MU_TCR, IMX_MU_xCR_TIEn(priv->dcfg->type, cp->idx), 0); 334 break; 335 default: 336 dev_warn_ratelimited(priv->dev, "Send data on wrong channel type: %d\n", cp->type); 337 return -EINVAL; 338 } 339 340 return 0; 341 } 342 343 static int imx_mu_specific_rx(struct imx_mu_priv *priv, struct imx_mu_con_priv *cp) 344 { 345 u32 *data; 346 int i, ret; 347 u32 xsr; 348 u32 size, max_size; 349 u32 num_rr = priv->num_rr; 350 351 data = (u32 *)priv->msg; 352 353 imx_mu_xcr_rmw(priv, IMX_MU_RCR, 0, IMX_MU_xCR_RIEn(priv->dcfg->type, 0)); 354 *data++ = imx_mu_read(priv, priv->dcfg->xRR); 355 356 if (priv->dcfg->type & IMX_MU_V2_S4) { 357 size = ((struct imx_s4_rpc_msg_max *)priv->msg)->hdr.size; 358 max_size = sizeof(struct imx_s4_rpc_msg_max); 359 } else { 360 size = ((struct imx_sc_rpc_msg_max *)priv->msg)->hdr.size; 361 max_size = sizeof(struct imx_sc_rpc_msg_max); 362 } 363 364 if (size > max_size / 4) { 365 dev_err(priv->dev, "Maximal message size (%u bytes) exceeded on RX; got: %i bytes\n", max_size, size << 2); 366 return -EINVAL; 367 } 368 369 for (i = 1; i < size; i++) { 370 ret = readl_poll_timeout(priv->base + priv->dcfg->xSR[IMX_MU_RSR], xsr, 371 xsr & IMX_MU_xSR_RFn(priv->dcfg->type, i % num_rr), 0, 372 5 * USEC_PER_SEC); 373 if (ret) { 374 dev_err(priv->dev, "timeout read idx %d\n", i); 375 return ret; 376 } 377 *data++ = imx_mu_read(priv, priv->dcfg->xRR + (i % num_rr) * 4); 378 } 379 380 imx_mu_xcr_rmw(priv, IMX_MU_RCR, IMX_MU_xCR_RIEn(priv->dcfg->type, 0), 0); 381 mbox_chan_received_data(cp->chan, (void *)priv->msg); 382 383 return 0; 384 } 385 386 static int imx_mu_seco_tx(struct imx_mu_priv *priv, struct imx_mu_con_priv *cp, 387 void *data) 388 { 389 struct imx_sc_rpc_msg_max *msg = data; 390 u32 *arg = data; 391 u32 byte_size; 392 int err; 393 int i; 394 395 dev_dbg(priv->dev, "Sending message\n"); 396 397 switch (cp->type) { 398 case IMX_MU_TYPE_TXDB: 399 byte_size = msg->hdr.size * sizeof(u32); 400 if (byte_size > sizeof(*msg)) { 401 /* 402 * The real message size can be different to 403 * struct imx_sc_rpc_msg_max size 404 */ 405 dev_err(priv->dev, 406 "Exceed max msg size (%zu) on TX, got: %i\n", 407 sizeof(*msg), byte_size); 408 return -EINVAL; 409 } 410 411 print_hex_dump_debug("from client ", DUMP_PREFIX_OFFSET, 4, 4, 412 data, byte_size, false); 413 414 /* Send first word */ 415 dev_dbg(priv->dev, "Sending header\n"); 416 imx_mu_write(priv, *arg++, priv->dcfg->xTR); 417 418 /* Send signaling */ 419 dev_dbg(priv->dev, "Sending signaling\n"); 420 imx_mu_xcr_rmw(priv, IMX_MU_GCR, 421 IMX_MU_xCR_GIRn(priv->dcfg->type, cp->idx), 0); 422 423 /* Send words to fill the mailbox */ 424 for (i = 1; i < 4 && i < msg->hdr.size; i++) { 425 dev_dbg(priv->dev, "Sending word %d\n", i); 426 imx_mu_write(priv, *arg++, 427 priv->dcfg->xTR + (i % 4) * 4); 428 } 429 430 /* Send rest of message waiting for remote read */ 431 for (; i < msg->hdr.size; i++) { 432 dev_dbg(priv->dev, "Sending word %d\n", i); 433 err = imx_mu_tx_waiting_write(priv, *arg++, i); 434 if (err) { 435 dev_err(priv->dev, "Timeout tx %d\n", i); 436 return err; 437 } 438 } 439 440 /* Simulate hack for mbox framework */ 441 queue_work(system_bh_wq, &cp->txdb_work); 442 443 break; 444 default: 445 dev_warn_ratelimited(priv->dev, 446 "Send data on wrong channel type: %d\n", 447 cp->type); 448 return -EINVAL; 449 } 450 451 return 0; 452 } 453 454 static int imx_mu_seco_rxdb(struct imx_mu_priv *priv, struct imx_mu_con_priv *cp) 455 { 456 struct imx_sc_rpc_msg_max msg; 457 u32 *data = (u32 *)&msg; 458 u32 byte_size; 459 int err = 0; 460 int i; 461 462 dev_dbg(priv->dev, "Receiving message\n"); 463 464 /* Read header */ 465 dev_dbg(priv->dev, "Receiving header\n"); 466 *data++ = imx_mu_read(priv, priv->dcfg->xRR); 467 byte_size = msg.hdr.size * sizeof(u32); 468 if (byte_size > sizeof(msg)) { 469 dev_err(priv->dev, "Exceed max msg size (%zu) on RX, got: %i\n", 470 sizeof(msg), byte_size); 471 err = -EINVAL; 472 goto error; 473 } 474 475 /* Read message waiting they are written */ 476 for (i = 1; i < msg.hdr.size; i++) { 477 dev_dbg(priv->dev, "Receiving word %d\n", i); 478 err = imx_mu_rx_waiting_read(priv, data++, i); 479 if (err) { 480 dev_err(priv->dev, "Timeout rx %d\n", i); 481 goto error; 482 } 483 } 484 485 /* Clear GIP */ 486 imx_mu_write(priv, IMX_MU_xSR_GIPn(priv->dcfg->type, cp->idx), 487 priv->dcfg->xSR[IMX_MU_GSR]); 488 489 print_hex_dump_debug("to client ", DUMP_PREFIX_OFFSET, 4, 4, 490 &msg, byte_size, false); 491 492 /* send data to client */ 493 dev_dbg(priv->dev, "Sending message to client\n"); 494 mbox_chan_received_data(cp->chan, (void *)&msg); 495 496 goto exit; 497 498 error: 499 mbox_chan_received_data(cp->chan, ERR_PTR(err)); 500 501 exit: 502 return err; 503 } 504 505 static void imx_mu_txdb_work(struct work_struct *t) 506 { 507 struct imx_mu_con_priv *cp = from_work(cp, t, txdb_work); 508 509 mbox_chan_txdone(cp->chan, 0); 510 } 511 512 static irqreturn_t imx_mu_isr(int irq, void *p) 513 { 514 struct mbox_chan *chan = p; 515 struct imx_mu_priv *priv = to_imx_mu_priv(chan->mbox); 516 struct imx_mu_con_priv *cp = chan->con_priv; 517 u32 val, ctrl; 518 519 switch (cp->type) { 520 case IMX_MU_TYPE_TX: 521 ctrl = imx_mu_read(priv, priv->dcfg->xCR[IMX_MU_TCR]); 522 val = imx_mu_read(priv, priv->dcfg->xSR[IMX_MU_TSR]); 523 val &= IMX_MU_xSR_TEn(priv->dcfg->type, cp->idx) & 524 (ctrl & IMX_MU_xCR_TIEn(priv->dcfg->type, cp->idx)); 525 break; 526 case IMX_MU_TYPE_RX: 527 ctrl = imx_mu_read(priv, priv->dcfg->xCR[IMX_MU_RCR]); 528 val = imx_mu_read(priv, priv->dcfg->xSR[IMX_MU_RSR]); 529 val &= IMX_MU_xSR_RFn(priv->dcfg->type, cp->idx) & 530 (ctrl & IMX_MU_xCR_RIEn(priv->dcfg->type, cp->idx)); 531 break; 532 case IMX_MU_TYPE_RXDB: 533 ctrl = imx_mu_read(priv, priv->dcfg->xCR[IMX_MU_GIER]); 534 val = imx_mu_read(priv, priv->dcfg->xSR[IMX_MU_GSR]); 535 val &= IMX_MU_xSR_GIPn(priv->dcfg->type, cp->idx) & 536 (ctrl & IMX_MU_xCR_GIEn(priv->dcfg->type, cp->idx)); 537 break; 538 case IMX_MU_TYPE_RST: 539 return IRQ_NONE; 540 default: 541 dev_warn_ratelimited(priv->dev, "Unhandled channel type %d\n", 542 cp->type); 543 return IRQ_NONE; 544 } 545 546 if (!val) 547 return IRQ_NONE; 548 549 if ((val == IMX_MU_xSR_TEn(priv->dcfg->type, cp->idx)) && 550 (cp->type == IMX_MU_TYPE_TX)) { 551 imx_mu_xcr_rmw(priv, IMX_MU_TCR, 0, IMX_MU_xCR_TIEn(priv->dcfg->type, cp->idx)); 552 mbox_chan_txdone(chan, 0); 553 } else if ((val == IMX_MU_xSR_RFn(priv->dcfg->type, cp->idx)) && 554 (cp->type == IMX_MU_TYPE_RX)) { 555 priv->dcfg->rx(priv, cp); 556 } else if ((val == IMX_MU_xSR_GIPn(priv->dcfg->type, cp->idx)) && 557 (cp->type == IMX_MU_TYPE_RXDB)) { 558 priv->dcfg->rxdb(priv, cp); 559 } else { 560 dev_warn_ratelimited(priv->dev, "Not handled interrupt\n"); 561 return IRQ_NONE; 562 } 563 564 if (priv->suspend) 565 pm_system_wakeup(); 566 567 return IRQ_HANDLED; 568 } 569 570 static int imx_mu_send_data(struct mbox_chan *chan, void *data) 571 { 572 struct imx_mu_priv *priv = to_imx_mu_priv(chan->mbox); 573 struct imx_mu_con_priv *cp = chan->con_priv; 574 575 return priv->dcfg->tx(priv, cp, data); 576 } 577 578 static int imx_mu_startup(struct mbox_chan *chan) 579 { 580 struct imx_mu_priv *priv = to_imx_mu_priv(chan->mbox); 581 struct imx_mu_con_priv *cp = chan->con_priv; 582 unsigned long irq_flag = 0; 583 int ret; 584 585 pm_runtime_get_sync(priv->dev); 586 if (cp->type == IMX_MU_TYPE_TXDB_V2) 587 return 0; 588 589 if (cp->type == IMX_MU_TYPE_TXDB) { 590 /* Tx doorbell don't have ACK support */ 591 INIT_WORK(&cp->txdb_work, imx_mu_txdb_work); 592 return 0; 593 } 594 595 /* IPC MU should be with IRQF_NO_SUSPEND set */ 596 if (!priv->dev->pm_domain) 597 irq_flag |= IRQF_NO_SUSPEND; 598 599 if (!(priv->dcfg->type & IMX_MU_V2_IRQ)) 600 irq_flag |= IRQF_SHARED; 601 602 ret = request_irq(priv->irq[cp->type], imx_mu_isr, irq_flag, cp->irq_desc, chan); 603 if (ret) { 604 dev_err(priv->dev, "Unable to acquire IRQ %d\n", priv->irq[cp->type]); 605 return ret; 606 } 607 608 switch (cp->type) { 609 case IMX_MU_TYPE_RX: 610 imx_mu_xcr_rmw(priv, IMX_MU_RCR, IMX_MU_xCR_RIEn(priv->dcfg->type, cp->idx), 0); 611 break; 612 case IMX_MU_TYPE_RXDB: 613 imx_mu_xcr_rmw(priv, IMX_MU_GIER, IMX_MU_xCR_GIEn(priv->dcfg->type, cp->idx), 0); 614 break; 615 default: 616 break; 617 } 618 619 return 0; 620 } 621 622 static void imx_mu_shutdown(struct mbox_chan *chan) 623 { 624 struct imx_mu_priv *priv = to_imx_mu_priv(chan->mbox); 625 struct imx_mu_con_priv *cp = chan->con_priv; 626 int ret; 627 u32 sr; 628 629 if (cp->type == IMX_MU_TYPE_TXDB_V2) { 630 pm_runtime_put_sync(priv->dev); 631 return; 632 } 633 634 if (cp->type == IMX_MU_TYPE_TXDB) { 635 cancel_work_sync(&cp->txdb_work); 636 pm_runtime_put_sync(priv->dev); 637 return; 638 } 639 640 switch (cp->type) { 641 case IMX_MU_TYPE_TX: 642 imx_mu_xcr_rmw(priv, IMX_MU_TCR, 0, IMX_MU_xCR_TIEn(priv->dcfg->type, cp->idx)); 643 break; 644 case IMX_MU_TYPE_RX: 645 imx_mu_xcr_rmw(priv, IMX_MU_RCR, 0, IMX_MU_xCR_RIEn(priv->dcfg->type, cp->idx)); 646 break; 647 case IMX_MU_TYPE_RXDB: 648 imx_mu_xcr_rmw(priv, IMX_MU_GIER, 0, IMX_MU_xCR_GIEn(priv->dcfg->type, cp->idx)); 649 break; 650 case IMX_MU_TYPE_RST: 651 imx_mu_xcr_rmw(priv, IMX_MU_CR, IMX_MU_xCR_RST(priv->dcfg->type), 0); 652 ret = readl_poll_timeout(priv->base + priv->dcfg->xSR[IMX_MU_SR], sr, 653 !(sr & IMX_MU_xSR_RST(priv->dcfg->type)), 1, 5); 654 if (ret) 655 dev_warn(priv->dev, "RST channel timeout\n"); 656 break; 657 default: 658 break; 659 } 660 661 free_irq(priv->irq[cp->type], chan); 662 pm_runtime_put_sync(priv->dev); 663 } 664 665 static const struct mbox_chan_ops imx_mu_ops = { 666 .send_data = imx_mu_send_data, 667 .startup = imx_mu_startup, 668 .shutdown = imx_mu_shutdown, 669 }; 670 671 static struct mbox_chan *imx_mu_specific_xlate(struct mbox_controller *mbox, 672 const struct of_phandle_args *sp) 673 { 674 u32 type, idx, chan; 675 676 if (sp->args_count != 2) { 677 dev_err(mbox->dev, "Invalid argument count %d\n", sp->args_count); 678 return ERR_PTR(-EINVAL); 679 } 680 681 type = sp->args[0]; /* channel type */ 682 idx = sp->args[1]; /* index */ 683 684 switch (type) { 685 case IMX_MU_TYPE_TX: 686 case IMX_MU_TYPE_RX: 687 if (idx != 0) 688 dev_err(mbox->dev, "Invalid chan idx: %d\n", idx); 689 chan = type; 690 break; 691 case IMX_MU_TYPE_RXDB: 692 chan = 2 + idx; 693 break; 694 default: 695 dev_err(mbox->dev, "Invalid chan type: %d\n", type); 696 return ERR_PTR(-EINVAL); 697 } 698 699 if (chan >= mbox->num_chans) { 700 dev_err(mbox->dev, "Not supported channel number: %d. (type: %d, idx: %d)\n", chan, type, idx); 701 return ERR_PTR(-EINVAL); 702 } 703 704 return &mbox->chans[chan]; 705 } 706 707 static struct mbox_chan * imx_mu_xlate(struct mbox_controller *mbox, 708 const struct of_phandle_args *sp) 709 { 710 struct mbox_chan *p_chan; 711 u32 type, idx, chan; 712 713 if (sp->args_count != 2) { 714 dev_err(mbox->dev, "Invalid argument count %d\n", sp->args_count); 715 return ERR_PTR(-EINVAL); 716 } 717 718 type = sp->args[0]; /* channel type */ 719 idx = sp->args[1]; /* index */ 720 721 /* RST only supports 1 channel */ 722 if ((type == IMX_MU_TYPE_RST) && idx) { 723 dev_err(mbox->dev, "Invalid RST channel %d\n", idx); 724 return ERR_PTR(-EINVAL); 725 } 726 727 chan = type * 4 + idx; 728 if (chan >= mbox->num_chans) { 729 dev_err(mbox->dev, "Not supported channel number: %d. (type: %d, idx: %d)\n", chan, type, idx); 730 return ERR_PTR(-EINVAL); 731 } 732 733 p_chan = &mbox->chans[chan]; 734 735 if (type == IMX_MU_TYPE_TXDB_V2) 736 p_chan->txdone_method = TXDONE_BY_ACK; 737 738 return p_chan; 739 } 740 741 static struct mbox_chan *imx_mu_seco_xlate(struct mbox_controller *mbox, 742 const struct of_phandle_args *sp) 743 { 744 u32 type; 745 746 if (sp->args_count < 1) { 747 dev_err(mbox->dev, "Invalid argument count %d\n", sp->args_count); 748 return ERR_PTR(-EINVAL); 749 } 750 751 type = sp->args[0]; /* channel type */ 752 753 /* Only supports TXDB and RXDB */ 754 if (type == IMX_MU_TYPE_TX || type == IMX_MU_TYPE_RX) { 755 dev_err(mbox->dev, "Invalid type: %d\n", type); 756 return ERR_PTR(-EINVAL); 757 } 758 759 return imx_mu_xlate(mbox, sp); 760 } 761 762 static void imx_mu_get_tr_rr(struct imx_mu_priv *priv) 763 { 764 u32 val; 765 766 if (priv->dcfg->type & IMX_MU_V2) { 767 val = imx_mu_read(priv, IMX_MU_V2_PAR_OFF); 768 priv->num_tr = FIELD_GET(IMX_MU_V2_TR_MASK, val); 769 priv->num_rr = FIELD_GET(IMX_MU_V2_RR_MASK, val); 770 } else { 771 priv->num_tr = 4; 772 priv->num_rr = 4; 773 } 774 } 775 776 static int imx_mu_init_generic(struct imx_mu_priv *priv) 777 { 778 unsigned int i; 779 unsigned int val; 780 781 if (priv->num_rr > 4 || priv->num_tr > 4) { 782 WARN_ONCE(true, "%s not support TR/RR larger than 4\n", __func__); 783 return -EOPNOTSUPP; 784 } 785 786 for (i = 0; i < IMX_MU_CHANS; i++) { 787 struct imx_mu_con_priv *cp = &priv->con_priv[i]; 788 789 cp->idx = i % 4; 790 cp->type = i >> 2; 791 cp->chan = &priv->mbox_chans[i]; 792 priv->mbox_chans[i].con_priv = cp; 793 snprintf(cp->irq_desc, sizeof(cp->irq_desc), 794 "%s[%i-%u]", dev_name(priv->dev), cp->type, cp->idx); 795 } 796 797 priv->mbox.num_chans = IMX_MU_CHANS; 798 priv->mbox.of_xlate = imx_mu_xlate; 799 800 if (priv->side_b) 801 return 0; 802 803 /* Set default MU configuration */ 804 for (i = 0; i < IMX_MU_xCR_MAX; i++) 805 imx_mu_write(priv, 0, priv->dcfg->xCR[i]); 806 807 /* Clear any pending GIP */ 808 val = imx_mu_read(priv, priv->dcfg->xSR[IMX_MU_GSR]); 809 imx_mu_write(priv, val, priv->dcfg->xSR[IMX_MU_GSR]); 810 811 /* Clear any pending RSR */ 812 for (i = 0; i < priv->num_rr; i++) 813 imx_mu_read(priv, priv->dcfg->xRR + i * 4); 814 815 return 0; 816 } 817 818 static int imx_mu_init_specific(struct imx_mu_priv *priv) 819 { 820 unsigned int i; 821 int num_chans = priv->dcfg->type & IMX_MU_V2_S4 ? IMX_MU_S4_CHANS : IMX_MU_SCU_CHANS; 822 823 for (i = 0; i < num_chans; i++) { 824 struct imx_mu_con_priv *cp = &priv->con_priv[i]; 825 826 cp->idx = i < 2 ? 0 : i - 2; 827 cp->type = i < 2 ? i : IMX_MU_TYPE_RXDB; 828 cp->chan = &priv->mbox_chans[i]; 829 priv->mbox_chans[i].con_priv = cp; 830 snprintf(cp->irq_desc, sizeof(cp->irq_desc), 831 "%s[%i-%u]", dev_name(priv->dev), cp->type, cp->idx); 832 } 833 834 priv->mbox.num_chans = num_chans; 835 priv->mbox.of_xlate = imx_mu_specific_xlate; 836 837 /* Set default MU configuration */ 838 for (i = 0; i < IMX_MU_xCR_MAX; i++) 839 imx_mu_write(priv, 0, priv->dcfg->xCR[i]); 840 841 return 0; 842 } 843 844 static int imx_mu_init_seco(struct imx_mu_priv *priv) 845 { 846 int ret; 847 848 ret = imx_mu_init_generic(priv); 849 if (ret) 850 return ret; 851 priv->mbox.of_xlate = imx_mu_seco_xlate; 852 853 return 0; 854 } 855 856 static int imx_mu_probe(struct platform_device *pdev) 857 { 858 struct device *dev = &pdev->dev; 859 struct device_node *np = dev->of_node; 860 struct imx_mu_priv *priv; 861 const struct imx_mu_dcfg *dcfg; 862 int i, ret; 863 u32 size; 864 865 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); 866 if (!priv) 867 return -ENOMEM; 868 869 priv->dev = dev; 870 871 priv->base = devm_platform_ioremap_resource(pdev, 0); 872 if (IS_ERR(priv->base)) 873 return PTR_ERR(priv->base); 874 875 dcfg = of_device_get_match_data(dev); 876 if (!dcfg) 877 return -EINVAL; 878 priv->dcfg = dcfg; 879 if (priv->dcfg->type & IMX_MU_V2_IRQ) { 880 priv->irq[IMX_MU_TYPE_TX] = platform_get_irq_byname(pdev, "tx"); 881 if (priv->irq[IMX_MU_TYPE_TX] < 0) 882 return priv->irq[IMX_MU_TYPE_TX]; 883 priv->irq[IMX_MU_TYPE_RX] = platform_get_irq_byname(pdev, "rx"); 884 if (priv->irq[IMX_MU_TYPE_RX] < 0) 885 return priv->irq[IMX_MU_TYPE_RX]; 886 } else { 887 ret = platform_get_irq(pdev, 0); 888 if (ret < 0) 889 return ret; 890 891 for (i = 0; i < IMX_MU_CHANS; i++) 892 priv->irq[i] = ret; 893 } 894 895 if (priv->dcfg->type & IMX_MU_V2_S4) 896 size = sizeof(struct imx_s4_rpc_msg_max); 897 else 898 size = sizeof(struct imx_sc_rpc_msg_max); 899 900 priv->msg = devm_kzalloc(dev, size, GFP_KERNEL); 901 if (!priv->msg) 902 return -ENOMEM; 903 904 priv->clk = devm_clk_get(dev, NULL); 905 if (IS_ERR(priv->clk)) { 906 if (PTR_ERR(priv->clk) != -ENOENT) 907 return PTR_ERR(priv->clk); 908 909 priv->clk = NULL; 910 } 911 912 ret = clk_prepare_enable(priv->clk); 913 if (ret) { 914 dev_err(dev, "Failed to enable clock\n"); 915 return ret; 916 } 917 918 imx_mu_get_tr_rr(priv); 919 920 priv->side_b = of_property_read_bool(np, "fsl,mu-side-b"); 921 922 ret = priv->dcfg->init(priv); 923 if (ret) { 924 dev_err(dev, "Failed to init MU\n"); 925 goto disable_clk; 926 } 927 928 spin_lock_init(&priv->xcr_lock); 929 930 priv->mbox.dev = dev; 931 priv->mbox.ops = &imx_mu_ops; 932 priv->mbox.chans = priv->mbox_chans; 933 priv->mbox.txdone_irq = true; 934 935 platform_set_drvdata(pdev, priv); 936 937 ret = devm_mbox_controller_register(dev, &priv->mbox); 938 if (ret) 939 goto disable_clk; 940 941 of_platform_populate(dev->of_node, NULL, NULL, dev); 942 943 pm_runtime_enable(dev); 944 945 ret = pm_runtime_resume_and_get(dev); 946 if (ret < 0) 947 goto disable_runtime_pm; 948 949 ret = pm_runtime_put_sync(dev); 950 if (ret < 0) 951 goto disable_runtime_pm; 952 953 clk_disable_unprepare(priv->clk); 954 955 return 0; 956 957 disable_runtime_pm: 958 pm_runtime_disable(dev); 959 disable_clk: 960 clk_disable_unprepare(priv->clk); 961 return ret; 962 } 963 964 static void imx_mu_remove(struct platform_device *pdev) 965 { 966 struct imx_mu_priv *priv = platform_get_drvdata(pdev); 967 968 pm_runtime_disable(priv->dev); 969 } 970 971 static const struct imx_mu_dcfg imx_mu_cfg_imx6sx = { 972 .tx = imx_mu_generic_tx, 973 .rx = imx_mu_generic_rx, 974 .rxdb = imx_mu_generic_rxdb, 975 .init = imx_mu_init_generic, 976 .xTR = 0x0, 977 .xRR = 0x10, 978 .xSR = {0x20, 0x20, 0x20, 0x20}, 979 .xCR = {0x24, 0x24, 0x24, 0x24, 0x24}, 980 }; 981 982 static const struct imx_mu_dcfg imx_mu_cfg_imx7ulp = { 983 .tx = imx_mu_generic_tx, 984 .rx = imx_mu_generic_rx, 985 .rxdb = imx_mu_generic_rxdb, 986 .init = imx_mu_init_generic, 987 .xTR = 0x20, 988 .xRR = 0x40, 989 .xSR = {0x60, 0x60, 0x60, 0x60}, 990 .xCR = {0x64, 0x64, 0x64, 0x64, 0x64}, 991 }; 992 993 static const struct imx_mu_dcfg imx_mu_cfg_imx8ulp = { 994 .tx = imx_mu_generic_tx, 995 .rx = imx_mu_generic_rx, 996 .rxdb = imx_mu_generic_rxdb, 997 .init = imx_mu_init_generic, 998 .type = IMX_MU_V2, 999 .xTR = 0x200, 1000 .xRR = 0x280, 1001 .xSR = {0xC, 0x118, 0x124, 0x12C}, 1002 .xCR = {0x8, 0x110, 0x114, 0x120, 0x128}, 1003 }; 1004 1005 static const struct imx_mu_dcfg imx_mu_cfg_imx8ulp_s4 = { 1006 .tx = imx_mu_specific_tx, 1007 .rx = imx_mu_specific_rx, 1008 .init = imx_mu_init_specific, 1009 .type = IMX_MU_V2 | IMX_MU_V2_S4, 1010 .xTR = 0x200, 1011 .xRR = 0x280, 1012 .xSR = {0xC, 0x118, 0x124, 0x12C}, 1013 .xCR = {0x8, 0x110, 0x114, 0x120, 0x128}, 1014 }; 1015 1016 static const struct imx_mu_dcfg imx_mu_cfg_imx93_s4 = { 1017 .tx = imx_mu_specific_tx, 1018 .rx = imx_mu_specific_rx, 1019 .init = imx_mu_init_specific, 1020 .type = IMX_MU_V2 | IMX_MU_V2_S4 | IMX_MU_V2_IRQ, 1021 .xTR = 0x200, 1022 .xRR = 0x280, 1023 .xSR = {0xC, 0x118, 0x124, 0x12C}, 1024 .xCR = {0x8, 0x110, 0x114, 0x120, 0x128}, 1025 }; 1026 1027 static const struct imx_mu_dcfg imx_mu_cfg_imx8_scu = { 1028 .tx = imx_mu_specific_tx, 1029 .rx = imx_mu_specific_rx, 1030 .init = imx_mu_init_specific, 1031 .rxdb = imx_mu_generic_rxdb, 1032 .xTR = 0x0, 1033 .xRR = 0x10, 1034 .xSR = {0x20, 0x20, 0x20, 0x20}, 1035 .xCR = {0x24, 0x24, 0x24, 0x24, 0x24}, 1036 }; 1037 1038 static const struct imx_mu_dcfg imx_mu_cfg_imx8_seco = { 1039 .tx = imx_mu_seco_tx, 1040 .rx = imx_mu_generic_rx, 1041 .rxdb = imx_mu_seco_rxdb, 1042 .init = imx_mu_init_seco, 1043 .xTR = 0x0, 1044 .xRR = 0x10, 1045 .xSR = {0x20, 0x20, 0x20, 0x20}, 1046 .xCR = {0x24, 0x24, 0x24, 0x24, 0x24}, 1047 }; 1048 1049 static const struct of_device_id imx_mu_dt_ids[] = { 1050 { .compatible = "fsl,imx7ulp-mu", .data = &imx_mu_cfg_imx7ulp }, 1051 { .compatible = "fsl,imx6sx-mu", .data = &imx_mu_cfg_imx6sx }, 1052 { .compatible = "fsl,imx8ulp-mu", .data = &imx_mu_cfg_imx8ulp }, 1053 { .compatible = "fsl,imx8ulp-mu-s4", .data = &imx_mu_cfg_imx8ulp_s4 }, 1054 { .compatible = "fsl,imx93-mu-s4", .data = &imx_mu_cfg_imx93_s4 }, 1055 { .compatible = "fsl,imx95-mu", .data = &imx_mu_cfg_imx8ulp }, 1056 { .compatible = "fsl,imx95-mu-ele", .data = &imx_mu_cfg_imx8ulp_s4 }, 1057 { .compatible = "fsl,imx95-mu-v2x", .data = &imx_mu_cfg_imx8ulp_s4 }, 1058 { .compatible = "fsl,imx8-mu-scu", .data = &imx_mu_cfg_imx8_scu }, 1059 { .compatible = "fsl,imx8-mu-seco", .data = &imx_mu_cfg_imx8_seco }, 1060 { }, 1061 }; 1062 MODULE_DEVICE_TABLE(of, imx_mu_dt_ids); 1063 1064 static int __maybe_unused imx_mu_suspend_noirq(struct device *dev) 1065 { 1066 struct imx_mu_priv *priv = dev_get_drvdata(dev); 1067 int i; 1068 1069 if (!priv->clk) { 1070 for (i = 0; i < IMX_MU_xCR_MAX; i++) 1071 priv->xcr[i] = imx_mu_read(priv, priv->dcfg->xCR[i]); 1072 } 1073 1074 priv->suspend = true; 1075 1076 return 0; 1077 } 1078 1079 static int __maybe_unused imx_mu_resume_noirq(struct device *dev) 1080 { 1081 struct imx_mu_priv *priv = dev_get_drvdata(dev); 1082 int i; 1083 1084 /* 1085 * ONLY restore MU when context lost, the TIE could 1086 * be set during noirq resume as there is MU data 1087 * communication going on, and restore the saved 1088 * value will overwrite the TIE and cause MU data 1089 * send failed, may lead to system freeze. This issue 1090 * is observed by testing freeze mode suspend. 1091 */ 1092 if (!priv->clk && !imx_mu_read(priv, priv->dcfg->xCR[0])) { 1093 for (i = 0; i < IMX_MU_xCR_MAX; i++) 1094 imx_mu_write(priv, priv->xcr[i], priv->dcfg->xCR[i]); 1095 } 1096 1097 priv->suspend = false; 1098 1099 return 0; 1100 } 1101 1102 static int __maybe_unused imx_mu_runtime_suspend(struct device *dev) 1103 { 1104 struct imx_mu_priv *priv = dev_get_drvdata(dev); 1105 1106 clk_disable_unprepare(priv->clk); 1107 1108 return 0; 1109 } 1110 1111 static int __maybe_unused imx_mu_runtime_resume(struct device *dev) 1112 { 1113 struct imx_mu_priv *priv = dev_get_drvdata(dev); 1114 int ret; 1115 1116 ret = clk_prepare_enable(priv->clk); 1117 if (ret) 1118 dev_err(dev, "failed to enable clock\n"); 1119 1120 return ret; 1121 } 1122 1123 static const struct dev_pm_ops imx_mu_pm_ops = { 1124 SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(imx_mu_suspend_noirq, 1125 imx_mu_resume_noirq) 1126 SET_RUNTIME_PM_OPS(imx_mu_runtime_suspend, 1127 imx_mu_runtime_resume, NULL) 1128 }; 1129 1130 static struct platform_driver imx_mu_driver = { 1131 .probe = imx_mu_probe, 1132 .remove = imx_mu_remove, 1133 .driver = { 1134 .name = "imx_mu", 1135 .of_match_table = imx_mu_dt_ids, 1136 .pm = &imx_mu_pm_ops, 1137 }, 1138 }; 1139 module_platform_driver(imx_mu_driver); 1140 1141 MODULE_AUTHOR("Oleksij Rempel <o.rempel@pengutronix.de>"); 1142 MODULE_DESCRIPTION("Message Unit driver for i.MX"); 1143 MODULE_LICENSE("GPL v2"); 1144