1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (c) 2018 Pengutronix, Oleksij Rempel <o.rempel@pengutronix.de> 4 * Copyright 2022 NXP, Peng Fan <peng.fan@nxp.com> 5 */ 6 7 #include <linux/bitfield.h> 8 #include <linux/clk.h> 9 #include <linux/firmware/imx/ipc.h> 10 #include <linux/firmware/imx/s4.h> 11 #include <linux/interrupt.h> 12 #include <linux/io.h> 13 #include <linux/iopoll.h> 14 #include <linux/jiffies.h> 15 #include <linux/kernel.h> 16 #include <linux/mailbox_controller.h> 17 #include <linux/module.h> 18 #include <linux/of.h> 19 #include <linux/of_platform.h> 20 #include <linux/platform_device.h> 21 #include <linux/pm_runtime.h> 22 #include <linux/suspend.h> 23 #include <linux/slab.h> 24 #include <linux/workqueue.h> 25 26 #define IMX_MU_CHANS 24 27 /* TX0/RX0/RXDB[0-3] */ 28 #define IMX_MU_SCU_CHANS 6 29 /* TX0/RX0 */ 30 #define IMX_MU_S4_CHANS 2 31 #define IMX_MU_CHAN_NAME_SIZE 32 32 33 #define IMX_MU_V2_PAR_OFF 0x4 34 #define IMX_MU_V2_TR_MASK GENMASK(7, 0) 35 #define IMX_MU_V2_RR_MASK GENMASK(15, 8) 36 37 #define IMX_MU_SECO_TX_TOUT (msecs_to_jiffies(3000)) 38 #define IMX_MU_SECO_RX_TOUT (msecs_to_jiffies(3000)) 39 40 /* Please not change TX & RX */ 41 enum imx_mu_chan_type { 42 IMX_MU_TYPE_TX = 0, /* Tx */ 43 IMX_MU_TYPE_RX = 1, /* Rx */ 44 IMX_MU_TYPE_TXDB = 2, /* Tx doorbell */ 45 IMX_MU_TYPE_RXDB = 3, /* Rx doorbell */ 46 IMX_MU_TYPE_RST = 4, /* Reset */ 47 IMX_MU_TYPE_TXDB_V2 = 5, /* Tx doorbell with S/W ACK */ 48 }; 49 50 enum imx_mu_xcr { 51 IMX_MU_CR, 52 IMX_MU_GIER, 53 IMX_MU_GCR, 54 IMX_MU_TCR, 55 IMX_MU_RCR, 56 IMX_MU_xCR_MAX, 57 }; 58 59 enum imx_mu_xsr { 60 IMX_MU_SR, 61 IMX_MU_GSR, 62 IMX_MU_TSR, 63 IMX_MU_RSR, 64 IMX_MU_xSR_MAX, 65 }; 66 67 struct imx_sc_rpc_msg_max { 68 struct imx_sc_rpc_msg hdr; 69 u32 data[30]; 70 }; 71 72 struct imx_s4_rpc_msg_max { 73 struct imx_s4_rpc_msg hdr; 74 u32 data[254]; 75 }; 76 77 struct imx_mu_con_priv { 78 unsigned int idx; 79 char irq_desc[IMX_MU_CHAN_NAME_SIZE]; 80 enum imx_mu_chan_type type; 81 struct mbox_chan *chan; 82 struct work_struct txdb_work; 83 bool shutdown; 84 }; 85 86 struct imx_mu_priv { 87 struct device *dev; 88 void __iomem *base; 89 void *msg; 90 raw_spinlock_t xcr_lock; /* control register lock */ 91 92 struct mbox_controller mbox; 93 struct mbox_chan mbox_chans[IMX_MU_CHANS]; 94 95 struct imx_mu_con_priv con_priv[IMX_MU_CHANS]; 96 const struct imx_mu_dcfg *dcfg; 97 struct clk *clk; 98 int irq[IMX_MU_CHANS]; 99 bool suspend; 100 bool side_b; 101 102 u32 xcr[IMX_MU_xCR_MAX]; 103 u32 num_tr; 104 u32 num_rr; 105 }; 106 107 enum imx_mu_type { 108 IMX_MU_V1, 109 IMX_MU_V2 = BIT(1), 110 IMX_MU_V2_S4 = BIT(15), 111 IMX_MU_V2_IRQ = BIT(16), 112 }; 113 114 struct imx_mu_dcfg { 115 int (*tx)(struct imx_mu_priv *priv, struct imx_mu_con_priv *cp, void *data); 116 int (*rx)(struct imx_mu_priv *priv, struct imx_mu_con_priv *cp); 117 int (*rxdb)(struct imx_mu_priv *priv, struct imx_mu_con_priv *cp); 118 int (*init)(struct imx_mu_priv *priv); 119 enum imx_mu_type type; 120 u32 xTR; /* Transmit Register0 */ 121 u32 xRR; /* Receive Register0 */ 122 u32 xSR[IMX_MU_xSR_MAX]; /* Status Registers */ 123 u32 xCR[IMX_MU_xCR_MAX]; /* Control Registers */ 124 bool skip_suspend_flag; 125 }; 126 127 #define IMX_MU_xSR_GIPn(type, x) (type & IMX_MU_V2 ? BIT(x) : BIT(28 + (3 - (x)))) 128 #define IMX_MU_xSR_RFn(type, x) (type & IMX_MU_V2 ? BIT(x) : BIT(24 + (3 - (x)))) 129 #define IMX_MU_xSR_TEn(type, x) (type & IMX_MU_V2 ? BIT(x) : BIT(20 + (3 - (x)))) 130 131 /* General Purpose Interrupt Enable */ 132 #define IMX_MU_xCR_GIEn(type, x) (type & IMX_MU_V2 ? BIT(x) : BIT(28 + (3 - (x)))) 133 /* Receive Interrupt Enable */ 134 #define IMX_MU_xCR_RIEn(type, x) (type & IMX_MU_V2 ? BIT(x) : BIT(24 + (3 - (x)))) 135 /* Transmit Interrupt Enable */ 136 #define IMX_MU_xCR_TIEn(type, x) (type & IMX_MU_V2 ? BIT(x) : BIT(20 + (3 - (x)))) 137 /* General Purpose Interrupt Request */ 138 #define IMX_MU_xCR_GIRn(type, x) (type & IMX_MU_V2 ? BIT(x) : BIT(16 + (3 - (x)))) 139 /* MU reset */ 140 #define IMX_MU_xCR_RST(type) (type & IMX_MU_V2 ? BIT(0) : BIT(5)) 141 #define IMX_MU_xSR_RST(type) (type & IMX_MU_V2 ? BIT(0) : BIT(7)) 142 143 144 static struct imx_mu_priv *to_imx_mu_priv(struct mbox_controller *mbox) 145 { 146 return container_of(mbox, struct imx_mu_priv, mbox); 147 } 148 149 static void imx_mu_write(struct imx_mu_priv *priv, u32 val, u32 offs) 150 { 151 iowrite32(val, priv->base + offs); 152 } 153 154 static u32 imx_mu_read(struct imx_mu_priv *priv, u32 offs) 155 { 156 return ioread32(priv->base + offs); 157 } 158 159 static int imx_mu_tx_waiting_write(struct imx_mu_priv *priv, u32 val, u32 idx) 160 { 161 u64 timeout_time = get_jiffies_64() + IMX_MU_SECO_TX_TOUT; 162 u32 status; 163 u32 can_write; 164 165 dev_dbg(priv->dev, "Trying to write %.8x to idx %d\n", val, idx); 166 167 do { 168 status = imx_mu_read(priv, priv->dcfg->xSR[IMX_MU_TSR]); 169 can_write = status & IMX_MU_xSR_TEn(priv->dcfg->type, idx % 4); 170 } while (!can_write && time_is_after_jiffies64(timeout_time)); 171 172 if (!can_write) { 173 dev_err(priv->dev, "timeout trying to write %.8x at %d(%.8x)\n", 174 val, idx, status); 175 return -ETIME; 176 } 177 178 imx_mu_write(priv, val, priv->dcfg->xTR + (idx % 4) * 4); 179 180 return 0; 181 } 182 183 static int imx_mu_rx_waiting_read(struct imx_mu_priv *priv, u32 *val, u32 idx) 184 { 185 u64 timeout_time = get_jiffies_64() + IMX_MU_SECO_RX_TOUT; 186 u32 status; 187 u32 can_read; 188 189 dev_dbg(priv->dev, "Trying to read from idx %d\n", idx); 190 191 do { 192 status = imx_mu_read(priv, priv->dcfg->xSR[IMX_MU_RSR]); 193 can_read = status & IMX_MU_xSR_RFn(priv->dcfg->type, idx % 4); 194 } while (!can_read && time_is_after_jiffies64(timeout_time)); 195 196 if (!can_read) { 197 dev_err(priv->dev, "timeout trying to read idx %d (%.8x)\n", 198 idx, status); 199 return -ETIME; 200 } 201 202 *val = imx_mu_read(priv, priv->dcfg->xRR + (idx % 4) * 4); 203 dev_dbg(priv->dev, "Read %.8x\n", *val); 204 205 return 0; 206 } 207 208 static u32 imx_mu_xcr_rmw(struct imx_mu_priv *priv, enum imx_mu_xcr type, u32 set, u32 clr) 209 { 210 u32 val; 211 212 guard(raw_spinlock_irqsave)(&priv->xcr_lock); 213 214 val = imx_mu_read(priv, priv->dcfg->xCR[type]); 215 val &= ~clr; 216 val |= set; 217 imx_mu_write(priv, val, priv->dcfg->xCR[type]); 218 219 return val; 220 } 221 222 static void imx_mu_xcr_clr_shut(struct imx_mu_priv *priv, struct imx_mu_con_priv *cp, 223 enum imx_mu_xcr type, u32 clr) 224 { 225 u32 val; 226 227 guard(raw_spinlock_irqsave)(&priv->xcr_lock); 228 cp->shutdown = true; 229 230 val = imx_mu_read(priv, priv->dcfg->xCR[type]); 231 val &= ~clr; 232 imx_mu_write(priv, val, priv->dcfg->xCR[type]); 233 } 234 235 static void imx_mu_xcr_set_act(struct imx_mu_priv *priv, struct imx_mu_con_priv *cp, 236 enum imx_mu_xcr type, u32 set) 237 { 238 u32 val; 239 240 guard(raw_spinlock_irqsave)(&priv->xcr_lock); 241 if (!cp->shutdown) { 242 val = imx_mu_read(priv, priv->dcfg->xCR[type]); 243 val |= set; 244 imx_mu_write(priv, val, priv->dcfg->xCR[type]); 245 } 246 } 247 248 static int imx_mu_generic_tx(struct imx_mu_priv *priv, 249 struct imx_mu_con_priv *cp, 250 void *data) 251 { 252 u32 *arg = data; 253 u32 val; 254 int ret, count; 255 256 ret = 0; 257 switch (cp->type) { 258 case IMX_MU_TYPE_TX: 259 imx_mu_write(priv, *arg, priv->dcfg->xTR + cp->idx * 4); 260 imx_mu_xcr_rmw(priv, IMX_MU_TCR, IMX_MU_xCR_TIEn(priv->dcfg->type, cp->idx), 0); 261 break; 262 case IMX_MU_TYPE_TXDB: 263 imx_mu_xcr_rmw(priv, IMX_MU_GCR, IMX_MU_xCR_GIRn(priv->dcfg->type, cp->idx), 0); 264 queue_work(system_bh_wq, &cp->txdb_work); 265 break; 266 case IMX_MU_TYPE_TXDB_V2: 267 imx_mu_write(priv, IMX_MU_xCR_GIRn(priv->dcfg->type, cp->idx), 268 priv->dcfg->xCR[IMX_MU_GCR]); 269 ret = -ETIMEDOUT; 270 count = 0; 271 while (ret && (count < 10)) { 272 ret = 273 readl_poll_timeout(priv->base + priv->dcfg->xCR[IMX_MU_GCR], val, 274 !(val & IMX_MU_xCR_GIRn(priv->dcfg->type, cp->idx)), 275 0, 10000); 276 277 if (ret) { 278 dev_warn_ratelimited(priv->dev, 279 "channel type: %d timeout, %d times, retry\n", 280 cp->type, ++count); 281 } 282 } 283 break; 284 default: 285 dev_warn_ratelimited(priv->dev, "Send data on wrong channel type: %d\n", cp->type); 286 return -EINVAL; 287 } 288 289 return ret; 290 } 291 292 static int imx_mu_generic_rx(struct imx_mu_priv *priv, 293 struct imx_mu_con_priv *cp) 294 { 295 u32 dat; 296 297 dat = imx_mu_read(priv, priv->dcfg->xRR + (cp->idx) * 4); 298 mbox_chan_received_data(cp->chan, (void *)&dat); 299 300 return 0; 301 } 302 303 static int imx_mu_generic_rxdb(struct imx_mu_priv *priv, 304 struct imx_mu_con_priv *cp) 305 { 306 imx_mu_write(priv, IMX_MU_xSR_GIPn(priv->dcfg->type, cp->idx), 307 priv->dcfg->xSR[IMX_MU_GSR]); 308 mbox_chan_received_data(cp->chan, NULL); 309 310 return 0; 311 } 312 313 static int imx_mu_specific_tx(struct imx_mu_priv *priv, struct imx_mu_con_priv *cp, void *data) 314 { 315 u32 *arg = data; 316 u32 num_tr = priv->num_tr; 317 int i, ret; 318 u32 xsr; 319 u32 size, max_size; 320 321 if (priv->dcfg->type & IMX_MU_V2_S4) { 322 size = ((struct imx_s4_rpc_msg_max *)data)->hdr.size; 323 max_size = sizeof(struct imx_s4_rpc_msg_max); 324 } else { 325 size = ((struct imx_sc_rpc_msg_max *)data)->hdr.size; 326 max_size = sizeof(struct imx_sc_rpc_msg_max); 327 } 328 329 switch (cp->type) { 330 case IMX_MU_TYPE_TX: 331 /* 332 * msg->hdr.size specifies the number of u32 words while 333 * sizeof yields bytes. 334 */ 335 336 if (size > max_size / 4) { 337 /* 338 * The real message size can be different to 339 * struct imx_sc_rpc_msg_max/imx_s4_rpc_msg_max size 340 */ 341 dev_err(priv->dev, "Maximal message size (%u bytes) exceeded on TX; got: %i bytes\n", max_size, size << 2); 342 return -EINVAL; 343 } 344 345 for (i = 0; i < num_tr && i < size; i++) 346 imx_mu_write(priv, *arg++, priv->dcfg->xTR + (i % num_tr) * 4); 347 for (; i < size; i++) { 348 ret = readl_poll_timeout(priv->base + priv->dcfg->xSR[IMX_MU_TSR], 349 xsr, 350 xsr & IMX_MU_xSR_TEn(priv->dcfg->type, i % num_tr), 351 0, 5 * USEC_PER_SEC); 352 if (ret) { 353 dev_err(priv->dev, "Send data index: %d timeout\n", i); 354 return ret; 355 } 356 imx_mu_write(priv, *arg++, priv->dcfg->xTR + (i % num_tr) * 4); 357 } 358 359 imx_mu_xcr_rmw(priv, IMX_MU_TCR, IMX_MU_xCR_TIEn(priv->dcfg->type, cp->idx), 0); 360 break; 361 default: 362 dev_warn_ratelimited(priv->dev, "Send data on wrong channel type: %d\n", cp->type); 363 return -EINVAL; 364 } 365 366 return 0; 367 } 368 369 static int imx_mu_specific_rx(struct imx_mu_priv *priv, struct imx_mu_con_priv *cp) 370 { 371 u32 *data; 372 int i, ret; 373 u32 xsr; 374 u32 size, max_size; 375 u32 num_rr = priv->num_rr; 376 377 data = (u32 *)priv->msg; 378 379 *data++ = imx_mu_read(priv, priv->dcfg->xRR); 380 381 if (priv->dcfg->type & IMX_MU_V2_S4) { 382 size = ((struct imx_s4_rpc_msg_max *)priv->msg)->hdr.size; 383 max_size = sizeof(struct imx_s4_rpc_msg_max); 384 } else { 385 size = ((struct imx_sc_rpc_msg_max *)priv->msg)->hdr.size; 386 max_size = sizeof(struct imx_sc_rpc_msg_max); 387 } 388 389 if (size > max_size / 4) { 390 dev_err(priv->dev, "Maximal message size (%u bytes) exceeded on RX; got: %i bytes\n", max_size, size << 2); 391 return -EINVAL; 392 } 393 394 for (i = 1; i < size; i++) { 395 ret = readl_poll_timeout(priv->base + priv->dcfg->xSR[IMX_MU_RSR], xsr, 396 xsr & IMX_MU_xSR_RFn(priv->dcfg->type, i % num_rr), 0, 397 5 * USEC_PER_SEC); 398 if (ret) { 399 dev_err(priv->dev, "timeout read idx %d\n", i); 400 return ret; 401 } 402 *data++ = imx_mu_read(priv, priv->dcfg->xRR + (i % num_rr) * 4); 403 } 404 405 mbox_chan_received_data(cp->chan, (void *)priv->msg); 406 407 return 0; 408 } 409 410 static int imx_mu_seco_tx(struct imx_mu_priv *priv, struct imx_mu_con_priv *cp, 411 void *data) 412 { 413 struct imx_sc_rpc_msg_max *msg = data; 414 u32 *arg = data; 415 u32 byte_size; 416 int err; 417 int i; 418 419 dev_dbg(priv->dev, "Sending message\n"); 420 421 switch (cp->type) { 422 case IMX_MU_TYPE_TXDB: 423 byte_size = msg->hdr.size * sizeof(u32); 424 if (byte_size > sizeof(*msg)) { 425 /* 426 * The real message size can be different to 427 * struct imx_sc_rpc_msg_max size 428 */ 429 dev_err(priv->dev, 430 "Exceed max msg size (%zu) on TX, got: %i\n", 431 sizeof(*msg), byte_size); 432 return -EINVAL; 433 } 434 435 print_hex_dump_debug("from client ", DUMP_PREFIX_OFFSET, 4, 4, 436 data, byte_size, false); 437 438 /* Send first word */ 439 dev_dbg(priv->dev, "Sending header\n"); 440 imx_mu_write(priv, *arg++, priv->dcfg->xTR); 441 442 /* Send signaling */ 443 dev_dbg(priv->dev, "Sending signaling\n"); 444 imx_mu_xcr_rmw(priv, IMX_MU_GCR, 445 IMX_MU_xCR_GIRn(priv->dcfg->type, cp->idx), 0); 446 447 /* Send words to fill the mailbox */ 448 for (i = 1; i < 4 && i < msg->hdr.size; i++) { 449 dev_dbg(priv->dev, "Sending word %d\n", i); 450 imx_mu_write(priv, *arg++, 451 priv->dcfg->xTR + (i % 4) * 4); 452 } 453 454 /* Send rest of message waiting for remote read */ 455 for (; i < msg->hdr.size; i++) { 456 dev_dbg(priv->dev, "Sending word %d\n", i); 457 err = imx_mu_tx_waiting_write(priv, *arg++, i); 458 if (err) { 459 dev_err(priv->dev, "Timeout tx %d\n", i); 460 return err; 461 } 462 } 463 464 /* Simulate hack for mbox framework */ 465 queue_work(system_bh_wq, &cp->txdb_work); 466 467 break; 468 default: 469 dev_warn_ratelimited(priv->dev, 470 "Send data on wrong channel type: %d\n", 471 cp->type); 472 return -EINVAL; 473 } 474 475 return 0; 476 } 477 478 static int imx_mu_seco_rxdb(struct imx_mu_priv *priv, struct imx_mu_con_priv *cp) 479 { 480 struct imx_sc_rpc_msg_max msg; 481 u32 *data = (u32 *)&msg; 482 u32 byte_size; 483 int err = 0; 484 int i; 485 486 dev_dbg(priv->dev, "Receiving message\n"); 487 488 /* Read header */ 489 dev_dbg(priv->dev, "Receiving header\n"); 490 *data++ = imx_mu_read(priv, priv->dcfg->xRR); 491 byte_size = msg.hdr.size * sizeof(u32); 492 if (byte_size > sizeof(msg)) { 493 dev_err(priv->dev, "Exceed max msg size (%zu) on RX, got: %i\n", 494 sizeof(msg), byte_size); 495 err = -EINVAL; 496 goto error; 497 } 498 499 /* Read message waiting they are written */ 500 for (i = 1; i < msg.hdr.size; i++) { 501 dev_dbg(priv->dev, "Receiving word %d\n", i); 502 err = imx_mu_rx_waiting_read(priv, data++, i); 503 if (err) { 504 dev_err(priv->dev, "Timeout rx %d\n", i); 505 goto error; 506 } 507 } 508 509 /* Clear GIP */ 510 imx_mu_write(priv, IMX_MU_xSR_GIPn(priv->dcfg->type, cp->idx), 511 priv->dcfg->xSR[IMX_MU_GSR]); 512 513 print_hex_dump_debug("to client ", DUMP_PREFIX_OFFSET, 4, 4, 514 &msg, byte_size, false); 515 516 /* send data to client */ 517 dev_dbg(priv->dev, "Sending message to client\n"); 518 mbox_chan_received_data(cp->chan, (void *)&msg); 519 520 goto exit; 521 522 error: 523 mbox_chan_received_data(cp->chan, ERR_PTR(err)); 524 525 exit: 526 return err; 527 } 528 529 static void imx_mu_txdb_work(struct work_struct *t) 530 { 531 struct imx_mu_con_priv *cp = from_work(cp, t, txdb_work); 532 533 mbox_chan_txdone(cp->chan, 0); 534 } 535 536 static irqreturn_t imx_mu_isr_th(int irq, void *p) 537 { 538 struct mbox_chan *chan = p; 539 struct imx_mu_priv *priv = to_imx_mu_priv(chan->mbox); 540 struct imx_mu_con_priv *cp = chan->con_priv; 541 542 switch (cp->type) { 543 case IMX_MU_TYPE_TX: 544 mbox_chan_txdone(chan, 0); 545 break; 546 547 case IMX_MU_TYPE_RX: 548 if (!priv->dcfg->rx(priv, cp)) 549 imx_mu_xcr_set_act(priv, cp, IMX_MU_RCR, IMX_MU_xCR_RIEn(priv->dcfg->type, cp->idx)); 550 break; 551 552 case IMX_MU_TYPE_RXDB: 553 if (!priv->dcfg->rxdb(priv, cp)) 554 imx_mu_xcr_set_act(priv, cp, IMX_MU_GIER, IMX_MU_xCR_GIEn(priv->dcfg->type, cp->idx)); 555 break; 556 557 default: 558 dev_warn_ratelimited(priv->dev, "Unhandled channel type %d\n", 559 cp->type); 560 return IRQ_NONE; 561 } 562 return IRQ_HANDLED; 563 } 564 565 static irqreturn_t imx_mu_isr(int irq, void *p) 566 { 567 struct mbox_chan *chan = p; 568 struct imx_mu_priv *priv = to_imx_mu_priv(chan->mbox); 569 struct imx_mu_con_priv *cp = chan->con_priv; 570 irqreturn_t ret = IRQ_HANDLED; 571 u32 val, ctrl; 572 573 switch (cp->type) { 574 case IMX_MU_TYPE_TX: 575 ctrl = imx_mu_read(priv, priv->dcfg->xCR[IMX_MU_TCR]); 576 val = imx_mu_read(priv, priv->dcfg->xSR[IMX_MU_TSR]); 577 val &= IMX_MU_xSR_TEn(priv->dcfg->type, cp->idx) & 578 (ctrl & IMX_MU_xCR_TIEn(priv->dcfg->type, cp->idx)); 579 break; 580 case IMX_MU_TYPE_RX: 581 ctrl = imx_mu_read(priv, priv->dcfg->xCR[IMX_MU_RCR]); 582 val = imx_mu_read(priv, priv->dcfg->xSR[IMX_MU_RSR]); 583 val &= IMX_MU_xSR_RFn(priv->dcfg->type, cp->idx) & 584 (ctrl & IMX_MU_xCR_RIEn(priv->dcfg->type, cp->idx)); 585 break; 586 case IMX_MU_TYPE_RXDB: 587 ctrl = imx_mu_read(priv, priv->dcfg->xCR[IMX_MU_GIER]); 588 val = imx_mu_read(priv, priv->dcfg->xSR[IMX_MU_GSR]); 589 val &= IMX_MU_xSR_GIPn(priv->dcfg->type, cp->idx) & 590 (ctrl & IMX_MU_xCR_GIEn(priv->dcfg->type, cp->idx)); 591 break; 592 case IMX_MU_TYPE_RST: 593 return IRQ_NONE; 594 default: 595 dev_warn_ratelimited(priv->dev, "Unhandled channel type %d\n", 596 cp->type); 597 return IRQ_NONE; 598 } 599 600 if (!val) 601 return IRQ_NONE; 602 603 if ((val == IMX_MU_xSR_TEn(priv->dcfg->type, cp->idx)) && 604 (cp->type == IMX_MU_TYPE_TX)) { 605 imx_mu_xcr_rmw(priv, IMX_MU_TCR, 0, IMX_MU_xCR_TIEn(priv->dcfg->type, cp->idx)); 606 ret = IRQ_WAKE_THREAD; 607 } else if ((val == IMX_MU_xSR_RFn(priv->dcfg->type, cp->idx)) && 608 (cp->type == IMX_MU_TYPE_RX)) { 609 imx_mu_xcr_rmw(priv, IMX_MU_RCR, 0, IMX_MU_xCR_RIEn(priv->dcfg->type, cp->idx)); 610 ret = IRQ_WAKE_THREAD; 611 } else if ((val == IMX_MU_xSR_GIPn(priv->dcfg->type, cp->idx)) && 612 (cp->type == IMX_MU_TYPE_RXDB)) { 613 imx_mu_xcr_rmw(priv, IMX_MU_GIER, 0, IMX_MU_xCR_GIEn(priv->dcfg->type, cp->idx)); 614 ret = IRQ_WAKE_THREAD; 615 } else { 616 dev_warn_ratelimited(priv->dev, "Not handled interrupt\n"); 617 return IRQ_NONE; 618 } 619 620 if (priv->suspend) 621 pm_system_wakeup(); 622 623 return ret; 624 } 625 626 static int imx_mu_send_data(struct mbox_chan *chan, void *data) 627 { 628 struct imx_mu_priv *priv = to_imx_mu_priv(chan->mbox); 629 struct imx_mu_con_priv *cp = chan->con_priv; 630 631 return priv->dcfg->tx(priv, cp, data); 632 } 633 634 static int imx_mu_startup(struct mbox_chan *chan) 635 { 636 struct imx_mu_priv *priv = to_imx_mu_priv(chan->mbox); 637 struct imx_mu_con_priv *cp = chan->con_priv; 638 unsigned long irq_flag = IRQF_NO_THREAD; 639 int ret; 640 641 pm_runtime_get_sync(priv->dev); 642 if (cp->type == IMX_MU_TYPE_TXDB_V2) 643 return 0; 644 645 if (cp->type == IMX_MU_TYPE_TXDB) { 646 /* Tx doorbell don't have ACK support */ 647 INIT_WORK(&cp->txdb_work, imx_mu_txdb_work); 648 return 0; 649 } 650 651 /* IPC MU should be with IRQF_NO_SUSPEND set */ 652 if (!priv->dev->pm_domain) 653 irq_flag |= IRQF_NO_SUSPEND; 654 655 if (!(priv->dcfg->type & IMX_MU_V2_IRQ)) 656 irq_flag |= IRQF_SHARED; 657 658 ret = request_threaded_irq(priv->irq[cp->type], imx_mu_isr, imx_mu_isr_th, 659 irq_flag, cp->irq_desc, chan); 660 if (ret) { 661 dev_err(priv->dev, "Unable to acquire IRQ %d\n", priv->irq[cp->type]); 662 return ret; 663 } 664 665 cp->shutdown = false; 666 switch (cp->type) { 667 case IMX_MU_TYPE_RX: 668 imx_mu_xcr_rmw(priv, IMX_MU_RCR, IMX_MU_xCR_RIEn(priv->dcfg->type, cp->idx), 0); 669 break; 670 case IMX_MU_TYPE_RXDB: 671 imx_mu_xcr_rmw(priv, IMX_MU_GIER, IMX_MU_xCR_GIEn(priv->dcfg->type, cp->idx), 0); 672 break; 673 default: 674 break; 675 } 676 677 return 0; 678 } 679 680 static void imx_mu_shutdown(struct mbox_chan *chan) 681 { 682 struct imx_mu_priv *priv = to_imx_mu_priv(chan->mbox); 683 struct imx_mu_con_priv *cp = chan->con_priv; 684 int ret; 685 u32 sr; 686 687 if (cp->type == IMX_MU_TYPE_TXDB_V2) { 688 pm_runtime_put_sync(priv->dev); 689 return; 690 } 691 692 if (cp->type == IMX_MU_TYPE_TXDB) { 693 cancel_work_sync(&cp->txdb_work); 694 pm_runtime_put_sync(priv->dev); 695 return; 696 } 697 698 switch (cp->type) { 699 case IMX_MU_TYPE_TX: 700 imx_mu_xcr_clr_shut(priv, cp, IMX_MU_TCR, IMX_MU_xCR_TIEn(priv->dcfg->type, cp->idx)); 701 break; 702 case IMX_MU_TYPE_RX: 703 imx_mu_xcr_clr_shut(priv, cp, IMX_MU_RCR, IMX_MU_xCR_RIEn(priv->dcfg->type, cp->idx)); 704 break; 705 case IMX_MU_TYPE_RXDB: 706 imx_mu_xcr_clr_shut(priv, cp, IMX_MU_GIER, IMX_MU_xCR_GIEn(priv->dcfg->type, cp->idx)); 707 break; 708 case IMX_MU_TYPE_RST: 709 imx_mu_xcr_rmw(priv, IMX_MU_CR, IMX_MU_xCR_RST(priv->dcfg->type), 0); 710 ret = readl_poll_timeout(priv->base + priv->dcfg->xSR[IMX_MU_SR], sr, 711 !(sr & IMX_MU_xSR_RST(priv->dcfg->type)), 1, 5); 712 if (ret) 713 dev_warn(priv->dev, "RST channel timeout\n"); 714 break; 715 default: 716 break; 717 } 718 719 free_irq(priv->irq[cp->type], chan); 720 pm_runtime_put_sync(priv->dev); 721 } 722 723 static const struct mbox_chan_ops imx_mu_ops = { 724 .send_data = imx_mu_send_data, 725 .startup = imx_mu_startup, 726 .shutdown = imx_mu_shutdown, 727 }; 728 729 static struct mbox_chan *imx_mu_specific_xlate(struct mbox_controller *mbox, 730 const struct of_phandle_args *sp) 731 { 732 u32 type, idx, chan; 733 734 if (sp->args_count != 2) { 735 dev_err(mbox->dev, "Invalid argument count %d\n", sp->args_count); 736 return ERR_PTR(-EINVAL); 737 } 738 739 type = sp->args[0]; /* channel type */ 740 idx = sp->args[1]; /* index */ 741 742 switch (type) { 743 case IMX_MU_TYPE_TX: 744 case IMX_MU_TYPE_RX: 745 if (idx != 0) 746 dev_err(mbox->dev, "Invalid chan idx: %d\n", idx); 747 chan = type; 748 break; 749 case IMX_MU_TYPE_RXDB: 750 chan = 2 + idx; 751 break; 752 default: 753 dev_err(mbox->dev, "Invalid chan type: %d\n", type); 754 return ERR_PTR(-EINVAL); 755 } 756 757 if (chan >= mbox->num_chans) { 758 dev_err(mbox->dev, "Not supported channel number: %d. (type: %d, idx: %d)\n", chan, type, idx); 759 return ERR_PTR(-EINVAL); 760 } 761 762 return &mbox->chans[chan]; 763 } 764 765 static struct mbox_chan * imx_mu_xlate(struct mbox_controller *mbox, 766 const struct of_phandle_args *sp) 767 { 768 struct mbox_chan *p_chan; 769 u32 type, idx, chan; 770 771 if (sp->args_count != 2) { 772 dev_err(mbox->dev, "Invalid argument count %d\n", sp->args_count); 773 return ERR_PTR(-EINVAL); 774 } 775 776 type = sp->args[0]; /* channel type */ 777 idx = sp->args[1]; /* index */ 778 779 /* RST only supports 1 channel */ 780 if ((type == IMX_MU_TYPE_RST) && idx) { 781 dev_err(mbox->dev, "Invalid RST channel %d\n", idx); 782 return ERR_PTR(-EINVAL); 783 } 784 785 chan = type * 4 + idx; 786 if (chan >= mbox->num_chans) { 787 dev_err(mbox->dev, "Not supported channel number: %d. (type: %d, idx: %d)\n", chan, type, idx); 788 return ERR_PTR(-EINVAL); 789 } 790 791 p_chan = &mbox->chans[chan]; 792 793 if (type == IMX_MU_TYPE_TXDB_V2) 794 p_chan->txdone_method = MBOX_TXDONE_BY_ACK; 795 796 return p_chan; 797 } 798 799 static struct mbox_chan *imx_mu_seco_xlate(struct mbox_controller *mbox, 800 const struct of_phandle_args *sp) 801 { 802 u32 type; 803 804 if (sp->args_count < 1) { 805 dev_err(mbox->dev, "Invalid argument count %d\n", sp->args_count); 806 return ERR_PTR(-EINVAL); 807 } 808 809 type = sp->args[0]; /* channel type */ 810 811 /* Only supports TXDB and RXDB */ 812 if (type == IMX_MU_TYPE_TX || type == IMX_MU_TYPE_RX) { 813 dev_err(mbox->dev, "Invalid type: %d\n", type); 814 return ERR_PTR(-EINVAL); 815 } 816 817 return imx_mu_xlate(mbox, sp); 818 } 819 820 static void imx_mu_get_tr_rr(struct imx_mu_priv *priv) 821 { 822 u32 val; 823 824 if (priv->dcfg->type & IMX_MU_V2) { 825 val = imx_mu_read(priv, IMX_MU_V2_PAR_OFF); 826 priv->num_tr = FIELD_GET(IMX_MU_V2_TR_MASK, val); 827 priv->num_rr = FIELD_GET(IMX_MU_V2_RR_MASK, val); 828 } else { 829 priv->num_tr = 4; 830 priv->num_rr = 4; 831 } 832 } 833 834 static int imx_mu_init_generic(struct imx_mu_priv *priv) 835 { 836 unsigned int i; 837 unsigned int val; 838 839 if (priv->num_rr > 4 || priv->num_tr > 4) { 840 WARN_ONCE(true, "%s not support TR/RR larger than 4\n", __func__); 841 return -EOPNOTSUPP; 842 } 843 844 for (i = 0; i < IMX_MU_CHANS; i++) { 845 struct imx_mu_con_priv *cp = &priv->con_priv[i]; 846 847 cp->idx = i % 4; 848 cp->type = i >> 2; 849 cp->chan = &priv->mbox_chans[i]; 850 priv->mbox_chans[i].con_priv = cp; 851 snprintf(cp->irq_desc, sizeof(cp->irq_desc), 852 "%s[%i-%u]", dev_name(priv->dev), cp->type, cp->idx); 853 } 854 855 priv->mbox.num_chans = IMX_MU_CHANS; 856 priv->mbox.of_xlate = imx_mu_xlate; 857 858 if (priv->side_b) 859 return 0; 860 861 /* Set default MU configuration */ 862 for (i = 0; i < IMX_MU_xCR_MAX; i++) 863 imx_mu_write(priv, 0, priv->dcfg->xCR[i]); 864 865 /* Clear any pending GIP */ 866 val = imx_mu_read(priv, priv->dcfg->xSR[IMX_MU_GSR]); 867 imx_mu_write(priv, val, priv->dcfg->xSR[IMX_MU_GSR]); 868 869 /* Clear any pending RSR */ 870 for (i = 0; i < priv->num_rr; i++) 871 imx_mu_read(priv, priv->dcfg->xRR + i * 4); 872 873 return 0; 874 } 875 876 static int imx_mu_init_specific(struct imx_mu_priv *priv) 877 { 878 unsigned int i; 879 int num_chans = priv->dcfg->type & IMX_MU_V2_S4 ? IMX_MU_S4_CHANS : IMX_MU_SCU_CHANS; 880 881 for (i = 0; i < num_chans; i++) { 882 struct imx_mu_con_priv *cp = &priv->con_priv[i]; 883 884 cp->idx = i < 2 ? 0 : i - 2; 885 cp->type = i < 2 ? i : IMX_MU_TYPE_RXDB; 886 cp->chan = &priv->mbox_chans[i]; 887 priv->mbox_chans[i].con_priv = cp; 888 snprintf(cp->irq_desc, sizeof(cp->irq_desc), 889 "%s[%i-%u]", dev_name(priv->dev), cp->type, cp->idx); 890 } 891 892 priv->mbox.num_chans = num_chans; 893 priv->mbox.of_xlate = imx_mu_specific_xlate; 894 895 /* Set default MU configuration */ 896 for (i = 0; i < IMX_MU_xCR_MAX; i++) 897 imx_mu_write(priv, 0, priv->dcfg->xCR[i]); 898 899 return 0; 900 } 901 902 static int imx_mu_init_seco(struct imx_mu_priv *priv) 903 { 904 int ret; 905 906 ret = imx_mu_init_generic(priv); 907 if (ret) 908 return ret; 909 priv->mbox.of_xlate = imx_mu_seco_xlate; 910 911 return 0; 912 } 913 914 static int imx_mu_probe(struct platform_device *pdev) 915 { 916 struct device *dev = &pdev->dev; 917 struct device_node *np = dev->of_node; 918 struct imx_mu_priv *priv; 919 const struct imx_mu_dcfg *dcfg; 920 int i, ret; 921 u32 size; 922 923 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); 924 if (!priv) 925 return -ENOMEM; 926 927 priv->dev = dev; 928 929 priv->base = devm_platform_ioremap_resource(pdev, 0); 930 if (IS_ERR(priv->base)) 931 return PTR_ERR(priv->base); 932 933 dcfg = of_device_get_match_data(dev); 934 if (!dcfg) 935 return -EINVAL; 936 priv->dcfg = dcfg; 937 if (priv->dcfg->type & IMX_MU_V2_IRQ) { 938 priv->irq[IMX_MU_TYPE_TX] = platform_get_irq_byname(pdev, "tx"); 939 if (priv->irq[IMX_MU_TYPE_TX] < 0) 940 return priv->irq[IMX_MU_TYPE_TX]; 941 priv->irq[IMX_MU_TYPE_RX] = platform_get_irq_byname(pdev, "rx"); 942 if (priv->irq[IMX_MU_TYPE_RX] < 0) 943 return priv->irq[IMX_MU_TYPE_RX]; 944 } else { 945 ret = platform_get_irq(pdev, 0); 946 if (ret < 0) 947 return ret; 948 949 for (i = 0; i < IMX_MU_CHANS; i++) 950 priv->irq[i] = ret; 951 } 952 953 if (priv->dcfg->type & IMX_MU_V2_S4) 954 size = sizeof(struct imx_s4_rpc_msg_max); 955 else 956 size = sizeof(struct imx_sc_rpc_msg_max); 957 958 priv->msg = devm_kzalloc(dev, size, GFP_KERNEL); 959 if (!priv->msg) 960 return -ENOMEM; 961 962 priv->clk = devm_clk_get(dev, NULL); 963 if (IS_ERR(priv->clk)) { 964 if (PTR_ERR(priv->clk) != -ENOENT) 965 return PTR_ERR(priv->clk); 966 967 priv->clk = NULL; 968 } 969 970 ret = clk_prepare_enable(priv->clk); 971 if (ret) { 972 dev_err(dev, "Failed to enable clock\n"); 973 return ret; 974 } 975 976 imx_mu_get_tr_rr(priv); 977 978 priv->side_b = of_property_read_bool(np, "fsl,mu-side-b"); 979 980 ret = priv->dcfg->init(priv); 981 if (ret) { 982 dev_err(dev, "Failed to init MU\n"); 983 goto disable_clk; 984 } 985 986 raw_spin_lock_init(&priv->xcr_lock); 987 988 priv->mbox.dev = dev; 989 priv->mbox.ops = &imx_mu_ops; 990 priv->mbox.chans = priv->mbox_chans; 991 priv->mbox.txdone_irq = true; 992 993 platform_set_drvdata(pdev, priv); 994 995 ret = devm_pm_runtime_enable(dev); 996 if (ret < 0) 997 goto disable_clk; 998 999 ret = pm_runtime_resume_and_get(dev); 1000 if (ret < 0) 1001 goto disable_clk; 1002 1003 ret = pm_runtime_put_sync(dev); 1004 if (ret < 0) 1005 goto disable_clk; 1006 1007 clk_disable_unprepare(priv->clk); 1008 1009 ret = devm_mbox_controller_register(dev, &priv->mbox); 1010 if (ret) 1011 goto err_out; 1012 1013 devm_of_platform_populate(dev); 1014 1015 return 0; 1016 1017 disable_clk: 1018 clk_disable_unprepare(priv->clk); 1019 err_out: 1020 return ret; 1021 } 1022 1023 static void imx_mu_remove(struct platform_device *pdev) 1024 { 1025 } 1026 1027 static const struct imx_mu_dcfg imx_mu_cfg_imx6sx = { 1028 .tx = imx_mu_generic_tx, 1029 .rx = imx_mu_generic_rx, 1030 .rxdb = imx_mu_generic_rxdb, 1031 .init = imx_mu_init_generic, 1032 .xTR = 0x0, 1033 .xRR = 0x10, 1034 .xSR = {0x20, 0x20, 0x20, 0x20}, 1035 .xCR = {0x24, 0x24, 0x24, 0x24, 0x24}, 1036 }; 1037 1038 static const struct imx_mu_dcfg imx_mu_cfg_imx7ulp = { 1039 .tx = imx_mu_generic_tx, 1040 .rx = imx_mu_generic_rx, 1041 .rxdb = imx_mu_generic_rxdb, 1042 .init = imx_mu_init_generic, 1043 .xTR = 0x20, 1044 .xRR = 0x40, 1045 .xSR = {0x60, 0x60, 0x60, 0x60}, 1046 .xCR = {0x64, 0x64, 0x64, 0x64, 0x64}, 1047 .skip_suspend_flag = true, 1048 }; 1049 1050 static const struct imx_mu_dcfg imx_mu_cfg_imx8ulp = { 1051 .tx = imx_mu_generic_tx, 1052 .rx = imx_mu_generic_rx, 1053 .rxdb = imx_mu_generic_rxdb, 1054 .init = imx_mu_init_generic, 1055 .type = IMX_MU_V2, 1056 .xTR = 0x200, 1057 .xRR = 0x280, 1058 .xSR = {0xC, 0x118, 0x124, 0x12C}, 1059 .xCR = {0x8, 0x110, 0x114, 0x120, 0x128}, 1060 }; 1061 1062 static const struct imx_mu_dcfg imx_mu_cfg_imx8ulp_s4 = { 1063 .tx = imx_mu_specific_tx, 1064 .rx = imx_mu_specific_rx, 1065 .init = imx_mu_init_specific, 1066 .type = IMX_MU_V2 | IMX_MU_V2_S4, 1067 .xTR = 0x200, 1068 .xRR = 0x280, 1069 .xSR = {0xC, 0x118, 0x124, 0x12C}, 1070 .xCR = {0x8, 0x110, 0x114, 0x120, 0x128}, 1071 }; 1072 1073 static const struct imx_mu_dcfg imx_mu_cfg_imx93_s4 = { 1074 .tx = imx_mu_specific_tx, 1075 .rx = imx_mu_specific_rx, 1076 .init = imx_mu_init_specific, 1077 .type = IMX_MU_V2 | IMX_MU_V2_S4 | IMX_MU_V2_IRQ, 1078 .xTR = 0x200, 1079 .xRR = 0x280, 1080 .xSR = {0xC, 0x118, 0x124, 0x12C}, 1081 .xCR = {0x8, 0x110, 0x114, 0x120, 0x128}, 1082 }; 1083 1084 static const struct imx_mu_dcfg imx_mu_cfg_imx8_scu = { 1085 .tx = imx_mu_specific_tx, 1086 .rx = imx_mu_specific_rx, 1087 .init = imx_mu_init_specific, 1088 .rxdb = imx_mu_generic_rxdb, 1089 .xTR = 0x0, 1090 .xRR = 0x10, 1091 .xSR = {0x20, 0x20, 0x20, 0x20}, 1092 .xCR = {0x24, 0x24, 0x24, 0x24, 0x24}, 1093 }; 1094 1095 static const struct imx_mu_dcfg imx_mu_cfg_imx8_seco = { 1096 .tx = imx_mu_seco_tx, 1097 .rx = imx_mu_generic_rx, 1098 .rxdb = imx_mu_seco_rxdb, 1099 .init = imx_mu_init_seco, 1100 .xTR = 0x0, 1101 .xRR = 0x10, 1102 .xSR = {0x20, 0x20, 0x20, 0x20}, 1103 .xCR = {0x24, 0x24, 0x24, 0x24, 0x24}, 1104 }; 1105 1106 static const struct of_device_id imx_mu_dt_ids[] = { 1107 { .compatible = "fsl,imx7ulp-mu", .data = &imx_mu_cfg_imx7ulp }, 1108 { .compatible = "fsl,imx6sx-mu", .data = &imx_mu_cfg_imx6sx }, 1109 { .compatible = "fsl,imx8ulp-mu", .data = &imx_mu_cfg_imx8ulp }, 1110 { .compatible = "fsl,imx8ulp-mu-s4", .data = &imx_mu_cfg_imx8ulp_s4 }, 1111 { .compatible = "fsl,imx93-mu-s4", .data = &imx_mu_cfg_imx93_s4 }, 1112 { .compatible = "fsl,imx95-mu", .data = &imx_mu_cfg_imx8ulp }, 1113 { .compatible = "fsl,imx95-mu-ele", .data = &imx_mu_cfg_imx8ulp_s4 }, 1114 { .compatible = "fsl,imx95-mu-v2x", .data = &imx_mu_cfg_imx8ulp_s4 }, 1115 { .compatible = "fsl,imx8-mu-scu", .data = &imx_mu_cfg_imx8_scu }, 1116 { .compatible = "fsl,imx8-mu-seco", .data = &imx_mu_cfg_imx8_seco }, 1117 { }, 1118 }; 1119 MODULE_DEVICE_TABLE(of, imx_mu_dt_ids); 1120 1121 static int __maybe_unused imx_mu_suspend_noirq(struct device *dev) 1122 { 1123 struct imx_mu_priv *priv = dev_get_drvdata(dev); 1124 int i; 1125 1126 if (!priv->clk) { 1127 for (i = 0; i < IMX_MU_xCR_MAX; i++) 1128 priv->xcr[i] = imx_mu_read(priv, priv->dcfg->xCR[i]); 1129 } 1130 1131 if (!priv->dcfg->skip_suspend_flag) 1132 priv->suspend = true; 1133 1134 return 0; 1135 } 1136 1137 static int __maybe_unused imx_mu_resume_noirq(struct device *dev) 1138 { 1139 struct imx_mu_priv *priv = dev_get_drvdata(dev); 1140 int i; 1141 1142 /* 1143 * ONLY restore MU when context lost, the TIE could 1144 * be set during noirq resume as there is MU data 1145 * communication going on, and restore the saved 1146 * value will overwrite the TIE and cause MU data 1147 * send failed, may lead to system freeze. This issue 1148 * is observed by testing freeze mode suspend. 1149 */ 1150 if (!priv->clk && !imx_mu_read(priv, priv->dcfg->xCR[0])) { 1151 for (i = 0; i < IMX_MU_xCR_MAX; i++) 1152 imx_mu_write(priv, priv->xcr[i], priv->dcfg->xCR[i]); 1153 } 1154 1155 if (!priv->dcfg->skip_suspend_flag) 1156 priv->suspend = false; 1157 1158 return 0; 1159 } 1160 1161 static int __maybe_unused imx_mu_runtime_suspend(struct device *dev) 1162 { 1163 struct imx_mu_priv *priv = dev_get_drvdata(dev); 1164 1165 clk_disable_unprepare(priv->clk); 1166 1167 return 0; 1168 } 1169 1170 static int __maybe_unused imx_mu_runtime_resume(struct device *dev) 1171 { 1172 struct imx_mu_priv *priv = dev_get_drvdata(dev); 1173 int ret; 1174 1175 ret = clk_prepare_enable(priv->clk); 1176 if (ret) 1177 dev_err(dev, "failed to enable clock\n"); 1178 1179 return ret; 1180 } 1181 1182 static const struct dev_pm_ops imx_mu_pm_ops = { 1183 SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(imx_mu_suspend_noirq, 1184 imx_mu_resume_noirq) 1185 SET_RUNTIME_PM_OPS(imx_mu_runtime_suspend, 1186 imx_mu_runtime_resume, NULL) 1187 }; 1188 1189 static struct platform_driver imx_mu_driver = { 1190 .probe = imx_mu_probe, 1191 .remove = imx_mu_remove, 1192 .driver = { 1193 .name = "imx_mu", 1194 .of_match_table = imx_mu_dt_ids, 1195 .pm = &imx_mu_pm_ops, 1196 }, 1197 }; 1198 module_platform_driver(imx_mu_driver); 1199 1200 MODULE_AUTHOR("Oleksij Rempel <o.rempel@pengutronix.de>"); 1201 MODULE_DESCRIPTION("Message Unit driver for i.MX"); 1202 MODULE_LICENSE("GPL v2"); 1203