1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * Copyright (C) 2024 Sophgo Technology Inc. 4 * Copyright (C) 2024 Yuntao Dai <d1581209858@live.com> 5 * Copyright (C) 2025 Junhui Liu <junhui.liu@pigmoral.tech> 6 */ 7 8 #include <linux/bits.h> 9 #include <linux/device.h> 10 #include <linux/err.h> 11 #include <linux/interrupt.h> 12 #include <linux/io.h> 13 #include <linux/kfifo.h> 14 #include <linux/mailbox_controller.h> 15 #include <linux/module.h> 16 #include <linux/platform_device.h> 17 #include <linux/slab.h> 18 19 #define RECV_CPU 1 20 21 #define MAILBOX_MAX_CHAN 8 22 #define MAILBOX_MSG_LEN 8 23 24 #define MBOX_EN_REG(cpu) (cpu << 2) 25 #define MBOX_DONE_REG(cpu) ((cpu << 2) + 2) 26 #define MBOX_SET_CLR_REG(cpu) (0x10 + (cpu << 4)) 27 #define MBOX_SET_INT_REG(cpu) (0x18 + (cpu << 4)) 28 #define MBOX_SET_REG 0x60 29 30 #define MAILBOX_CONTEXT_OFFSET 0x0400 31 #define MAILBOX_CONTEXT_SIZE 0x0040 32 33 #define MBOX_CONTEXT_BASE_INDEX(base, index) \ 34 ((u64 __iomem *)(base + MAILBOX_CONTEXT_OFFSET) + index) 35 36 /** 37 * struct cv1800_mbox_chan_priv - cv1800 mailbox channel private data 38 * @idx: index of channel 39 * @cpu: send to which processor 40 */ 41 struct cv1800_mbox_chan_priv { 42 int idx; 43 int cpu; 44 }; 45 46 struct cv1800_mbox { 47 struct mbox_controller mbox; 48 struct cv1800_mbox_chan_priv priv[MAILBOX_MAX_CHAN]; 49 struct mbox_chan chans[MAILBOX_MAX_CHAN]; 50 u64 __iomem *content[MAILBOX_MAX_CHAN]; 51 void __iomem *mbox_base; 52 int recvid; 53 }; 54 55 static irqreturn_t cv1800_mbox_isr(int irq, void *dev_id) 56 { 57 struct cv1800_mbox *mbox = (struct cv1800_mbox *)dev_id; 58 size_t i; 59 u64 msg; 60 int ret = IRQ_NONE; 61 62 for (i = 0; i < MAILBOX_MAX_CHAN; i++) { 63 if (mbox->content[i] && mbox->chans[i].cl) { 64 memcpy_fromio(&msg, mbox->content[i], MAILBOX_MSG_LEN); 65 mbox->content[i] = NULL; 66 mbox_chan_received_data(&mbox->chans[i], (void *)&msg); 67 ret = IRQ_HANDLED; 68 } 69 } 70 71 return ret; 72 } 73 74 static irqreturn_t cv1800_mbox_irq(int irq, void *dev_id) 75 { 76 struct cv1800_mbox *mbox = (struct cv1800_mbox *)dev_id; 77 u8 set, valid; 78 size_t i; 79 int ret = IRQ_NONE; 80 81 set = readb(mbox->mbox_base + MBOX_SET_INT_REG(RECV_CPU)); 82 83 if (!set) 84 return ret; 85 86 for (i = 0; i < MAILBOX_MAX_CHAN; i++) { 87 valid = set & BIT(i); 88 if (valid) { 89 mbox->content[i] = 90 MBOX_CONTEXT_BASE_INDEX(mbox->mbox_base, i); 91 writeb(valid, mbox->mbox_base + 92 MBOX_SET_CLR_REG(RECV_CPU)); 93 writeb(~valid, mbox->mbox_base + MBOX_EN_REG(RECV_CPU)); 94 ret = IRQ_WAKE_THREAD; 95 } 96 } 97 98 return ret; 99 } 100 101 static int cv1800_mbox_send_data(struct mbox_chan *chan, void *data) 102 { 103 struct cv1800_mbox_chan_priv *priv = 104 (struct cv1800_mbox_chan_priv *)chan->con_priv; 105 struct cv1800_mbox *mbox = dev_get_drvdata(chan->mbox->dev); 106 int idx = priv->idx; 107 int cpu = priv->cpu; 108 u8 en, valid; 109 110 memcpy_toio(MBOX_CONTEXT_BASE_INDEX(mbox->mbox_base, idx), 111 data, MAILBOX_MSG_LEN); 112 113 valid = BIT(idx); 114 writeb(valid, mbox->mbox_base + MBOX_SET_CLR_REG(cpu)); 115 en = readb(mbox->mbox_base + MBOX_EN_REG(cpu)); 116 writeb(en | valid, mbox->mbox_base + MBOX_EN_REG(cpu)); 117 writeb(valid, mbox->mbox_base + MBOX_SET_REG); 118 119 return 0; 120 } 121 122 static bool cv1800_last_tx_done(struct mbox_chan *chan) 123 { 124 struct cv1800_mbox_chan_priv *priv = 125 (struct cv1800_mbox_chan_priv *)chan->con_priv; 126 struct cv1800_mbox *mbox = dev_get_drvdata(chan->mbox->dev); 127 u8 en; 128 129 en = readb(mbox->mbox_base + MBOX_EN_REG(priv->cpu)); 130 131 return !(en & BIT(priv->idx)); 132 } 133 134 static const struct mbox_chan_ops cv1800_mbox_chan_ops = { 135 .send_data = cv1800_mbox_send_data, 136 .last_tx_done = cv1800_last_tx_done, 137 }; 138 139 static struct mbox_chan *cv1800_mbox_xlate(struct mbox_controller *mbox, 140 const struct of_phandle_args *spec) 141 { 142 struct cv1800_mbox_chan_priv *priv; 143 144 int idx = spec->args[0]; 145 int cpu = spec->args[1]; 146 147 if (idx >= mbox->num_chans) 148 return ERR_PTR(-EINVAL); 149 150 priv = mbox->chans[idx].con_priv; 151 priv->cpu = cpu; 152 153 return &mbox->chans[idx]; 154 } 155 156 static const struct of_device_id cv1800_mbox_of_match[] = { 157 { .compatible = "sophgo,cv1800b-mailbox", }, 158 {}, 159 }; 160 MODULE_DEVICE_TABLE(of, cv1800_mbox_of_match); 161 162 static int cv1800_mbox_probe(struct platform_device *pdev) 163 { 164 struct device *dev = &pdev->dev; 165 struct cv1800_mbox *mb; 166 int irq, idx, err; 167 168 mb = devm_kzalloc(dev, sizeof(*mb), GFP_KERNEL); 169 if (!mb) 170 return -ENOMEM; 171 172 mb->mbox_base = devm_platform_ioremap_resource(pdev, 0); 173 if (IS_ERR(mb->mbox_base)) 174 return dev_err_probe(dev, PTR_ERR(mb->mbox_base), 175 "Failed to map resource\n"); 176 177 mb->mbox.dev = dev; 178 mb->mbox.chans = mb->chans; 179 mb->mbox.txdone_poll = true; 180 mb->mbox.ops = &cv1800_mbox_chan_ops; 181 mb->mbox.num_chans = MAILBOX_MAX_CHAN; 182 mb->mbox.of_xlate = cv1800_mbox_xlate; 183 184 irq = platform_get_irq(pdev, 0); 185 if (irq < 0) 186 return irq; 187 188 err = devm_request_threaded_irq(dev, irq, cv1800_mbox_irq, 189 cv1800_mbox_isr, IRQF_ONESHOT, 190 dev_name(&pdev->dev), mb); 191 if (err < 0) 192 return dev_err_probe(dev, err, "Failed to register irq\n"); 193 194 for (idx = 0; idx < MAILBOX_MAX_CHAN; idx++) { 195 mb->priv[idx].idx = idx; 196 mb->mbox.chans[idx].con_priv = &mb->priv[idx]; 197 } 198 199 platform_set_drvdata(pdev, mb); 200 201 err = devm_mbox_controller_register(dev, &mb->mbox); 202 if (err) 203 return dev_err_probe(dev, err, "Failed to register mailbox\n"); 204 205 return 0; 206 } 207 208 static struct platform_driver cv1800_mbox_driver = { 209 .driver = { 210 .name = "cv1800-mbox", 211 .of_match_table = cv1800_mbox_of_match, 212 }, 213 .probe = cv1800_mbox_probe, 214 }; 215 216 module_platform_driver(cv1800_mbox_driver); 217 218 MODULE_DESCRIPTION("cv1800 mailbox driver"); 219 MODULE_LICENSE("GPL"); 220