1 /* 2 * Copyright 2016 Broadcom 3 * 4 * This program is free software; you can redistribute it and/or modify 5 * it under the terms of the GNU General Public License, version 2, as 6 * published by the Free Software Foundation (the "GPL"). 7 * 8 * This program is distributed in the hope that it will be useful, but 9 * WITHOUT ANY WARRANTY; without even the implied warranty of 10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 11 * General Public License version 2 (GPLv2) for more details. 12 * 13 * You should have received a copy of the GNU General Public License 14 * version 2 (GPLv2) along with this source code. 15 */ 16 17 /* 18 * Broadcom PDC Mailbox Driver 19 * The PDC provides a ring based programming interface to one or more hardware 20 * offload engines. For example, the PDC driver works with both SPU-M and SPU2 21 * cryptographic offload hardware. In some chips the PDC is referred to as MDE, 22 * and in others the FA2/FA+ hardware is used with this PDC driver. 23 * 24 * The PDC driver registers with the Linux mailbox framework as a mailbox 25 * controller, once for each PDC instance. Ring 0 for each PDC is registered as 26 * a mailbox channel. The PDC driver uses interrupts to determine when data 27 * transfers to and from an offload engine are complete. The PDC driver uses 28 * threaded IRQs so that response messages are handled outside of interrupt 29 * context. 30 * 31 * The PDC driver allows multiple messages to be pending in the descriptor 32 * rings. The tx_msg_start descriptor index indicates where the last message 33 * starts. The txin_numd value at this index indicates how many descriptor 34 * indexes make up the message. Similar state is kept on the receive side. When 35 * an rx interrupt indicates a response is ready, the PDC driver processes numd 36 * descriptors from the tx and rx ring, thus processing one response at a time. 37 */ 38 39 #include <linux/errno.h> 40 #include <linux/module.h> 41 #include <linux/init.h> 42 #include <linux/slab.h> 43 #include <linux/debugfs.h> 44 #include <linux/interrupt.h> 45 #include <linux/wait.h> 46 #include <linux/platform_device.h> 47 #include <linux/io.h> 48 #include <linux/of.h> 49 #include <linux/of_device.h> 50 #include <linux/of_address.h> 51 #include <linux/of_irq.h> 52 #include <linux/mailbox_controller.h> 53 #include <linux/mailbox/brcm-message.h> 54 #include <linux/scatterlist.h> 55 #include <linux/dma-direction.h> 56 #include <linux/dma-mapping.h> 57 #include <linux/dmapool.h> 58 59 #define PDC_SUCCESS 0 60 61 #define RING_ENTRY_SIZE sizeof(struct dma64dd) 62 63 /* # entries in PDC dma ring */ 64 #define PDC_RING_ENTRIES 512 65 /* 66 * Minimum number of ring descriptor entries that must be free to tell mailbox 67 * framework that it can submit another request 68 */ 69 #define PDC_RING_SPACE_MIN 15 70 71 #define PDC_RING_SIZE (PDC_RING_ENTRIES * RING_ENTRY_SIZE) 72 /* Rings are 8k aligned */ 73 #define RING_ALIGN_ORDER 13 74 #define RING_ALIGN BIT(RING_ALIGN_ORDER) 75 76 #define RX_BUF_ALIGN_ORDER 5 77 #define RX_BUF_ALIGN BIT(RX_BUF_ALIGN_ORDER) 78 79 /* descriptor bumping macros */ 80 #define XXD(x, max_mask) ((x) & (max_mask)) 81 #define TXD(x, max_mask) XXD((x), (max_mask)) 82 #define RXD(x, max_mask) XXD((x), (max_mask)) 83 #define NEXTTXD(i, max_mask) TXD((i) + 1, (max_mask)) 84 #define PREVTXD(i, max_mask) TXD((i) - 1, (max_mask)) 85 #define NEXTRXD(i, max_mask) RXD((i) + 1, (max_mask)) 86 #define PREVRXD(i, max_mask) RXD((i) - 1, (max_mask)) 87 #define NTXDACTIVE(h, t, max_mask) TXD((t) - (h), (max_mask)) 88 #define NRXDACTIVE(h, t, max_mask) RXD((t) - (h), (max_mask)) 89 90 /* Length of BCM header at start of SPU msg, in bytes */ 91 #define BCM_HDR_LEN 8 92 93 /* 94 * PDC driver reserves ringset 0 on each SPU for its own use. The driver does 95 * not currently support use of multiple ringsets on a single PDC engine. 96 */ 97 #define PDC_RINGSET 0 98 99 /* 100 * Interrupt mask and status definitions. Enable interrupts for tx and rx on 101 * ring 0 102 */ 103 #define PDC_RCVINT_0 (16 + PDC_RINGSET) 104 #define PDC_RCVINTEN_0 BIT(PDC_RCVINT_0) 105 #define PDC_INTMASK (PDC_RCVINTEN_0) 106 #define PDC_LAZY_FRAMECOUNT 1 107 #define PDC_LAZY_TIMEOUT 10000 108 #define PDC_LAZY_INT (PDC_LAZY_TIMEOUT | (PDC_LAZY_FRAMECOUNT << 24)) 109 #define PDC_INTMASK_OFFSET 0x24 110 #define PDC_INTSTATUS_OFFSET 0x20 111 #define PDC_RCVLAZY0_OFFSET (0x30 + 4 * PDC_RINGSET) 112 #define FA_RCVLAZY0_OFFSET 0x100 113 114 /* 115 * For SPU2, configure MDE_CKSUM_CONTROL to write 17 bytes of metadata 116 * before frame 117 */ 118 #define PDC_SPU2_RESP_HDR_LEN 17 119 #define PDC_CKSUM_CTRL BIT(27) 120 #define PDC_CKSUM_CTRL_OFFSET 0x400 121 122 #define PDC_SPUM_RESP_HDR_LEN 32 123 124 /* 125 * Sets the following bits for write to transmit control reg: 126 * 11 - PtyChkDisable - parity check is disabled 127 * 20:18 - BurstLen = 3 -> 2^7 = 128 byte data reads from memory 128 */ 129 #define PDC_TX_CTL 0x000C0800 130 131 /* Bit in tx control reg to enable tx channel */ 132 #define PDC_TX_ENABLE 0x1 133 134 /* 135 * Sets the following bits for write to receive control reg: 136 * 7:1 - RcvOffset - size in bytes of status region at start of rx frame buf 137 * 9 - SepRxHdrDescEn - place start of new frames only in descriptors 138 * that have StartOfFrame set 139 * 10 - OflowContinue - on rx FIFO overflow, clear rx fifo, discard all 140 * remaining bytes in current frame, report error 141 * in rx frame status for current frame 142 * 11 - PtyChkDisable - parity check is disabled 143 * 20:18 - BurstLen = 3 -> 2^7 = 128 byte data reads from memory 144 */ 145 #define PDC_RX_CTL 0x000C0E00 146 147 /* Bit in rx control reg to enable rx channel */ 148 #define PDC_RX_ENABLE 0x1 149 150 #define CRYPTO_D64_RS0_CD_MASK ((PDC_RING_ENTRIES * RING_ENTRY_SIZE) - 1) 151 152 /* descriptor flags */ 153 #define D64_CTRL1_EOT BIT(28) /* end of descriptor table */ 154 #define D64_CTRL1_IOC BIT(29) /* interrupt on complete */ 155 #define D64_CTRL1_EOF BIT(30) /* end of frame */ 156 #define D64_CTRL1_SOF BIT(31) /* start of frame */ 157 158 #define RX_STATUS_OVERFLOW 0x00800000 159 #define RX_STATUS_LEN 0x0000FFFF 160 161 #define PDC_TXREGS_OFFSET 0x200 162 #define PDC_RXREGS_OFFSET 0x220 163 164 /* Maximum size buffer the DMA engine can handle */ 165 #define PDC_DMA_BUF_MAX 16384 166 167 enum pdc_hw { 168 FA_HW, /* FA2/FA+ hardware (i.e. Northstar Plus) */ 169 PDC_HW /* PDC/MDE hardware (i.e. Northstar 2, Pegasus) */ 170 }; 171 172 struct pdc_dma_map { 173 void *ctx; /* opaque context associated with frame */ 174 }; 175 176 /* dma descriptor */ 177 struct dma64dd { 178 u32 ctrl1; /* misc control bits */ 179 u32 ctrl2; /* buffer count and address extension */ 180 u32 addrlow; /* memory address of the date buffer, bits 31:0 */ 181 u32 addrhigh; /* memory address of the date buffer, bits 63:32 */ 182 }; 183 184 /* dma registers per channel(xmt or rcv) */ 185 struct dma64_regs { 186 u32 control; /* enable, et al */ 187 u32 ptr; /* last descriptor posted to chip */ 188 u32 addrlow; /* descriptor ring base address low 32-bits */ 189 u32 addrhigh; /* descriptor ring base address bits 63:32 */ 190 u32 status0; /* last rx descriptor written by hw */ 191 u32 status1; /* driver does not use */ 192 }; 193 194 /* cpp contortions to concatenate w/arg prescan */ 195 #ifndef PAD 196 #define _PADLINE(line) pad ## line 197 #define _XSTR(line) _PADLINE(line) 198 #define PAD _XSTR(__LINE__) 199 #endif /* PAD */ 200 201 /* dma registers. matches hw layout. */ 202 struct dma64 { 203 struct dma64_regs dmaxmt; /* dma tx */ 204 u32 PAD[2]; 205 struct dma64_regs dmarcv; /* dma rx */ 206 u32 PAD[2]; 207 }; 208 209 /* PDC registers */ 210 struct pdc_regs { 211 u32 devcontrol; /* 0x000 */ 212 u32 devstatus; /* 0x004 */ 213 u32 PAD; 214 u32 biststatus; /* 0x00c */ 215 u32 PAD[4]; 216 u32 intstatus; /* 0x020 */ 217 u32 intmask; /* 0x024 */ 218 u32 gptimer; /* 0x028 */ 219 220 u32 PAD; 221 u32 intrcvlazy_0; /* 0x030 (Only in PDC, not FA2) */ 222 u32 intrcvlazy_1; /* 0x034 (Only in PDC, not FA2) */ 223 u32 intrcvlazy_2; /* 0x038 (Only in PDC, not FA2) */ 224 u32 intrcvlazy_3; /* 0x03c (Only in PDC, not FA2) */ 225 226 u32 PAD[48]; 227 u32 fa_intrecvlazy; /* 0x100 (Only in FA2, not PDC) */ 228 u32 flowctlthresh; /* 0x104 */ 229 u32 wrrthresh; /* 0x108 */ 230 u32 gmac_idle_cnt_thresh; /* 0x10c */ 231 232 u32 PAD[4]; 233 u32 ifioaccessaddr; /* 0x120 */ 234 u32 ifioaccessbyte; /* 0x124 */ 235 u32 ifioaccessdata; /* 0x128 */ 236 237 u32 PAD[21]; 238 u32 phyaccess; /* 0x180 */ 239 u32 PAD; 240 u32 phycontrol; /* 0x188 */ 241 u32 txqctl; /* 0x18c */ 242 u32 rxqctl; /* 0x190 */ 243 u32 gpioselect; /* 0x194 */ 244 u32 gpio_output_en; /* 0x198 */ 245 u32 PAD; /* 0x19c */ 246 u32 txq_rxq_mem_ctl; /* 0x1a0 */ 247 u32 memory_ecc_status; /* 0x1a4 */ 248 u32 serdes_ctl; /* 0x1a8 */ 249 u32 serdes_status0; /* 0x1ac */ 250 u32 serdes_status1; /* 0x1b0 */ 251 u32 PAD[11]; /* 0x1b4-1dc */ 252 u32 clk_ctl_st; /* 0x1e0 */ 253 u32 hw_war; /* 0x1e4 (Only in PDC, not FA2) */ 254 u32 pwrctl; /* 0x1e8 */ 255 u32 PAD[5]; 256 257 #define PDC_NUM_DMA_RINGS 4 258 struct dma64 dmaregs[PDC_NUM_DMA_RINGS]; /* 0x0200 - 0x2fc */ 259 260 /* more registers follow, but we don't use them */ 261 }; 262 263 /* structure for allocating/freeing DMA rings */ 264 struct pdc_ring_alloc { 265 dma_addr_t dmabase; /* DMA address of start of ring */ 266 void *vbase; /* base kernel virtual address of ring */ 267 u32 size; /* ring allocation size in bytes */ 268 }; 269 270 /* 271 * context associated with a receive descriptor. 272 * @rxp_ctx: opaque context associated with frame that starts at each 273 * rx ring index. 274 * @dst_sg: Scatterlist used to form reply frames beginning at a given ring 275 * index. Retained in order to unmap each sg after reply is processed. 276 * @rxin_numd: Number of rx descriptors associated with the message that starts 277 * at a descriptor index. Not set for every index. For example, 278 * if descriptor index i points to a scatterlist with 4 entries, 279 * then the next three descriptor indexes don't have a value set. 280 * @resp_hdr: Virtual address of buffer used to catch DMA rx status 281 * @resp_hdr_daddr: physical address of DMA rx status buffer 282 */ 283 struct pdc_rx_ctx { 284 void *rxp_ctx; 285 struct scatterlist *dst_sg; 286 u32 rxin_numd; 287 void *resp_hdr; 288 dma_addr_t resp_hdr_daddr; 289 }; 290 291 /* PDC state structure */ 292 struct pdc_state { 293 /* Index of the PDC whose state is in this structure instance */ 294 u8 pdc_idx; 295 296 /* Platform device for this PDC instance */ 297 struct platform_device *pdev; 298 299 /* 300 * Each PDC instance has a mailbox controller. PDC receives request 301 * messages through mailboxes, and sends response messages through the 302 * mailbox framework. 303 */ 304 struct mbox_controller mbc; 305 306 unsigned int pdc_irq; 307 308 /* tasklet for deferred processing after DMA rx interrupt */ 309 struct tasklet_struct rx_tasklet; 310 311 /* Number of bytes of receive status prior to each rx frame */ 312 u32 rx_status_len; 313 /* Whether a BCM header is prepended to each frame */ 314 bool use_bcm_hdr; 315 /* Sum of length of BCM header and rx status header */ 316 u32 pdc_resp_hdr_len; 317 318 /* The base virtual address of DMA hw registers */ 319 void __iomem *pdc_reg_vbase; 320 321 /* Pool for allocation of DMA rings */ 322 struct dma_pool *ring_pool; 323 324 /* Pool for allocation of metadata buffers for response messages */ 325 struct dma_pool *rx_buf_pool; 326 327 /* 328 * The base virtual address of DMA tx/rx descriptor rings. Corresponding 329 * DMA address and size of ring allocation. 330 */ 331 struct pdc_ring_alloc tx_ring_alloc; 332 struct pdc_ring_alloc rx_ring_alloc; 333 334 struct pdc_regs *regs; /* start of PDC registers */ 335 336 struct dma64_regs *txregs_64; /* dma tx engine registers */ 337 struct dma64_regs *rxregs_64; /* dma rx engine registers */ 338 339 /* 340 * Arrays of PDC_RING_ENTRIES descriptors 341 * To use multiple ringsets, this needs to be extended 342 */ 343 struct dma64dd *txd_64; /* tx descriptor ring */ 344 struct dma64dd *rxd_64; /* rx descriptor ring */ 345 346 /* descriptor ring sizes */ 347 u32 ntxd; /* # tx descriptors */ 348 u32 nrxd; /* # rx descriptors */ 349 u32 nrxpost; /* # rx buffers to keep posted */ 350 u32 ntxpost; /* max number of tx buffers that can be posted */ 351 352 /* 353 * Index of next tx descriptor to reclaim. That is, the descriptor 354 * index of the oldest tx buffer for which the host has yet to process 355 * the corresponding response. 356 */ 357 u32 txin; 358 359 /* 360 * Index of the first receive descriptor for the sequence of 361 * message fragments currently under construction. Used to build up 362 * the rxin_numd count for a message. Updated to rxout when the host 363 * starts a new sequence of rx buffers for a new message. 364 */ 365 u32 tx_msg_start; 366 367 /* Index of next tx descriptor to post. */ 368 u32 txout; 369 370 /* 371 * Number of tx descriptors associated with the message that starts 372 * at this tx descriptor index. 373 */ 374 u32 txin_numd[PDC_RING_ENTRIES]; 375 376 /* 377 * Index of next rx descriptor to reclaim. This is the index of 378 * the next descriptor whose data has yet to be processed by the host. 379 */ 380 u32 rxin; 381 382 /* 383 * Index of the first receive descriptor for the sequence of 384 * message fragments currently under construction. Used to build up 385 * the rxin_numd count for a message. Updated to rxout when the host 386 * starts a new sequence of rx buffers for a new message. 387 */ 388 u32 rx_msg_start; 389 390 /* 391 * Saved value of current hardware rx descriptor index. 392 * The last rx buffer written by the hw is the index previous to 393 * this one. 394 */ 395 u32 last_rx_curr; 396 397 /* Index of next rx descriptor to post. */ 398 u32 rxout; 399 400 struct pdc_rx_ctx rx_ctx[PDC_RING_ENTRIES]; 401 402 /* 403 * Scatterlists used to form request and reply frames beginning at a 404 * given ring index. Retained in order to unmap each sg after reply 405 * is processed 406 */ 407 struct scatterlist *src_sg[PDC_RING_ENTRIES]; 408 409 /* counters */ 410 u32 pdc_requests; /* number of request messages submitted */ 411 u32 pdc_replies; /* number of reply messages received */ 412 u32 last_tx_not_done; /* too few tx descriptors to indicate done */ 413 u32 tx_ring_full; /* unable to accept msg because tx ring full */ 414 u32 rx_ring_full; /* unable to accept msg because rx ring full */ 415 u32 txnobuf; /* unable to create tx descriptor */ 416 u32 rxnobuf; /* unable to create rx descriptor */ 417 u32 rx_oflow; /* count of rx overflows */ 418 419 /* hardware type - FA2 or PDC/MDE */ 420 enum pdc_hw hw_type; 421 }; 422 423 /* Global variables */ 424 425 struct pdc_globals { 426 /* Actual number of SPUs in hardware, as reported by device tree */ 427 u32 num_spu; 428 }; 429 430 static struct pdc_globals pdcg; 431 432 /* top level debug FS directory for PDC driver */ 433 static struct dentry *debugfs_dir; 434 435 static ssize_t pdc_debugfs_read(struct file *filp, char __user *ubuf, 436 size_t count, loff_t *offp) 437 { 438 struct pdc_state *pdcs; 439 char *buf; 440 ssize_t ret, out_offset, out_count; 441 442 out_count = 512; 443 444 buf = kmalloc(out_count, GFP_KERNEL); 445 if (!buf) 446 return -ENOMEM; 447 448 pdcs = filp->private_data; 449 out_offset = 0; 450 out_offset += snprintf(buf + out_offset, out_count - out_offset, 451 "SPU %u stats:\n", pdcs->pdc_idx); 452 out_offset += snprintf(buf + out_offset, out_count - out_offset, 453 "PDC requests....................%u\n", 454 pdcs->pdc_requests); 455 out_offset += snprintf(buf + out_offset, out_count - out_offset, 456 "PDC responses...................%u\n", 457 pdcs->pdc_replies); 458 out_offset += snprintf(buf + out_offset, out_count - out_offset, 459 "Tx not done.....................%u\n", 460 pdcs->last_tx_not_done); 461 out_offset += snprintf(buf + out_offset, out_count - out_offset, 462 "Tx ring full....................%u\n", 463 pdcs->tx_ring_full); 464 out_offset += snprintf(buf + out_offset, out_count - out_offset, 465 "Rx ring full....................%u\n", 466 pdcs->rx_ring_full); 467 out_offset += snprintf(buf + out_offset, out_count - out_offset, 468 "Tx desc write fail. Ring full...%u\n", 469 pdcs->txnobuf); 470 out_offset += snprintf(buf + out_offset, out_count - out_offset, 471 "Rx desc write fail. Ring full...%u\n", 472 pdcs->rxnobuf); 473 out_offset += snprintf(buf + out_offset, out_count - out_offset, 474 "Receive overflow................%u\n", 475 pdcs->rx_oflow); 476 out_offset += snprintf(buf + out_offset, out_count - out_offset, 477 "Num frags in rx ring............%u\n", 478 NRXDACTIVE(pdcs->rxin, pdcs->last_rx_curr, 479 pdcs->nrxpost)); 480 481 if (out_offset > out_count) 482 out_offset = out_count; 483 484 ret = simple_read_from_buffer(ubuf, count, offp, buf, out_offset); 485 kfree(buf); 486 return ret; 487 } 488 489 static const struct file_operations pdc_debugfs_stats = { 490 .owner = THIS_MODULE, 491 .open = simple_open, 492 .read = pdc_debugfs_read, 493 }; 494 495 /** 496 * pdc_setup_debugfs() - Create the debug FS directories. If the top-level 497 * directory has not yet been created, create it now. Create a stats file in 498 * this directory for a SPU. 499 * @pdcs: PDC state structure 500 */ 501 static void pdc_setup_debugfs(struct pdc_state *pdcs) 502 { 503 char spu_stats_name[16]; 504 505 if (!debugfs_initialized()) 506 return; 507 508 snprintf(spu_stats_name, 16, "pdc%d_stats", pdcs->pdc_idx); 509 if (!debugfs_dir) 510 debugfs_dir = debugfs_create_dir(KBUILD_MODNAME, NULL); 511 512 /* S_IRUSR == 0400 */ 513 debugfs_create_file(spu_stats_name, 0400, debugfs_dir, pdcs, 514 &pdc_debugfs_stats); 515 } 516 517 static void pdc_free_debugfs(void) 518 { 519 debugfs_remove_recursive(debugfs_dir); 520 debugfs_dir = NULL; 521 } 522 523 /** 524 * pdc_build_rxd() - Build DMA descriptor to receive SPU result. 525 * @pdcs: PDC state for SPU that will generate result 526 * @dma_addr: DMA address of buffer that descriptor is being built for 527 * @buf_len: Length of the receive buffer, in bytes 528 * @flags: Flags to be stored in descriptor 529 */ 530 static inline void 531 pdc_build_rxd(struct pdc_state *pdcs, dma_addr_t dma_addr, 532 u32 buf_len, u32 flags) 533 { 534 struct device *dev = &pdcs->pdev->dev; 535 struct dma64dd *rxd = &pdcs->rxd_64[pdcs->rxout]; 536 537 dev_dbg(dev, 538 "Writing rx descriptor for PDC %u at index %u with length %u. flags %#x\n", 539 pdcs->pdc_idx, pdcs->rxout, buf_len, flags); 540 541 rxd->addrlow = cpu_to_le32(lower_32_bits(dma_addr)); 542 rxd->addrhigh = cpu_to_le32(upper_32_bits(dma_addr)); 543 rxd->ctrl1 = cpu_to_le32(flags); 544 rxd->ctrl2 = cpu_to_le32(buf_len); 545 546 /* bump ring index and return */ 547 pdcs->rxout = NEXTRXD(pdcs->rxout, pdcs->nrxpost); 548 } 549 550 /** 551 * pdc_build_txd() - Build a DMA descriptor to transmit a SPU request to 552 * hardware. 553 * @pdcs: PDC state for the SPU that will process this request 554 * @dma_addr: DMA address of packet to be transmitted 555 * @buf_len: Length of tx buffer, in bytes 556 * @flags: Flags to be stored in descriptor 557 */ 558 static inline void 559 pdc_build_txd(struct pdc_state *pdcs, dma_addr_t dma_addr, u32 buf_len, 560 u32 flags) 561 { 562 struct device *dev = &pdcs->pdev->dev; 563 struct dma64dd *txd = &pdcs->txd_64[pdcs->txout]; 564 565 dev_dbg(dev, 566 "Writing tx descriptor for PDC %u at index %u with length %u, flags %#x\n", 567 pdcs->pdc_idx, pdcs->txout, buf_len, flags); 568 569 txd->addrlow = cpu_to_le32(lower_32_bits(dma_addr)); 570 txd->addrhigh = cpu_to_le32(upper_32_bits(dma_addr)); 571 txd->ctrl1 = cpu_to_le32(flags); 572 txd->ctrl2 = cpu_to_le32(buf_len); 573 574 /* bump ring index and return */ 575 pdcs->txout = NEXTTXD(pdcs->txout, pdcs->ntxpost); 576 } 577 578 /** 579 * pdc_receive_one() - Receive a response message from a given SPU. 580 * @pdcs: PDC state for the SPU to receive from 581 * 582 * When the return code indicates success, the response message is available in 583 * the receive buffers provided prior to submission of the request. 584 * 585 * Return: PDC_SUCCESS if one or more receive descriptors was processed 586 * -EAGAIN indicates that no response message is available 587 * -EIO an error occurred 588 */ 589 static int 590 pdc_receive_one(struct pdc_state *pdcs) 591 { 592 struct device *dev = &pdcs->pdev->dev; 593 struct mbox_controller *mbc; 594 struct mbox_chan *chan; 595 struct brcm_message mssg; 596 u32 len, rx_status; 597 u32 num_frags; 598 u8 *resp_hdr; /* virtual addr of start of resp message DMA header */ 599 u32 frags_rdy; /* number of fragments ready to read */ 600 u32 rx_idx; /* ring index of start of receive frame */ 601 dma_addr_t resp_hdr_daddr; 602 struct pdc_rx_ctx *rx_ctx; 603 604 mbc = &pdcs->mbc; 605 chan = &mbc->chans[0]; 606 mssg.type = BRCM_MESSAGE_SPU; 607 608 /* 609 * return if a complete response message is not yet ready. 610 * rxin_numd[rxin] is the number of fragments in the next msg 611 * to read. 612 */ 613 frags_rdy = NRXDACTIVE(pdcs->rxin, pdcs->last_rx_curr, pdcs->nrxpost); 614 if ((frags_rdy == 0) || 615 (frags_rdy < pdcs->rx_ctx[pdcs->rxin].rxin_numd)) 616 /* No response ready */ 617 return -EAGAIN; 618 619 num_frags = pdcs->txin_numd[pdcs->txin]; 620 WARN_ON(num_frags == 0); 621 622 dma_unmap_sg(dev, pdcs->src_sg[pdcs->txin], 623 sg_nents(pdcs->src_sg[pdcs->txin]), DMA_TO_DEVICE); 624 625 pdcs->txin = (pdcs->txin + num_frags) & pdcs->ntxpost; 626 627 dev_dbg(dev, "PDC %u reclaimed %d tx descriptors", 628 pdcs->pdc_idx, num_frags); 629 630 rx_idx = pdcs->rxin; 631 rx_ctx = &pdcs->rx_ctx[rx_idx]; 632 num_frags = rx_ctx->rxin_numd; 633 /* Return opaque context with result */ 634 mssg.ctx = rx_ctx->rxp_ctx; 635 rx_ctx->rxp_ctx = NULL; 636 resp_hdr = rx_ctx->resp_hdr; 637 resp_hdr_daddr = rx_ctx->resp_hdr_daddr; 638 dma_unmap_sg(dev, rx_ctx->dst_sg, sg_nents(rx_ctx->dst_sg), 639 DMA_FROM_DEVICE); 640 641 pdcs->rxin = (pdcs->rxin + num_frags) & pdcs->nrxpost; 642 643 dev_dbg(dev, "PDC %u reclaimed %d rx descriptors", 644 pdcs->pdc_idx, num_frags); 645 646 dev_dbg(dev, 647 "PDC %u txin %u, txout %u, rxin %u, rxout %u, last_rx_curr %u\n", 648 pdcs->pdc_idx, pdcs->txin, pdcs->txout, pdcs->rxin, 649 pdcs->rxout, pdcs->last_rx_curr); 650 651 if (pdcs->pdc_resp_hdr_len == PDC_SPUM_RESP_HDR_LEN) { 652 /* 653 * For SPU-M, get length of response msg and rx overflow status. 654 */ 655 rx_status = *((u32 *)resp_hdr); 656 len = rx_status & RX_STATUS_LEN; 657 dev_dbg(dev, 658 "SPU response length %u bytes", len); 659 if (unlikely(((rx_status & RX_STATUS_OVERFLOW) || (!len)))) { 660 if (rx_status & RX_STATUS_OVERFLOW) { 661 dev_err_ratelimited(dev, 662 "crypto receive overflow"); 663 pdcs->rx_oflow++; 664 } else { 665 dev_info_ratelimited(dev, "crypto rx len = 0"); 666 } 667 return -EIO; 668 } 669 } 670 671 dma_pool_free(pdcs->rx_buf_pool, resp_hdr, resp_hdr_daddr); 672 673 mbox_chan_received_data(chan, &mssg); 674 675 pdcs->pdc_replies++; 676 return PDC_SUCCESS; 677 } 678 679 /** 680 * pdc_receive() - Process as many responses as are available in the rx ring. 681 * @pdcs: PDC state 682 * 683 * Called within the hard IRQ. 684 * Return: 685 */ 686 static int 687 pdc_receive(struct pdc_state *pdcs) 688 { 689 int rx_status; 690 691 /* read last_rx_curr from register once */ 692 pdcs->last_rx_curr = 693 (ioread32(&pdcs->rxregs_64->status0) & 694 CRYPTO_D64_RS0_CD_MASK) / RING_ENTRY_SIZE; 695 696 do { 697 /* Could be many frames ready */ 698 rx_status = pdc_receive_one(pdcs); 699 } while (rx_status == PDC_SUCCESS); 700 701 return 0; 702 } 703 704 /** 705 * pdc_tx_list_sg_add() - Add the buffers in a scatterlist to the transmit 706 * descriptors for a given SPU. The scatterlist buffers contain the data for a 707 * SPU request message. 708 * @spu_idx: The index of the SPU to submit the request to, [0, max_spu) 709 * @sg: Scatterlist whose buffers contain part of the SPU request 710 * 711 * If a scatterlist buffer is larger than PDC_DMA_BUF_MAX, multiple descriptors 712 * are written for that buffer, each <= PDC_DMA_BUF_MAX byte in length. 713 * 714 * Return: PDC_SUCCESS if successful 715 * < 0 otherwise 716 */ 717 static int pdc_tx_list_sg_add(struct pdc_state *pdcs, struct scatterlist *sg) 718 { 719 u32 flags = 0; 720 u32 eot; 721 u32 tx_avail; 722 723 /* 724 * Num descriptors needed. Conservatively assume we need a descriptor 725 * for every entry in sg. 726 */ 727 u32 num_desc; 728 u32 desc_w = 0; /* Number of tx descriptors written */ 729 u32 bufcnt; /* Number of bytes of buffer pointed to by descriptor */ 730 dma_addr_t databufptr; /* DMA address to put in descriptor */ 731 732 num_desc = (u32)sg_nents(sg); 733 734 /* check whether enough tx descriptors are available */ 735 tx_avail = pdcs->ntxpost - NTXDACTIVE(pdcs->txin, pdcs->txout, 736 pdcs->ntxpost); 737 if (unlikely(num_desc > tx_avail)) { 738 pdcs->txnobuf++; 739 return -ENOSPC; 740 } 741 742 /* build tx descriptors */ 743 if (pdcs->tx_msg_start == pdcs->txout) { 744 /* Start of frame */ 745 pdcs->txin_numd[pdcs->tx_msg_start] = 0; 746 pdcs->src_sg[pdcs->txout] = sg; 747 flags = D64_CTRL1_SOF; 748 } 749 750 while (sg) { 751 if (unlikely(pdcs->txout == (pdcs->ntxd - 1))) 752 eot = D64_CTRL1_EOT; 753 else 754 eot = 0; 755 756 /* 757 * If sg buffer larger than PDC limit, split across 758 * multiple descriptors 759 */ 760 bufcnt = sg_dma_len(sg); 761 databufptr = sg_dma_address(sg); 762 while (bufcnt > PDC_DMA_BUF_MAX) { 763 pdc_build_txd(pdcs, databufptr, PDC_DMA_BUF_MAX, 764 flags | eot); 765 desc_w++; 766 bufcnt -= PDC_DMA_BUF_MAX; 767 databufptr += PDC_DMA_BUF_MAX; 768 if (unlikely(pdcs->txout == (pdcs->ntxd - 1))) 769 eot = D64_CTRL1_EOT; 770 else 771 eot = 0; 772 } 773 sg = sg_next(sg); 774 if (!sg) 775 /* Writing last descriptor for frame */ 776 flags |= (D64_CTRL1_EOF | D64_CTRL1_IOC); 777 pdc_build_txd(pdcs, databufptr, bufcnt, flags | eot); 778 desc_w++; 779 /* Clear start of frame after first descriptor */ 780 flags &= ~D64_CTRL1_SOF; 781 } 782 pdcs->txin_numd[pdcs->tx_msg_start] += desc_w; 783 784 return PDC_SUCCESS; 785 } 786 787 /** 788 * pdc_tx_list_final() - Initiate DMA transfer of last frame written to tx 789 * ring. 790 * @pdcs: PDC state for SPU to process the request 791 * 792 * Sets the index of the last descriptor written in both the rx and tx ring. 793 * 794 * Return: PDC_SUCCESS 795 */ 796 static int pdc_tx_list_final(struct pdc_state *pdcs) 797 { 798 /* 799 * write barrier to ensure all register writes are complete 800 * before chip starts to process new request 801 */ 802 wmb(); 803 iowrite32(pdcs->rxout << 4, &pdcs->rxregs_64->ptr); 804 iowrite32(pdcs->txout << 4, &pdcs->txregs_64->ptr); 805 pdcs->pdc_requests++; 806 807 return PDC_SUCCESS; 808 } 809 810 /** 811 * pdc_rx_list_init() - Start a new receive descriptor list for a given PDC. 812 * @pdcs: PDC state for SPU handling request 813 * @dst_sg: scatterlist providing rx buffers for response to be returned to 814 * mailbox client 815 * @ctx: Opaque context for this request 816 * 817 * Posts a single receive descriptor to hold the metadata that precedes a 818 * response. For example, with SPU-M, the metadata is a 32-byte DMA header and 819 * an 8-byte BCM header. Moves the msg_start descriptor indexes for both tx and 820 * rx to indicate the start of a new message. 821 * 822 * Return: PDC_SUCCESS if successful 823 * < 0 if an error (e.g., rx ring is full) 824 */ 825 static int pdc_rx_list_init(struct pdc_state *pdcs, struct scatterlist *dst_sg, 826 void *ctx) 827 { 828 u32 flags = 0; 829 u32 rx_avail; 830 u32 rx_pkt_cnt = 1; /* Adding a single rx buffer */ 831 dma_addr_t daddr; 832 void *vaddr; 833 struct pdc_rx_ctx *rx_ctx; 834 835 rx_avail = pdcs->nrxpost - NRXDACTIVE(pdcs->rxin, pdcs->rxout, 836 pdcs->nrxpost); 837 if (unlikely(rx_pkt_cnt > rx_avail)) { 838 pdcs->rxnobuf++; 839 return -ENOSPC; 840 } 841 842 /* allocate a buffer for the dma rx status */ 843 vaddr = dma_pool_zalloc(pdcs->rx_buf_pool, GFP_ATOMIC, &daddr); 844 if (unlikely(!vaddr)) 845 return -ENOMEM; 846 847 /* 848 * Update msg_start indexes for both tx and rx to indicate the start 849 * of a new sequence of descriptor indexes that contain the fragments 850 * of the same message. 851 */ 852 pdcs->rx_msg_start = pdcs->rxout; 853 pdcs->tx_msg_start = pdcs->txout; 854 855 /* This is always the first descriptor in the receive sequence */ 856 flags = D64_CTRL1_SOF; 857 pdcs->rx_ctx[pdcs->rx_msg_start].rxin_numd = 1; 858 859 if (unlikely(pdcs->rxout == (pdcs->nrxd - 1))) 860 flags |= D64_CTRL1_EOT; 861 862 rx_ctx = &pdcs->rx_ctx[pdcs->rxout]; 863 rx_ctx->rxp_ctx = ctx; 864 rx_ctx->dst_sg = dst_sg; 865 rx_ctx->resp_hdr = vaddr; 866 rx_ctx->resp_hdr_daddr = daddr; 867 pdc_build_rxd(pdcs, daddr, pdcs->pdc_resp_hdr_len, flags); 868 return PDC_SUCCESS; 869 } 870 871 /** 872 * pdc_rx_list_sg_add() - Add the buffers in a scatterlist to the receive 873 * descriptors for a given SPU. The caller must have already DMA mapped the 874 * scatterlist. 875 * @spu_idx: Indicates which SPU the buffers are for 876 * @sg: Scatterlist whose buffers are added to the receive ring 877 * 878 * If a receive buffer in the scatterlist is larger than PDC_DMA_BUF_MAX, 879 * multiple receive descriptors are written, each with a buffer <= 880 * PDC_DMA_BUF_MAX. 881 * 882 * Return: PDC_SUCCESS if successful 883 * < 0 otherwise (e.g., receive ring is full) 884 */ 885 static int pdc_rx_list_sg_add(struct pdc_state *pdcs, struct scatterlist *sg) 886 { 887 u32 flags = 0; 888 u32 rx_avail; 889 890 /* 891 * Num descriptors needed. Conservatively assume we need a descriptor 892 * for every entry from our starting point in the scatterlist. 893 */ 894 u32 num_desc; 895 u32 desc_w = 0; /* Number of tx descriptors written */ 896 u32 bufcnt; /* Number of bytes of buffer pointed to by descriptor */ 897 dma_addr_t databufptr; /* DMA address to put in descriptor */ 898 899 num_desc = (u32)sg_nents(sg); 900 901 rx_avail = pdcs->nrxpost - NRXDACTIVE(pdcs->rxin, pdcs->rxout, 902 pdcs->nrxpost); 903 if (unlikely(num_desc > rx_avail)) { 904 pdcs->rxnobuf++; 905 return -ENOSPC; 906 } 907 908 while (sg) { 909 if (unlikely(pdcs->rxout == (pdcs->nrxd - 1))) 910 flags = D64_CTRL1_EOT; 911 else 912 flags = 0; 913 914 /* 915 * If sg buffer larger than PDC limit, split across 916 * multiple descriptors 917 */ 918 bufcnt = sg_dma_len(sg); 919 databufptr = sg_dma_address(sg); 920 while (bufcnt > PDC_DMA_BUF_MAX) { 921 pdc_build_rxd(pdcs, databufptr, PDC_DMA_BUF_MAX, flags); 922 desc_w++; 923 bufcnt -= PDC_DMA_BUF_MAX; 924 databufptr += PDC_DMA_BUF_MAX; 925 if (unlikely(pdcs->rxout == (pdcs->nrxd - 1))) 926 flags = D64_CTRL1_EOT; 927 else 928 flags = 0; 929 } 930 pdc_build_rxd(pdcs, databufptr, bufcnt, flags); 931 desc_w++; 932 sg = sg_next(sg); 933 } 934 pdcs->rx_ctx[pdcs->rx_msg_start].rxin_numd += desc_w; 935 936 return PDC_SUCCESS; 937 } 938 939 /** 940 * pdc_irq_handler() - Interrupt handler called in interrupt context. 941 * @irq: Interrupt number that has fired 942 * @data: device struct for DMA engine that generated the interrupt 943 * 944 * We have to clear the device interrupt status flags here. So cache the 945 * status for later use in the thread function. Other than that, just return 946 * WAKE_THREAD to invoke the thread function. 947 * 948 * Return: IRQ_WAKE_THREAD if interrupt is ours 949 * IRQ_NONE otherwise 950 */ 951 static irqreturn_t pdc_irq_handler(int irq, void *data) 952 { 953 struct device *dev = (struct device *)data; 954 struct pdc_state *pdcs = dev_get_drvdata(dev); 955 u32 intstatus = ioread32(pdcs->pdc_reg_vbase + PDC_INTSTATUS_OFFSET); 956 957 if (unlikely(intstatus == 0)) 958 return IRQ_NONE; 959 960 /* Disable interrupts until soft handler runs */ 961 iowrite32(0, pdcs->pdc_reg_vbase + PDC_INTMASK_OFFSET); 962 963 /* Clear interrupt flags in device */ 964 iowrite32(intstatus, pdcs->pdc_reg_vbase + PDC_INTSTATUS_OFFSET); 965 966 /* Wakeup IRQ thread */ 967 tasklet_schedule(&pdcs->rx_tasklet); 968 return IRQ_HANDLED; 969 } 970 971 /** 972 * pdc_tasklet_cb() - Tasklet callback that runs the deferred processing after 973 * a DMA receive interrupt. Reenables the receive interrupt. 974 * @data: PDC state structure 975 */ 976 static void pdc_tasklet_cb(unsigned long data) 977 { 978 struct pdc_state *pdcs = (struct pdc_state *)data; 979 980 pdc_receive(pdcs); 981 982 /* reenable interrupts */ 983 iowrite32(PDC_INTMASK, pdcs->pdc_reg_vbase + PDC_INTMASK_OFFSET); 984 } 985 986 /** 987 * pdc_ring_init() - Allocate DMA rings and initialize constant fields of 988 * descriptors in one ringset. 989 * @pdcs: PDC instance state 990 * @ringset: index of ringset being used 991 * 992 * Return: PDC_SUCCESS if ring initialized 993 * < 0 otherwise 994 */ 995 static int pdc_ring_init(struct pdc_state *pdcs, int ringset) 996 { 997 int i; 998 int err = PDC_SUCCESS; 999 struct dma64 *dma_reg; 1000 struct device *dev = &pdcs->pdev->dev; 1001 struct pdc_ring_alloc tx; 1002 struct pdc_ring_alloc rx; 1003 1004 /* Allocate tx ring */ 1005 tx.vbase = dma_pool_zalloc(pdcs->ring_pool, GFP_KERNEL, &tx.dmabase); 1006 if (unlikely(!tx.vbase)) { 1007 err = -ENOMEM; 1008 goto done; 1009 } 1010 1011 /* Allocate rx ring */ 1012 rx.vbase = dma_pool_zalloc(pdcs->ring_pool, GFP_KERNEL, &rx.dmabase); 1013 if (unlikely(!rx.vbase)) { 1014 err = -ENOMEM; 1015 goto fail_dealloc; 1016 } 1017 1018 dev_dbg(dev, " - base DMA addr of tx ring %pad", &tx.dmabase); 1019 dev_dbg(dev, " - base virtual addr of tx ring %p", tx.vbase); 1020 dev_dbg(dev, " - base DMA addr of rx ring %pad", &rx.dmabase); 1021 dev_dbg(dev, " - base virtual addr of rx ring %p", rx.vbase); 1022 1023 memcpy(&pdcs->tx_ring_alloc, &tx, sizeof(tx)); 1024 memcpy(&pdcs->rx_ring_alloc, &rx, sizeof(rx)); 1025 1026 pdcs->rxin = 0; 1027 pdcs->rx_msg_start = 0; 1028 pdcs->last_rx_curr = 0; 1029 pdcs->rxout = 0; 1030 pdcs->txin = 0; 1031 pdcs->tx_msg_start = 0; 1032 pdcs->txout = 0; 1033 1034 /* Set descriptor array base addresses */ 1035 pdcs->txd_64 = (struct dma64dd *)pdcs->tx_ring_alloc.vbase; 1036 pdcs->rxd_64 = (struct dma64dd *)pdcs->rx_ring_alloc.vbase; 1037 1038 /* Tell device the base DMA address of each ring */ 1039 dma_reg = &pdcs->regs->dmaregs[ringset]; 1040 1041 /* But first disable DMA and set curptr to 0 for both TX & RX */ 1042 iowrite32(PDC_TX_CTL, &dma_reg->dmaxmt.control); 1043 iowrite32((PDC_RX_CTL + (pdcs->rx_status_len << 1)), 1044 &dma_reg->dmarcv.control); 1045 iowrite32(0, &dma_reg->dmaxmt.ptr); 1046 iowrite32(0, &dma_reg->dmarcv.ptr); 1047 1048 /* Set base DMA addresses */ 1049 iowrite32(lower_32_bits(pdcs->tx_ring_alloc.dmabase), 1050 &dma_reg->dmaxmt.addrlow); 1051 iowrite32(upper_32_bits(pdcs->tx_ring_alloc.dmabase), 1052 &dma_reg->dmaxmt.addrhigh); 1053 1054 iowrite32(lower_32_bits(pdcs->rx_ring_alloc.dmabase), 1055 &dma_reg->dmarcv.addrlow); 1056 iowrite32(upper_32_bits(pdcs->rx_ring_alloc.dmabase), 1057 &dma_reg->dmarcv.addrhigh); 1058 1059 /* Re-enable DMA */ 1060 iowrite32(PDC_TX_CTL | PDC_TX_ENABLE, &dma_reg->dmaxmt.control); 1061 iowrite32((PDC_RX_CTL | PDC_RX_ENABLE | (pdcs->rx_status_len << 1)), 1062 &dma_reg->dmarcv.control); 1063 1064 /* Initialize descriptors */ 1065 for (i = 0; i < PDC_RING_ENTRIES; i++) { 1066 /* Every tx descriptor can be used for start of frame. */ 1067 if (i != pdcs->ntxpost) { 1068 iowrite32(D64_CTRL1_SOF | D64_CTRL1_EOF, 1069 &pdcs->txd_64[i].ctrl1); 1070 } else { 1071 /* Last descriptor in ringset. Set End of Table. */ 1072 iowrite32(D64_CTRL1_SOF | D64_CTRL1_EOF | 1073 D64_CTRL1_EOT, &pdcs->txd_64[i].ctrl1); 1074 } 1075 1076 /* Every rx descriptor can be used for start of frame */ 1077 if (i != pdcs->nrxpost) { 1078 iowrite32(D64_CTRL1_SOF, 1079 &pdcs->rxd_64[i].ctrl1); 1080 } else { 1081 /* Last descriptor in ringset. Set End of Table. */ 1082 iowrite32(D64_CTRL1_SOF | D64_CTRL1_EOT, 1083 &pdcs->rxd_64[i].ctrl1); 1084 } 1085 } 1086 return PDC_SUCCESS; 1087 1088 fail_dealloc: 1089 dma_pool_free(pdcs->ring_pool, tx.vbase, tx.dmabase); 1090 done: 1091 return err; 1092 } 1093 1094 static void pdc_ring_free(struct pdc_state *pdcs) 1095 { 1096 if (pdcs->tx_ring_alloc.vbase) { 1097 dma_pool_free(pdcs->ring_pool, pdcs->tx_ring_alloc.vbase, 1098 pdcs->tx_ring_alloc.dmabase); 1099 pdcs->tx_ring_alloc.vbase = NULL; 1100 } 1101 1102 if (pdcs->rx_ring_alloc.vbase) { 1103 dma_pool_free(pdcs->ring_pool, pdcs->rx_ring_alloc.vbase, 1104 pdcs->rx_ring_alloc.dmabase); 1105 pdcs->rx_ring_alloc.vbase = NULL; 1106 } 1107 } 1108 1109 /** 1110 * pdc_desc_count() - Count the number of DMA descriptors that will be required 1111 * for a given scatterlist. Account for the max length of a DMA buffer. 1112 * @sg: Scatterlist to be DMA'd 1113 * Return: Number of descriptors required 1114 */ 1115 static u32 pdc_desc_count(struct scatterlist *sg) 1116 { 1117 u32 cnt = 0; 1118 1119 while (sg) { 1120 cnt += ((sg->length / PDC_DMA_BUF_MAX) + 1); 1121 sg = sg_next(sg); 1122 } 1123 return cnt; 1124 } 1125 1126 /** 1127 * pdc_rings_full() - Check whether the tx ring has room for tx_cnt descriptors 1128 * and the rx ring has room for rx_cnt descriptors. 1129 * @pdcs: PDC state 1130 * @tx_cnt: The number of descriptors required in the tx ring 1131 * @rx_cnt: The number of descriptors required i the rx ring 1132 * 1133 * Return: true if one of the rings does not have enough space 1134 * false if sufficient space is available in both rings 1135 */ 1136 static bool pdc_rings_full(struct pdc_state *pdcs, int tx_cnt, int rx_cnt) 1137 { 1138 u32 rx_avail; 1139 u32 tx_avail; 1140 bool full = false; 1141 1142 /* Check if the tx and rx rings are likely to have enough space */ 1143 rx_avail = pdcs->nrxpost - NRXDACTIVE(pdcs->rxin, pdcs->rxout, 1144 pdcs->nrxpost); 1145 if (unlikely(rx_cnt > rx_avail)) { 1146 pdcs->rx_ring_full++; 1147 full = true; 1148 } 1149 1150 if (likely(!full)) { 1151 tx_avail = pdcs->ntxpost - NTXDACTIVE(pdcs->txin, pdcs->txout, 1152 pdcs->ntxpost); 1153 if (unlikely(tx_cnt > tx_avail)) { 1154 pdcs->tx_ring_full++; 1155 full = true; 1156 } 1157 } 1158 return full; 1159 } 1160 1161 /** 1162 * pdc_last_tx_done() - If both the tx and rx rings have at least 1163 * PDC_RING_SPACE_MIN descriptors available, then indicate that the mailbox 1164 * framework can submit another message. 1165 * @chan: mailbox channel to check 1166 * Return: true if PDC can accept another message on this channel 1167 */ 1168 static bool pdc_last_tx_done(struct mbox_chan *chan) 1169 { 1170 struct pdc_state *pdcs = chan->con_priv; 1171 bool ret; 1172 1173 if (unlikely(pdc_rings_full(pdcs, PDC_RING_SPACE_MIN, 1174 PDC_RING_SPACE_MIN))) { 1175 pdcs->last_tx_not_done++; 1176 ret = false; 1177 } else { 1178 ret = true; 1179 } 1180 return ret; 1181 } 1182 1183 /** 1184 * pdc_send_data() - mailbox send_data function 1185 * @chan: The mailbox channel on which the data is sent. The channel 1186 * corresponds to a DMA ringset. 1187 * @data: The mailbox message to be sent. The message must be a 1188 * brcm_message structure. 1189 * 1190 * This function is registered as the send_data function for the mailbox 1191 * controller. From the destination scatterlist in the mailbox message, it 1192 * creates a sequence of receive descriptors in the rx ring. From the source 1193 * scatterlist, it creates a sequence of transmit descriptors in the tx ring. 1194 * After creating the descriptors, it writes the rx ptr and tx ptr registers to 1195 * initiate the DMA transfer. 1196 * 1197 * This function does the DMA map and unmap of the src and dst scatterlists in 1198 * the mailbox message. 1199 * 1200 * Return: 0 if successful 1201 * -ENOTSUPP if the mailbox message is a type this driver does not 1202 * support 1203 * < 0 if an error 1204 */ 1205 static int pdc_send_data(struct mbox_chan *chan, void *data) 1206 { 1207 struct pdc_state *pdcs = chan->con_priv; 1208 struct device *dev = &pdcs->pdev->dev; 1209 struct brcm_message *mssg = data; 1210 int err = PDC_SUCCESS; 1211 int src_nent; 1212 int dst_nent; 1213 int nent; 1214 u32 tx_desc_req; 1215 u32 rx_desc_req; 1216 1217 if (unlikely(mssg->type != BRCM_MESSAGE_SPU)) 1218 return -ENOTSUPP; 1219 1220 src_nent = sg_nents(mssg->spu.src); 1221 if (likely(src_nent)) { 1222 nent = dma_map_sg(dev, mssg->spu.src, src_nent, DMA_TO_DEVICE); 1223 if (unlikely(nent == 0)) 1224 return -EIO; 1225 } 1226 1227 dst_nent = sg_nents(mssg->spu.dst); 1228 if (likely(dst_nent)) { 1229 nent = dma_map_sg(dev, mssg->spu.dst, dst_nent, 1230 DMA_FROM_DEVICE); 1231 if (unlikely(nent == 0)) { 1232 dma_unmap_sg(dev, mssg->spu.src, src_nent, 1233 DMA_TO_DEVICE); 1234 return -EIO; 1235 } 1236 } 1237 1238 /* 1239 * Check if the tx and rx rings have enough space. Do this prior to 1240 * writing any tx or rx descriptors. Need to ensure that we do not write 1241 * a partial set of descriptors, or write just rx descriptors but 1242 * corresponding tx descriptors don't fit. Note that we want this check 1243 * and the entire sequence of descriptor to happen without another 1244 * thread getting in. The channel spin lock in the mailbox framework 1245 * ensures this. 1246 */ 1247 tx_desc_req = pdc_desc_count(mssg->spu.src); 1248 rx_desc_req = pdc_desc_count(mssg->spu.dst); 1249 if (unlikely(pdc_rings_full(pdcs, tx_desc_req, rx_desc_req + 1))) 1250 return -ENOSPC; 1251 1252 /* Create rx descriptors to SPU catch response */ 1253 err = pdc_rx_list_init(pdcs, mssg->spu.dst, mssg->ctx); 1254 err |= pdc_rx_list_sg_add(pdcs, mssg->spu.dst); 1255 1256 /* Create tx descriptors to submit SPU request */ 1257 err |= pdc_tx_list_sg_add(pdcs, mssg->spu.src); 1258 err |= pdc_tx_list_final(pdcs); /* initiate transfer */ 1259 1260 if (unlikely(err)) 1261 dev_err(&pdcs->pdev->dev, 1262 "%s failed with error %d", __func__, err); 1263 1264 return err; 1265 } 1266 1267 static int pdc_startup(struct mbox_chan *chan) 1268 { 1269 return pdc_ring_init(chan->con_priv, PDC_RINGSET); 1270 } 1271 1272 static void pdc_shutdown(struct mbox_chan *chan) 1273 { 1274 struct pdc_state *pdcs = chan->con_priv; 1275 1276 if (!pdcs) 1277 return; 1278 1279 dev_dbg(&pdcs->pdev->dev, 1280 "Shutdown mailbox channel for PDC %u", pdcs->pdc_idx); 1281 pdc_ring_free(pdcs); 1282 } 1283 1284 /** 1285 * pdc_hw_init() - Use the given initialization parameters to initialize the 1286 * state for one of the PDCs. 1287 * @pdcs: state of the PDC 1288 */ 1289 static 1290 void pdc_hw_init(struct pdc_state *pdcs) 1291 { 1292 struct platform_device *pdev; 1293 struct device *dev; 1294 struct dma64 *dma_reg; 1295 int ringset = PDC_RINGSET; 1296 1297 pdev = pdcs->pdev; 1298 dev = &pdev->dev; 1299 1300 dev_dbg(dev, "PDC %u initial values:", pdcs->pdc_idx); 1301 dev_dbg(dev, "state structure: %p", 1302 pdcs); 1303 dev_dbg(dev, " - base virtual addr of hw regs %p", 1304 pdcs->pdc_reg_vbase); 1305 1306 /* initialize data structures */ 1307 pdcs->regs = (struct pdc_regs *)pdcs->pdc_reg_vbase; 1308 pdcs->txregs_64 = (struct dma64_regs *) 1309 (((u8 *)pdcs->pdc_reg_vbase) + 1310 PDC_TXREGS_OFFSET + (sizeof(struct dma64) * ringset)); 1311 pdcs->rxregs_64 = (struct dma64_regs *) 1312 (((u8 *)pdcs->pdc_reg_vbase) + 1313 PDC_RXREGS_OFFSET + (sizeof(struct dma64) * ringset)); 1314 1315 pdcs->ntxd = PDC_RING_ENTRIES; 1316 pdcs->nrxd = PDC_RING_ENTRIES; 1317 pdcs->ntxpost = PDC_RING_ENTRIES - 1; 1318 pdcs->nrxpost = PDC_RING_ENTRIES - 1; 1319 iowrite32(0, &pdcs->regs->intmask); 1320 1321 dma_reg = &pdcs->regs->dmaregs[ringset]; 1322 1323 /* Configure DMA but will enable later in pdc_ring_init() */ 1324 iowrite32(PDC_TX_CTL, &dma_reg->dmaxmt.control); 1325 1326 iowrite32(PDC_RX_CTL + (pdcs->rx_status_len << 1), 1327 &dma_reg->dmarcv.control); 1328 1329 /* Reset current index pointers after making sure DMA is disabled */ 1330 iowrite32(0, &dma_reg->dmaxmt.ptr); 1331 iowrite32(0, &dma_reg->dmarcv.ptr); 1332 1333 if (pdcs->pdc_resp_hdr_len == PDC_SPU2_RESP_HDR_LEN) 1334 iowrite32(PDC_CKSUM_CTRL, 1335 pdcs->pdc_reg_vbase + PDC_CKSUM_CTRL_OFFSET); 1336 } 1337 1338 /** 1339 * pdc_hw_disable() - Disable the tx and rx control in the hw. 1340 * @pdcs: PDC state structure 1341 * 1342 */ 1343 static void pdc_hw_disable(struct pdc_state *pdcs) 1344 { 1345 struct dma64 *dma_reg; 1346 1347 dma_reg = &pdcs->regs->dmaregs[PDC_RINGSET]; 1348 iowrite32(PDC_TX_CTL, &dma_reg->dmaxmt.control); 1349 iowrite32(PDC_RX_CTL + (pdcs->rx_status_len << 1), 1350 &dma_reg->dmarcv.control); 1351 } 1352 1353 /** 1354 * pdc_rx_buf_pool_create() - Pool of receive buffers used to catch the metadata 1355 * header returned with each response message. 1356 * @pdcs: PDC state structure 1357 * 1358 * The metadata is not returned to the mailbox client. So the PDC driver 1359 * manages these buffers. 1360 * 1361 * Return: PDC_SUCCESS 1362 * -ENOMEM if pool creation fails 1363 */ 1364 static int pdc_rx_buf_pool_create(struct pdc_state *pdcs) 1365 { 1366 struct platform_device *pdev; 1367 struct device *dev; 1368 1369 pdev = pdcs->pdev; 1370 dev = &pdev->dev; 1371 1372 pdcs->pdc_resp_hdr_len = pdcs->rx_status_len; 1373 if (pdcs->use_bcm_hdr) 1374 pdcs->pdc_resp_hdr_len += BCM_HDR_LEN; 1375 1376 pdcs->rx_buf_pool = dma_pool_create("pdc rx bufs", dev, 1377 pdcs->pdc_resp_hdr_len, 1378 RX_BUF_ALIGN, 0); 1379 if (!pdcs->rx_buf_pool) 1380 return -ENOMEM; 1381 1382 return PDC_SUCCESS; 1383 } 1384 1385 /** 1386 * pdc_interrupts_init() - Initialize the interrupt configuration for a PDC and 1387 * specify a threaded IRQ handler for deferred handling of interrupts outside of 1388 * interrupt context. 1389 * @pdcs: PDC state 1390 * 1391 * Set the interrupt mask for transmit and receive done. 1392 * Set the lazy interrupt frame count to generate an interrupt for just one pkt. 1393 * 1394 * Return: PDC_SUCCESS 1395 * <0 if threaded irq request fails 1396 */ 1397 static int pdc_interrupts_init(struct pdc_state *pdcs) 1398 { 1399 struct platform_device *pdev = pdcs->pdev; 1400 struct device *dev = &pdev->dev; 1401 struct device_node *dn = pdev->dev.of_node; 1402 int err; 1403 1404 /* interrupt configuration */ 1405 iowrite32(PDC_INTMASK, pdcs->pdc_reg_vbase + PDC_INTMASK_OFFSET); 1406 1407 if (pdcs->hw_type == FA_HW) 1408 iowrite32(PDC_LAZY_INT, pdcs->pdc_reg_vbase + 1409 FA_RCVLAZY0_OFFSET); 1410 else 1411 iowrite32(PDC_LAZY_INT, pdcs->pdc_reg_vbase + 1412 PDC_RCVLAZY0_OFFSET); 1413 1414 /* read irq from device tree */ 1415 pdcs->pdc_irq = irq_of_parse_and_map(dn, 0); 1416 dev_dbg(dev, "pdc device %s irq %u for pdcs %p", 1417 dev_name(dev), pdcs->pdc_irq, pdcs); 1418 1419 err = devm_request_irq(dev, pdcs->pdc_irq, pdc_irq_handler, 0, 1420 dev_name(dev), dev); 1421 if (err) { 1422 dev_err(dev, "IRQ %u request failed with err %d\n", 1423 pdcs->pdc_irq, err); 1424 return err; 1425 } 1426 return PDC_SUCCESS; 1427 } 1428 1429 static const struct mbox_chan_ops pdc_mbox_chan_ops = { 1430 .send_data = pdc_send_data, 1431 .last_tx_done = pdc_last_tx_done, 1432 .startup = pdc_startup, 1433 .shutdown = pdc_shutdown 1434 }; 1435 1436 /** 1437 * pdc_mb_init() - Initialize the mailbox controller. 1438 * @pdcs: PDC state 1439 * 1440 * Each PDC is a mailbox controller. Each ringset is a mailbox channel. Kernel 1441 * driver only uses one ringset and thus one mb channel. PDC uses the transmit 1442 * complete interrupt to determine when a mailbox message has successfully been 1443 * transmitted. 1444 * 1445 * Return: 0 on success 1446 * < 0 if there is an allocation or registration failure 1447 */ 1448 static int pdc_mb_init(struct pdc_state *pdcs) 1449 { 1450 struct device *dev = &pdcs->pdev->dev; 1451 struct mbox_controller *mbc; 1452 int chan_index; 1453 int err; 1454 1455 mbc = &pdcs->mbc; 1456 mbc->dev = dev; 1457 mbc->ops = &pdc_mbox_chan_ops; 1458 mbc->num_chans = 1; 1459 mbc->chans = devm_kcalloc(dev, mbc->num_chans, sizeof(*mbc->chans), 1460 GFP_KERNEL); 1461 if (!mbc->chans) 1462 return -ENOMEM; 1463 1464 mbc->txdone_irq = false; 1465 mbc->txdone_poll = true; 1466 mbc->txpoll_period = 1; 1467 for (chan_index = 0; chan_index < mbc->num_chans; chan_index++) 1468 mbc->chans[chan_index].con_priv = pdcs; 1469 1470 /* Register mailbox controller */ 1471 err = devm_mbox_controller_register(dev, mbc); 1472 if (err) { 1473 dev_crit(dev, 1474 "Failed to register PDC mailbox controller. Error %d.", 1475 err); 1476 return err; 1477 } 1478 return 0; 1479 } 1480 1481 /* Device tree API */ 1482 static const int pdc_hw = PDC_HW; 1483 static const int fa_hw = FA_HW; 1484 1485 static const struct of_device_id pdc_mbox_of_match[] = { 1486 {.compatible = "brcm,iproc-pdc-mbox", .data = &pdc_hw}, 1487 {.compatible = "brcm,iproc-fa2-mbox", .data = &fa_hw}, 1488 { /* sentinel */ } 1489 }; 1490 MODULE_DEVICE_TABLE(of, pdc_mbox_of_match); 1491 1492 /** 1493 * pdc_dt_read() - Read application-specific data from device tree. 1494 * @pdev: Platform device 1495 * @pdcs: PDC state 1496 * 1497 * Reads the number of bytes of receive status that precede each received frame. 1498 * Reads whether transmit and received frames should be preceded by an 8-byte 1499 * BCM header. 1500 * 1501 * Return: 0 if successful 1502 * -ENODEV if device not available 1503 */ 1504 static int pdc_dt_read(struct platform_device *pdev, struct pdc_state *pdcs) 1505 { 1506 struct device *dev = &pdev->dev; 1507 struct device_node *dn = pdev->dev.of_node; 1508 const struct of_device_id *match; 1509 const int *hw_type; 1510 int err; 1511 1512 err = of_property_read_u32(dn, "brcm,rx-status-len", 1513 &pdcs->rx_status_len); 1514 if (err < 0) 1515 dev_err(dev, 1516 "%s failed to get DMA receive status length from device tree", 1517 __func__); 1518 1519 pdcs->use_bcm_hdr = of_property_read_bool(dn, "brcm,use-bcm-hdr"); 1520 1521 pdcs->hw_type = PDC_HW; 1522 1523 match = of_match_device(of_match_ptr(pdc_mbox_of_match), dev); 1524 if (match != NULL) { 1525 hw_type = match->data; 1526 pdcs->hw_type = *hw_type; 1527 } 1528 1529 return 0; 1530 } 1531 1532 /** 1533 * pdc_probe() - Probe function for PDC driver. 1534 * @pdev: PDC platform device 1535 * 1536 * Reserve and map register regions defined in device tree. 1537 * Allocate and initialize tx and rx DMA rings. 1538 * Initialize a mailbox controller for each PDC. 1539 * 1540 * Return: 0 if successful 1541 * < 0 if an error 1542 */ 1543 static int pdc_probe(struct platform_device *pdev) 1544 { 1545 int err = 0; 1546 struct device *dev = &pdev->dev; 1547 struct resource *pdc_regs; 1548 struct pdc_state *pdcs; 1549 1550 /* PDC state for one SPU */ 1551 pdcs = devm_kzalloc(dev, sizeof(*pdcs), GFP_KERNEL); 1552 if (!pdcs) { 1553 err = -ENOMEM; 1554 goto cleanup; 1555 } 1556 1557 pdcs->pdev = pdev; 1558 platform_set_drvdata(pdev, pdcs); 1559 pdcs->pdc_idx = pdcg.num_spu; 1560 pdcg.num_spu++; 1561 1562 err = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(39)); 1563 if (err) { 1564 dev_warn(dev, "PDC device cannot perform DMA. Error %d.", err); 1565 goto cleanup; 1566 } 1567 1568 /* Create DMA pool for tx ring */ 1569 pdcs->ring_pool = dma_pool_create("pdc rings", dev, PDC_RING_SIZE, 1570 RING_ALIGN, 0); 1571 if (!pdcs->ring_pool) { 1572 err = -ENOMEM; 1573 goto cleanup; 1574 } 1575 1576 err = pdc_dt_read(pdev, pdcs); 1577 if (err) 1578 goto cleanup_ring_pool; 1579 1580 pdc_regs = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1581 if (!pdc_regs) { 1582 err = -ENODEV; 1583 goto cleanup_ring_pool; 1584 } 1585 dev_dbg(dev, "PDC register region res.start = %pa, res.end = %pa", 1586 &pdc_regs->start, &pdc_regs->end); 1587 1588 pdcs->pdc_reg_vbase = devm_ioremap_resource(&pdev->dev, pdc_regs); 1589 if (IS_ERR(pdcs->pdc_reg_vbase)) { 1590 err = PTR_ERR(pdcs->pdc_reg_vbase); 1591 dev_err(&pdev->dev, "Failed to map registers: %d\n", err); 1592 goto cleanup_ring_pool; 1593 } 1594 1595 /* create rx buffer pool after dt read to know how big buffers are */ 1596 err = pdc_rx_buf_pool_create(pdcs); 1597 if (err) 1598 goto cleanup_ring_pool; 1599 1600 pdc_hw_init(pdcs); 1601 1602 /* Init tasklet for deferred DMA rx processing */ 1603 tasklet_init(&pdcs->rx_tasklet, pdc_tasklet_cb, (unsigned long)pdcs); 1604 1605 err = pdc_interrupts_init(pdcs); 1606 if (err) 1607 goto cleanup_buf_pool; 1608 1609 /* Initialize mailbox controller */ 1610 err = pdc_mb_init(pdcs); 1611 if (err) 1612 goto cleanup_buf_pool; 1613 1614 pdc_setup_debugfs(pdcs); 1615 1616 dev_dbg(dev, "pdc_probe() successful"); 1617 return PDC_SUCCESS; 1618 1619 cleanup_buf_pool: 1620 tasklet_kill(&pdcs->rx_tasklet); 1621 dma_pool_destroy(pdcs->rx_buf_pool); 1622 1623 cleanup_ring_pool: 1624 dma_pool_destroy(pdcs->ring_pool); 1625 1626 cleanup: 1627 return err; 1628 } 1629 1630 static int pdc_remove(struct platform_device *pdev) 1631 { 1632 struct pdc_state *pdcs = platform_get_drvdata(pdev); 1633 1634 pdc_free_debugfs(); 1635 1636 tasklet_kill(&pdcs->rx_tasklet); 1637 1638 pdc_hw_disable(pdcs); 1639 1640 dma_pool_destroy(pdcs->rx_buf_pool); 1641 dma_pool_destroy(pdcs->ring_pool); 1642 return 0; 1643 } 1644 1645 static struct platform_driver pdc_mbox_driver = { 1646 .probe = pdc_probe, 1647 .remove = pdc_remove, 1648 .driver = { 1649 .name = "brcm-iproc-pdc-mbox", 1650 .of_match_table = of_match_ptr(pdc_mbox_of_match), 1651 }, 1652 }; 1653 module_platform_driver(pdc_mbox_driver); 1654 1655 MODULE_AUTHOR("Rob Rice <rob.rice@broadcom.com>"); 1656 MODULE_DESCRIPTION("Broadcom PDC mailbox driver"); 1657 MODULE_LICENSE("GPL v2"); 1658