1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (C) 2021-2023 Samuel Holland <samuel@sholland.org> 4 * 5 * Partly based on drivers/leds/leds-turris-omnia.c, which is: 6 * Copyright (c) 2020 by Marek Behún <kabel@kernel.org> 7 */ 8 9 #include <linux/bitfield.h> 10 #include <linux/clk.h> 11 #include <linux/delay.h> 12 #include <linux/dma-mapping.h> 13 #include <linux/dmaengine.h> 14 #include <linux/interrupt.h> 15 #include <linux/io.h> 16 #include <linux/led-class-multicolor.h> 17 #include <linux/leds.h> 18 #include <linux/mod_devicetable.h> 19 #include <linux/module.h> 20 #include <linux/platform_device.h> 21 #include <linux/pm.h> 22 #include <linux/property.h> 23 #include <linux/reset.h> 24 #include <linux/spinlock.h> 25 26 #define LEDC_CTRL_REG 0x0000 27 #define LEDC_CTRL_REG_DATA_LENGTH GENMASK(28, 16) 28 #define LEDC_CTRL_REG_RGB_MODE GENMASK(8, 6) 29 #define LEDC_CTRL_REG_LEDC_EN BIT(0) 30 #define LEDC_T01_TIMING_CTRL_REG 0x0004 31 #define LEDC_T01_TIMING_CTRL_REG_T1H GENMASK(26, 21) 32 #define LEDC_T01_TIMING_CTRL_REG_T1L GENMASK(20, 16) 33 #define LEDC_T01_TIMING_CTRL_REG_T0H GENMASK(10, 6) 34 #define LEDC_T01_TIMING_CTRL_REG_T0L GENMASK(5, 0) 35 #define LEDC_RESET_TIMING_CTRL_REG 0x000c 36 #define LEDC_RESET_TIMING_CTRL_REG_TR GENMASK(28, 16) 37 #define LEDC_RESET_TIMING_CTRL_REG_LED_NUM GENMASK(9, 0) 38 #define LEDC_DATA_REG 0x0014 39 #define LEDC_DMA_CTRL_REG 0x0018 40 #define LEDC_DMA_CTRL_REG_DMA_EN BIT(5) 41 #define LEDC_DMA_CTRL_REG_FIFO_TRIG_LEVEL GENMASK(4, 0) 42 #define LEDC_INT_CTRL_REG 0x001c 43 #define LEDC_INT_CTRL_REG_GLOBAL_INT_EN BIT(5) 44 #define LEDC_INT_CTRL_REG_FIFO_CPUREQ_INT_EN BIT(1) 45 #define LEDC_INT_CTRL_REG_TRANS_FINISH_INT_EN BIT(0) 46 #define LEDC_INT_STS_REG 0x0020 47 #define LEDC_INT_STS_REG_FIFO_WLW GENMASK(15, 10) 48 #define LEDC_INT_STS_REG_FIFO_CPUREQ_INT BIT(1) 49 #define LEDC_INT_STS_REG_TRANS_FINISH_INT BIT(0) 50 51 #define LEDC_FIFO_DEPTH 32U 52 #define LEDC_MAX_LEDS 1024 53 #define LEDC_CHANNELS_PER_LED 3 /* RGB */ 54 55 #define LEDS_TO_BYTES(n) ((n) * sizeof(u32)) 56 57 struct sun50i_a100_ledc_led { 58 struct led_classdev_mc mc_cdev; 59 struct mc_subled subled_info[LEDC_CHANNELS_PER_LED]; 60 u32 addr; 61 }; 62 63 #define to_ledc_led(mc) container_of(mc, struct sun50i_a100_ledc_led, mc_cdev) 64 65 struct sun50i_a100_ledc_timing { 66 u32 t0h_ns; 67 u32 t0l_ns; 68 u32 t1h_ns; 69 u32 t1l_ns; 70 u32 treset_ns; 71 }; 72 73 struct sun50i_a100_ledc { 74 struct device *dev; 75 void __iomem *base; 76 struct clk *bus_clk; 77 struct clk *mod_clk; 78 struct reset_control *reset; 79 80 u32 *buffer; 81 struct dma_chan *dma_chan; 82 dma_addr_t dma_handle; 83 unsigned int pio_length; 84 unsigned int pio_offset; 85 86 spinlock_t lock; 87 unsigned int next_length; 88 bool xfer_active; 89 90 u32 format; 91 struct sun50i_a100_ledc_timing timing; 92 93 u32 max_addr; 94 u32 num_leds; 95 struct sun50i_a100_ledc_led leds[] __counted_by(num_leds); 96 }; 97 98 static int sun50i_a100_ledc_dma_xfer(struct sun50i_a100_ledc *priv, unsigned int length) 99 { 100 struct dma_async_tx_descriptor *desc; 101 dma_cookie_t cookie; 102 103 desc = dmaengine_prep_slave_single(priv->dma_chan, priv->dma_handle, 104 LEDS_TO_BYTES(length), DMA_MEM_TO_DEV, 0); 105 if (!desc) 106 return -ENOMEM; 107 108 cookie = dmaengine_submit(desc); 109 if (dma_submit_error(cookie)) 110 return -EIO; 111 112 dma_async_issue_pending(priv->dma_chan); 113 114 return 0; 115 } 116 117 static void sun50i_a100_ledc_pio_xfer(struct sun50i_a100_ledc *priv, unsigned int fifo_used) 118 { 119 unsigned int burst, length, offset; 120 u32 control; 121 122 length = priv->pio_length; 123 offset = priv->pio_offset; 124 burst = min(length, LEDC_FIFO_DEPTH - fifo_used); 125 126 iowrite32_rep(priv->base + LEDC_DATA_REG, priv->buffer + offset, burst); 127 128 if (burst < length) { 129 priv->pio_length = length - burst; 130 priv->pio_offset = offset + burst; 131 132 if (!offset) { 133 control = readl(priv->base + LEDC_INT_CTRL_REG); 134 control |= LEDC_INT_CTRL_REG_FIFO_CPUREQ_INT_EN; 135 writel(control, priv->base + LEDC_INT_CTRL_REG); 136 } 137 } else { 138 /* Disable the request IRQ once all data is written. */ 139 control = readl(priv->base + LEDC_INT_CTRL_REG); 140 control &= ~LEDC_INT_CTRL_REG_FIFO_CPUREQ_INT_EN; 141 writel(control, priv->base + LEDC_INT_CTRL_REG); 142 } 143 } 144 145 static void sun50i_a100_ledc_start_xfer(struct sun50i_a100_ledc *priv, unsigned int length) 146 { 147 bool use_dma = false; 148 u32 control; 149 150 if (priv->dma_chan && length > LEDC_FIFO_DEPTH) { 151 int ret; 152 153 ret = sun50i_a100_ledc_dma_xfer(priv, length); 154 if (ret) 155 dev_warn(priv->dev, "Failed to set up DMA (%d), using PIO\n", ret); 156 else 157 use_dma = true; 158 } 159 160 /* The DMA trigger level must be at least the burst length. */ 161 control = FIELD_PREP(LEDC_DMA_CTRL_REG_DMA_EN, use_dma) | 162 FIELD_PREP_CONST(LEDC_DMA_CTRL_REG_FIFO_TRIG_LEVEL, LEDC_FIFO_DEPTH / 2); 163 writel(control, priv->base + LEDC_DMA_CTRL_REG); 164 165 control = readl(priv->base + LEDC_CTRL_REG); 166 control &= ~LEDC_CTRL_REG_DATA_LENGTH; 167 control |= FIELD_PREP(LEDC_CTRL_REG_DATA_LENGTH, length) | LEDC_CTRL_REG_LEDC_EN; 168 writel(control, priv->base + LEDC_CTRL_REG); 169 170 if (!use_dma) { 171 /* The FIFO is empty when starting a new transfer. */ 172 unsigned int fifo_used = 0; 173 174 priv->pio_length = length; 175 priv->pio_offset = 0; 176 177 sun50i_a100_ledc_pio_xfer(priv, fifo_used); 178 } 179 } 180 181 static irqreturn_t sun50i_a100_ledc_irq(int irq, void *data) 182 { 183 struct sun50i_a100_ledc *priv = data; 184 u32 status; 185 186 status = readl(priv->base + LEDC_INT_STS_REG); 187 188 if (status & LEDC_INT_STS_REG_TRANS_FINISH_INT) { 189 unsigned int next_length; 190 191 spin_lock(&priv->lock); 192 193 /* If another transfer is queued, dequeue and start it. */ 194 next_length = priv->next_length; 195 if (next_length) 196 priv->next_length = 0; 197 else 198 priv->xfer_active = false; 199 200 spin_unlock(&priv->lock); 201 202 if (next_length) 203 sun50i_a100_ledc_start_xfer(priv, next_length); 204 } else if (status & LEDC_INT_STS_REG_FIFO_CPUREQ_INT) { 205 /* Continue the current transfer. */ 206 sun50i_a100_ledc_pio_xfer(priv, FIELD_GET(LEDC_INT_STS_REG_FIFO_WLW, status)); 207 } 208 209 /* Clear the W1C status bits. */ 210 writel(status, priv->base + LEDC_INT_STS_REG); 211 212 return IRQ_HANDLED; 213 } 214 215 static void sun50i_a100_ledc_brightness_set(struct led_classdev *cdev, 216 enum led_brightness brightness) 217 { 218 struct sun50i_a100_ledc *priv = dev_get_drvdata(cdev->dev->parent); 219 struct led_classdev_mc *mc_cdev = lcdev_to_mccdev(cdev); 220 struct sun50i_a100_ledc_led *led = to_ledc_led(mc_cdev); 221 unsigned int next_length; 222 unsigned long flags; 223 bool xfer_active; 224 225 led_mc_calc_color_components(mc_cdev, brightness); 226 227 priv->buffer[led->addr] = led->subled_info[0].brightness << 16 | 228 led->subled_info[1].brightness << 8 | 229 led->subled_info[2].brightness; 230 231 spin_lock_irqsave(&priv->lock, flags); 232 233 /* Start, enqueue, or extend an enqueued transfer, as appropriate. */ 234 next_length = max(priv->next_length, led->addr + 1); 235 xfer_active = priv->xfer_active; 236 if (xfer_active) 237 priv->next_length = next_length; 238 else 239 priv->xfer_active = true; 240 241 spin_unlock_irqrestore(&priv->lock, flags); 242 243 if (!xfer_active) 244 sun50i_a100_ledc_start_xfer(priv, next_length); 245 } 246 247 static const char *const sun50i_a100_ledc_formats[] = { 248 "rgb", "rbg", "grb", "gbr", "brg", "bgr", 249 }; 250 251 static int sun50i_a100_ledc_parse_format(struct device *dev, 252 struct sun50i_a100_ledc *priv) 253 { 254 const char *format = "grb"; 255 int i; 256 257 device_property_read_string(dev, "allwinner,pixel-format", &format); 258 259 i = match_string(sun50i_a100_ledc_formats, ARRAY_SIZE(sun50i_a100_ledc_formats), format); 260 if (i < 0) 261 return dev_err_probe(dev, i, "Bad pixel format '%s'\n", format); 262 263 priv->format = i; 264 return 0; 265 } 266 267 static void sun50i_a100_ledc_set_format(struct sun50i_a100_ledc *priv) 268 { 269 u32 control; 270 271 control = readl(priv->base + LEDC_CTRL_REG); 272 control &= ~LEDC_CTRL_REG_RGB_MODE; 273 control |= FIELD_PREP(LEDC_CTRL_REG_RGB_MODE, priv->format); 274 writel(control, priv->base + LEDC_CTRL_REG); 275 } 276 277 static const struct sun50i_a100_ledc_timing sun50i_a100_ledc_default_timing = { 278 .t0h_ns = 336, 279 .t0l_ns = 840, 280 .t1h_ns = 882, 281 .t1l_ns = 294, 282 .treset_ns = 300000, 283 }; 284 285 static int sun50i_a100_ledc_parse_timing(struct device *dev, 286 struct sun50i_a100_ledc *priv) 287 { 288 struct sun50i_a100_ledc_timing *timing = &priv->timing; 289 290 *timing = sun50i_a100_ledc_default_timing; 291 292 device_property_read_u32(dev, "allwinner,t0h-ns", &timing->t0h_ns); 293 device_property_read_u32(dev, "allwinner,t0l-ns", &timing->t0l_ns); 294 device_property_read_u32(dev, "allwinner,t1h-ns", &timing->t1h_ns); 295 device_property_read_u32(dev, "allwinner,t1l-ns", &timing->t1l_ns); 296 device_property_read_u32(dev, "allwinner,treset-ns", &timing->treset_ns); 297 298 return 0; 299 } 300 301 static void sun50i_a100_ledc_set_timing(struct sun50i_a100_ledc *priv) 302 { 303 const struct sun50i_a100_ledc_timing *timing = &priv->timing; 304 unsigned long mod_freq = clk_get_rate(priv->mod_clk); 305 u32 cycle_ns; 306 u32 control; 307 308 if (!mod_freq) 309 return; 310 311 cycle_ns = NSEC_PER_SEC / mod_freq; 312 control = FIELD_PREP(LEDC_T01_TIMING_CTRL_REG_T1H, timing->t1h_ns / cycle_ns) | 313 FIELD_PREP(LEDC_T01_TIMING_CTRL_REG_T1L, timing->t1l_ns / cycle_ns) | 314 FIELD_PREP(LEDC_T01_TIMING_CTRL_REG_T0H, timing->t0h_ns / cycle_ns) | 315 FIELD_PREP(LEDC_T01_TIMING_CTRL_REG_T0L, timing->t0l_ns / cycle_ns); 316 writel(control, priv->base + LEDC_T01_TIMING_CTRL_REG); 317 318 control = FIELD_PREP(LEDC_RESET_TIMING_CTRL_REG_TR, timing->treset_ns / cycle_ns) | 319 FIELD_PREP(LEDC_RESET_TIMING_CTRL_REG_LED_NUM, priv->max_addr); 320 writel(control, priv->base + LEDC_RESET_TIMING_CTRL_REG); 321 } 322 323 static int sun50i_a100_ledc_resume(struct device *dev) 324 { 325 struct sun50i_a100_ledc *priv = dev_get_drvdata(dev); 326 int ret; 327 328 ret = reset_control_deassert(priv->reset); 329 if (ret) 330 return ret; 331 332 ret = clk_prepare_enable(priv->bus_clk); 333 if (ret) 334 goto err_assert_reset; 335 336 ret = clk_prepare_enable(priv->mod_clk); 337 if (ret) 338 goto err_disable_bus_clk; 339 340 sun50i_a100_ledc_set_format(priv); 341 sun50i_a100_ledc_set_timing(priv); 342 343 writel(LEDC_INT_CTRL_REG_GLOBAL_INT_EN | LEDC_INT_CTRL_REG_TRANS_FINISH_INT_EN, 344 priv->base + LEDC_INT_CTRL_REG); 345 346 return 0; 347 348 err_disable_bus_clk: 349 clk_disable_unprepare(priv->bus_clk); 350 err_assert_reset: 351 reset_control_assert(priv->reset); 352 353 return ret; 354 } 355 356 static int sun50i_a100_ledc_suspend(struct device *dev) 357 { 358 struct sun50i_a100_ledc *priv = dev_get_drvdata(dev); 359 360 /* Wait for all transfers to complete. */ 361 for (;;) { 362 unsigned long flags; 363 bool xfer_active; 364 365 spin_lock_irqsave(&priv->lock, flags); 366 xfer_active = priv->xfer_active; 367 spin_unlock_irqrestore(&priv->lock, flags); 368 if (!xfer_active) 369 break; 370 371 usleep_range(1000, 1100); 372 } 373 374 clk_disable_unprepare(priv->mod_clk); 375 clk_disable_unprepare(priv->bus_clk); 376 reset_control_assert(priv->reset); 377 378 return 0; 379 } 380 381 static void sun50i_a100_ledc_dma_cleanup(void *data) 382 { 383 struct sun50i_a100_ledc *priv = data; 384 385 dma_release_channel(priv->dma_chan); 386 } 387 388 static int sun50i_a100_ledc_probe(struct platform_device *pdev) 389 { 390 struct dma_slave_config dma_cfg = {}; 391 struct led_init_data init_data = {}; 392 struct sun50i_a100_ledc_led *led; 393 struct device *dev = &pdev->dev; 394 struct sun50i_a100_ledc *priv; 395 struct fwnode_handle *child; 396 struct resource *mem; 397 u32 max_addr = 0; 398 u32 num_leds = 0; 399 int irq, ret; 400 401 /* 402 * The maximum LED address must be known in sun50i_a100_ledc_resume() before 403 * class device registration, so parse and validate the subnodes up front. 404 */ 405 device_for_each_child_node(dev, child) { 406 u32 addr, color; 407 408 ret = fwnode_property_read_u32(child, "reg", &addr); 409 if (ret || addr >= LEDC_MAX_LEDS) { 410 fwnode_handle_put(child); 411 return dev_err_probe(dev, -EINVAL, "'reg' must be between 0 and %d\n", 412 LEDC_MAX_LEDS - 1); 413 } 414 415 ret = fwnode_property_read_u32(child, "color", &color); 416 if (ret || color != LED_COLOR_ID_RGB) { 417 fwnode_handle_put(child); 418 return dev_err_probe(dev, -EINVAL, "'color' must be LED_COLOR_ID_RGB\n"); 419 } 420 421 max_addr = max(max_addr, addr); 422 num_leds++; 423 } 424 425 if (!num_leds) 426 return -ENODEV; 427 428 priv = devm_kzalloc(dev, struct_size(priv, leds, num_leds), GFP_KERNEL); 429 if (!priv) 430 return -ENOMEM; 431 432 priv->dev = dev; 433 priv->max_addr = max_addr; 434 priv->num_leds = num_leds; 435 spin_lock_init(&priv->lock); 436 dev_set_drvdata(dev, priv); 437 438 ret = sun50i_a100_ledc_parse_format(dev, priv); 439 if (ret) 440 return ret; 441 442 ret = sun50i_a100_ledc_parse_timing(dev, priv); 443 if (ret) 444 return ret; 445 446 priv->base = devm_platform_get_and_ioremap_resource(pdev, 0, &mem); 447 if (IS_ERR(priv->base)) 448 return PTR_ERR(priv->base); 449 450 priv->bus_clk = devm_clk_get(dev, "bus"); 451 if (IS_ERR(priv->bus_clk)) 452 return PTR_ERR(priv->bus_clk); 453 454 priv->mod_clk = devm_clk_get(dev, "mod"); 455 if (IS_ERR(priv->mod_clk)) 456 return PTR_ERR(priv->mod_clk); 457 458 priv->reset = devm_reset_control_get_exclusive(dev, NULL); 459 if (IS_ERR(priv->reset)) 460 return PTR_ERR(priv->reset); 461 462 priv->dma_chan = dma_request_chan(dev, "tx"); 463 if (IS_ERR(priv->dma_chan)) { 464 if (PTR_ERR(priv->dma_chan) != -ENODEV) 465 return PTR_ERR(priv->dma_chan); 466 467 priv->dma_chan = NULL; 468 469 priv->buffer = devm_kzalloc(dev, LEDS_TO_BYTES(LEDC_MAX_LEDS), GFP_KERNEL); 470 if (!priv->buffer) 471 return -ENOMEM; 472 } else { 473 ret = devm_add_action_or_reset(dev, sun50i_a100_ledc_dma_cleanup, priv); 474 if (ret) 475 return ret; 476 477 dma_cfg.dst_addr = mem->start + LEDC_DATA_REG; 478 dma_cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; 479 dma_cfg.dst_maxburst = LEDC_FIFO_DEPTH / 2; 480 481 ret = dmaengine_slave_config(priv->dma_chan, &dma_cfg); 482 if (ret) 483 return ret; 484 485 priv->buffer = dmam_alloc_attrs(dmaengine_get_dma_device(priv->dma_chan), 486 LEDS_TO_BYTES(LEDC_MAX_LEDS), &priv->dma_handle, 487 GFP_KERNEL, DMA_ATTR_WRITE_COMBINE); 488 if (!priv->buffer) 489 return -ENOMEM; 490 } 491 492 irq = platform_get_irq(pdev, 0); 493 if (irq < 0) 494 return irq; 495 496 ret = devm_request_irq(dev, irq, sun50i_a100_ledc_irq, 0, dev_name(dev), priv); 497 if (ret) 498 return ret; 499 500 ret = sun50i_a100_ledc_resume(dev); 501 if (ret) 502 return ret; 503 504 led = priv->leds; 505 device_for_each_child_node(dev, child) { 506 struct led_classdev *cdev; 507 508 /* The node was already validated above. */ 509 fwnode_property_read_u32(child, "reg", &led->addr); 510 511 led->subled_info[0].color_index = LED_COLOR_ID_RED; 512 led->subled_info[0].channel = 0; 513 led->subled_info[1].color_index = LED_COLOR_ID_GREEN; 514 led->subled_info[1].channel = 1; 515 led->subled_info[2].color_index = LED_COLOR_ID_BLUE; 516 led->subled_info[2].channel = 2; 517 518 led->mc_cdev.num_colors = ARRAY_SIZE(led->subled_info); 519 led->mc_cdev.subled_info = led->subled_info; 520 521 cdev = &led->mc_cdev.led_cdev; 522 cdev->max_brightness = U8_MAX; 523 cdev->brightness_set = sun50i_a100_ledc_brightness_set; 524 525 init_data.fwnode = child; 526 527 ret = led_classdev_multicolor_register_ext(dev, &led->mc_cdev, &init_data); 528 if (ret) { 529 dev_err_probe(dev, ret, "Failed to register multicolor LED %u", led->addr); 530 goto err_put_child; 531 } 532 533 led++; 534 } 535 536 dev_info(dev, "Registered %u LEDs\n", num_leds); 537 538 return 0; 539 540 err_put_child: 541 fwnode_handle_put(child); 542 while (led-- > priv->leds) 543 led_classdev_multicolor_unregister(&led->mc_cdev); 544 sun50i_a100_ledc_suspend(&pdev->dev); 545 546 return ret; 547 } 548 549 static void sun50i_a100_ledc_remove(struct platform_device *pdev) 550 { 551 struct sun50i_a100_ledc *priv = platform_get_drvdata(pdev); 552 553 for (u32 i = 0; i < priv->num_leds; i++) 554 led_classdev_multicolor_unregister(&priv->leds[i].mc_cdev); 555 sun50i_a100_ledc_suspend(&pdev->dev); 556 } 557 558 static const struct of_device_id sun50i_a100_ledc_of_match[] = { 559 { .compatible = "allwinner,sun50i-a100-ledc" }, 560 {} 561 }; 562 MODULE_DEVICE_TABLE(of, sun50i_a100_ledc_of_match); 563 564 static DEFINE_SIMPLE_DEV_PM_OPS(sun50i_a100_ledc_pm, 565 sun50i_a100_ledc_suspend, 566 sun50i_a100_ledc_resume); 567 568 static struct platform_driver sun50i_a100_ledc_driver = { 569 .probe = sun50i_a100_ledc_probe, 570 .remove_new = sun50i_a100_ledc_remove, 571 .shutdown = sun50i_a100_ledc_remove, 572 .driver = { 573 .name = "sun50i-a100-ledc", 574 .of_match_table = sun50i_a100_ledc_of_match, 575 .pm = pm_ptr(&sun50i_a100_ledc_pm), 576 }, 577 }; 578 module_platform_driver(sun50i_a100_ledc_driver); 579 580 MODULE_AUTHOR("Samuel Holland <samuel@sholland.org>"); 581 MODULE_DESCRIPTION("Allwinner A100 LED controller driver"); 582 MODULE_LICENSE("GPL"); 583