1 /* 2 * SPEAr platform shared irq layer source file 3 * 4 * Copyright (C) 2009-2012 ST Microelectronics 5 * Viresh Kumar <viresh.linux@gmail.com> 6 * 7 * Copyright (C) 2012 ST Microelectronics 8 * Shiraz Hashim <shiraz.linux.kernel@gmail.com> 9 * 10 * This file is licensed under the terms of the GNU General Public 11 * License version 2. This program is licensed "as is" without any 12 * warranty of any kind, whether express or implied. 13 */ 14 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 15 16 #include <linux/err.h> 17 #include <linux/export.h> 18 #include <linux/interrupt.h> 19 #include <linux/io.h> 20 #include <linux/irq.h> 21 #include <linux/irqdomain.h> 22 #include <linux/of.h> 23 #include <linux/of_address.h> 24 #include <linux/of_irq.h> 25 #include <linux/spinlock.h> 26 27 #include "irqchip.h" 28 29 /* 30 * struct spear_shirq: shared irq structure 31 * 32 * base: Base register address 33 * status_reg: Status register offset for chained interrupt handler 34 * mask_reg: Mask register offset for irq chip 35 * mask: Mask to apply to the status register 36 * virq_base: Base virtual interrupt number 37 * nr_irqs: Number of interrupts handled by this block 38 * offset: Bit offset of the first interrupt 39 * irq_chip: Interrupt controller chip used for this instance, 40 * if NULL group is disabled, but accounted 41 */ 42 struct spear_shirq { 43 void __iomem *base; 44 u32 status_reg; 45 u32 mask_reg; 46 u32 mask; 47 u32 virq_base; 48 u32 nr_irqs; 49 u32 offset; 50 struct irq_chip *irq_chip; 51 }; 52 53 /* spear300 shared irq registers offsets and masks */ 54 #define SPEAR300_INT_ENB_MASK_REG 0x54 55 #define SPEAR300_INT_STS_MASK_REG 0x58 56 57 static DEFINE_RAW_SPINLOCK(shirq_lock); 58 59 static void shirq_irq_mask(struct irq_data *d) 60 { 61 struct spear_shirq *shirq = irq_data_get_irq_chip_data(d); 62 u32 val, shift = d->irq - shirq->virq_base + shirq->offset; 63 u32 __iomem *reg = shirq->base + shirq->mask_reg; 64 65 raw_spin_lock(&shirq_lock); 66 val = readl(reg) & ~(0x1 << shift); 67 writel(val, reg); 68 raw_spin_unlock(&shirq_lock); 69 } 70 71 static void shirq_irq_unmask(struct irq_data *d) 72 { 73 struct spear_shirq *shirq = irq_data_get_irq_chip_data(d); 74 u32 val, shift = d->irq - shirq->virq_base + shirq->offset; 75 u32 __iomem *reg = shirq->base + shirq->mask_reg; 76 77 raw_spin_lock(&shirq_lock); 78 val = readl(reg) | (0x1 << shift); 79 writel(val, reg); 80 raw_spin_unlock(&shirq_lock); 81 } 82 83 static struct irq_chip shirq_chip = { 84 .name = "spear-shirq", 85 .irq_mask = shirq_irq_mask, 86 .irq_unmask = shirq_irq_unmask, 87 }; 88 89 static struct spear_shirq spear300_shirq_ras1 = { 90 .offset = 0, 91 .nr_irqs = 9, 92 .mask = ((0x1 << 9) - 1) << 0, 93 .irq_chip = &shirq_chip, 94 .status_reg = SPEAR300_INT_STS_MASK_REG, 95 .mask_reg = SPEAR300_INT_ENB_MASK_REG, 96 }; 97 98 static struct spear_shirq *spear300_shirq_blocks[] = { 99 &spear300_shirq_ras1, 100 }; 101 102 /* spear310 shared irq registers offsets and masks */ 103 #define SPEAR310_INT_STS_MASK_REG 0x04 104 105 static struct spear_shirq spear310_shirq_ras1 = { 106 .offset = 0, 107 .nr_irqs = 8, 108 .mask = ((0x1 << 8) - 1) << 0, 109 .irq_chip = &dummy_irq_chip, 110 .status_reg = SPEAR310_INT_STS_MASK_REG, 111 }; 112 113 static struct spear_shirq spear310_shirq_ras2 = { 114 .offset = 8, 115 .nr_irqs = 5, 116 .mask = ((0x1 << 5) - 1) << 8, 117 .irq_chip = &dummy_irq_chip, 118 .status_reg = SPEAR310_INT_STS_MASK_REG, 119 }; 120 121 static struct spear_shirq spear310_shirq_ras3 = { 122 .offset = 13, 123 .nr_irqs = 1, 124 .mask = ((0x1 << 1) - 1) << 13, 125 .irq_chip = &dummy_irq_chip, 126 .status_reg = SPEAR310_INT_STS_MASK_REG, 127 }; 128 129 static struct spear_shirq spear310_shirq_intrcomm_ras = { 130 .offset = 14, 131 .nr_irqs = 3, 132 .mask = ((0x1 << 3) - 1) << 14, 133 .irq_chip = &dummy_irq_chip, 134 .status_reg = SPEAR310_INT_STS_MASK_REG, 135 }; 136 137 static struct spear_shirq *spear310_shirq_blocks[] = { 138 &spear310_shirq_ras1, 139 &spear310_shirq_ras2, 140 &spear310_shirq_ras3, 141 &spear310_shirq_intrcomm_ras, 142 }; 143 144 /* spear320 shared irq registers offsets and masks */ 145 #define SPEAR320_INT_STS_MASK_REG 0x04 146 #define SPEAR320_INT_CLR_MASK_REG 0x04 147 #define SPEAR320_INT_ENB_MASK_REG 0x08 148 149 static struct spear_shirq spear320_shirq_ras3 = { 150 .offset = 0, 151 .nr_irqs = 7, 152 .mask = ((0x1 << 7) - 1) << 0, 153 }; 154 155 static struct spear_shirq spear320_shirq_ras1 = { 156 .offset = 7, 157 .nr_irqs = 3, 158 .mask = ((0x1 << 3) - 1) << 7, 159 .irq_chip = &dummy_irq_chip, 160 .status_reg = SPEAR320_INT_STS_MASK_REG, 161 }; 162 163 static struct spear_shirq spear320_shirq_ras2 = { 164 .offset = 10, 165 .nr_irqs = 1, 166 .mask = ((0x1 << 1) - 1) << 10, 167 .irq_chip = &dummy_irq_chip, 168 .status_reg = SPEAR320_INT_STS_MASK_REG, 169 }; 170 171 static struct spear_shirq spear320_shirq_intrcomm_ras = { 172 .offset = 11, 173 .nr_irqs = 11, 174 .mask = ((0x1 << 11) - 1) << 11, 175 .irq_chip = &dummy_irq_chip, 176 .status_reg = SPEAR320_INT_STS_MASK_REG, 177 }; 178 179 static struct spear_shirq *spear320_shirq_blocks[] = { 180 &spear320_shirq_ras3, 181 &spear320_shirq_ras1, 182 &spear320_shirq_ras2, 183 &spear320_shirq_intrcomm_ras, 184 }; 185 186 static void shirq_handler(unsigned irq, struct irq_desc *desc) 187 { 188 struct spear_shirq *shirq = irq_get_handler_data(irq); 189 u32 pend; 190 191 pend = readl(shirq->base + shirq->status_reg) & shirq->mask; 192 pend >>= shirq->offset; 193 194 while (pend) { 195 int irq = __ffs(pend); 196 197 pend &= ~(0x1 << irq); 198 generic_handle_irq(shirq->virq_base + irq); 199 } 200 } 201 202 static void __init spear_shirq_register(struct spear_shirq *shirq, 203 int parent_irq) 204 { 205 int i; 206 207 if (!shirq->irq_chip) 208 return; 209 210 irq_set_chained_handler(parent_irq, shirq_handler); 211 irq_set_handler_data(parent_irq, shirq); 212 213 for (i = 0; i < shirq->nr_irqs; i++) { 214 irq_set_chip_and_handler(shirq->virq_base + i, 215 shirq->irq_chip, handle_simple_irq); 216 set_irq_flags(shirq->virq_base + i, IRQF_VALID); 217 irq_set_chip_data(shirq->virq_base + i, shirq); 218 } 219 } 220 221 static int __init shirq_init(struct spear_shirq **shirq_blocks, int block_nr, 222 struct device_node *np) 223 { 224 int i, parent_irq, virq_base, hwirq = 0, nr_irqs = 0; 225 struct irq_domain *shirq_domain; 226 void __iomem *base; 227 228 base = of_iomap(np, 0); 229 if (!base) { 230 pr_err("%s: failed to map shirq registers\n", __func__); 231 return -ENXIO; 232 } 233 234 for (i = 0; i < block_nr; i++) 235 nr_irqs += shirq_blocks[i]->nr_irqs; 236 237 virq_base = irq_alloc_descs(-1, 0, nr_irqs, 0); 238 if (IS_ERR_VALUE(virq_base)) { 239 pr_err("%s: irq desc alloc failed\n", __func__); 240 goto err_unmap; 241 } 242 243 shirq_domain = irq_domain_add_legacy(np, nr_irqs, virq_base, 0, 244 &irq_domain_simple_ops, NULL); 245 if (WARN_ON(!shirq_domain)) { 246 pr_warn("%s: irq domain init failed\n", __func__); 247 goto err_free_desc; 248 } 249 250 for (i = 0; i < block_nr; i++) { 251 shirq_blocks[i]->base = base; 252 shirq_blocks[i]->virq_base = irq_find_mapping(shirq_domain, 253 hwirq); 254 255 parent_irq = irq_of_parse_and_map(np, i); 256 spear_shirq_register(shirq_blocks[i], parent_irq); 257 hwirq += shirq_blocks[i]->nr_irqs; 258 } 259 260 return 0; 261 262 err_free_desc: 263 irq_free_descs(virq_base, nr_irqs); 264 err_unmap: 265 iounmap(base); 266 return -ENXIO; 267 } 268 269 static int __init spear300_shirq_of_init(struct device_node *np, 270 struct device_node *parent) 271 { 272 return shirq_init(spear300_shirq_blocks, 273 ARRAY_SIZE(spear300_shirq_blocks), np); 274 } 275 IRQCHIP_DECLARE(spear300_shirq, "st,spear300-shirq", spear300_shirq_of_init); 276 277 static int __init spear310_shirq_of_init(struct device_node *np, 278 struct device_node *parent) 279 { 280 return shirq_init(spear310_shirq_blocks, 281 ARRAY_SIZE(spear310_shirq_blocks), np); 282 } 283 IRQCHIP_DECLARE(spear310_shirq, "st,spear310-shirq", spear310_shirq_of_init); 284 285 static int __init spear320_shirq_of_init(struct device_node *np, 286 struct device_node *parent) 287 { 288 return shirq_init(spear320_shirq_blocks, 289 ARRAY_SIZE(spear320_shirq_blocks), np); 290 } 291 IRQCHIP_DECLARE(spear320_shirq, "st,spear320-shirq", spear320_shirq_of_init); 292