xref: /linux/drivers/irqchip/qcom-pdc.c (revision 9d4f24bfe043274d9274bcfe223b901bd8fb7182)
1 // SPDX-License-Identifier: GPL-2.0
2 /*
3  * Copyright (c) 2017-2019, The Linux Foundation. All rights reserved.
4  */
5 
6 #include <linux/err.h>
7 #include <linux/init.h>
8 #include <linux/interrupt.h>
9 #include <linux/irq.h>
10 #include <linux/irqchip.h>
11 #include <linux/irqdomain.h>
12 #include <linux/io.h>
13 #include <linux/kernel.h>
14 #include <linux/module.h>
15 #include <linux/of.h>
16 #include <linux/of_address.h>
17 #include <linux/of_device.h>
18 #include <linux/of_irq.h>
19 #include <linux/soc/qcom/irq.h>
20 #include <linux/spinlock.h>
21 #include <linux/slab.h>
22 #include <linux/types.h>
23 
24 #define PDC_MAX_IRQS		168
25 #define PDC_MAX_GPIO_IRQS	256
26 
27 #define CLEAR_INTR(reg, intr)	(reg & ~(1 << intr))
28 #define ENABLE_INTR(reg, intr)	(reg | (1 << intr))
29 
30 #define IRQ_ENABLE_BANK		0x10
31 #define IRQ_i_CFG		0x110
32 
33 #define PDC_NO_PARENT_IRQ	~0UL
34 
35 struct pdc_pin_region {
36 	u32 pin_base;
37 	u32 parent_base;
38 	u32 cnt;
39 };
40 
41 static DEFINE_RAW_SPINLOCK(pdc_lock);
42 static void __iomem *pdc_base;
43 static struct pdc_pin_region *pdc_region;
44 static int pdc_region_cnt;
45 
46 static void pdc_reg_write(int reg, u32 i, u32 val)
47 {
48 	writel_relaxed(val, pdc_base + reg + i * sizeof(u32));
49 }
50 
51 static u32 pdc_reg_read(int reg, u32 i)
52 {
53 	return readl_relaxed(pdc_base + reg + i * sizeof(u32));
54 }
55 
56 static void pdc_enable_intr(struct irq_data *d, bool on)
57 {
58 	int pin_out = d->hwirq;
59 	u32 index, mask;
60 	u32 enable;
61 
62 	index = pin_out / 32;
63 	mask = pin_out % 32;
64 
65 	raw_spin_lock(&pdc_lock);
66 	enable = pdc_reg_read(IRQ_ENABLE_BANK, index);
67 	enable = on ? ENABLE_INTR(enable, mask) : CLEAR_INTR(enable, mask);
68 	pdc_reg_write(IRQ_ENABLE_BANK, index, enable);
69 	raw_spin_unlock(&pdc_lock);
70 }
71 
72 static void qcom_pdc_gic_disable(struct irq_data *d)
73 {
74 	pdc_enable_intr(d, false);
75 	irq_chip_disable_parent(d);
76 }
77 
78 static void qcom_pdc_gic_enable(struct irq_data *d)
79 {
80 	pdc_enable_intr(d, true);
81 	irq_chip_enable_parent(d);
82 }
83 
84 /*
85  * GIC does not handle falling edge or active low. To allow falling edge and
86  * active low interrupts to be handled at GIC, PDC has an inverter that inverts
87  * falling edge into a rising edge and active low into an active high.
88  * For the inverter to work, the polarity bit in the IRQ_CONFIG register has to
89  * set as per the table below.
90  * Level sensitive active low    LOW
91  * Rising edge sensitive         NOT USED
92  * Falling edge sensitive        LOW
93  * Dual Edge sensitive           NOT USED
94  * Level sensitive active High   HIGH
95  * Falling Edge sensitive        NOT USED
96  * Rising edge sensitive         HIGH
97  * Dual Edge sensitive           HIGH
98  */
99 enum pdc_irq_config_bits {
100 	PDC_LEVEL_LOW		= 0b000,
101 	PDC_EDGE_FALLING	= 0b010,
102 	PDC_LEVEL_HIGH		= 0b100,
103 	PDC_EDGE_RISING		= 0b110,
104 	PDC_EDGE_DUAL		= 0b111,
105 };
106 
107 /**
108  * qcom_pdc_gic_set_type: Configure PDC for the interrupt
109  *
110  * @d: the interrupt data
111  * @type: the interrupt type
112  *
113  * If @type is edge triggered, forward that as Rising edge as PDC
114  * takes care of converting falling edge to rising edge signal
115  * If @type is level, then forward that as level high as PDC
116  * takes care of converting falling edge to rising edge signal
117  */
118 static int qcom_pdc_gic_set_type(struct irq_data *d, unsigned int type)
119 {
120 	enum pdc_irq_config_bits pdc_type;
121 	enum pdc_irq_config_bits old_pdc_type;
122 	int ret;
123 
124 	switch (type) {
125 	case IRQ_TYPE_EDGE_RISING:
126 		pdc_type = PDC_EDGE_RISING;
127 		break;
128 	case IRQ_TYPE_EDGE_FALLING:
129 		pdc_type = PDC_EDGE_FALLING;
130 		type = IRQ_TYPE_EDGE_RISING;
131 		break;
132 	case IRQ_TYPE_EDGE_BOTH:
133 		pdc_type = PDC_EDGE_DUAL;
134 		type = IRQ_TYPE_EDGE_RISING;
135 		break;
136 	case IRQ_TYPE_LEVEL_HIGH:
137 		pdc_type = PDC_LEVEL_HIGH;
138 		break;
139 	case IRQ_TYPE_LEVEL_LOW:
140 		pdc_type = PDC_LEVEL_LOW;
141 		type = IRQ_TYPE_LEVEL_HIGH;
142 		break;
143 	default:
144 		WARN_ON(1);
145 		return -EINVAL;
146 	}
147 
148 	old_pdc_type = pdc_reg_read(IRQ_i_CFG, d->hwirq);
149 	pdc_reg_write(IRQ_i_CFG, d->hwirq, pdc_type);
150 
151 	ret = irq_chip_set_type_parent(d, type);
152 	if (ret)
153 		return ret;
154 
155 	/*
156 	 * When we change types the PDC can give a phantom interrupt.
157 	 * Clear it.  Specifically the phantom shows up when reconfiguring
158 	 * polarity of interrupt without changing the state of the signal
159 	 * but let's be consistent and clear it always.
160 	 *
161 	 * Doing this works because we have IRQCHIP_SET_TYPE_MASKED so the
162 	 * interrupt will be cleared before the rest of the system sees it.
163 	 */
164 	if (old_pdc_type != pdc_type)
165 		irq_chip_set_parent_state(d, IRQCHIP_STATE_PENDING, false);
166 
167 	return 0;
168 }
169 
170 static struct irq_chip qcom_pdc_gic_chip = {
171 	.name			= "PDC",
172 	.irq_eoi		= irq_chip_eoi_parent,
173 	.irq_mask		= irq_chip_mask_parent,
174 	.irq_unmask		= irq_chip_unmask_parent,
175 	.irq_disable		= qcom_pdc_gic_disable,
176 	.irq_enable		= qcom_pdc_gic_enable,
177 	.irq_get_irqchip_state	= irq_chip_get_parent_state,
178 	.irq_set_irqchip_state	= irq_chip_set_parent_state,
179 	.irq_retrigger		= irq_chip_retrigger_hierarchy,
180 	.irq_set_type		= qcom_pdc_gic_set_type,
181 	.flags			= IRQCHIP_MASK_ON_SUSPEND |
182 				  IRQCHIP_SET_TYPE_MASKED |
183 				  IRQCHIP_SKIP_SET_WAKE |
184 				  IRQCHIP_ENABLE_WAKEUP_ON_SUSPEND,
185 	.irq_set_vcpu_affinity	= irq_chip_set_vcpu_affinity_parent,
186 	.irq_set_affinity	= irq_chip_set_affinity_parent,
187 };
188 
189 static irq_hw_number_t get_parent_hwirq(int pin)
190 {
191 	int i;
192 	struct pdc_pin_region *region;
193 
194 	for (i = 0; i < pdc_region_cnt; i++) {
195 		region = &pdc_region[i];
196 		if (pin >= region->pin_base &&
197 		    pin < region->pin_base + region->cnt)
198 			return (region->parent_base + pin - region->pin_base);
199 	}
200 
201 	return PDC_NO_PARENT_IRQ;
202 }
203 
204 static int qcom_pdc_translate(struct irq_domain *d, struct irq_fwspec *fwspec,
205 			      unsigned long *hwirq, unsigned int *type)
206 {
207 	if (is_of_node(fwspec->fwnode)) {
208 		if (fwspec->param_count != 2)
209 			return -EINVAL;
210 
211 		*hwirq = fwspec->param[0];
212 		*type = fwspec->param[1] & IRQ_TYPE_SENSE_MASK;
213 		return 0;
214 	}
215 
216 	return -EINVAL;
217 }
218 
219 static int qcom_pdc_alloc(struct irq_domain *domain, unsigned int virq,
220 			  unsigned int nr_irqs, void *data)
221 {
222 	struct irq_fwspec *fwspec = data;
223 	struct irq_fwspec parent_fwspec;
224 	irq_hw_number_t hwirq, parent_hwirq;
225 	unsigned int type;
226 	int ret;
227 
228 	ret = qcom_pdc_translate(domain, fwspec, &hwirq, &type);
229 	if (ret)
230 		return ret;
231 
232 	ret  = irq_domain_set_hwirq_and_chip(domain, virq, hwirq,
233 					     &qcom_pdc_gic_chip, NULL);
234 	if (ret)
235 		return ret;
236 
237 	parent_hwirq = get_parent_hwirq(hwirq);
238 	if (parent_hwirq == PDC_NO_PARENT_IRQ)
239 		return irq_domain_disconnect_hierarchy(domain->parent, virq);
240 
241 	if (type & IRQ_TYPE_EDGE_BOTH)
242 		type = IRQ_TYPE_EDGE_RISING;
243 
244 	if (type & IRQ_TYPE_LEVEL_MASK)
245 		type = IRQ_TYPE_LEVEL_HIGH;
246 
247 	parent_fwspec.fwnode      = domain->parent->fwnode;
248 	parent_fwspec.param_count = 3;
249 	parent_fwspec.param[0]    = 0;
250 	parent_fwspec.param[1]    = parent_hwirq;
251 	parent_fwspec.param[2]    = type;
252 
253 	return irq_domain_alloc_irqs_parent(domain, virq, nr_irqs,
254 					    &parent_fwspec);
255 }
256 
257 static const struct irq_domain_ops qcom_pdc_ops = {
258 	.translate	= qcom_pdc_translate,
259 	.alloc		= qcom_pdc_alloc,
260 	.free		= irq_domain_free_irqs_common,
261 };
262 
263 static int qcom_pdc_gpio_alloc(struct irq_domain *domain, unsigned int virq,
264 			       unsigned int nr_irqs, void *data)
265 {
266 	struct irq_fwspec *fwspec = data;
267 	struct irq_fwspec parent_fwspec;
268 	irq_hw_number_t hwirq, parent_hwirq;
269 	unsigned int type;
270 	int ret;
271 
272 	ret = qcom_pdc_translate(domain, fwspec, &hwirq, &type);
273 	if (ret)
274 		return ret;
275 
276 	if (hwirq == GPIO_NO_WAKE_IRQ)
277 		return irq_domain_disconnect_hierarchy(domain, virq);
278 
279 	ret = irq_domain_set_hwirq_and_chip(domain, virq, hwirq,
280 					    &qcom_pdc_gic_chip, NULL);
281 	if (ret)
282 		return ret;
283 
284 	parent_hwirq = get_parent_hwirq(hwirq);
285 	if (parent_hwirq == PDC_NO_PARENT_IRQ)
286 		return irq_domain_disconnect_hierarchy(domain->parent, virq);
287 
288 	if (type & IRQ_TYPE_EDGE_BOTH)
289 		type = IRQ_TYPE_EDGE_RISING;
290 
291 	if (type & IRQ_TYPE_LEVEL_MASK)
292 		type = IRQ_TYPE_LEVEL_HIGH;
293 
294 	parent_fwspec.fwnode      = domain->parent->fwnode;
295 	parent_fwspec.param_count = 3;
296 	parent_fwspec.param[0]    = 0;
297 	parent_fwspec.param[1]    = parent_hwirq;
298 	parent_fwspec.param[2]    = type;
299 
300 	return irq_domain_alloc_irqs_parent(domain, virq, nr_irqs,
301 					    &parent_fwspec);
302 }
303 
304 static int qcom_pdc_gpio_domain_select(struct irq_domain *d,
305 				       struct irq_fwspec *fwspec,
306 				       enum irq_domain_bus_token bus_token)
307 {
308 	return bus_token == DOMAIN_BUS_WAKEUP;
309 }
310 
311 static const struct irq_domain_ops qcom_pdc_gpio_ops = {
312 	.select		= qcom_pdc_gpio_domain_select,
313 	.alloc		= qcom_pdc_gpio_alloc,
314 	.free		= irq_domain_free_irqs_common,
315 };
316 
317 static int pdc_setup_pin_mapping(struct device_node *np)
318 {
319 	int ret, n, i;
320 	u32 irq_index, reg_index, val;
321 
322 	n = of_property_count_elems_of_size(np, "qcom,pdc-ranges", sizeof(u32));
323 	if (n <= 0 || n % 3)
324 		return -EINVAL;
325 
326 	pdc_region_cnt = n / 3;
327 	pdc_region = kcalloc(pdc_region_cnt, sizeof(*pdc_region), GFP_KERNEL);
328 	if (!pdc_region) {
329 		pdc_region_cnt = 0;
330 		return -ENOMEM;
331 	}
332 
333 	for (n = 0; n < pdc_region_cnt; n++) {
334 		ret = of_property_read_u32_index(np, "qcom,pdc-ranges",
335 						 n * 3 + 0,
336 						 &pdc_region[n].pin_base);
337 		if (ret)
338 			return ret;
339 		ret = of_property_read_u32_index(np, "qcom,pdc-ranges",
340 						 n * 3 + 1,
341 						 &pdc_region[n].parent_base);
342 		if (ret)
343 			return ret;
344 		ret = of_property_read_u32_index(np, "qcom,pdc-ranges",
345 						 n * 3 + 2,
346 						 &pdc_region[n].cnt);
347 		if (ret)
348 			return ret;
349 
350 		for (i = 0; i < pdc_region[n].cnt; i++) {
351 			reg_index = (i + pdc_region[n].pin_base) >> 5;
352 			irq_index = (i + pdc_region[n].pin_base) & 0x1f;
353 			val = pdc_reg_read(IRQ_ENABLE_BANK, reg_index);
354 			val &= ~BIT(irq_index);
355 			pdc_reg_write(IRQ_ENABLE_BANK, reg_index, val);
356 		}
357 	}
358 
359 	return 0;
360 }
361 
362 static int qcom_pdc_init(struct device_node *node, struct device_node *parent)
363 {
364 	struct irq_domain *parent_domain, *pdc_domain, *pdc_gpio_domain;
365 	int ret;
366 
367 	pdc_base = of_iomap(node, 0);
368 	if (!pdc_base) {
369 		pr_err("%pOF: unable to map PDC registers\n", node);
370 		return -ENXIO;
371 	}
372 
373 	parent_domain = irq_find_host(parent);
374 	if (!parent_domain) {
375 		pr_err("%pOF: unable to find PDC's parent domain\n", node);
376 		ret = -ENXIO;
377 		goto fail;
378 	}
379 
380 	ret = pdc_setup_pin_mapping(node);
381 	if (ret) {
382 		pr_err("%pOF: failed to init PDC pin-hwirq mapping\n", node);
383 		goto fail;
384 	}
385 
386 	pdc_domain = irq_domain_create_hierarchy(parent_domain, 0, PDC_MAX_IRQS,
387 						 of_fwnode_handle(node),
388 						 &qcom_pdc_ops, NULL);
389 	if (!pdc_domain) {
390 		pr_err("%pOF: GIC domain add failed\n", node);
391 		ret = -ENOMEM;
392 		goto fail;
393 	}
394 
395 	pdc_gpio_domain = irq_domain_create_hierarchy(parent_domain,
396 					IRQ_DOMAIN_FLAG_QCOM_PDC_WAKEUP,
397 					PDC_MAX_GPIO_IRQS,
398 					of_fwnode_handle(node),
399 					&qcom_pdc_gpio_ops, NULL);
400 	if (!pdc_gpio_domain) {
401 		pr_err("%pOF: PDC domain add failed for GPIO domain\n", node);
402 		ret = -ENOMEM;
403 		goto remove;
404 	}
405 
406 	irq_domain_update_bus_token(pdc_gpio_domain, DOMAIN_BUS_WAKEUP);
407 
408 	return 0;
409 
410 remove:
411 	irq_domain_remove(pdc_domain);
412 fail:
413 	kfree(pdc_region);
414 	iounmap(pdc_base);
415 	return ret;
416 }
417 
418 IRQCHIP_PLATFORM_DRIVER_BEGIN(qcom_pdc)
419 IRQCHIP_MATCH("qcom,pdc", qcom_pdc_init)
420 IRQCHIP_PLATFORM_DRIVER_END(qcom_pdc)
421 MODULE_DESCRIPTION("Qualcomm Technologies, Inc. Power Domain Controller");
422 MODULE_LICENSE("GPL v2");
423