1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (c) 2017-2019, The Linux Foundation. All rights reserved. 4 */ 5 6 #include <linux/err.h> 7 #include <linux/init.h> 8 #include <linux/irq.h> 9 #include <linux/irqchip.h> 10 #include <linux/irqdomain.h> 11 #include <linux/io.h> 12 #include <linux/kernel.h> 13 #include <linux/of.h> 14 #include <linux/of_address.h> 15 #include <linux/of_device.h> 16 #include <linux/soc/qcom/irq.h> 17 #include <linux/spinlock.h> 18 #include <linux/slab.h> 19 #include <linux/types.h> 20 21 #define PDC_MAX_IRQS 168 22 #define PDC_MAX_GPIO_IRQS 256 23 24 #define CLEAR_INTR(reg, intr) (reg & ~(1 << intr)) 25 #define ENABLE_INTR(reg, intr) (reg | (1 << intr)) 26 27 #define IRQ_ENABLE_BANK 0x10 28 #define IRQ_i_CFG 0x110 29 30 #define PDC_NO_PARENT_IRQ ~0UL 31 32 struct pdc_pin_region { 33 u32 pin_base; 34 u32 parent_base; 35 u32 cnt; 36 }; 37 38 static DEFINE_RAW_SPINLOCK(pdc_lock); 39 static void __iomem *pdc_base; 40 static struct pdc_pin_region *pdc_region; 41 static int pdc_region_cnt; 42 43 static void pdc_reg_write(int reg, u32 i, u32 val) 44 { 45 writel_relaxed(val, pdc_base + reg + i * sizeof(u32)); 46 } 47 48 static u32 pdc_reg_read(int reg, u32 i) 49 { 50 return readl_relaxed(pdc_base + reg + i * sizeof(u32)); 51 } 52 53 static void pdc_enable_intr(struct irq_data *d, bool on) 54 { 55 int pin_out = d->hwirq; 56 u32 index, mask; 57 u32 enable; 58 59 index = pin_out / 32; 60 mask = pin_out % 32; 61 62 raw_spin_lock(&pdc_lock); 63 enable = pdc_reg_read(IRQ_ENABLE_BANK, index); 64 enable = on ? ENABLE_INTR(enable, mask) : CLEAR_INTR(enable, mask); 65 pdc_reg_write(IRQ_ENABLE_BANK, index, enable); 66 raw_spin_unlock(&pdc_lock); 67 } 68 69 static void qcom_pdc_gic_disable(struct irq_data *d) 70 { 71 if (d->hwirq == GPIO_NO_WAKE_IRQ) 72 return; 73 74 pdc_enable_intr(d, false); 75 irq_chip_disable_parent(d); 76 } 77 78 static void qcom_pdc_gic_enable(struct irq_data *d) 79 { 80 if (d->hwirq == GPIO_NO_WAKE_IRQ) 81 return; 82 83 pdc_enable_intr(d, true); 84 irq_chip_enable_parent(d); 85 } 86 87 static void qcom_pdc_gic_mask(struct irq_data *d) 88 { 89 if (d->hwirq == GPIO_NO_WAKE_IRQ) 90 return; 91 92 irq_chip_mask_parent(d); 93 } 94 95 static void qcom_pdc_gic_unmask(struct irq_data *d) 96 { 97 if (d->hwirq == GPIO_NO_WAKE_IRQ) 98 return; 99 100 irq_chip_unmask_parent(d); 101 } 102 103 /* 104 * GIC does not handle falling edge or active low. To allow falling edge and 105 * active low interrupts to be handled at GIC, PDC has an inverter that inverts 106 * falling edge into a rising edge and active low into an active high. 107 * For the inverter to work, the polarity bit in the IRQ_CONFIG register has to 108 * set as per the table below. 109 * Level sensitive active low LOW 110 * Rising edge sensitive NOT USED 111 * Falling edge sensitive LOW 112 * Dual Edge sensitive NOT USED 113 * Level sensitive active High HIGH 114 * Falling Edge sensitive NOT USED 115 * Rising edge sensitive HIGH 116 * Dual Edge sensitive HIGH 117 */ 118 enum pdc_irq_config_bits { 119 PDC_LEVEL_LOW = 0b000, 120 PDC_EDGE_FALLING = 0b010, 121 PDC_LEVEL_HIGH = 0b100, 122 PDC_EDGE_RISING = 0b110, 123 PDC_EDGE_DUAL = 0b111, 124 }; 125 126 /** 127 * qcom_pdc_gic_set_type: Configure PDC for the interrupt 128 * 129 * @d: the interrupt data 130 * @type: the interrupt type 131 * 132 * If @type is edge triggered, forward that as Rising edge as PDC 133 * takes care of converting falling edge to rising edge signal 134 * If @type is level, then forward that as level high as PDC 135 * takes care of converting falling edge to rising edge signal 136 */ 137 static int qcom_pdc_gic_set_type(struct irq_data *d, unsigned int type) 138 { 139 int pin_out = d->hwirq; 140 enum pdc_irq_config_bits pdc_type; 141 142 if (pin_out == GPIO_NO_WAKE_IRQ) 143 return 0; 144 145 switch (type) { 146 case IRQ_TYPE_EDGE_RISING: 147 pdc_type = PDC_EDGE_RISING; 148 break; 149 case IRQ_TYPE_EDGE_FALLING: 150 pdc_type = PDC_EDGE_FALLING; 151 type = IRQ_TYPE_EDGE_RISING; 152 break; 153 case IRQ_TYPE_EDGE_BOTH: 154 pdc_type = PDC_EDGE_DUAL; 155 type = IRQ_TYPE_EDGE_RISING; 156 break; 157 case IRQ_TYPE_LEVEL_HIGH: 158 pdc_type = PDC_LEVEL_HIGH; 159 break; 160 case IRQ_TYPE_LEVEL_LOW: 161 pdc_type = PDC_LEVEL_LOW; 162 type = IRQ_TYPE_LEVEL_HIGH; 163 break; 164 default: 165 WARN_ON(1); 166 return -EINVAL; 167 } 168 169 pdc_reg_write(IRQ_i_CFG, pin_out, pdc_type); 170 171 return irq_chip_set_type_parent(d, type); 172 } 173 174 static struct irq_chip qcom_pdc_gic_chip = { 175 .name = "PDC", 176 .irq_eoi = irq_chip_eoi_parent, 177 .irq_mask = qcom_pdc_gic_mask, 178 .irq_unmask = qcom_pdc_gic_unmask, 179 .irq_disable = qcom_pdc_gic_disable, 180 .irq_enable = qcom_pdc_gic_enable, 181 .irq_retrigger = irq_chip_retrigger_hierarchy, 182 .irq_set_type = qcom_pdc_gic_set_type, 183 .flags = IRQCHIP_MASK_ON_SUSPEND | 184 IRQCHIP_SET_TYPE_MASKED | 185 IRQCHIP_SKIP_SET_WAKE, 186 .irq_set_vcpu_affinity = irq_chip_set_vcpu_affinity_parent, 187 .irq_set_affinity = irq_chip_set_affinity_parent, 188 }; 189 190 static irq_hw_number_t get_parent_hwirq(int pin) 191 { 192 int i; 193 struct pdc_pin_region *region; 194 195 for (i = 0; i < pdc_region_cnt; i++) { 196 region = &pdc_region[i]; 197 if (pin >= region->pin_base && 198 pin < region->pin_base + region->cnt) 199 return (region->parent_base + pin - region->pin_base); 200 } 201 202 return PDC_NO_PARENT_IRQ; 203 } 204 205 static int qcom_pdc_translate(struct irq_domain *d, struct irq_fwspec *fwspec, 206 unsigned long *hwirq, unsigned int *type) 207 { 208 if (is_of_node(fwspec->fwnode)) { 209 if (fwspec->param_count != 2) 210 return -EINVAL; 211 212 *hwirq = fwspec->param[0]; 213 *type = fwspec->param[1] & IRQ_TYPE_SENSE_MASK; 214 return 0; 215 } 216 217 return -EINVAL; 218 } 219 220 static int qcom_pdc_alloc(struct irq_domain *domain, unsigned int virq, 221 unsigned int nr_irqs, void *data) 222 { 223 struct irq_fwspec *fwspec = data; 224 struct irq_fwspec parent_fwspec; 225 irq_hw_number_t hwirq, parent_hwirq; 226 unsigned int type; 227 int ret; 228 229 ret = qcom_pdc_translate(domain, fwspec, &hwirq, &type); 230 if (ret) 231 return ret; 232 233 ret = irq_domain_set_hwirq_and_chip(domain, virq, hwirq, 234 &qcom_pdc_gic_chip, NULL); 235 if (ret) 236 return ret; 237 238 parent_hwirq = get_parent_hwirq(hwirq); 239 if (parent_hwirq == PDC_NO_PARENT_IRQ) 240 return 0; 241 242 if (type & IRQ_TYPE_EDGE_BOTH) 243 type = IRQ_TYPE_EDGE_RISING; 244 245 if (type & IRQ_TYPE_LEVEL_MASK) 246 type = IRQ_TYPE_LEVEL_HIGH; 247 248 parent_fwspec.fwnode = domain->parent->fwnode; 249 parent_fwspec.param_count = 3; 250 parent_fwspec.param[0] = 0; 251 parent_fwspec.param[1] = parent_hwirq; 252 parent_fwspec.param[2] = type; 253 254 return irq_domain_alloc_irqs_parent(domain, virq, nr_irqs, 255 &parent_fwspec); 256 } 257 258 static const struct irq_domain_ops qcom_pdc_ops = { 259 .translate = qcom_pdc_translate, 260 .alloc = qcom_pdc_alloc, 261 .free = irq_domain_free_irqs_common, 262 }; 263 264 static int qcom_pdc_gpio_alloc(struct irq_domain *domain, unsigned int virq, 265 unsigned int nr_irqs, void *data) 266 { 267 struct irq_fwspec *fwspec = data; 268 struct irq_fwspec parent_fwspec; 269 irq_hw_number_t hwirq, parent_hwirq; 270 unsigned int type; 271 int ret; 272 273 ret = qcom_pdc_translate(domain, fwspec, &hwirq, &type); 274 if (ret) 275 return ret; 276 277 ret = irq_domain_set_hwirq_and_chip(domain, virq, hwirq, 278 &qcom_pdc_gic_chip, NULL); 279 if (ret) 280 return ret; 281 282 if (hwirq == GPIO_NO_WAKE_IRQ) 283 return 0; 284 285 parent_hwirq = get_parent_hwirq(hwirq); 286 if (parent_hwirq == PDC_NO_PARENT_IRQ) 287 return 0; 288 289 if (type & IRQ_TYPE_EDGE_BOTH) 290 type = IRQ_TYPE_EDGE_RISING; 291 292 if (type & IRQ_TYPE_LEVEL_MASK) 293 type = IRQ_TYPE_LEVEL_HIGH; 294 295 parent_fwspec.fwnode = domain->parent->fwnode; 296 parent_fwspec.param_count = 3; 297 parent_fwspec.param[0] = 0; 298 parent_fwspec.param[1] = parent_hwirq; 299 parent_fwspec.param[2] = type; 300 301 return irq_domain_alloc_irqs_parent(domain, virq, nr_irqs, 302 &parent_fwspec); 303 } 304 305 static int qcom_pdc_gpio_domain_select(struct irq_domain *d, 306 struct irq_fwspec *fwspec, 307 enum irq_domain_bus_token bus_token) 308 { 309 return bus_token == DOMAIN_BUS_WAKEUP; 310 } 311 312 static const struct irq_domain_ops qcom_pdc_gpio_ops = { 313 .select = qcom_pdc_gpio_domain_select, 314 .alloc = qcom_pdc_gpio_alloc, 315 .free = irq_domain_free_irqs_common, 316 }; 317 318 static int pdc_setup_pin_mapping(struct device_node *np) 319 { 320 int ret, n; 321 322 n = of_property_count_elems_of_size(np, "qcom,pdc-ranges", sizeof(u32)); 323 if (n <= 0 || n % 3) 324 return -EINVAL; 325 326 pdc_region_cnt = n / 3; 327 pdc_region = kcalloc(pdc_region_cnt, sizeof(*pdc_region), GFP_KERNEL); 328 if (!pdc_region) { 329 pdc_region_cnt = 0; 330 return -ENOMEM; 331 } 332 333 for (n = 0; n < pdc_region_cnt; n++) { 334 ret = of_property_read_u32_index(np, "qcom,pdc-ranges", 335 n * 3 + 0, 336 &pdc_region[n].pin_base); 337 if (ret) 338 return ret; 339 ret = of_property_read_u32_index(np, "qcom,pdc-ranges", 340 n * 3 + 1, 341 &pdc_region[n].parent_base); 342 if (ret) 343 return ret; 344 ret = of_property_read_u32_index(np, "qcom,pdc-ranges", 345 n * 3 + 2, 346 &pdc_region[n].cnt); 347 if (ret) 348 return ret; 349 } 350 351 return 0; 352 } 353 354 static int qcom_pdc_init(struct device_node *node, struct device_node *parent) 355 { 356 struct irq_domain *parent_domain, *pdc_domain, *pdc_gpio_domain; 357 int ret; 358 359 pdc_base = of_iomap(node, 0); 360 if (!pdc_base) { 361 pr_err("%pOF: unable to map PDC registers\n", node); 362 return -ENXIO; 363 } 364 365 parent_domain = irq_find_host(parent); 366 if (!parent_domain) { 367 pr_err("%pOF: unable to find PDC's parent domain\n", node); 368 ret = -ENXIO; 369 goto fail; 370 } 371 372 ret = pdc_setup_pin_mapping(node); 373 if (ret) { 374 pr_err("%pOF: failed to init PDC pin-hwirq mapping\n", node); 375 goto fail; 376 } 377 378 pdc_domain = irq_domain_create_hierarchy(parent_domain, 0, PDC_MAX_IRQS, 379 of_fwnode_handle(node), 380 &qcom_pdc_ops, NULL); 381 if (!pdc_domain) { 382 pr_err("%pOF: GIC domain add failed\n", node); 383 ret = -ENOMEM; 384 goto fail; 385 } 386 387 pdc_gpio_domain = irq_domain_create_hierarchy(parent_domain, 388 IRQ_DOMAIN_FLAG_QCOM_PDC_WAKEUP, 389 PDC_MAX_GPIO_IRQS, 390 of_fwnode_handle(node), 391 &qcom_pdc_gpio_ops, NULL); 392 if (!pdc_gpio_domain) { 393 pr_err("%pOF: PDC domain add failed for GPIO domain\n", node); 394 ret = -ENOMEM; 395 goto remove; 396 } 397 398 irq_domain_update_bus_token(pdc_gpio_domain, DOMAIN_BUS_WAKEUP); 399 400 return 0; 401 402 remove: 403 irq_domain_remove(pdc_domain); 404 fail: 405 kfree(pdc_region); 406 iounmap(pdc_base); 407 return ret; 408 } 409 410 IRQCHIP_DECLARE(qcom_pdc, "qcom,pdc", qcom_pdc_init); 411