1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (C) Maxime Coquelin 2015 4 * Copyright (C) STMicroelectronics 2017 5 * Author: Maxime Coquelin <mcoquelin.stm32@gmail.com> 6 */ 7 8 #include <linux/bitops.h> 9 #include <linux/delay.h> 10 #include <linux/hwspinlock.h> 11 #include <linux/interrupt.h> 12 #include <linux/io.h> 13 #include <linux/irq.h> 14 #include <linux/irqchip.h> 15 #include <linux/irqchip/chained_irq.h> 16 #include <linux/irqdomain.h> 17 #include <linux/module.h> 18 #include <linux/of_address.h> 19 #include <linux/of_irq.h> 20 #include <linux/of_platform.h> 21 #include <linux/syscore_ops.h> 22 23 #include <dt-bindings/interrupt-controller/arm-gic.h> 24 25 #define IRQS_PER_BANK 32 26 27 #define HWSPNLCK_TIMEOUT 1000 /* usec */ 28 29 struct stm32_exti_bank { 30 u32 imr_ofst; 31 u32 emr_ofst; 32 u32 rtsr_ofst; 33 u32 ftsr_ofst; 34 u32 swier_ofst; 35 u32 rpr_ofst; 36 u32 fpr_ofst; 37 }; 38 39 #define UNDEF_REG ~0 40 41 struct stm32_desc_irq { 42 u32 exti; 43 u32 irq_parent; 44 struct irq_chip *chip; 45 }; 46 47 struct stm32_exti_drv_data { 48 const struct stm32_exti_bank **exti_banks; 49 const struct stm32_desc_irq *desc_irqs; 50 u32 bank_nr; 51 u32 irq_nr; 52 }; 53 54 struct stm32_exti_chip_data { 55 struct stm32_exti_host_data *host_data; 56 const struct stm32_exti_bank *reg_bank; 57 struct raw_spinlock rlock; 58 u32 wake_active; 59 u32 mask_cache; 60 u32 rtsr_cache; 61 u32 ftsr_cache; 62 }; 63 64 struct stm32_exti_host_data { 65 void __iomem *base; 66 struct stm32_exti_chip_data *chips_data; 67 const struct stm32_exti_drv_data *drv_data; 68 struct hwspinlock *hwlock; 69 }; 70 71 static struct stm32_exti_host_data *stm32_host_data; 72 73 static const struct stm32_exti_bank stm32f4xx_exti_b1 = { 74 .imr_ofst = 0x00, 75 .emr_ofst = 0x04, 76 .rtsr_ofst = 0x08, 77 .ftsr_ofst = 0x0C, 78 .swier_ofst = 0x10, 79 .rpr_ofst = 0x14, 80 .fpr_ofst = UNDEF_REG, 81 }; 82 83 static const struct stm32_exti_bank *stm32f4xx_exti_banks[] = { 84 &stm32f4xx_exti_b1, 85 }; 86 87 static const struct stm32_exti_drv_data stm32f4xx_drv_data = { 88 .exti_banks = stm32f4xx_exti_banks, 89 .bank_nr = ARRAY_SIZE(stm32f4xx_exti_banks), 90 }; 91 92 static const struct stm32_exti_bank stm32h7xx_exti_b1 = { 93 .imr_ofst = 0x80, 94 .emr_ofst = 0x84, 95 .rtsr_ofst = 0x00, 96 .ftsr_ofst = 0x04, 97 .swier_ofst = 0x08, 98 .rpr_ofst = 0x88, 99 .fpr_ofst = UNDEF_REG, 100 }; 101 102 static const struct stm32_exti_bank stm32h7xx_exti_b2 = { 103 .imr_ofst = 0x90, 104 .emr_ofst = 0x94, 105 .rtsr_ofst = 0x20, 106 .ftsr_ofst = 0x24, 107 .swier_ofst = 0x28, 108 .rpr_ofst = 0x98, 109 .fpr_ofst = UNDEF_REG, 110 }; 111 112 static const struct stm32_exti_bank stm32h7xx_exti_b3 = { 113 .imr_ofst = 0xA0, 114 .emr_ofst = 0xA4, 115 .rtsr_ofst = 0x40, 116 .ftsr_ofst = 0x44, 117 .swier_ofst = 0x48, 118 .rpr_ofst = 0xA8, 119 .fpr_ofst = UNDEF_REG, 120 }; 121 122 static const struct stm32_exti_bank *stm32h7xx_exti_banks[] = { 123 &stm32h7xx_exti_b1, 124 &stm32h7xx_exti_b2, 125 &stm32h7xx_exti_b3, 126 }; 127 128 static const struct stm32_exti_drv_data stm32h7xx_drv_data = { 129 .exti_banks = stm32h7xx_exti_banks, 130 .bank_nr = ARRAY_SIZE(stm32h7xx_exti_banks), 131 }; 132 133 static const struct stm32_exti_bank stm32mp1_exti_b1 = { 134 .imr_ofst = 0x80, 135 .emr_ofst = 0x84, 136 .rtsr_ofst = 0x00, 137 .ftsr_ofst = 0x04, 138 .swier_ofst = 0x08, 139 .rpr_ofst = 0x0C, 140 .fpr_ofst = 0x10, 141 }; 142 143 static const struct stm32_exti_bank stm32mp1_exti_b2 = { 144 .imr_ofst = 0x90, 145 .emr_ofst = 0x94, 146 .rtsr_ofst = 0x20, 147 .ftsr_ofst = 0x24, 148 .swier_ofst = 0x28, 149 .rpr_ofst = 0x2C, 150 .fpr_ofst = 0x30, 151 }; 152 153 static const struct stm32_exti_bank stm32mp1_exti_b3 = { 154 .imr_ofst = 0xA0, 155 .emr_ofst = 0xA4, 156 .rtsr_ofst = 0x40, 157 .ftsr_ofst = 0x44, 158 .swier_ofst = 0x48, 159 .rpr_ofst = 0x4C, 160 .fpr_ofst = 0x50, 161 }; 162 163 static const struct stm32_exti_bank *stm32mp1_exti_banks[] = { 164 &stm32mp1_exti_b1, 165 &stm32mp1_exti_b2, 166 &stm32mp1_exti_b3, 167 }; 168 169 static struct irq_chip stm32_exti_h_chip; 170 static struct irq_chip stm32_exti_h_chip_direct; 171 172 static const struct stm32_desc_irq stm32mp1_desc_irq[] = { 173 { .exti = 0, .irq_parent = 6, .chip = &stm32_exti_h_chip }, 174 { .exti = 1, .irq_parent = 7, .chip = &stm32_exti_h_chip }, 175 { .exti = 2, .irq_parent = 8, .chip = &stm32_exti_h_chip }, 176 { .exti = 3, .irq_parent = 9, .chip = &stm32_exti_h_chip }, 177 { .exti = 4, .irq_parent = 10, .chip = &stm32_exti_h_chip }, 178 { .exti = 5, .irq_parent = 23, .chip = &stm32_exti_h_chip }, 179 { .exti = 6, .irq_parent = 64, .chip = &stm32_exti_h_chip }, 180 { .exti = 7, .irq_parent = 65, .chip = &stm32_exti_h_chip }, 181 { .exti = 8, .irq_parent = 66, .chip = &stm32_exti_h_chip }, 182 { .exti = 9, .irq_parent = 67, .chip = &stm32_exti_h_chip }, 183 { .exti = 10, .irq_parent = 40, .chip = &stm32_exti_h_chip }, 184 { .exti = 11, .irq_parent = 42, .chip = &stm32_exti_h_chip }, 185 { .exti = 12, .irq_parent = 76, .chip = &stm32_exti_h_chip }, 186 { .exti = 13, .irq_parent = 77, .chip = &stm32_exti_h_chip }, 187 { .exti = 14, .irq_parent = 121, .chip = &stm32_exti_h_chip }, 188 { .exti = 15, .irq_parent = 127, .chip = &stm32_exti_h_chip }, 189 { .exti = 16, .irq_parent = 1, .chip = &stm32_exti_h_chip }, 190 { .exti = 19, .irq_parent = 3, .chip = &stm32_exti_h_chip_direct }, 191 { .exti = 21, .irq_parent = 31, .chip = &stm32_exti_h_chip_direct }, 192 { .exti = 22, .irq_parent = 33, .chip = &stm32_exti_h_chip_direct }, 193 { .exti = 23, .irq_parent = 72, .chip = &stm32_exti_h_chip_direct }, 194 { .exti = 24, .irq_parent = 95, .chip = &stm32_exti_h_chip_direct }, 195 { .exti = 25, .irq_parent = 107, .chip = &stm32_exti_h_chip_direct }, 196 { .exti = 26, .irq_parent = 37, .chip = &stm32_exti_h_chip_direct }, 197 { .exti = 27, .irq_parent = 38, .chip = &stm32_exti_h_chip_direct }, 198 { .exti = 28, .irq_parent = 39, .chip = &stm32_exti_h_chip_direct }, 199 { .exti = 29, .irq_parent = 71, .chip = &stm32_exti_h_chip_direct }, 200 { .exti = 30, .irq_parent = 52, .chip = &stm32_exti_h_chip_direct }, 201 { .exti = 31, .irq_parent = 53, .chip = &stm32_exti_h_chip_direct }, 202 { .exti = 32, .irq_parent = 82, .chip = &stm32_exti_h_chip_direct }, 203 { .exti = 33, .irq_parent = 83, .chip = &stm32_exti_h_chip_direct }, 204 { .exti = 47, .irq_parent = 93, .chip = &stm32_exti_h_chip_direct }, 205 { .exti = 48, .irq_parent = 138, .chip = &stm32_exti_h_chip_direct }, 206 { .exti = 50, .irq_parent = 139, .chip = &stm32_exti_h_chip_direct }, 207 { .exti = 52, .irq_parent = 140, .chip = &stm32_exti_h_chip_direct }, 208 { .exti = 53, .irq_parent = 141, .chip = &stm32_exti_h_chip_direct }, 209 { .exti = 54, .irq_parent = 135, .chip = &stm32_exti_h_chip_direct }, 210 { .exti = 61, .irq_parent = 100, .chip = &stm32_exti_h_chip_direct }, 211 { .exti = 65, .irq_parent = 144, .chip = &stm32_exti_h_chip }, 212 { .exti = 68, .irq_parent = 143, .chip = &stm32_exti_h_chip }, 213 { .exti = 70, .irq_parent = 62, .chip = &stm32_exti_h_chip_direct }, 214 { .exti = 73, .irq_parent = 129, .chip = &stm32_exti_h_chip }, 215 }; 216 217 static const struct stm32_exti_drv_data stm32mp1_drv_data = { 218 .exti_banks = stm32mp1_exti_banks, 219 .bank_nr = ARRAY_SIZE(stm32mp1_exti_banks), 220 .desc_irqs = stm32mp1_desc_irq, 221 .irq_nr = ARRAY_SIZE(stm32mp1_desc_irq), 222 }; 223 224 static const struct 225 stm32_desc_irq *stm32_exti_get_desc(const struct stm32_exti_drv_data *drv_data, 226 irq_hw_number_t hwirq) 227 { 228 const struct stm32_desc_irq *desc = NULL; 229 int i; 230 231 if (!drv_data->desc_irqs) 232 return NULL; 233 234 for (i = 0; i < drv_data->irq_nr; i++) { 235 desc = &drv_data->desc_irqs[i]; 236 if (desc->exti == hwirq) 237 break; 238 } 239 240 return desc; 241 } 242 243 static unsigned long stm32_exti_pending(struct irq_chip_generic *gc) 244 { 245 struct stm32_exti_chip_data *chip_data = gc->private; 246 const struct stm32_exti_bank *stm32_bank = chip_data->reg_bank; 247 unsigned long pending; 248 249 pending = irq_reg_readl(gc, stm32_bank->rpr_ofst); 250 if (stm32_bank->fpr_ofst != UNDEF_REG) 251 pending |= irq_reg_readl(gc, stm32_bank->fpr_ofst); 252 253 return pending; 254 } 255 256 static void stm32_irq_handler(struct irq_desc *desc) 257 { 258 struct irq_domain *domain = irq_desc_get_handler_data(desc); 259 struct irq_chip *chip = irq_desc_get_chip(desc); 260 unsigned int virq, nbanks = domain->gc->num_chips; 261 struct irq_chip_generic *gc; 262 unsigned long pending; 263 int n, i, irq_base = 0; 264 265 chained_irq_enter(chip, desc); 266 267 for (i = 0; i < nbanks; i++, irq_base += IRQS_PER_BANK) { 268 gc = irq_get_domain_generic_chip(domain, irq_base); 269 270 while ((pending = stm32_exti_pending(gc))) { 271 for_each_set_bit(n, &pending, IRQS_PER_BANK) { 272 virq = irq_find_mapping(domain, irq_base + n); 273 generic_handle_irq(virq); 274 } 275 } 276 } 277 278 chained_irq_exit(chip, desc); 279 } 280 281 static int stm32_exti_set_type(struct irq_data *d, 282 unsigned int type, u32 *rtsr, u32 *ftsr) 283 { 284 u32 mask = BIT(d->hwirq % IRQS_PER_BANK); 285 286 switch (type) { 287 case IRQ_TYPE_EDGE_RISING: 288 *rtsr |= mask; 289 *ftsr &= ~mask; 290 break; 291 case IRQ_TYPE_EDGE_FALLING: 292 *rtsr &= ~mask; 293 *ftsr |= mask; 294 break; 295 case IRQ_TYPE_EDGE_BOTH: 296 *rtsr |= mask; 297 *ftsr |= mask; 298 break; 299 default: 300 return -EINVAL; 301 } 302 303 return 0; 304 } 305 306 static int stm32_irq_set_type(struct irq_data *d, unsigned int type) 307 { 308 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); 309 struct stm32_exti_chip_data *chip_data = gc->private; 310 const struct stm32_exti_bank *stm32_bank = chip_data->reg_bank; 311 struct hwspinlock *hwlock = chip_data->host_data->hwlock; 312 u32 rtsr, ftsr; 313 int err; 314 315 irq_gc_lock(gc); 316 317 if (hwlock) { 318 err = hwspin_lock_timeout_in_atomic(hwlock, HWSPNLCK_TIMEOUT); 319 if (err) { 320 pr_err("%s can't get hwspinlock (%d)\n", __func__, err); 321 goto unlock; 322 } 323 } 324 325 rtsr = irq_reg_readl(gc, stm32_bank->rtsr_ofst); 326 ftsr = irq_reg_readl(gc, stm32_bank->ftsr_ofst); 327 328 err = stm32_exti_set_type(d, type, &rtsr, &ftsr); 329 if (err) 330 goto unspinlock; 331 332 irq_reg_writel(gc, rtsr, stm32_bank->rtsr_ofst); 333 irq_reg_writel(gc, ftsr, stm32_bank->ftsr_ofst); 334 335 unspinlock: 336 if (hwlock) 337 hwspin_unlock_in_atomic(hwlock); 338 unlock: 339 irq_gc_unlock(gc); 340 341 return err; 342 } 343 344 static void stm32_chip_suspend(struct stm32_exti_chip_data *chip_data, 345 u32 wake_active) 346 { 347 const struct stm32_exti_bank *stm32_bank = chip_data->reg_bank; 348 void __iomem *base = chip_data->host_data->base; 349 350 /* save rtsr, ftsr registers */ 351 chip_data->rtsr_cache = readl_relaxed(base + stm32_bank->rtsr_ofst); 352 chip_data->ftsr_cache = readl_relaxed(base + stm32_bank->ftsr_ofst); 353 354 writel_relaxed(wake_active, base + stm32_bank->imr_ofst); 355 } 356 357 static void stm32_chip_resume(struct stm32_exti_chip_data *chip_data, 358 u32 mask_cache) 359 { 360 const struct stm32_exti_bank *stm32_bank = chip_data->reg_bank; 361 void __iomem *base = chip_data->host_data->base; 362 363 /* restore rtsr, ftsr, registers */ 364 writel_relaxed(chip_data->rtsr_cache, base + stm32_bank->rtsr_ofst); 365 writel_relaxed(chip_data->ftsr_cache, base + stm32_bank->ftsr_ofst); 366 367 writel_relaxed(mask_cache, base + stm32_bank->imr_ofst); 368 } 369 370 static void stm32_irq_suspend(struct irq_chip_generic *gc) 371 { 372 struct stm32_exti_chip_data *chip_data = gc->private; 373 374 irq_gc_lock(gc); 375 stm32_chip_suspend(chip_data, gc->wake_active); 376 irq_gc_unlock(gc); 377 } 378 379 static void stm32_irq_resume(struct irq_chip_generic *gc) 380 { 381 struct stm32_exti_chip_data *chip_data = gc->private; 382 383 irq_gc_lock(gc); 384 stm32_chip_resume(chip_data, gc->mask_cache); 385 irq_gc_unlock(gc); 386 } 387 388 static int stm32_exti_alloc(struct irq_domain *d, unsigned int virq, 389 unsigned int nr_irqs, void *data) 390 { 391 struct irq_fwspec *fwspec = data; 392 irq_hw_number_t hwirq; 393 394 hwirq = fwspec->param[0]; 395 396 irq_map_generic_chip(d, virq, hwirq); 397 398 return 0; 399 } 400 401 static void stm32_exti_free(struct irq_domain *d, unsigned int virq, 402 unsigned int nr_irqs) 403 { 404 struct irq_data *data = irq_domain_get_irq_data(d, virq); 405 406 irq_domain_reset_irq_data(data); 407 } 408 409 static const struct irq_domain_ops irq_exti_domain_ops = { 410 .map = irq_map_generic_chip, 411 .alloc = stm32_exti_alloc, 412 .free = stm32_exti_free, 413 }; 414 415 static void stm32_irq_ack(struct irq_data *d) 416 { 417 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); 418 struct stm32_exti_chip_data *chip_data = gc->private; 419 const struct stm32_exti_bank *stm32_bank = chip_data->reg_bank; 420 421 irq_gc_lock(gc); 422 423 irq_reg_writel(gc, d->mask, stm32_bank->rpr_ofst); 424 if (stm32_bank->fpr_ofst != UNDEF_REG) 425 irq_reg_writel(gc, d->mask, stm32_bank->fpr_ofst); 426 427 irq_gc_unlock(gc); 428 } 429 430 /* directly set the target bit without reading first. */ 431 static inline void stm32_exti_write_bit(struct irq_data *d, u32 reg) 432 { 433 struct stm32_exti_chip_data *chip_data = irq_data_get_irq_chip_data(d); 434 void __iomem *base = chip_data->host_data->base; 435 u32 val = BIT(d->hwirq % IRQS_PER_BANK); 436 437 writel_relaxed(val, base + reg); 438 } 439 440 static inline u32 stm32_exti_set_bit(struct irq_data *d, u32 reg) 441 { 442 struct stm32_exti_chip_data *chip_data = irq_data_get_irq_chip_data(d); 443 void __iomem *base = chip_data->host_data->base; 444 u32 val; 445 446 val = readl_relaxed(base + reg); 447 val |= BIT(d->hwirq % IRQS_PER_BANK); 448 writel_relaxed(val, base + reg); 449 450 return val; 451 } 452 453 static inline u32 stm32_exti_clr_bit(struct irq_data *d, u32 reg) 454 { 455 struct stm32_exti_chip_data *chip_data = irq_data_get_irq_chip_data(d); 456 void __iomem *base = chip_data->host_data->base; 457 u32 val; 458 459 val = readl_relaxed(base + reg); 460 val &= ~BIT(d->hwirq % IRQS_PER_BANK); 461 writel_relaxed(val, base + reg); 462 463 return val; 464 } 465 466 static void stm32_exti_h_eoi(struct irq_data *d) 467 { 468 struct stm32_exti_chip_data *chip_data = irq_data_get_irq_chip_data(d); 469 const struct stm32_exti_bank *stm32_bank = chip_data->reg_bank; 470 471 raw_spin_lock(&chip_data->rlock); 472 473 stm32_exti_write_bit(d, stm32_bank->rpr_ofst); 474 if (stm32_bank->fpr_ofst != UNDEF_REG) 475 stm32_exti_write_bit(d, stm32_bank->fpr_ofst); 476 477 raw_spin_unlock(&chip_data->rlock); 478 479 if (d->parent_data->chip) 480 irq_chip_eoi_parent(d); 481 } 482 483 static void stm32_exti_h_mask(struct irq_data *d) 484 { 485 struct stm32_exti_chip_data *chip_data = irq_data_get_irq_chip_data(d); 486 const struct stm32_exti_bank *stm32_bank = chip_data->reg_bank; 487 488 raw_spin_lock(&chip_data->rlock); 489 chip_data->mask_cache = stm32_exti_clr_bit(d, stm32_bank->imr_ofst); 490 raw_spin_unlock(&chip_data->rlock); 491 492 if (d->parent_data->chip) 493 irq_chip_mask_parent(d); 494 } 495 496 static void stm32_exti_h_unmask(struct irq_data *d) 497 { 498 struct stm32_exti_chip_data *chip_data = irq_data_get_irq_chip_data(d); 499 const struct stm32_exti_bank *stm32_bank = chip_data->reg_bank; 500 501 raw_spin_lock(&chip_data->rlock); 502 chip_data->mask_cache = stm32_exti_set_bit(d, stm32_bank->imr_ofst); 503 raw_spin_unlock(&chip_data->rlock); 504 505 if (d->parent_data->chip) 506 irq_chip_unmask_parent(d); 507 } 508 509 static int stm32_exti_h_set_type(struct irq_data *d, unsigned int type) 510 { 511 struct stm32_exti_chip_data *chip_data = irq_data_get_irq_chip_data(d); 512 const struct stm32_exti_bank *stm32_bank = chip_data->reg_bank; 513 struct hwspinlock *hwlock = chip_data->host_data->hwlock; 514 void __iomem *base = chip_data->host_data->base; 515 u32 rtsr, ftsr; 516 int err; 517 518 raw_spin_lock(&chip_data->rlock); 519 520 if (hwlock) { 521 err = hwspin_lock_timeout_in_atomic(hwlock, HWSPNLCK_TIMEOUT); 522 if (err) { 523 pr_err("%s can't get hwspinlock (%d)\n", __func__, err); 524 goto unlock; 525 } 526 } 527 528 rtsr = readl_relaxed(base + stm32_bank->rtsr_ofst); 529 ftsr = readl_relaxed(base + stm32_bank->ftsr_ofst); 530 531 err = stm32_exti_set_type(d, type, &rtsr, &ftsr); 532 if (err) 533 goto unspinlock; 534 535 writel_relaxed(rtsr, base + stm32_bank->rtsr_ofst); 536 writel_relaxed(ftsr, base + stm32_bank->ftsr_ofst); 537 538 unspinlock: 539 if (hwlock) 540 hwspin_unlock_in_atomic(hwlock); 541 unlock: 542 raw_spin_unlock(&chip_data->rlock); 543 544 return err; 545 } 546 547 static int stm32_exti_h_set_wake(struct irq_data *d, unsigned int on) 548 { 549 struct stm32_exti_chip_data *chip_data = irq_data_get_irq_chip_data(d); 550 u32 mask = BIT(d->hwirq % IRQS_PER_BANK); 551 552 raw_spin_lock(&chip_data->rlock); 553 554 if (on) 555 chip_data->wake_active |= mask; 556 else 557 chip_data->wake_active &= ~mask; 558 559 raw_spin_unlock(&chip_data->rlock); 560 561 return 0; 562 } 563 564 static int stm32_exti_h_set_affinity(struct irq_data *d, 565 const struct cpumask *dest, bool force) 566 { 567 if (d->parent_data->chip) 568 return irq_chip_set_affinity_parent(d, dest, force); 569 570 return -EINVAL; 571 } 572 573 static int __maybe_unused stm32_exti_h_suspend(void) 574 { 575 struct stm32_exti_chip_data *chip_data; 576 int i; 577 578 for (i = 0; i < stm32_host_data->drv_data->bank_nr; i++) { 579 chip_data = &stm32_host_data->chips_data[i]; 580 raw_spin_lock(&chip_data->rlock); 581 stm32_chip_suspend(chip_data, chip_data->wake_active); 582 raw_spin_unlock(&chip_data->rlock); 583 } 584 585 return 0; 586 } 587 588 static void __maybe_unused stm32_exti_h_resume(void) 589 { 590 struct stm32_exti_chip_data *chip_data; 591 int i; 592 593 for (i = 0; i < stm32_host_data->drv_data->bank_nr; i++) { 594 chip_data = &stm32_host_data->chips_data[i]; 595 raw_spin_lock(&chip_data->rlock); 596 stm32_chip_resume(chip_data, chip_data->mask_cache); 597 raw_spin_unlock(&chip_data->rlock); 598 } 599 } 600 601 static struct syscore_ops stm32_exti_h_syscore_ops = { 602 #ifdef CONFIG_PM_SLEEP 603 .suspend = stm32_exti_h_suspend, 604 .resume = stm32_exti_h_resume, 605 #endif 606 }; 607 608 static void stm32_exti_h_syscore_init(struct stm32_exti_host_data *host_data) 609 { 610 stm32_host_data = host_data; 611 register_syscore_ops(&stm32_exti_h_syscore_ops); 612 } 613 614 static void stm32_exti_h_syscore_deinit(void) 615 { 616 unregister_syscore_ops(&stm32_exti_h_syscore_ops); 617 } 618 619 static int stm32_exti_h_retrigger(struct irq_data *d) 620 { 621 struct stm32_exti_chip_data *chip_data = irq_data_get_irq_chip_data(d); 622 const struct stm32_exti_bank *stm32_bank = chip_data->reg_bank; 623 void __iomem *base = chip_data->host_data->base; 624 u32 mask = BIT(d->hwirq % IRQS_PER_BANK); 625 626 writel_relaxed(mask, base + stm32_bank->swier_ofst); 627 628 return 0; 629 } 630 631 static struct irq_chip stm32_exti_h_chip = { 632 .name = "stm32-exti-h", 633 .irq_eoi = stm32_exti_h_eoi, 634 .irq_mask = stm32_exti_h_mask, 635 .irq_unmask = stm32_exti_h_unmask, 636 .irq_retrigger = stm32_exti_h_retrigger, 637 .irq_set_type = stm32_exti_h_set_type, 638 .irq_set_wake = stm32_exti_h_set_wake, 639 .flags = IRQCHIP_MASK_ON_SUSPEND, 640 .irq_set_affinity = IS_ENABLED(CONFIG_SMP) ? stm32_exti_h_set_affinity : NULL, 641 }; 642 643 static struct irq_chip stm32_exti_h_chip_direct = { 644 .name = "stm32-exti-h-direct", 645 .irq_eoi = irq_chip_eoi_parent, 646 .irq_ack = irq_chip_ack_parent, 647 .irq_mask = irq_chip_mask_parent, 648 .irq_unmask = irq_chip_unmask_parent, 649 .irq_retrigger = irq_chip_retrigger_hierarchy, 650 .irq_set_type = irq_chip_set_type_parent, 651 .irq_set_wake = stm32_exti_h_set_wake, 652 .flags = IRQCHIP_MASK_ON_SUSPEND, 653 .irq_set_affinity = IS_ENABLED(CONFIG_SMP) ? irq_chip_set_affinity_parent : NULL, 654 }; 655 656 static int stm32_exti_h_domain_alloc(struct irq_domain *dm, 657 unsigned int virq, 658 unsigned int nr_irqs, void *data) 659 { 660 struct stm32_exti_host_data *host_data = dm->host_data; 661 struct stm32_exti_chip_data *chip_data; 662 const struct stm32_desc_irq *desc; 663 struct irq_fwspec *fwspec = data; 664 struct irq_fwspec p_fwspec; 665 irq_hw_number_t hwirq; 666 int bank; 667 668 hwirq = fwspec->param[0]; 669 bank = hwirq / IRQS_PER_BANK; 670 chip_data = &host_data->chips_data[bank]; 671 672 673 desc = stm32_exti_get_desc(host_data->drv_data, hwirq); 674 if (!desc) 675 return -EINVAL; 676 677 irq_domain_set_hwirq_and_chip(dm, virq, hwirq, desc->chip, 678 chip_data); 679 if (desc->irq_parent) { 680 p_fwspec.fwnode = dm->parent->fwnode; 681 p_fwspec.param_count = 3; 682 p_fwspec.param[0] = GIC_SPI; 683 p_fwspec.param[1] = desc->irq_parent; 684 p_fwspec.param[2] = IRQ_TYPE_LEVEL_HIGH; 685 686 return irq_domain_alloc_irqs_parent(dm, virq, 1, &p_fwspec); 687 } 688 689 return 0; 690 } 691 692 static struct 693 stm32_exti_host_data *stm32_exti_host_init(const struct stm32_exti_drv_data *dd, 694 struct device_node *node) 695 { 696 struct stm32_exti_host_data *host_data; 697 698 host_data = kzalloc(sizeof(*host_data), GFP_KERNEL); 699 if (!host_data) 700 return NULL; 701 702 host_data->drv_data = dd; 703 host_data->chips_data = kcalloc(dd->bank_nr, 704 sizeof(struct stm32_exti_chip_data), 705 GFP_KERNEL); 706 if (!host_data->chips_data) 707 goto free_host_data; 708 709 host_data->base = of_iomap(node, 0); 710 if (!host_data->base) { 711 pr_err("%pOF: Unable to map registers\n", node); 712 goto free_chips_data; 713 } 714 715 stm32_host_data = host_data; 716 717 return host_data; 718 719 free_chips_data: 720 kfree(host_data->chips_data); 721 free_host_data: 722 kfree(host_data); 723 724 return NULL; 725 } 726 727 static struct 728 stm32_exti_chip_data *stm32_exti_chip_init(struct stm32_exti_host_data *h_data, 729 u32 bank_idx, 730 struct device_node *node) 731 { 732 const struct stm32_exti_bank *stm32_bank; 733 struct stm32_exti_chip_data *chip_data; 734 void __iomem *base = h_data->base; 735 736 stm32_bank = h_data->drv_data->exti_banks[bank_idx]; 737 chip_data = &h_data->chips_data[bank_idx]; 738 chip_data->host_data = h_data; 739 chip_data->reg_bank = stm32_bank; 740 741 raw_spin_lock_init(&chip_data->rlock); 742 743 /* 744 * This IP has no reset, so after hot reboot we should 745 * clear registers to avoid residue 746 */ 747 writel_relaxed(0, base + stm32_bank->imr_ofst); 748 writel_relaxed(0, base + stm32_bank->emr_ofst); 749 750 pr_info("%pOF: bank%d\n", node, bank_idx); 751 752 return chip_data; 753 } 754 755 static int __init stm32_exti_init(const struct stm32_exti_drv_data *drv_data, 756 struct device_node *node) 757 { 758 struct stm32_exti_host_data *host_data; 759 unsigned int clr = IRQ_NOREQUEST | IRQ_NOPROBE | IRQ_NOAUTOEN; 760 int nr_irqs, ret, i; 761 struct irq_chip_generic *gc; 762 struct irq_domain *domain; 763 764 host_data = stm32_exti_host_init(drv_data, node); 765 if (!host_data) 766 return -ENOMEM; 767 768 domain = irq_domain_add_linear(node, drv_data->bank_nr * IRQS_PER_BANK, 769 &irq_exti_domain_ops, NULL); 770 if (!domain) { 771 pr_err("%pOFn: Could not register interrupt domain.\n", 772 node); 773 ret = -ENOMEM; 774 goto out_unmap; 775 } 776 777 ret = irq_alloc_domain_generic_chips(domain, IRQS_PER_BANK, 1, "exti", 778 handle_edge_irq, clr, 0, 0); 779 if (ret) { 780 pr_err("%pOF: Could not allocate generic interrupt chip.\n", 781 node); 782 goto out_free_domain; 783 } 784 785 for (i = 0; i < drv_data->bank_nr; i++) { 786 const struct stm32_exti_bank *stm32_bank; 787 struct stm32_exti_chip_data *chip_data; 788 789 stm32_bank = drv_data->exti_banks[i]; 790 chip_data = stm32_exti_chip_init(host_data, i, node); 791 792 gc = irq_get_domain_generic_chip(domain, i * IRQS_PER_BANK); 793 794 gc->reg_base = host_data->base; 795 gc->chip_types->type = IRQ_TYPE_EDGE_BOTH; 796 gc->chip_types->chip.irq_ack = stm32_irq_ack; 797 gc->chip_types->chip.irq_mask = irq_gc_mask_clr_bit; 798 gc->chip_types->chip.irq_unmask = irq_gc_mask_set_bit; 799 gc->chip_types->chip.irq_set_type = stm32_irq_set_type; 800 gc->chip_types->chip.irq_set_wake = irq_gc_set_wake; 801 gc->suspend = stm32_irq_suspend; 802 gc->resume = stm32_irq_resume; 803 gc->wake_enabled = IRQ_MSK(IRQS_PER_BANK); 804 805 gc->chip_types->regs.mask = stm32_bank->imr_ofst; 806 gc->private = (void *)chip_data; 807 } 808 809 nr_irqs = of_irq_count(node); 810 for (i = 0; i < nr_irqs; i++) { 811 unsigned int irq = irq_of_parse_and_map(node, i); 812 813 irq_set_handler_data(irq, domain); 814 irq_set_chained_handler(irq, stm32_irq_handler); 815 } 816 817 return 0; 818 819 out_free_domain: 820 irq_domain_remove(domain); 821 out_unmap: 822 iounmap(host_data->base); 823 kfree(host_data->chips_data); 824 kfree(host_data); 825 return ret; 826 } 827 828 static const struct irq_domain_ops stm32_exti_h_domain_ops = { 829 .alloc = stm32_exti_h_domain_alloc, 830 .free = irq_domain_free_irqs_common, 831 .xlate = irq_domain_xlate_twocell, 832 }; 833 834 static void stm32_exti_remove_irq(void *data) 835 { 836 struct irq_domain *domain = data; 837 838 irq_domain_remove(domain); 839 } 840 841 static int stm32_exti_remove(struct platform_device *pdev) 842 { 843 stm32_exti_h_syscore_deinit(); 844 return 0; 845 } 846 847 static int stm32_exti_probe(struct platform_device *pdev) 848 { 849 int ret, i; 850 struct device *dev = &pdev->dev; 851 struct device_node *np = dev->of_node; 852 struct irq_domain *parent_domain, *domain; 853 struct stm32_exti_host_data *host_data; 854 const struct stm32_exti_drv_data *drv_data; 855 struct resource *res; 856 857 host_data = devm_kzalloc(dev, sizeof(*host_data), GFP_KERNEL); 858 if (!host_data) 859 return -ENOMEM; 860 861 /* check for optional hwspinlock which may be not available yet */ 862 ret = of_hwspin_lock_get_id(np, 0); 863 if (ret == -EPROBE_DEFER) 864 /* hwspinlock framework not yet ready */ 865 return ret; 866 867 if (ret >= 0) { 868 host_data->hwlock = devm_hwspin_lock_request_specific(dev, ret); 869 if (!host_data->hwlock) { 870 dev_err(dev, "Failed to request hwspinlock\n"); 871 return -EINVAL; 872 } 873 } else if (ret != -ENOENT) { 874 /* note: ENOENT is a valid case (means 'no hwspinlock') */ 875 dev_err(dev, "Failed to get hwspinlock\n"); 876 return ret; 877 } 878 879 /* initialize host_data */ 880 drv_data = of_device_get_match_data(dev); 881 if (!drv_data) { 882 dev_err(dev, "no of match data\n"); 883 return -ENODEV; 884 } 885 host_data->drv_data = drv_data; 886 887 host_data->chips_data = devm_kcalloc(dev, drv_data->bank_nr, 888 sizeof(*host_data->chips_data), 889 GFP_KERNEL); 890 if (!host_data->chips_data) 891 return -ENOMEM; 892 893 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 894 host_data->base = devm_ioremap_resource(dev, res); 895 if (IS_ERR(host_data->base)) { 896 dev_err(dev, "Unable to map registers\n"); 897 return PTR_ERR(host_data->base); 898 } 899 900 for (i = 0; i < drv_data->bank_nr; i++) 901 stm32_exti_chip_init(host_data, i, np); 902 903 parent_domain = irq_find_host(of_irq_find_parent(np)); 904 if (!parent_domain) { 905 dev_err(dev, "GIC interrupt-parent not found\n"); 906 return -EINVAL; 907 } 908 909 domain = irq_domain_add_hierarchy(parent_domain, 0, 910 drv_data->bank_nr * IRQS_PER_BANK, 911 np, &stm32_exti_h_domain_ops, 912 host_data); 913 914 if (!domain) { 915 dev_err(dev, "Could not register exti domain\n"); 916 return -ENOMEM; 917 } 918 919 ret = devm_add_action_or_reset(dev, stm32_exti_remove_irq, domain); 920 if (ret) 921 return ret; 922 923 stm32_exti_h_syscore_init(host_data); 924 925 return 0; 926 } 927 928 /* platform driver only for MP1 */ 929 static const struct of_device_id stm32_exti_ids[] = { 930 { .compatible = "st,stm32mp1-exti", .data = &stm32mp1_drv_data}, 931 {}, 932 }; 933 MODULE_DEVICE_TABLE(of, stm32_exti_ids); 934 935 static struct platform_driver stm32_exti_driver = { 936 .probe = stm32_exti_probe, 937 .remove = stm32_exti_remove, 938 .driver = { 939 .name = "stm32_exti", 940 .of_match_table = stm32_exti_ids, 941 }, 942 }; 943 944 static int __init stm32_exti_arch_init(void) 945 { 946 return platform_driver_register(&stm32_exti_driver); 947 } 948 949 static void __exit stm32_exti_arch_exit(void) 950 { 951 return platform_driver_unregister(&stm32_exti_driver); 952 } 953 954 arch_initcall(stm32_exti_arch_init); 955 module_exit(stm32_exti_arch_exit); 956 957 /* no platform driver for F4 and H7 */ 958 static int __init stm32f4_exti_of_init(struct device_node *np, 959 struct device_node *parent) 960 { 961 return stm32_exti_init(&stm32f4xx_drv_data, np); 962 } 963 964 IRQCHIP_DECLARE(stm32f4_exti, "st,stm32-exti", stm32f4_exti_of_init); 965 966 static int __init stm32h7_exti_of_init(struct device_node *np, 967 struct device_node *parent) 968 { 969 return stm32_exti_init(&stm32h7xx_drv_data, np); 970 } 971 972 IRQCHIP_DECLARE(stm32h7_exti, "st,stm32h7-exti", stm32h7_exti_of_init); 973