1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (C) Maxime Coquelin 2015 4 * Copyright (C) STMicroelectronics 2017 5 * Author: Maxime Coquelin <mcoquelin.stm32@gmail.com> 6 */ 7 8 #include <linux/bitops.h> 9 #include <linux/delay.h> 10 #include <linux/hwspinlock.h> 11 #include <linux/interrupt.h> 12 #include <linux/io.h> 13 #include <linux/irq.h> 14 #include <linux/irqchip.h> 15 #include <linux/irqchip/chained_irq.h> 16 #include <linux/irqdomain.h> 17 #include <linux/mod_devicetable.h> 18 #include <linux/module.h> 19 #include <linux/of_address.h> 20 #include <linux/of_irq.h> 21 #include <linux/platform_device.h> 22 #include <linux/pm.h> 23 24 #include <dt-bindings/interrupt-controller/arm-gic.h> 25 26 #define IRQS_PER_BANK 32 27 28 #define HWSPNLCK_TIMEOUT 1000 /* usec */ 29 30 #define EXTI_EnCIDCFGR(n) (0x180 + (n) * 4) 31 #define EXTI_HWCFGR1 0x3f0 32 33 /* Register: EXTI_EnCIDCFGR(n) */ 34 #define EXTI_CIDCFGR_CFEN_MASK BIT(0) 35 #define EXTI_CIDCFGR_CID_MASK GENMASK(6, 4) 36 #define EXTI_CIDCFGR_CID_SHIFT 4 37 38 /* Register: EXTI_HWCFGR1 */ 39 #define EXTI_HWCFGR1_CIDWIDTH_MASK GENMASK(27, 24) 40 41 #define EXTI_CID1 1 42 43 struct stm32_exti_bank { 44 u32 imr_ofst; 45 u32 emr_ofst; 46 u32 rtsr_ofst; 47 u32 ftsr_ofst; 48 u32 swier_ofst; 49 u32 rpr_ofst; 50 u32 fpr_ofst; 51 u32 trg_ofst; 52 u32 seccfgr_ofst; 53 }; 54 55 #define UNDEF_REG ~0 56 57 struct stm32_exti_drv_data { 58 const struct stm32_exti_bank **exti_banks; 59 const u8 *desc_irqs; 60 u32 bank_nr; 61 }; 62 63 struct stm32_exti_chip_data { 64 struct stm32_exti_host_data *host_data; 65 const struct stm32_exti_bank *reg_bank; 66 struct raw_spinlock rlock; 67 u32 wake_active; 68 u32 mask_cache; 69 u32 rtsr_cache; 70 u32 ftsr_cache; 71 u32 event_reserved; 72 }; 73 74 struct stm32_exti_host_data { 75 void __iomem *base; 76 struct device *dev; 77 struct stm32_exti_chip_data *chips_data; 78 const struct stm32_exti_drv_data *drv_data; 79 struct hwspinlock *hwlock; 80 bool dt_has_irqs_desc; /* skip internal desc_irqs array and get it from DT */ 81 }; 82 83 static const struct stm32_exti_bank stm32f4xx_exti_b1 = { 84 .imr_ofst = 0x00, 85 .emr_ofst = 0x04, 86 .rtsr_ofst = 0x08, 87 .ftsr_ofst = 0x0C, 88 .swier_ofst = 0x10, 89 .rpr_ofst = 0x14, 90 .fpr_ofst = UNDEF_REG, 91 .trg_ofst = UNDEF_REG, 92 .seccfgr_ofst = UNDEF_REG, 93 }; 94 95 static const struct stm32_exti_bank *stm32f4xx_exti_banks[] = { 96 &stm32f4xx_exti_b1, 97 }; 98 99 static const struct stm32_exti_drv_data stm32f4xx_drv_data = { 100 .exti_banks = stm32f4xx_exti_banks, 101 .bank_nr = ARRAY_SIZE(stm32f4xx_exti_banks), 102 }; 103 104 static const struct stm32_exti_bank stm32h7xx_exti_b1 = { 105 .imr_ofst = 0x80, 106 .emr_ofst = 0x84, 107 .rtsr_ofst = 0x00, 108 .ftsr_ofst = 0x04, 109 .swier_ofst = 0x08, 110 .rpr_ofst = 0x88, 111 .fpr_ofst = UNDEF_REG, 112 .trg_ofst = UNDEF_REG, 113 .seccfgr_ofst = UNDEF_REG, 114 }; 115 116 static const struct stm32_exti_bank stm32h7xx_exti_b2 = { 117 .imr_ofst = 0x90, 118 .emr_ofst = 0x94, 119 .rtsr_ofst = 0x20, 120 .ftsr_ofst = 0x24, 121 .swier_ofst = 0x28, 122 .rpr_ofst = 0x98, 123 .fpr_ofst = UNDEF_REG, 124 .trg_ofst = UNDEF_REG, 125 .seccfgr_ofst = UNDEF_REG, 126 }; 127 128 static const struct stm32_exti_bank stm32h7xx_exti_b3 = { 129 .imr_ofst = 0xA0, 130 .emr_ofst = 0xA4, 131 .rtsr_ofst = 0x40, 132 .ftsr_ofst = 0x44, 133 .swier_ofst = 0x48, 134 .rpr_ofst = 0xA8, 135 .fpr_ofst = UNDEF_REG, 136 .trg_ofst = UNDEF_REG, 137 .seccfgr_ofst = UNDEF_REG, 138 }; 139 140 static const struct stm32_exti_bank *stm32h7xx_exti_banks[] = { 141 &stm32h7xx_exti_b1, 142 &stm32h7xx_exti_b2, 143 &stm32h7xx_exti_b3, 144 }; 145 146 static const struct stm32_exti_drv_data stm32h7xx_drv_data = { 147 .exti_banks = stm32h7xx_exti_banks, 148 .bank_nr = ARRAY_SIZE(stm32h7xx_exti_banks), 149 }; 150 151 static const struct stm32_exti_bank stm32mp1_exti_b1 = { 152 .imr_ofst = 0x80, 153 .emr_ofst = UNDEF_REG, 154 .rtsr_ofst = 0x00, 155 .ftsr_ofst = 0x04, 156 .swier_ofst = 0x08, 157 .rpr_ofst = 0x0C, 158 .fpr_ofst = 0x10, 159 .trg_ofst = 0x3EC, 160 .seccfgr_ofst = 0x14, 161 }; 162 163 static const struct stm32_exti_bank stm32mp1_exti_b2 = { 164 .imr_ofst = 0x90, 165 .emr_ofst = UNDEF_REG, 166 .rtsr_ofst = 0x20, 167 .ftsr_ofst = 0x24, 168 .swier_ofst = 0x28, 169 .rpr_ofst = 0x2C, 170 .fpr_ofst = 0x30, 171 .trg_ofst = 0x3E8, 172 .seccfgr_ofst = 0x34, 173 }; 174 175 static const struct stm32_exti_bank stm32mp1_exti_b3 = { 176 .imr_ofst = 0xA0, 177 .emr_ofst = UNDEF_REG, 178 .rtsr_ofst = 0x40, 179 .ftsr_ofst = 0x44, 180 .swier_ofst = 0x48, 181 .rpr_ofst = 0x4C, 182 .fpr_ofst = 0x50, 183 .trg_ofst = 0x3E4, 184 .seccfgr_ofst = 0x54, 185 }; 186 187 static const struct stm32_exti_bank *stm32mp1_exti_banks[] = { 188 &stm32mp1_exti_b1, 189 &stm32mp1_exti_b2, 190 &stm32mp1_exti_b3, 191 }; 192 193 static struct irq_chip stm32_exti_h_chip; 194 static struct irq_chip stm32_exti_h_chip_direct; 195 196 #define EXTI_INVALID_IRQ U8_MAX 197 #define STM32MP1_DESC_IRQ_SIZE (ARRAY_SIZE(stm32mp1_exti_banks) * IRQS_PER_BANK) 198 199 /* 200 * Use some intentionally tricky logic here to initialize the whole array to 201 * EXTI_INVALID_IRQ, but then override certain fields, requiring us to indicate 202 * that we "know" that there are overrides in this structure, and we'll need to 203 * disable that warning from W=1 builds. 204 */ 205 __diag_push(); 206 __diag_ignore_all("-Woverride-init", 207 "logic to initialize all and then override some is OK"); 208 209 static const u8 stm32mp1_desc_irq[] = { 210 /* default value */ 211 [0 ... (STM32MP1_DESC_IRQ_SIZE - 1)] = EXTI_INVALID_IRQ, 212 213 [0] = 6, 214 [1] = 7, 215 [2] = 8, 216 [3] = 9, 217 [4] = 10, 218 [5] = 23, 219 [6] = 64, 220 [7] = 65, 221 [8] = 66, 222 [9] = 67, 223 [10] = 40, 224 [11] = 42, 225 [12] = 76, 226 [13] = 77, 227 [14] = 121, 228 [15] = 127, 229 [16] = 1, 230 [19] = 3, 231 [21] = 31, 232 [22] = 33, 233 [23] = 72, 234 [24] = 95, 235 [25] = 107, 236 [26] = 37, 237 [27] = 38, 238 [28] = 39, 239 [29] = 71, 240 [30] = 52, 241 [31] = 53, 242 [32] = 82, 243 [33] = 83, 244 [46] = 151, 245 [47] = 93, 246 [48] = 138, 247 [50] = 139, 248 [52] = 140, 249 [53] = 141, 250 [54] = 135, 251 [61] = 100, 252 [65] = 144, 253 [68] = 143, 254 [70] = 62, 255 [73] = 129, 256 }; 257 258 static const u8 stm32mp13_desc_irq[] = { 259 /* default value */ 260 [0 ... (STM32MP1_DESC_IRQ_SIZE - 1)] = EXTI_INVALID_IRQ, 261 262 [0] = 6, 263 [1] = 7, 264 [2] = 8, 265 [3] = 9, 266 [4] = 10, 267 [5] = 24, 268 [6] = 65, 269 [7] = 66, 270 [8] = 67, 271 [9] = 68, 272 [10] = 41, 273 [11] = 43, 274 [12] = 77, 275 [13] = 78, 276 [14] = 106, 277 [15] = 109, 278 [16] = 1, 279 [19] = 3, 280 [21] = 32, 281 [22] = 34, 282 [23] = 73, 283 [24] = 93, 284 [25] = 114, 285 [26] = 38, 286 [27] = 39, 287 [28] = 40, 288 [29] = 72, 289 [30] = 53, 290 [31] = 54, 291 [32] = 83, 292 [33] = 84, 293 [44] = 96, 294 [47] = 92, 295 [48] = 116, 296 [50] = 117, 297 [52] = 118, 298 [53] = 119, 299 [68] = 63, 300 [70] = 98, 301 }; 302 303 __diag_pop(); 304 305 static const struct stm32_exti_drv_data stm32mp1_drv_data = { 306 .exti_banks = stm32mp1_exti_banks, 307 .bank_nr = ARRAY_SIZE(stm32mp1_exti_banks), 308 .desc_irqs = stm32mp1_desc_irq, 309 }; 310 311 static const struct stm32_exti_drv_data stm32mp13_drv_data = { 312 .exti_banks = stm32mp1_exti_banks, 313 .bank_nr = ARRAY_SIZE(stm32mp1_exti_banks), 314 .desc_irqs = stm32mp13_desc_irq, 315 }; 316 317 static unsigned long stm32_exti_pending(struct irq_chip_generic *gc) 318 { 319 struct stm32_exti_chip_data *chip_data = gc->private; 320 const struct stm32_exti_bank *stm32_bank = chip_data->reg_bank; 321 unsigned long pending; 322 323 pending = irq_reg_readl(gc, stm32_bank->rpr_ofst); 324 if (stm32_bank->fpr_ofst != UNDEF_REG) 325 pending |= irq_reg_readl(gc, stm32_bank->fpr_ofst); 326 327 return pending; 328 } 329 330 static void stm32_irq_handler(struct irq_desc *desc) 331 { 332 struct irq_domain *domain = irq_desc_get_handler_data(desc); 333 struct irq_chip *chip = irq_desc_get_chip(desc); 334 unsigned int nbanks = domain->gc->num_chips; 335 struct irq_chip_generic *gc; 336 unsigned long pending; 337 int n, i, irq_base = 0; 338 339 chained_irq_enter(chip, desc); 340 341 for (i = 0; i < nbanks; i++, irq_base += IRQS_PER_BANK) { 342 gc = irq_get_domain_generic_chip(domain, irq_base); 343 344 while ((pending = stm32_exti_pending(gc))) { 345 for_each_set_bit(n, &pending, IRQS_PER_BANK) 346 generic_handle_domain_irq(domain, irq_base + n); 347 } 348 } 349 350 chained_irq_exit(chip, desc); 351 } 352 353 static int stm32_exti_set_type(struct irq_data *d, 354 unsigned int type, u32 *rtsr, u32 *ftsr) 355 { 356 u32 mask = BIT(d->hwirq % IRQS_PER_BANK); 357 358 switch (type) { 359 case IRQ_TYPE_EDGE_RISING: 360 *rtsr |= mask; 361 *ftsr &= ~mask; 362 break; 363 case IRQ_TYPE_EDGE_FALLING: 364 *rtsr &= ~mask; 365 *ftsr |= mask; 366 break; 367 case IRQ_TYPE_EDGE_BOTH: 368 *rtsr |= mask; 369 *ftsr |= mask; 370 break; 371 default: 372 return -EINVAL; 373 } 374 375 return 0; 376 } 377 378 static int stm32_irq_set_type(struct irq_data *d, unsigned int type) 379 { 380 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); 381 struct stm32_exti_chip_data *chip_data = gc->private; 382 const struct stm32_exti_bank *stm32_bank = chip_data->reg_bank; 383 struct hwspinlock *hwlock = chip_data->host_data->hwlock; 384 u32 rtsr, ftsr; 385 int err; 386 387 irq_gc_lock(gc); 388 389 if (hwlock) { 390 err = hwspin_lock_timeout_in_atomic(hwlock, HWSPNLCK_TIMEOUT); 391 if (err) { 392 pr_err("%s can't get hwspinlock (%d)\n", __func__, err); 393 goto unlock; 394 } 395 } 396 397 rtsr = irq_reg_readl(gc, stm32_bank->rtsr_ofst); 398 ftsr = irq_reg_readl(gc, stm32_bank->ftsr_ofst); 399 400 err = stm32_exti_set_type(d, type, &rtsr, &ftsr); 401 if (err) 402 goto unspinlock; 403 404 irq_reg_writel(gc, rtsr, stm32_bank->rtsr_ofst); 405 irq_reg_writel(gc, ftsr, stm32_bank->ftsr_ofst); 406 407 unspinlock: 408 if (hwlock) 409 hwspin_unlock_in_atomic(hwlock); 410 unlock: 411 irq_gc_unlock(gc); 412 413 return err; 414 } 415 416 static void stm32_chip_suspend(struct stm32_exti_chip_data *chip_data, 417 u32 wake_active) 418 { 419 const struct stm32_exti_bank *stm32_bank = chip_data->reg_bank; 420 void __iomem *base = chip_data->host_data->base; 421 422 /* save rtsr, ftsr registers */ 423 chip_data->rtsr_cache = readl_relaxed(base + stm32_bank->rtsr_ofst); 424 chip_data->ftsr_cache = readl_relaxed(base + stm32_bank->ftsr_ofst); 425 426 writel_relaxed(wake_active, base + stm32_bank->imr_ofst); 427 } 428 429 static void stm32_chip_resume(struct stm32_exti_chip_data *chip_data, 430 u32 mask_cache) 431 { 432 const struct stm32_exti_bank *stm32_bank = chip_data->reg_bank; 433 void __iomem *base = chip_data->host_data->base; 434 435 /* restore rtsr, ftsr, registers */ 436 writel_relaxed(chip_data->rtsr_cache, base + stm32_bank->rtsr_ofst); 437 writel_relaxed(chip_data->ftsr_cache, base + stm32_bank->ftsr_ofst); 438 439 writel_relaxed(mask_cache, base + stm32_bank->imr_ofst); 440 } 441 442 static void stm32_irq_suspend(struct irq_chip_generic *gc) 443 { 444 struct stm32_exti_chip_data *chip_data = gc->private; 445 446 irq_gc_lock(gc); 447 stm32_chip_suspend(chip_data, gc->wake_active); 448 irq_gc_unlock(gc); 449 } 450 451 static void stm32_irq_resume(struct irq_chip_generic *gc) 452 { 453 struct stm32_exti_chip_data *chip_data = gc->private; 454 455 irq_gc_lock(gc); 456 stm32_chip_resume(chip_data, gc->mask_cache); 457 irq_gc_unlock(gc); 458 } 459 460 static int stm32_exti_alloc(struct irq_domain *d, unsigned int virq, 461 unsigned int nr_irqs, void *data) 462 { 463 struct irq_fwspec *fwspec = data; 464 irq_hw_number_t hwirq; 465 466 hwirq = fwspec->param[0]; 467 468 irq_map_generic_chip(d, virq, hwirq); 469 470 return 0; 471 } 472 473 static void stm32_exti_free(struct irq_domain *d, unsigned int virq, 474 unsigned int nr_irqs) 475 { 476 struct irq_data *data = irq_domain_get_irq_data(d, virq); 477 478 irq_domain_reset_irq_data(data); 479 } 480 481 static const struct irq_domain_ops irq_exti_domain_ops = { 482 .map = irq_map_generic_chip, 483 .alloc = stm32_exti_alloc, 484 .free = stm32_exti_free, 485 .xlate = irq_domain_xlate_twocell, 486 }; 487 488 static void stm32_irq_ack(struct irq_data *d) 489 { 490 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); 491 struct stm32_exti_chip_data *chip_data = gc->private; 492 const struct stm32_exti_bank *stm32_bank = chip_data->reg_bank; 493 494 irq_gc_lock(gc); 495 496 irq_reg_writel(gc, d->mask, stm32_bank->rpr_ofst); 497 if (stm32_bank->fpr_ofst != UNDEF_REG) 498 irq_reg_writel(gc, d->mask, stm32_bank->fpr_ofst); 499 500 irq_gc_unlock(gc); 501 } 502 503 /* directly set the target bit without reading first. */ 504 static inline void stm32_exti_write_bit(struct irq_data *d, u32 reg) 505 { 506 struct stm32_exti_chip_data *chip_data = irq_data_get_irq_chip_data(d); 507 void __iomem *base = chip_data->host_data->base; 508 u32 val = BIT(d->hwirq % IRQS_PER_BANK); 509 510 writel_relaxed(val, base + reg); 511 } 512 513 static inline u32 stm32_exti_set_bit(struct irq_data *d, u32 reg) 514 { 515 struct stm32_exti_chip_data *chip_data = irq_data_get_irq_chip_data(d); 516 void __iomem *base = chip_data->host_data->base; 517 u32 val; 518 519 val = readl_relaxed(base + reg); 520 val |= BIT(d->hwirq % IRQS_PER_BANK); 521 writel_relaxed(val, base + reg); 522 523 return val; 524 } 525 526 static inline u32 stm32_exti_clr_bit(struct irq_data *d, u32 reg) 527 { 528 struct stm32_exti_chip_data *chip_data = irq_data_get_irq_chip_data(d); 529 void __iomem *base = chip_data->host_data->base; 530 u32 val; 531 532 val = readl_relaxed(base + reg); 533 val &= ~BIT(d->hwirq % IRQS_PER_BANK); 534 writel_relaxed(val, base + reg); 535 536 return val; 537 } 538 539 static void stm32_exti_h_eoi(struct irq_data *d) 540 { 541 struct stm32_exti_chip_data *chip_data = irq_data_get_irq_chip_data(d); 542 const struct stm32_exti_bank *stm32_bank = chip_data->reg_bank; 543 544 raw_spin_lock(&chip_data->rlock); 545 546 stm32_exti_write_bit(d, stm32_bank->rpr_ofst); 547 if (stm32_bank->fpr_ofst != UNDEF_REG) 548 stm32_exti_write_bit(d, stm32_bank->fpr_ofst); 549 550 raw_spin_unlock(&chip_data->rlock); 551 552 if (d->parent_data->chip) 553 irq_chip_eoi_parent(d); 554 } 555 556 static void stm32_exti_h_mask(struct irq_data *d) 557 { 558 struct stm32_exti_chip_data *chip_data = irq_data_get_irq_chip_data(d); 559 const struct stm32_exti_bank *stm32_bank = chip_data->reg_bank; 560 561 raw_spin_lock(&chip_data->rlock); 562 chip_data->mask_cache = stm32_exti_clr_bit(d, stm32_bank->imr_ofst); 563 raw_spin_unlock(&chip_data->rlock); 564 565 if (d->parent_data->chip) 566 irq_chip_mask_parent(d); 567 } 568 569 static void stm32_exti_h_unmask(struct irq_data *d) 570 { 571 struct stm32_exti_chip_data *chip_data = irq_data_get_irq_chip_data(d); 572 const struct stm32_exti_bank *stm32_bank = chip_data->reg_bank; 573 574 raw_spin_lock(&chip_data->rlock); 575 chip_data->mask_cache = stm32_exti_set_bit(d, stm32_bank->imr_ofst); 576 raw_spin_unlock(&chip_data->rlock); 577 578 if (d->parent_data->chip) 579 irq_chip_unmask_parent(d); 580 } 581 582 static int stm32_exti_h_set_type(struct irq_data *d, unsigned int type) 583 { 584 struct stm32_exti_chip_data *chip_data = irq_data_get_irq_chip_data(d); 585 const struct stm32_exti_bank *stm32_bank = chip_data->reg_bank; 586 struct hwspinlock *hwlock = chip_data->host_data->hwlock; 587 void __iomem *base = chip_data->host_data->base; 588 u32 rtsr, ftsr; 589 int err; 590 591 raw_spin_lock(&chip_data->rlock); 592 593 if (hwlock) { 594 err = hwspin_lock_timeout_in_atomic(hwlock, HWSPNLCK_TIMEOUT); 595 if (err) { 596 pr_err("%s can't get hwspinlock (%d)\n", __func__, err); 597 goto unlock; 598 } 599 } 600 601 rtsr = readl_relaxed(base + stm32_bank->rtsr_ofst); 602 ftsr = readl_relaxed(base + stm32_bank->ftsr_ofst); 603 604 err = stm32_exti_set_type(d, type, &rtsr, &ftsr); 605 if (err) 606 goto unspinlock; 607 608 writel_relaxed(rtsr, base + stm32_bank->rtsr_ofst); 609 writel_relaxed(ftsr, base + stm32_bank->ftsr_ofst); 610 611 unspinlock: 612 if (hwlock) 613 hwspin_unlock_in_atomic(hwlock); 614 unlock: 615 raw_spin_unlock(&chip_data->rlock); 616 617 return err; 618 } 619 620 static int stm32_exti_h_set_wake(struct irq_data *d, unsigned int on) 621 { 622 struct stm32_exti_chip_data *chip_data = irq_data_get_irq_chip_data(d); 623 u32 mask = BIT(d->hwirq % IRQS_PER_BANK); 624 625 raw_spin_lock(&chip_data->rlock); 626 627 if (on) 628 chip_data->wake_active |= mask; 629 else 630 chip_data->wake_active &= ~mask; 631 632 raw_spin_unlock(&chip_data->rlock); 633 634 return 0; 635 } 636 637 static int stm32_exti_h_set_affinity(struct irq_data *d, 638 const struct cpumask *dest, bool force) 639 { 640 if (d->parent_data->chip) 641 return irq_chip_set_affinity_parent(d, dest, force); 642 643 return IRQ_SET_MASK_OK_DONE; 644 } 645 646 static int stm32_exti_h_suspend(struct device *dev) 647 { 648 struct stm32_exti_host_data *host_data = dev_get_drvdata(dev); 649 struct stm32_exti_chip_data *chip_data; 650 int i; 651 652 for (i = 0; i < host_data->drv_data->bank_nr; i++) { 653 chip_data = &host_data->chips_data[i]; 654 stm32_chip_suspend(chip_data, chip_data->wake_active); 655 } 656 657 return 0; 658 } 659 660 static int stm32_exti_h_resume(struct device *dev) 661 { 662 struct stm32_exti_host_data *host_data = dev_get_drvdata(dev); 663 struct stm32_exti_chip_data *chip_data; 664 int i; 665 666 for (i = 0; i < host_data->drv_data->bank_nr; i++) { 667 chip_data = &host_data->chips_data[i]; 668 stm32_chip_resume(chip_data, chip_data->mask_cache); 669 } 670 671 return 0; 672 } 673 674 static int stm32_exti_h_retrigger(struct irq_data *d) 675 { 676 struct stm32_exti_chip_data *chip_data = irq_data_get_irq_chip_data(d); 677 const struct stm32_exti_bank *stm32_bank = chip_data->reg_bank; 678 void __iomem *base = chip_data->host_data->base; 679 u32 mask = BIT(d->hwirq % IRQS_PER_BANK); 680 681 writel_relaxed(mask, base + stm32_bank->swier_ofst); 682 683 return 0; 684 } 685 686 static struct irq_chip stm32_exti_h_chip = { 687 .name = "stm32-exti-h", 688 .irq_eoi = stm32_exti_h_eoi, 689 .irq_mask = stm32_exti_h_mask, 690 .irq_unmask = stm32_exti_h_unmask, 691 .irq_retrigger = stm32_exti_h_retrigger, 692 .irq_set_type = stm32_exti_h_set_type, 693 .irq_set_wake = stm32_exti_h_set_wake, 694 .flags = IRQCHIP_MASK_ON_SUSPEND, 695 .irq_set_affinity = IS_ENABLED(CONFIG_SMP) ? stm32_exti_h_set_affinity : NULL, 696 }; 697 698 static struct irq_chip stm32_exti_h_chip_direct = { 699 .name = "stm32-exti-h-direct", 700 .irq_eoi = irq_chip_eoi_parent, 701 .irq_ack = irq_chip_ack_parent, 702 .irq_mask = stm32_exti_h_mask, 703 .irq_unmask = stm32_exti_h_unmask, 704 .irq_retrigger = irq_chip_retrigger_hierarchy, 705 .irq_set_type = irq_chip_set_type_parent, 706 .irq_set_wake = stm32_exti_h_set_wake, 707 .flags = IRQCHIP_MASK_ON_SUSPEND, 708 .irq_set_affinity = IS_ENABLED(CONFIG_SMP) ? irq_chip_set_affinity_parent : NULL, 709 }; 710 711 static int stm32_exti_h_domain_alloc(struct irq_domain *dm, 712 unsigned int virq, 713 unsigned int nr_irqs, void *data) 714 { 715 struct stm32_exti_host_data *host_data = dm->host_data; 716 struct stm32_exti_chip_data *chip_data; 717 u8 desc_irq; 718 struct irq_fwspec *fwspec = data; 719 struct irq_fwspec p_fwspec; 720 irq_hw_number_t hwirq; 721 int bank; 722 u32 event_trg; 723 struct irq_chip *chip; 724 725 hwirq = fwspec->param[0]; 726 if (hwirq >= host_data->drv_data->bank_nr * IRQS_PER_BANK) 727 return -EINVAL; 728 729 bank = hwirq / IRQS_PER_BANK; 730 chip_data = &host_data->chips_data[bank]; 731 732 /* Check if event is reserved (Secure) */ 733 if (chip_data->event_reserved & BIT(hwirq % IRQS_PER_BANK)) { 734 dev_err(host_data->dev, "event %lu is reserved, secure\n", hwirq); 735 return -EPERM; 736 } 737 738 event_trg = readl_relaxed(host_data->base + chip_data->reg_bank->trg_ofst); 739 chip = (event_trg & BIT(hwirq % IRQS_PER_BANK)) ? 740 &stm32_exti_h_chip : &stm32_exti_h_chip_direct; 741 742 irq_domain_set_hwirq_and_chip(dm, virq, hwirq, chip, chip_data); 743 744 if (host_data->dt_has_irqs_desc) { 745 struct of_phandle_args out_irq; 746 int ret; 747 748 ret = of_irq_parse_one(host_data->dev->of_node, hwirq, &out_irq); 749 if (ret) 750 return ret; 751 /* we only support one parent, so far */ 752 if (of_node_to_fwnode(out_irq.np) != dm->parent->fwnode) 753 return -EINVAL; 754 755 of_phandle_args_to_fwspec(out_irq.np, out_irq.args, 756 out_irq.args_count, &p_fwspec); 757 758 return irq_domain_alloc_irqs_parent(dm, virq, 1, &p_fwspec); 759 } 760 761 if (!host_data->drv_data->desc_irqs) 762 return -EINVAL; 763 764 desc_irq = host_data->drv_data->desc_irqs[hwirq]; 765 if (desc_irq != EXTI_INVALID_IRQ) { 766 p_fwspec.fwnode = dm->parent->fwnode; 767 p_fwspec.param_count = 3; 768 p_fwspec.param[0] = GIC_SPI; 769 p_fwspec.param[1] = desc_irq; 770 p_fwspec.param[2] = IRQ_TYPE_LEVEL_HIGH; 771 772 return irq_domain_alloc_irqs_parent(dm, virq, 1, &p_fwspec); 773 } 774 775 return 0; 776 } 777 778 static struct 779 stm32_exti_host_data *stm32_exti_host_init(const struct stm32_exti_drv_data *dd, 780 struct device_node *node) 781 { 782 struct stm32_exti_host_data *host_data; 783 784 host_data = kzalloc(sizeof(*host_data), GFP_KERNEL); 785 if (!host_data) 786 return NULL; 787 788 host_data->drv_data = dd; 789 host_data->chips_data = kcalloc(dd->bank_nr, 790 sizeof(struct stm32_exti_chip_data), 791 GFP_KERNEL); 792 if (!host_data->chips_data) 793 goto free_host_data; 794 795 host_data->base = of_iomap(node, 0); 796 if (!host_data->base) { 797 pr_err("%pOF: Unable to map registers\n", node); 798 goto free_chips_data; 799 } 800 801 return host_data; 802 803 free_chips_data: 804 kfree(host_data->chips_data); 805 free_host_data: 806 kfree(host_data); 807 808 return NULL; 809 } 810 811 static struct 812 stm32_exti_chip_data *stm32_exti_chip_init(struct stm32_exti_host_data *h_data, 813 u32 bank_idx, 814 struct device_node *node) 815 { 816 const struct stm32_exti_bank *stm32_bank; 817 struct stm32_exti_chip_data *chip_data; 818 void __iomem *base = h_data->base; 819 820 stm32_bank = h_data->drv_data->exti_banks[bank_idx]; 821 chip_data = &h_data->chips_data[bank_idx]; 822 chip_data->host_data = h_data; 823 chip_data->reg_bank = stm32_bank; 824 825 raw_spin_lock_init(&chip_data->rlock); 826 827 /* 828 * This IP has no reset, so after hot reboot we should 829 * clear registers to avoid residue 830 */ 831 writel_relaxed(0, base + stm32_bank->imr_ofst); 832 if (stm32_bank->emr_ofst != UNDEF_REG) 833 writel_relaxed(0, base + stm32_bank->emr_ofst); 834 835 /* reserve Secure events */ 836 if (stm32_bank->seccfgr_ofst != UNDEF_REG) 837 chip_data->event_reserved = readl_relaxed(base + stm32_bank->seccfgr_ofst); 838 839 pr_info("%pOF: bank%d\n", node, bank_idx); 840 841 return chip_data; 842 } 843 844 static int __init stm32_exti_init(const struct stm32_exti_drv_data *drv_data, 845 struct device_node *node) 846 { 847 struct stm32_exti_host_data *host_data; 848 unsigned int clr = IRQ_NOREQUEST | IRQ_NOPROBE | IRQ_NOAUTOEN; 849 int nr_irqs, ret, i; 850 struct irq_chip_generic *gc; 851 struct irq_domain *domain; 852 853 host_data = stm32_exti_host_init(drv_data, node); 854 if (!host_data) 855 return -ENOMEM; 856 857 domain = irq_domain_add_linear(node, drv_data->bank_nr * IRQS_PER_BANK, 858 &irq_exti_domain_ops, NULL); 859 if (!domain) { 860 pr_err("%pOFn: Could not register interrupt domain.\n", 861 node); 862 ret = -ENOMEM; 863 goto out_unmap; 864 } 865 866 ret = irq_alloc_domain_generic_chips(domain, IRQS_PER_BANK, 1, "exti", 867 handle_edge_irq, clr, 0, 0); 868 if (ret) { 869 pr_err("%pOF: Could not allocate generic interrupt chip.\n", 870 node); 871 goto out_free_domain; 872 } 873 874 for (i = 0; i < drv_data->bank_nr; i++) { 875 const struct stm32_exti_bank *stm32_bank; 876 struct stm32_exti_chip_data *chip_data; 877 878 stm32_bank = drv_data->exti_banks[i]; 879 chip_data = stm32_exti_chip_init(host_data, i, node); 880 881 gc = irq_get_domain_generic_chip(domain, i * IRQS_PER_BANK); 882 883 gc->reg_base = host_data->base; 884 gc->chip_types->type = IRQ_TYPE_EDGE_BOTH; 885 gc->chip_types->chip.irq_ack = stm32_irq_ack; 886 gc->chip_types->chip.irq_mask = irq_gc_mask_clr_bit; 887 gc->chip_types->chip.irq_unmask = irq_gc_mask_set_bit; 888 gc->chip_types->chip.irq_set_type = stm32_irq_set_type; 889 gc->chip_types->chip.irq_set_wake = irq_gc_set_wake; 890 gc->suspend = stm32_irq_suspend; 891 gc->resume = stm32_irq_resume; 892 gc->wake_enabled = IRQ_MSK(IRQS_PER_BANK); 893 894 gc->chip_types->regs.mask = stm32_bank->imr_ofst; 895 gc->private = (void *)chip_data; 896 } 897 898 nr_irqs = of_irq_count(node); 899 for (i = 0; i < nr_irqs; i++) { 900 unsigned int irq = irq_of_parse_and_map(node, i); 901 902 irq_set_handler_data(irq, domain); 903 irq_set_chained_handler(irq, stm32_irq_handler); 904 } 905 906 return 0; 907 908 out_free_domain: 909 irq_domain_remove(domain); 910 out_unmap: 911 iounmap(host_data->base); 912 kfree(host_data->chips_data); 913 kfree(host_data); 914 return ret; 915 } 916 917 static const struct irq_domain_ops stm32_exti_h_domain_ops = { 918 .alloc = stm32_exti_h_domain_alloc, 919 .free = irq_domain_free_irqs_common, 920 .xlate = irq_domain_xlate_twocell, 921 }; 922 923 static void stm32_exti_check_rif(struct stm32_exti_host_data *host_data) 924 { 925 unsigned int bank, i, event; 926 u32 cid, cidcfgr, hwcfgr1; 927 928 /* quit on CID not supported */ 929 hwcfgr1 = readl_relaxed(host_data->base + EXTI_HWCFGR1); 930 if ((hwcfgr1 & EXTI_HWCFGR1_CIDWIDTH_MASK) == 0) 931 return; 932 933 for (bank = 0; bank < host_data->drv_data->bank_nr; bank++) { 934 for (i = 0; i < IRQS_PER_BANK; i++) { 935 event = bank * IRQS_PER_BANK + i; 936 cidcfgr = readl_relaxed(host_data->base + EXTI_EnCIDCFGR(event)); 937 cid = (cidcfgr & EXTI_CIDCFGR_CID_MASK) >> EXTI_CIDCFGR_CID_SHIFT; 938 if ((cidcfgr & EXTI_CIDCFGR_CFEN_MASK) && cid != EXTI_CID1) 939 host_data->chips_data[bank].event_reserved |= BIT(i); 940 } 941 } 942 } 943 944 static void stm32_exti_remove_irq(void *data) 945 { 946 struct irq_domain *domain = data; 947 948 irq_domain_remove(domain); 949 } 950 951 static int stm32_exti_probe(struct platform_device *pdev) 952 { 953 int ret, i; 954 struct device *dev = &pdev->dev; 955 struct device_node *np = dev->of_node; 956 struct irq_domain *parent_domain, *domain; 957 struct stm32_exti_host_data *host_data; 958 const struct stm32_exti_drv_data *drv_data; 959 960 host_data = devm_kzalloc(dev, sizeof(*host_data), GFP_KERNEL); 961 if (!host_data) 962 return -ENOMEM; 963 964 dev_set_drvdata(dev, host_data); 965 host_data->dev = dev; 966 967 /* check for optional hwspinlock which may be not available yet */ 968 ret = of_hwspin_lock_get_id(np, 0); 969 if (ret == -EPROBE_DEFER) 970 /* hwspinlock framework not yet ready */ 971 return ret; 972 973 if (ret >= 0) { 974 host_data->hwlock = devm_hwspin_lock_request_specific(dev, ret); 975 if (!host_data->hwlock) { 976 dev_err(dev, "Failed to request hwspinlock\n"); 977 return -EINVAL; 978 } 979 } else if (ret != -ENOENT) { 980 /* note: ENOENT is a valid case (means 'no hwspinlock') */ 981 dev_err(dev, "Failed to get hwspinlock\n"); 982 return ret; 983 } 984 985 /* initialize host_data */ 986 drv_data = of_device_get_match_data(dev); 987 if (!drv_data) { 988 dev_err(dev, "no of match data\n"); 989 return -ENODEV; 990 } 991 host_data->drv_data = drv_data; 992 993 host_data->chips_data = devm_kcalloc(dev, drv_data->bank_nr, 994 sizeof(*host_data->chips_data), 995 GFP_KERNEL); 996 if (!host_data->chips_data) 997 return -ENOMEM; 998 999 host_data->base = devm_platform_ioremap_resource(pdev, 0); 1000 if (IS_ERR(host_data->base)) 1001 return PTR_ERR(host_data->base); 1002 1003 for (i = 0; i < drv_data->bank_nr; i++) 1004 stm32_exti_chip_init(host_data, i, np); 1005 1006 stm32_exti_check_rif(host_data); 1007 1008 parent_domain = irq_find_host(of_irq_find_parent(np)); 1009 if (!parent_domain) { 1010 dev_err(dev, "GIC interrupt-parent not found\n"); 1011 return -EINVAL; 1012 } 1013 1014 domain = irq_domain_add_hierarchy(parent_domain, 0, 1015 drv_data->bank_nr * IRQS_PER_BANK, 1016 np, &stm32_exti_h_domain_ops, 1017 host_data); 1018 1019 if (!domain) { 1020 dev_err(dev, "Could not register exti domain\n"); 1021 return -ENOMEM; 1022 } 1023 1024 ret = devm_add_action_or_reset(dev, stm32_exti_remove_irq, domain); 1025 if (ret) 1026 return ret; 1027 1028 if (of_property_read_bool(np, "interrupts-extended")) 1029 host_data->dt_has_irqs_desc = true; 1030 1031 return 0; 1032 } 1033 1034 /* platform driver only for MP1 */ 1035 static const struct of_device_id stm32_exti_ids[] = { 1036 { .compatible = "st,stm32mp1-exti", .data = &stm32mp1_drv_data}, 1037 { .compatible = "st,stm32mp13-exti", .data = &stm32mp13_drv_data}, 1038 {}, 1039 }; 1040 MODULE_DEVICE_TABLE(of, stm32_exti_ids); 1041 1042 static const struct dev_pm_ops stm32_exti_dev_pm_ops = { 1043 NOIRQ_SYSTEM_SLEEP_PM_OPS(stm32_exti_h_suspend, stm32_exti_h_resume) 1044 }; 1045 1046 static struct platform_driver stm32_exti_driver = { 1047 .probe = stm32_exti_probe, 1048 .driver = { 1049 .name = "stm32_exti", 1050 .of_match_table = stm32_exti_ids, 1051 .pm = &stm32_exti_dev_pm_ops, 1052 }, 1053 }; 1054 1055 static int __init stm32_exti_arch_init(void) 1056 { 1057 return platform_driver_register(&stm32_exti_driver); 1058 } 1059 1060 static void __exit stm32_exti_arch_exit(void) 1061 { 1062 return platform_driver_unregister(&stm32_exti_driver); 1063 } 1064 1065 arch_initcall(stm32_exti_arch_init); 1066 module_exit(stm32_exti_arch_exit); 1067 1068 /* no platform driver for F4 and H7 */ 1069 static int __init stm32f4_exti_of_init(struct device_node *np, 1070 struct device_node *parent) 1071 { 1072 return stm32_exti_init(&stm32f4xx_drv_data, np); 1073 } 1074 1075 IRQCHIP_DECLARE(stm32f4_exti, "st,stm32-exti", stm32f4_exti_of_init); 1076 1077 static int __init stm32h7_exti_of_init(struct device_node *np, 1078 struct device_node *parent) 1079 { 1080 return stm32_exti_init(&stm32h7xx_drv_data, np); 1081 } 1082 1083 IRQCHIP_DECLARE(stm32h7_exti, "st,stm32h7-exti", stm32h7_exti_of_init); 1084