1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (C) 2017 SiFive 4 * Copyright (C) 2018 Christoph Hellwig 5 */ 6 #define pr_fmt(fmt) "riscv-plic: " fmt 7 #include <linux/cpu.h> 8 #include <linux/interrupt.h> 9 #include <linux/io.h> 10 #include <linux/irq.h> 11 #include <linux/irqchip.h> 12 #include <linux/irqchip/chained_irq.h> 13 #include <linux/irqdomain.h> 14 #include <linux/module.h> 15 #include <linux/of.h> 16 #include <linux/of_address.h> 17 #include <linux/of_irq.h> 18 #include <linux/platform_device.h> 19 #include <linux/spinlock.h> 20 #include <linux/syscore_ops.h> 21 #include <asm/smp.h> 22 23 /* 24 * This driver implements a version of the RISC-V PLIC with the actual layout 25 * specified in chapter 8 of the SiFive U5 Coreplex Series Manual: 26 * 27 * https://static.dev.sifive.com/U54-MC-RVCoreIP.pdf 28 * 29 * The largest number supported by devices marked as 'sifive,plic-1.0.0', is 30 * 1024, of which device 0 is defined as non-existent by the RISC-V Privileged 31 * Spec. 32 */ 33 34 #define MAX_DEVICES 1024 35 #define MAX_CONTEXTS 15872 36 37 /* 38 * Each interrupt source has a priority register associated with it. 39 * We always hardwire it to one in Linux. 40 */ 41 #define PRIORITY_BASE 0 42 #define PRIORITY_PER_ID 4 43 44 /* 45 * Each hart context has a vector of interrupt enable bits associated with it. 46 * There's one bit for each interrupt source. 47 */ 48 #define CONTEXT_ENABLE_BASE 0x2000 49 #define CONTEXT_ENABLE_SIZE 0x80 50 51 /* 52 * Each hart context has a set of control registers associated with it. Right 53 * now there's only two: a source priority threshold over which the hart will 54 * take an interrupt, and a register to claim interrupts. 55 */ 56 #define CONTEXT_BASE 0x200000 57 #define CONTEXT_SIZE 0x1000 58 #define CONTEXT_THRESHOLD 0x00 59 #define CONTEXT_CLAIM 0x04 60 61 #define PLIC_DISABLE_THRESHOLD 0x7 62 #define PLIC_ENABLE_THRESHOLD 0 63 64 #define PLIC_QUIRK_EDGE_INTERRUPT 0 65 66 struct plic_priv { 67 struct fwnode_handle *fwnode; 68 struct cpumask lmask; 69 struct irq_domain *irqdomain; 70 void __iomem *regs; 71 unsigned long plic_quirks; 72 unsigned int nr_irqs; 73 unsigned long *prio_save; 74 }; 75 76 struct plic_handler { 77 bool present; 78 void __iomem *hart_base; 79 /* 80 * Protect mask operations on the registers given that we can't 81 * assume atomic memory operations work on them. 82 */ 83 raw_spinlock_t enable_lock; 84 void __iomem *enable_base; 85 u32 *enable_save; 86 struct plic_priv *priv; 87 }; 88 static int plic_parent_irq __ro_after_init; 89 static bool plic_global_setup_done __ro_after_init; 90 static DEFINE_PER_CPU(struct plic_handler, plic_handlers); 91 92 static int plic_irq_set_type(struct irq_data *d, unsigned int type); 93 94 static void __plic_toggle(void __iomem *enable_base, int hwirq, int enable) 95 { 96 u32 __iomem *reg = enable_base + (hwirq / 32) * sizeof(u32); 97 u32 hwirq_mask = 1 << (hwirq % 32); 98 99 if (enable) 100 writel(readl(reg) | hwirq_mask, reg); 101 else 102 writel(readl(reg) & ~hwirq_mask, reg); 103 } 104 105 static void plic_toggle(struct plic_handler *handler, int hwirq, int enable) 106 { 107 unsigned long flags; 108 109 raw_spin_lock_irqsave(&handler->enable_lock, flags); 110 __plic_toggle(handler->enable_base, hwirq, enable); 111 raw_spin_unlock_irqrestore(&handler->enable_lock, flags); 112 } 113 114 static inline void plic_irq_toggle(const struct cpumask *mask, 115 struct irq_data *d, int enable) 116 { 117 int cpu; 118 119 for_each_cpu(cpu, mask) { 120 struct plic_handler *handler = per_cpu_ptr(&plic_handlers, cpu); 121 122 plic_toggle(handler, d->hwirq, enable); 123 } 124 } 125 126 static void plic_irq_enable(struct irq_data *d) 127 { 128 plic_irq_toggle(irq_data_get_effective_affinity_mask(d), d, 1); 129 } 130 131 static void plic_irq_disable(struct irq_data *d) 132 { 133 plic_irq_toggle(irq_data_get_effective_affinity_mask(d), d, 0); 134 } 135 136 static void plic_irq_unmask(struct irq_data *d) 137 { 138 struct plic_priv *priv = irq_data_get_irq_chip_data(d); 139 140 writel(1, priv->regs + PRIORITY_BASE + d->hwirq * PRIORITY_PER_ID); 141 } 142 143 static void plic_irq_mask(struct irq_data *d) 144 { 145 struct plic_priv *priv = irq_data_get_irq_chip_data(d); 146 147 writel(0, priv->regs + PRIORITY_BASE + d->hwirq * PRIORITY_PER_ID); 148 } 149 150 static void plic_irq_eoi(struct irq_data *d) 151 { 152 struct plic_handler *handler = this_cpu_ptr(&plic_handlers); 153 154 if (unlikely(irqd_irq_disabled(d))) { 155 plic_toggle(handler, d->hwirq, 1); 156 writel(d->hwirq, handler->hart_base + CONTEXT_CLAIM); 157 plic_toggle(handler, d->hwirq, 0); 158 } else { 159 writel(d->hwirq, handler->hart_base + CONTEXT_CLAIM); 160 } 161 } 162 163 #ifdef CONFIG_SMP 164 static int plic_set_affinity(struct irq_data *d, 165 const struct cpumask *mask_val, bool force) 166 { 167 unsigned int cpu; 168 struct plic_priv *priv = irq_data_get_irq_chip_data(d); 169 170 if (force) 171 cpu = cpumask_first_and(&priv->lmask, mask_val); 172 else 173 cpu = cpumask_first_and_and(&priv->lmask, mask_val, cpu_online_mask); 174 175 if (cpu >= nr_cpu_ids) 176 return -EINVAL; 177 178 plic_irq_disable(d); 179 180 irq_data_update_effective_affinity(d, cpumask_of(cpu)); 181 182 if (!irqd_irq_disabled(d)) 183 plic_irq_enable(d); 184 185 return IRQ_SET_MASK_OK_DONE; 186 } 187 #endif 188 189 static struct irq_chip plic_edge_chip = { 190 .name = "SiFive PLIC", 191 .irq_enable = plic_irq_enable, 192 .irq_disable = plic_irq_disable, 193 .irq_ack = plic_irq_eoi, 194 .irq_mask = plic_irq_mask, 195 .irq_unmask = plic_irq_unmask, 196 #ifdef CONFIG_SMP 197 .irq_set_affinity = plic_set_affinity, 198 #endif 199 .irq_set_type = plic_irq_set_type, 200 .flags = IRQCHIP_SKIP_SET_WAKE | 201 IRQCHIP_AFFINITY_PRE_STARTUP, 202 }; 203 204 static struct irq_chip plic_chip = { 205 .name = "SiFive PLIC", 206 .irq_enable = plic_irq_enable, 207 .irq_disable = plic_irq_disable, 208 .irq_mask = plic_irq_mask, 209 .irq_unmask = plic_irq_unmask, 210 .irq_eoi = plic_irq_eoi, 211 #ifdef CONFIG_SMP 212 .irq_set_affinity = plic_set_affinity, 213 #endif 214 .irq_set_type = plic_irq_set_type, 215 .flags = IRQCHIP_SKIP_SET_WAKE | 216 IRQCHIP_AFFINITY_PRE_STARTUP, 217 }; 218 219 static int plic_irq_set_type(struct irq_data *d, unsigned int type) 220 { 221 struct plic_priv *priv = irq_data_get_irq_chip_data(d); 222 223 if (!test_bit(PLIC_QUIRK_EDGE_INTERRUPT, &priv->plic_quirks)) 224 return IRQ_SET_MASK_OK_NOCOPY; 225 226 switch (type) { 227 case IRQ_TYPE_EDGE_RISING: 228 irq_set_chip_handler_name_locked(d, &plic_edge_chip, 229 handle_edge_irq, NULL); 230 break; 231 case IRQ_TYPE_LEVEL_HIGH: 232 irq_set_chip_handler_name_locked(d, &plic_chip, 233 handle_fasteoi_irq, NULL); 234 break; 235 default: 236 return -EINVAL; 237 } 238 239 return IRQ_SET_MASK_OK; 240 } 241 242 static int plic_irq_suspend(void) 243 { 244 unsigned int i, cpu; 245 unsigned long flags; 246 u32 __iomem *reg; 247 struct plic_priv *priv; 248 249 priv = per_cpu_ptr(&plic_handlers, smp_processor_id())->priv; 250 251 for (i = 0; i < priv->nr_irqs; i++) 252 if (readl(priv->regs + PRIORITY_BASE + i * PRIORITY_PER_ID)) 253 __set_bit(i, priv->prio_save); 254 else 255 __clear_bit(i, priv->prio_save); 256 257 for_each_cpu(cpu, cpu_present_mask) { 258 struct plic_handler *handler = per_cpu_ptr(&plic_handlers, cpu); 259 260 if (!handler->present) 261 continue; 262 263 raw_spin_lock_irqsave(&handler->enable_lock, flags); 264 for (i = 0; i < DIV_ROUND_UP(priv->nr_irqs, 32); i++) { 265 reg = handler->enable_base + i * sizeof(u32); 266 handler->enable_save[i] = readl(reg); 267 } 268 raw_spin_unlock_irqrestore(&handler->enable_lock, flags); 269 } 270 271 return 0; 272 } 273 274 static void plic_irq_resume(void) 275 { 276 unsigned int i, index, cpu; 277 unsigned long flags; 278 u32 __iomem *reg; 279 struct plic_priv *priv; 280 281 priv = per_cpu_ptr(&plic_handlers, smp_processor_id())->priv; 282 283 for (i = 0; i < priv->nr_irqs; i++) { 284 index = BIT_WORD(i); 285 writel((priv->prio_save[index] & BIT_MASK(i)) ? 1 : 0, 286 priv->regs + PRIORITY_BASE + i * PRIORITY_PER_ID); 287 } 288 289 for_each_cpu(cpu, cpu_present_mask) { 290 struct plic_handler *handler = per_cpu_ptr(&plic_handlers, cpu); 291 292 if (!handler->present) 293 continue; 294 295 raw_spin_lock_irqsave(&handler->enable_lock, flags); 296 for (i = 0; i < DIV_ROUND_UP(priv->nr_irqs, 32); i++) { 297 reg = handler->enable_base + i * sizeof(u32); 298 writel(handler->enable_save[i], reg); 299 } 300 raw_spin_unlock_irqrestore(&handler->enable_lock, flags); 301 } 302 } 303 304 static struct syscore_ops plic_irq_syscore_ops = { 305 .suspend = plic_irq_suspend, 306 .resume = plic_irq_resume, 307 }; 308 309 static int plic_irqdomain_map(struct irq_domain *d, unsigned int irq, 310 irq_hw_number_t hwirq) 311 { 312 struct plic_priv *priv = d->host_data; 313 314 irq_domain_set_info(d, irq, hwirq, &plic_chip, d->host_data, 315 handle_fasteoi_irq, NULL, NULL); 316 irq_set_noprobe(irq); 317 irq_set_affinity(irq, &priv->lmask); 318 return 0; 319 } 320 321 static int plic_irq_domain_translate(struct irq_domain *d, 322 struct irq_fwspec *fwspec, 323 unsigned long *hwirq, 324 unsigned int *type) 325 { 326 struct plic_priv *priv = d->host_data; 327 328 if (test_bit(PLIC_QUIRK_EDGE_INTERRUPT, &priv->plic_quirks)) 329 return irq_domain_translate_twocell(d, fwspec, hwirq, type); 330 331 return irq_domain_translate_onecell(d, fwspec, hwirq, type); 332 } 333 334 static int plic_irq_domain_alloc(struct irq_domain *domain, unsigned int virq, 335 unsigned int nr_irqs, void *arg) 336 { 337 int i, ret; 338 irq_hw_number_t hwirq; 339 unsigned int type; 340 struct irq_fwspec *fwspec = arg; 341 342 ret = plic_irq_domain_translate(domain, fwspec, &hwirq, &type); 343 if (ret) 344 return ret; 345 346 for (i = 0; i < nr_irqs; i++) { 347 ret = plic_irqdomain_map(domain, virq + i, hwirq + i); 348 if (ret) 349 return ret; 350 } 351 352 return 0; 353 } 354 355 static const struct irq_domain_ops plic_irqdomain_ops = { 356 .translate = plic_irq_domain_translate, 357 .alloc = plic_irq_domain_alloc, 358 .free = irq_domain_free_irqs_top, 359 }; 360 361 /* 362 * Handling an interrupt is a two-step process: first you claim the interrupt 363 * by reading the claim register, then you complete the interrupt by writing 364 * that source ID back to the same claim register. This automatically enables 365 * and disables the interrupt, so there's nothing else to do. 366 */ 367 static void plic_handle_irq(struct irq_desc *desc) 368 { 369 struct plic_handler *handler = this_cpu_ptr(&plic_handlers); 370 struct irq_chip *chip = irq_desc_get_chip(desc); 371 void __iomem *claim = handler->hart_base + CONTEXT_CLAIM; 372 irq_hw_number_t hwirq; 373 374 WARN_ON_ONCE(!handler->present); 375 376 chained_irq_enter(chip, desc); 377 378 while ((hwirq = readl(claim))) { 379 int err = generic_handle_domain_irq(handler->priv->irqdomain, 380 hwirq); 381 if (unlikely(err)) { 382 pr_warn_ratelimited("%pfwP: can't find mapping for hwirq %lu\n", 383 handler->priv->fwnode, hwirq); 384 } 385 } 386 387 chained_irq_exit(chip, desc); 388 } 389 390 static void plic_set_threshold(struct plic_handler *handler, u32 threshold) 391 { 392 /* priority must be > threshold to trigger an interrupt */ 393 writel(threshold, handler->hart_base + CONTEXT_THRESHOLD); 394 } 395 396 static int plic_dying_cpu(unsigned int cpu) 397 { 398 if (plic_parent_irq) 399 disable_percpu_irq(plic_parent_irq); 400 401 return 0; 402 } 403 404 static int plic_starting_cpu(unsigned int cpu) 405 { 406 struct plic_handler *handler = this_cpu_ptr(&plic_handlers); 407 408 if (plic_parent_irq) 409 enable_percpu_irq(plic_parent_irq, 410 irq_get_trigger_type(plic_parent_irq)); 411 else 412 pr_warn("%pfwP: cpu%d: parent irq not available\n", 413 handler->priv->fwnode, cpu); 414 plic_set_threshold(handler, PLIC_ENABLE_THRESHOLD); 415 416 return 0; 417 } 418 419 static const struct of_device_id plic_match[] = { 420 { .compatible = "sifive,plic-1.0.0" }, 421 { .compatible = "riscv,plic0" }, 422 { .compatible = "andestech,nceplic100", 423 .data = (const void *)BIT(PLIC_QUIRK_EDGE_INTERRUPT) }, 424 { .compatible = "thead,c900-plic", 425 .data = (const void *)BIT(PLIC_QUIRK_EDGE_INTERRUPT) }, 426 {} 427 }; 428 429 static int plic_parse_nr_irqs_and_contexts(struct fwnode_handle *fwnode, 430 u32 *nr_irqs, u32 *nr_contexts) 431 { 432 int rc; 433 434 /* 435 * Currently, only OF fwnode is supported so extend this 436 * function for ACPI support. 437 */ 438 if (!is_of_node(fwnode)) 439 return -EINVAL; 440 441 rc = of_property_read_u32(to_of_node(fwnode), "riscv,ndev", nr_irqs); 442 if (rc) { 443 pr_err("%pfwP: riscv,ndev property not available\n", fwnode); 444 return rc; 445 } 446 447 *nr_contexts = of_irq_count(to_of_node(fwnode)); 448 if (WARN_ON(!(*nr_contexts))) { 449 pr_err("%pfwP: no PLIC context available\n", fwnode); 450 return -EINVAL; 451 } 452 453 return 0; 454 } 455 456 static int plic_parse_context_parent(struct fwnode_handle *fwnode, u32 context, 457 u32 *parent_hwirq, int *parent_cpu) 458 { 459 struct of_phandle_args parent; 460 unsigned long hartid; 461 int rc; 462 463 /* 464 * Currently, only OF fwnode is supported so extend this 465 * function for ACPI support. 466 */ 467 if (!is_of_node(fwnode)) 468 return -EINVAL; 469 470 rc = of_irq_parse_one(to_of_node(fwnode), context, &parent); 471 if (rc) 472 return rc; 473 474 rc = riscv_of_parent_hartid(parent.np, &hartid); 475 if (rc) 476 return rc; 477 478 *parent_hwirq = parent.args[0]; 479 *parent_cpu = riscv_hartid_to_cpuid(hartid); 480 return 0; 481 } 482 483 static int plic_probe(struct fwnode_handle *fwnode) 484 { 485 int error = 0, nr_contexts, nr_handlers = 0, cpu, i; 486 unsigned long plic_quirks = 0; 487 struct plic_handler *handler; 488 u32 nr_irqs, parent_hwirq; 489 struct plic_priv *priv; 490 irq_hw_number_t hwirq; 491 void __iomem *regs; 492 493 if (is_of_node(fwnode)) { 494 const struct of_device_id *id; 495 496 id = of_match_node(plic_match, to_of_node(fwnode)); 497 if (id) 498 plic_quirks = (unsigned long)id->data; 499 500 regs = of_iomap(to_of_node(fwnode), 0); 501 if (!regs) 502 return -ENOMEM; 503 } else { 504 return -ENODEV; 505 } 506 507 error = plic_parse_nr_irqs_and_contexts(fwnode, &nr_irqs, &nr_contexts); 508 if (error) 509 goto fail_free_regs; 510 511 priv = kzalloc(sizeof(*priv), GFP_KERNEL); 512 if (!priv) { 513 error = -ENOMEM; 514 goto fail_free_regs; 515 } 516 517 priv->fwnode = fwnode; 518 priv->plic_quirks = plic_quirks; 519 priv->nr_irqs = nr_irqs; 520 priv->regs = regs; 521 522 priv->prio_save = bitmap_zalloc(nr_irqs, GFP_KERNEL); 523 if (!priv->prio_save) { 524 error = -ENOMEM; 525 goto fail_free_priv; 526 } 527 528 for (i = 0; i < nr_contexts; i++) { 529 error = plic_parse_context_parent(fwnode, i, &parent_hwirq, &cpu); 530 if (error) { 531 pr_warn("%pfwP: hwirq for context%d not found\n", fwnode, i); 532 continue; 533 } 534 535 /* 536 * Skip contexts other than external interrupts for our 537 * privilege level. 538 */ 539 if (parent_hwirq != RV_IRQ_EXT) { 540 /* Disable S-mode enable bits if running in M-mode. */ 541 if (IS_ENABLED(CONFIG_RISCV_M_MODE)) { 542 void __iomem *enable_base = priv->regs + 543 CONTEXT_ENABLE_BASE + 544 i * CONTEXT_ENABLE_SIZE; 545 546 for (hwirq = 1; hwirq <= nr_irqs; hwirq++) 547 __plic_toggle(enable_base, hwirq, 0); 548 } 549 continue; 550 } 551 552 if (cpu < 0) { 553 pr_warn("%pfwP: Invalid cpuid for context %d\n", fwnode, i); 554 continue; 555 } 556 557 /* 558 * When running in M-mode we need to ignore the S-mode handler. 559 * Here we assume it always comes later, but that might be a 560 * little fragile. 561 */ 562 handler = per_cpu_ptr(&plic_handlers, cpu); 563 if (handler->present) { 564 pr_warn("%pfwP: handler already present for context %d.\n", fwnode, i); 565 plic_set_threshold(handler, PLIC_DISABLE_THRESHOLD); 566 goto done; 567 } 568 569 cpumask_set_cpu(cpu, &priv->lmask); 570 handler->present = true; 571 handler->hart_base = priv->regs + CONTEXT_BASE + 572 i * CONTEXT_SIZE; 573 raw_spin_lock_init(&handler->enable_lock); 574 handler->enable_base = priv->regs + CONTEXT_ENABLE_BASE + 575 i * CONTEXT_ENABLE_SIZE; 576 handler->priv = priv; 577 578 handler->enable_save = kcalloc(DIV_ROUND_UP(nr_irqs, 32), 579 sizeof(*handler->enable_save), GFP_KERNEL); 580 if (!handler->enable_save) 581 goto fail_cleanup_contexts; 582 done: 583 for (hwirq = 1; hwirq <= nr_irqs; hwirq++) { 584 plic_toggle(handler, hwirq, 0); 585 writel(1, priv->regs + PRIORITY_BASE + 586 hwirq * PRIORITY_PER_ID); 587 } 588 nr_handlers++; 589 } 590 591 priv->irqdomain = irq_domain_add_linear(to_of_node(fwnode), nr_irqs + 1, 592 &plic_irqdomain_ops, priv); 593 if (WARN_ON(!priv->irqdomain)) 594 goto fail_cleanup_contexts; 595 596 /* 597 * We can have multiple PLIC instances so setup global state 598 * and register syscore operations only once after context 599 * handlers of all online CPUs are initialized. 600 */ 601 if (!plic_global_setup_done) { 602 struct irq_domain *domain; 603 bool global_setup = true; 604 605 for_each_online_cpu(cpu) { 606 handler = per_cpu_ptr(&plic_handlers, cpu); 607 if (!handler->present) { 608 global_setup = false; 609 break; 610 } 611 } 612 613 if (global_setup) { 614 /* Find parent domain and register chained handler */ 615 domain = irq_find_matching_fwnode(riscv_get_intc_hwnode(), DOMAIN_BUS_ANY); 616 if (domain) 617 plic_parent_irq = irq_create_mapping(domain, RV_IRQ_EXT); 618 if (plic_parent_irq) 619 irq_set_chained_handler(plic_parent_irq, plic_handle_irq); 620 621 cpuhp_setup_state(CPUHP_AP_IRQ_SIFIVE_PLIC_STARTING, 622 "irqchip/sifive/plic:starting", 623 plic_starting_cpu, plic_dying_cpu); 624 register_syscore_ops(&plic_irq_syscore_ops); 625 plic_global_setup_done = true; 626 } 627 } 628 629 pr_info("%pfwP: mapped %d interrupts with %d handlers for %d contexts.\n", 630 fwnode, nr_irqs, nr_handlers, nr_contexts); 631 return 0; 632 633 fail_cleanup_contexts: 634 for (i = 0; i < nr_contexts; i++) { 635 if (plic_parse_context_parent(fwnode, i, &parent_hwirq, &cpu)) 636 continue; 637 if (parent_hwirq != RV_IRQ_EXT || cpu < 0) 638 continue; 639 640 handler = per_cpu_ptr(&plic_handlers, cpu); 641 handler->present = false; 642 handler->hart_base = NULL; 643 handler->enable_base = NULL; 644 kfree(handler->enable_save); 645 handler->enable_save = NULL; 646 handler->priv = NULL; 647 } 648 bitmap_free(priv->prio_save); 649 fail_free_priv: 650 kfree(priv); 651 fail_free_regs: 652 iounmap(regs); 653 return error; 654 } 655 656 static int plic_platform_probe(struct platform_device *pdev) 657 { 658 return plic_probe(pdev->dev.fwnode); 659 } 660 661 static struct platform_driver plic_driver = { 662 .driver = { 663 .name = "riscv-plic", 664 .of_match_table = plic_match, 665 .suppress_bind_attrs = true, 666 }, 667 .probe = plic_platform_probe, 668 }; 669 builtin_platform_driver(plic_driver); 670 671 static int __init plic_early_probe(struct device_node *node, 672 struct device_node *parent) 673 { 674 return plic_probe(&node->fwnode); 675 } 676 677 IRQCHIP_DECLARE(riscv, "allwinner,sun20i-d1-plic", plic_early_probe); 678