1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * SG2042 MSI Controller 4 * 5 * Copyright (C) 2024 Sophgo Technology Inc. 6 * Copyright (C) 2024 Chen Wang <unicorn_wang@outlook.com> 7 */ 8 9 #include <linux/cleanup.h> 10 #include <linux/io.h> 11 #include <linux/irq.h> 12 #include <linux/irqdomain.h> 13 #include <linux/kernel.h> 14 #include <linux/module.h> 15 #include <linux/msi.h> 16 #include <linux/platform_device.h> 17 #include <linux/property.h> 18 #include <linux/slab.h> 19 20 #include <linux/irqchip/irq-msi-lib.h> 21 22 struct sg204x_msi_chip_info { 23 const struct irq_chip *irqchip; 24 const struct msi_parent_ops *parent_ops; 25 }; 26 27 /** 28 * struct sg204x_msi_chipdata - chip data for the SG204x MSI IRQ controller 29 * @reg_clr: clear reg, see TRM, 10.1.33, GP_INTR0_CLR 30 * @doorbell_addr: see TRM, 10.1.32, GP_INTR0_SET 31 * @irq_first: First vectors number that MSIs starts 32 * @num_irqs: Number of vectors for MSIs 33 * @irq_type: IRQ type for MSIs 34 * @msi_map: mapping for allocated MSI vectors. 35 * @msi_map_lock: Lock for msi_map 36 * @chip_info: chip specific infomations 37 */ 38 struct sg204x_msi_chipdata { 39 void __iomem *reg_clr; 40 41 phys_addr_t doorbell_addr; 42 43 u32 irq_first; 44 u32 num_irqs; 45 unsigned int irq_type; 46 47 unsigned long *msi_map; 48 struct mutex msi_map_lock; 49 50 const struct sg204x_msi_chip_info *chip_info; 51 }; 52 53 static int sg204x_msi_allocate_hwirq(struct sg204x_msi_chipdata *data, int num_req) 54 { 55 int first; 56 57 guard(mutex)(&data->msi_map_lock); 58 first = bitmap_find_free_region(data->msi_map, data->num_irqs, 59 get_count_order(num_req)); 60 return first >= 0 ? first : -ENOSPC; 61 } 62 63 static void sg204x_msi_free_hwirq(struct sg204x_msi_chipdata *data, int hwirq, int num_req) 64 { 65 guard(mutex)(&data->msi_map_lock); 66 bitmap_release_region(data->msi_map, hwirq, get_count_order(num_req)); 67 } 68 69 static void sg2042_msi_irq_ack(struct irq_data *d) 70 { 71 struct sg204x_msi_chipdata *data = irq_data_get_irq_chip_data(d); 72 int bit_off = d->hwirq; 73 74 writel(1 << bit_off, data->reg_clr); 75 76 irq_chip_ack_parent(d); 77 } 78 79 static void sg2042_msi_irq_compose_msi_msg(struct irq_data *d, struct msi_msg *msg) 80 { 81 struct sg204x_msi_chipdata *data = irq_data_get_irq_chip_data(d); 82 83 msg->address_hi = upper_32_bits(data->doorbell_addr); 84 msg->address_lo = lower_32_bits(data->doorbell_addr); 85 msg->data = 1 << d->hwirq; 86 } 87 88 static const struct irq_chip sg2042_msi_middle_irq_chip = { 89 .name = "SG2042 MSI", 90 .irq_startup = irq_chip_startup_parent, 91 .irq_shutdown = irq_chip_shutdown_parent, 92 .irq_ack = sg2042_msi_irq_ack, 93 .irq_mask = irq_chip_mask_parent, 94 .irq_unmask = irq_chip_unmask_parent, 95 #ifdef CONFIG_SMP 96 .irq_set_affinity = irq_chip_set_affinity_parent, 97 #endif 98 .irq_compose_msi_msg = sg2042_msi_irq_compose_msi_msg, 99 }; 100 101 static void sg2044_msi_irq_ack(struct irq_data *d) 102 { 103 struct sg204x_msi_chipdata *data = irq_data_get_irq_chip_data(d); 104 105 writel(0, (u32 __iomem *)data->reg_clr + d->hwirq); 106 irq_chip_ack_parent(d); 107 } 108 109 static void sg2044_msi_irq_compose_msi_msg(struct irq_data *d, struct msi_msg *msg) 110 { 111 struct sg204x_msi_chipdata *data = irq_data_get_irq_chip_data(d); 112 phys_addr_t doorbell = data->doorbell_addr + 4 * (d->hwirq / 32); 113 114 msg->address_lo = lower_32_bits(doorbell); 115 msg->address_hi = upper_32_bits(doorbell); 116 msg->data = d->hwirq % 32; 117 } 118 119 static struct irq_chip sg2044_msi_middle_irq_chip = { 120 .name = "SG2044 MSI", 121 .irq_startup = irq_chip_startup_parent, 122 .irq_shutdown = irq_chip_shutdown_parent, 123 .irq_ack = sg2044_msi_irq_ack, 124 .irq_mask = irq_chip_mask_parent, 125 .irq_unmask = irq_chip_unmask_parent, 126 #ifdef CONFIG_SMP 127 .irq_set_affinity = irq_chip_set_affinity_parent, 128 #endif 129 .irq_compose_msi_msg = sg2044_msi_irq_compose_msi_msg, 130 }; 131 132 static int sg204x_msi_parent_domain_alloc(struct irq_domain *domain, unsigned int virq, int hwirq) 133 { 134 struct sg204x_msi_chipdata *data = domain->host_data; 135 struct irq_fwspec fwspec; 136 struct irq_data *d; 137 int ret; 138 139 fwspec.fwnode = domain->parent->fwnode; 140 fwspec.param_count = 2; 141 fwspec.param[0] = data->irq_first + hwirq; 142 fwspec.param[1] = data->irq_type; 143 144 ret = irq_domain_alloc_irqs_parent(domain, virq, 1, &fwspec); 145 if (ret) 146 return ret; 147 148 d = irq_domain_get_irq_data(domain->parent, virq); 149 return d->chip->irq_set_type(d, data->irq_type); 150 } 151 152 static int sg204x_msi_middle_domain_alloc(struct irq_domain *domain, unsigned int virq, 153 unsigned int nr_irqs, void *args) 154 { 155 struct sg204x_msi_chipdata *data = domain->host_data; 156 int hwirq, err, i; 157 158 hwirq = sg204x_msi_allocate_hwirq(data, nr_irqs); 159 if (hwirq < 0) 160 return hwirq; 161 162 for (i = 0; i < nr_irqs; i++) { 163 err = sg204x_msi_parent_domain_alloc(domain, virq + i, hwirq + i); 164 if (err) 165 goto err_hwirq; 166 167 irq_domain_set_hwirq_and_chip(domain, virq + i, hwirq + i, 168 data->chip_info->irqchip, data); 169 } 170 return 0; 171 172 err_hwirq: 173 sg204x_msi_free_hwirq(data, hwirq, nr_irqs); 174 irq_domain_free_irqs_parent(domain, virq, i); 175 return err; 176 } 177 178 static void sg204x_msi_middle_domain_free(struct irq_domain *domain, unsigned int virq, 179 unsigned int nr_irqs) 180 { 181 struct irq_data *d = irq_domain_get_irq_data(domain, virq); 182 struct sg204x_msi_chipdata *data = irq_data_get_irq_chip_data(d); 183 184 irq_domain_free_irqs_parent(domain, virq, nr_irqs); 185 sg204x_msi_free_hwirq(data, d->hwirq, nr_irqs); 186 } 187 188 static const struct irq_domain_ops sg204x_msi_middle_domain_ops = { 189 .alloc = sg204x_msi_middle_domain_alloc, 190 .free = sg204x_msi_middle_domain_free, 191 .select = msi_lib_irq_domain_select, 192 }; 193 194 #define SG2042_MSI_FLAGS_REQUIRED (MSI_FLAG_USE_DEF_DOM_OPS | \ 195 MSI_FLAG_USE_DEF_CHIP_OPS | \ 196 MSI_FLAG_PCI_MSI_MASK_PARENT | \ 197 MSI_FLAG_PCI_MSI_STARTUP_PARENT) 198 199 #define SG2042_MSI_FLAGS_SUPPORTED MSI_GENERIC_FLAGS_MASK 200 201 static const struct msi_parent_ops sg2042_msi_parent_ops = { 202 .required_flags = SG2042_MSI_FLAGS_REQUIRED, 203 .supported_flags = SG2042_MSI_FLAGS_SUPPORTED, 204 .chip_flags = MSI_CHIP_FLAG_SET_ACK, 205 .bus_select_mask = MATCH_PCI_MSI, 206 .bus_select_token = DOMAIN_BUS_NEXUS, 207 .prefix = "SG2042-", 208 .init_dev_msi_info = msi_lib_init_dev_msi_info, 209 }; 210 211 #define SG2044_MSI_FLAGS_REQUIRED (MSI_FLAG_USE_DEF_DOM_OPS | \ 212 MSI_FLAG_USE_DEF_CHIP_OPS | \ 213 MSI_FLAG_PCI_MSI_MASK_PARENT | \ 214 MSI_FLAG_PCI_MSI_STARTUP_PARENT) 215 216 #define SG2044_MSI_FLAGS_SUPPORTED (MSI_GENERIC_FLAGS_MASK | \ 217 MSI_FLAG_MULTI_PCI_MSI | \ 218 MSI_FLAG_PCI_MSIX) 219 220 static const struct msi_parent_ops sg2044_msi_parent_ops = { 221 .required_flags = SG2044_MSI_FLAGS_REQUIRED, 222 .supported_flags = SG2044_MSI_FLAGS_SUPPORTED, 223 .chip_flags = MSI_CHIP_FLAG_SET_EOI | MSI_CHIP_FLAG_SET_ACK, 224 .bus_select_mask = MATCH_PCI_MSI, 225 .bus_select_token = DOMAIN_BUS_NEXUS, 226 .prefix = "SG2044-", 227 .init_dev_msi_info = msi_lib_init_dev_msi_info, 228 }; 229 230 static int sg204x_msi_init_domains(struct sg204x_msi_chipdata *data, 231 struct irq_domain *plic_domain, struct device *dev) 232 { 233 struct irq_domain_info info = { 234 .ops = &sg204x_msi_middle_domain_ops, 235 .parent = plic_domain, 236 .size = data->num_irqs, 237 .fwnode = dev_fwnode(dev), 238 .host_data = data, 239 }; 240 241 if (!msi_create_parent_irq_domain(&info, data->chip_info->parent_ops)) { 242 pr_err("Failed to create the MSI middle domain\n"); 243 return -ENOMEM; 244 } 245 return 0; 246 } 247 248 static int sg2042_msi_probe(struct platform_device *pdev) 249 { 250 struct fwnode_reference_args args = { }; 251 struct sg204x_msi_chipdata *data; 252 struct device *dev = &pdev->dev; 253 struct irq_domain *plic_domain; 254 struct resource *res; 255 int ret; 256 257 data = devm_kzalloc(dev, sizeof(struct sg204x_msi_chipdata), GFP_KERNEL); 258 if (!data) 259 return -ENOMEM; 260 261 data->chip_info = device_get_match_data(&pdev->dev); 262 if (!data->chip_info) { 263 dev_err(&pdev->dev, "Failed to get irqchip\n"); 264 return -EINVAL; 265 } 266 267 data->reg_clr = devm_platform_ioremap_resource_byname(pdev, "clr"); 268 if (IS_ERR(data->reg_clr)) { 269 dev_err(dev, "Failed to map clear register\n"); 270 return PTR_ERR(data->reg_clr); 271 } 272 273 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "doorbell"); 274 if (!res) { 275 dev_err(dev, "Failed get resource from set\n"); 276 return -EINVAL; 277 } 278 data->doorbell_addr = res->start; 279 280 ret = fwnode_property_get_reference_args(dev_fwnode(dev), "msi-ranges", 281 "#interrupt-cells", 0, 0, &args); 282 if (ret) { 283 dev_err(dev, "Unable to parse MSI vec base\n"); 284 return ret; 285 } 286 fwnode_handle_put(args.fwnode); 287 288 ret = fwnode_property_get_reference_args(dev_fwnode(dev), "msi-ranges", NULL, 289 args.nargs + 1, 0, &args); 290 if (ret) { 291 dev_err(dev, "Unable to parse MSI vec number\n"); 292 return ret; 293 } 294 295 plic_domain = irq_find_matching_fwnode(args.fwnode, DOMAIN_BUS_ANY); 296 fwnode_handle_put(args.fwnode); 297 if (!plic_domain) { 298 pr_err("Failed to find the PLIC domain\n"); 299 return -ENXIO; 300 } 301 302 data->irq_first = (u32)args.args[0]; 303 data->irq_type = (unsigned int)args.args[1]; 304 data->num_irqs = (u32)args.args[args.nargs - 1]; 305 306 mutex_init(&data->msi_map_lock); 307 308 data->msi_map = devm_bitmap_zalloc(&pdev->dev, data->num_irqs, GFP_KERNEL); 309 if (!data->msi_map) { 310 dev_err(&pdev->dev, "Unable to allocate msi mapping\n"); 311 return -ENOMEM; 312 } 313 314 return sg204x_msi_init_domains(data, plic_domain, dev); 315 } 316 317 static const struct sg204x_msi_chip_info sg2042_chip_info = { 318 .irqchip = &sg2042_msi_middle_irq_chip, 319 .parent_ops = &sg2042_msi_parent_ops, 320 }; 321 322 static const struct sg204x_msi_chip_info sg2044_chip_info = { 323 .irqchip = &sg2044_msi_middle_irq_chip, 324 .parent_ops = &sg2044_msi_parent_ops, 325 }; 326 327 static const struct of_device_id sg2042_msi_of_match[] = { 328 { .compatible = "sophgo,sg2042-msi", .data = &sg2042_chip_info }, 329 { .compatible = "sophgo,sg2044-msi", .data = &sg2044_chip_info }, 330 { } 331 }; 332 333 static struct platform_driver sg2042_msi_driver = { 334 .driver = { 335 .name = "sg2042-msi", 336 .of_match_table = sg2042_msi_of_match, 337 }, 338 .probe = sg2042_msi_probe, 339 }; 340 builtin_platform_driver(sg2042_msi_driver); 341