1aa43953eSAnup Patel // SPDX-License-Identifier: GPL-2.0 2aa43953eSAnup Patel /* Copyright (C) 2025 Ventana Micro Systems Inc. */ 3aa43953eSAnup Patel 4*4752b0cfSSunil V L #include <linux/acpi.h> 5aa43953eSAnup Patel #include <linux/bits.h> 6aa43953eSAnup Patel #include <linux/bug.h> 7aa43953eSAnup Patel #include <linux/device.h> 8aa43953eSAnup Patel #include <linux/device/devres.h> 9aa43953eSAnup Patel #include <linux/dev_printk.h> 10aa43953eSAnup Patel #include <linux/errno.h> 11aa43953eSAnup Patel #include <linux/irq.h> 12aa43953eSAnup Patel #include <linux/irqdomain.h> 13*4752b0cfSSunil V L #include <linux/irqchip/riscv-imsic.h> 14aa43953eSAnup Patel #include <linux/mailbox_client.h> 15aa43953eSAnup Patel #include <linux/mailbox/riscv-rpmi-message.h> 16aa43953eSAnup Patel #include <linux/module.h> 17aa43953eSAnup Patel #include <linux/msi.h> 18aa43953eSAnup Patel #include <linux/of_irq.h> 19aa43953eSAnup Patel #include <linux/platform_device.h> 20aa43953eSAnup Patel #include <linux/types.h> 21aa43953eSAnup Patel 22aa43953eSAnup Patel struct rpmi_sysmsi_get_attrs_rx { 23aa43953eSAnup Patel __le32 status; 24aa43953eSAnup Patel __le32 sys_num_msi; 25aa43953eSAnup Patel __le32 flag0; 26aa43953eSAnup Patel __le32 flag1; 27aa43953eSAnup Patel }; 28aa43953eSAnup Patel 29aa43953eSAnup Patel #define RPMI_SYSMSI_MSI_ATTRIBUTES_FLAG0_PREF_PRIV BIT(0) 30aa43953eSAnup Patel 31aa43953eSAnup Patel struct rpmi_sysmsi_set_msi_state_tx { 32aa43953eSAnup Patel __le32 sys_msi_index; 33aa43953eSAnup Patel __le32 sys_msi_state; 34aa43953eSAnup Patel }; 35aa43953eSAnup Patel 36aa43953eSAnup Patel struct rpmi_sysmsi_set_msi_state_rx { 37aa43953eSAnup Patel __le32 status; 38aa43953eSAnup Patel }; 39aa43953eSAnup Patel 40aa43953eSAnup Patel #define RPMI_SYSMSI_MSI_STATE_ENABLE BIT(0) 41aa43953eSAnup Patel #define RPMI_SYSMSI_MSI_STATE_PENDING BIT(1) 42aa43953eSAnup Patel 43aa43953eSAnup Patel struct rpmi_sysmsi_set_msi_target_tx { 44aa43953eSAnup Patel __le32 sys_msi_index; 45aa43953eSAnup Patel __le32 sys_msi_address_low; 46aa43953eSAnup Patel __le32 sys_msi_address_high; 47aa43953eSAnup Patel __le32 sys_msi_data; 48aa43953eSAnup Patel }; 49aa43953eSAnup Patel 50aa43953eSAnup Patel struct rpmi_sysmsi_set_msi_target_rx { 51aa43953eSAnup Patel __le32 status; 52aa43953eSAnup Patel }; 53aa43953eSAnup Patel 54aa43953eSAnup Patel struct rpmi_sysmsi_priv { 55aa43953eSAnup Patel struct device *dev; 56aa43953eSAnup Patel struct mbox_client client; 57aa43953eSAnup Patel struct mbox_chan *chan; 58aa43953eSAnup Patel u32 nr_irqs; 59aa43953eSAnup Patel u32 gsi_base; 60aa43953eSAnup Patel }; 61aa43953eSAnup Patel 62aa43953eSAnup Patel static int rpmi_sysmsi_get_num_msi(struct rpmi_sysmsi_priv *priv) 63aa43953eSAnup Patel { 64aa43953eSAnup Patel struct rpmi_sysmsi_get_attrs_rx rx; 65aa43953eSAnup Patel struct rpmi_mbox_message msg; 66aa43953eSAnup Patel int ret; 67aa43953eSAnup Patel 68aa43953eSAnup Patel rpmi_mbox_init_send_with_response(&msg, RPMI_SYSMSI_SRV_GET_ATTRIBUTES, 69aa43953eSAnup Patel NULL, 0, &rx, sizeof(rx)); 70aa43953eSAnup Patel ret = rpmi_mbox_send_message(priv->chan, &msg); 71aa43953eSAnup Patel if (ret) 72aa43953eSAnup Patel return ret; 73aa43953eSAnup Patel if (rx.status) 74aa43953eSAnup Patel return rpmi_to_linux_error(le32_to_cpu(rx.status)); 75aa43953eSAnup Patel 76aa43953eSAnup Patel return le32_to_cpu(rx.sys_num_msi); 77aa43953eSAnup Patel } 78aa43953eSAnup Patel 79aa43953eSAnup Patel static int rpmi_sysmsi_set_msi_state(struct rpmi_sysmsi_priv *priv, 80aa43953eSAnup Patel u32 sys_msi_index, u32 sys_msi_state) 81aa43953eSAnup Patel { 82aa43953eSAnup Patel struct rpmi_sysmsi_set_msi_state_tx tx; 83aa43953eSAnup Patel struct rpmi_sysmsi_set_msi_state_rx rx; 84aa43953eSAnup Patel struct rpmi_mbox_message msg; 85aa43953eSAnup Patel int ret; 86aa43953eSAnup Patel 87aa43953eSAnup Patel tx.sys_msi_index = cpu_to_le32(sys_msi_index); 88aa43953eSAnup Patel tx.sys_msi_state = cpu_to_le32(sys_msi_state); 89aa43953eSAnup Patel rpmi_mbox_init_send_with_response(&msg, RPMI_SYSMSI_SRV_SET_MSI_STATE, 90aa43953eSAnup Patel &tx, sizeof(tx), &rx, sizeof(rx)); 91aa43953eSAnup Patel ret = rpmi_mbox_send_message(priv->chan, &msg); 92aa43953eSAnup Patel if (ret) 93aa43953eSAnup Patel return ret; 94aa43953eSAnup Patel if (rx.status) 95aa43953eSAnup Patel return rpmi_to_linux_error(le32_to_cpu(rx.status)); 96aa43953eSAnup Patel 97aa43953eSAnup Patel return 0; 98aa43953eSAnup Patel } 99aa43953eSAnup Patel 100aa43953eSAnup Patel static int rpmi_sysmsi_set_msi_target(struct rpmi_sysmsi_priv *priv, 101aa43953eSAnup Patel u32 sys_msi_index, struct msi_msg *m) 102aa43953eSAnup Patel { 103aa43953eSAnup Patel struct rpmi_sysmsi_set_msi_target_tx tx; 104aa43953eSAnup Patel struct rpmi_sysmsi_set_msi_target_rx rx; 105aa43953eSAnup Patel struct rpmi_mbox_message msg; 106aa43953eSAnup Patel int ret; 107aa43953eSAnup Patel 108aa43953eSAnup Patel tx.sys_msi_index = cpu_to_le32(sys_msi_index); 109aa43953eSAnup Patel tx.sys_msi_address_low = cpu_to_le32(m->address_lo); 110aa43953eSAnup Patel tx.sys_msi_address_high = cpu_to_le32(m->address_hi); 111aa43953eSAnup Patel tx.sys_msi_data = cpu_to_le32(m->data); 112aa43953eSAnup Patel rpmi_mbox_init_send_with_response(&msg, RPMI_SYSMSI_SRV_SET_MSI_TARGET, 113aa43953eSAnup Patel &tx, sizeof(tx), &rx, sizeof(rx)); 114aa43953eSAnup Patel ret = rpmi_mbox_send_message(priv->chan, &msg); 115aa43953eSAnup Patel if (ret) 116aa43953eSAnup Patel return ret; 117aa43953eSAnup Patel if (rx.status) 118aa43953eSAnup Patel return rpmi_to_linux_error(le32_to_cpu(rx.status)); 119aa43953eSAnup Patel 120aa43953eSAnup Patel return 0; 121aa43953eSAnup Patel } 122aa43953eSAnup Patel 123aa43953eSAnup Patel static void rpmi_sysmsi_irq_mask(struct irq_data *d) 124aa43953eSAnup Patel { 125aa43953eSAnup Patel struct rpmi_sysmsi_priv *priv = irq_data_get_irq_chip_data(d); 126aa43953eSAnup Patel irq_hw_number_t hwirq = irqd_to_hwirq(d); 127aa43953eSAnup Patel int ret; 128aa43953eSAnup Patel 129aa43953eSAnup Patel ret = rpmi_sysmsi_set_msi_state(priv, hwirq, 0); 130aa43953eSAnup Patel if (ret) 131aa43953eSAnup Patel dev_warn(priv->dev, "Failed to mask hwirq %lu (error %d)\n", hwirq, ret); 132aa43953eSAnup Patel irq_chip_mask_parent(d); 133aa43953eSAnup Patel } 134aa43953eSAnup Patel 135aa43953eSAnup Patel static void rpmi_sysmsi_irq_unmask(struct irq_data *d) 136aa43953eSAnup Patel { 137aa43953eSAnup Patel struct rpmi_sysmsi_priv *priv = irq_data_get_irq_chip_data(d); 138aa43953eSAnup Patel irq_hw_number_t hwirq = irqd_to_hwirq(d); 139aa43953eSAnup Patel int ret; 140aa43953eSAnup Patel 141aa43953eSAnup Patel irq_chip_unmask_parent(d); 142aa43953eSAnup Patel ret = rpmi_sysmsi_set_msi_state(priv, hwirq, RPMI_SYSMSI_MSI_STATE_ENABLE); 143aa43953eSAnup Patel if (ret) 144aa43953eSAnup Patel dev_warn(priv->dev, "Failed to unmask hwirq %lu (error %d)\n", hwirq, ret); 145aa43953eSAnup Patel } 146aa43953eSAnup Patel 147aa43953eSAnup Patel static void rpmi_sysmsi_write_msg(struct irq_data *d, struct msi_msg *msg) 148aa43953eSAnup Patel { 149aa43953eSAnup Patel struct rpmi_sysmsi_priv *priv = irq_data_get_irq_chip_data(d); 150aa43953eSAnup Patel irq_hw_number_t hwirq = irqd_to_hwirq(d); 151aa43953eSAnup Patel int ret; 152aa43953eSAnup Patel 153aa43953eSAnup Patel /* For zeroed MSI, do nothing as of now */ 154aa43953eSAnup Patel if (!msg->address_hi && !msg->address_lo && !msg->data) 155aa43953eSAnup Patel return; 156aa43953eSAnup Patel 157aa43953eSAnup Patel ret = rpmi_sysmsi_set_msi_target(priv, hwirq, msg); 158aa43953eSAnup Patel if (ret) 159aa43953eSAnup Patel dev_warn(priv->dev, "Failed to set target for hwirq %lu (error %d)\n", hwirq, ret); 160aa43953eSAnup Patel } 161aa43953eSAnup Patel 162aa43953eSAnup Patel static void rpmi_sysmsi_set_desc(msi_alloc_info_t *arg, struct msi_desc *desc) 163aa43953eSAnup Patel { 164aa43953eSAnup Patel arg->desc = desc; 165aa43953eSAnup Patel arg->hwirq = desc->data.icookie.value; 166aa43953eSAnup Patel } 167aa43953eSAnup Patel 168aa43953eSAnup Patel static int rpmi_sysmsi_translate(struct irq_domain *d, struct irq_fwspec *fwspec, 169aa43953eSAnup Patel unsigned long *hwirq, unsigned int *type) 170aa43953eSAnup Patel { 171aa43953eSAnup Patel struct msi_domain_info *info = d->host_data; 172aa43953eSAnup Patel struct rpmi_sysmsi_priv *priv = info->data; 173aa43953eSAnup Patel 174aa43953eSAnup Patel if (WARN_ON(fwspec->param_count < 1)) 175aa43953eSAnup Patel return -EINVAL; 176aa43953eSAnup Patel 177aa43953eSAnup Patel /* For DT, gsi_base is always zero. */ 178aa43953eSAnup Patel *hwirq = fwspec->param[0] - priv->gsi_base; 179aa43953eSAnup Patel *type = IRQ_TYPE_NONE; 180aa43953eSAnup Patel return 0; 181aa43953eSAnup Patel } 182aa43953eSAnup Patel 183aa43953eSAnup Patel static const struct msi_domain_template rpmi_sysmsi_template = { 184aa43953eSAnup Patel .chip = { 185aa43953eSAnup Patel .name = "RPMI-SYSMSI", 186aa43953eSAnup Patel .irq_mask = rpmi_sysmsi_irq_mask, 187aa43953eSAnup Patel .irq_unmask = rpmi_sysmsi_irq_unmask, 188aa43953eSAnup Patel #ifdef CONFIG_SMP 189aa43953eSAnup Patel .irq_set_affinity = irq_chip_set_affinity_parent, 190aa43953eSAnup Patel #endif 191aa43953eSAnup Patel .irq_write_msi_msg = rpmi_sysmsi_write_msg, 192aa43953eSAnup Patel .flags = IRQCHIP_SET_TYPE_MASKED | 193aa43953eSAnup Patel IRQCHIP_SKIP_SET_WAKE | 194aa43953eSAnup Patel IRQCHIP_MASK_ON_SUSPEND, 195aa43953eSAnup Patel }, 196aa43953eSAnup Patel 197aa43953eSAnup Patel .ops = { 198aa43953eSAnup Patel .set_desc = rpmi_sysmsi_set_desc, 199aa43953eSAnup Patel .msi_translate = rpmi_sysmsi_translate, 200aa43953eSAnup Patel }, 201aa43953eSAnup Patel 202aa43953eSAnup Patel .info = { 203aa43953eSAnup Patel .bus_token = DOMAIN_BUS_WIRED_TO_MSI, 204aa43953eSAnup Patel .flags = MSI_FLAG_USE_DEV_FWNODE, 205aa43953eSAnup Patel .handler = handle_simple_irq, 206aa43953eSAnup Patel .handler_name = "simple", 207aa43953eSAnup Patel }, 208aa43953eSAnup Patel }; 209aa43953eSAnup Patel 210aa43953eSAnup Patel static int rpmi_sysmsi_probe(struct platform_device *pdev) 211aa43953eSAnup Patel { 212aa43953eSAnup Patel struct device *dev = &pdev->dev; 213aa43953eSAnup Patel struct rpmi_sysmsi_priv *priv; 214*4752b0cfSSunil V L struct fwnode_handle *fwnode; 215*4752b0cfSSunil V L u32 id; 216aa43953eSAnup Patel int rc; 217aa43953eSAnup Patel 218aa43953eSAnup Patel priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); 219aa43953eSAnup Patel if (!priv) 220aa43953eSAnup Patel return -ENOMEM; 221aa43953eSAnup Patel priv->dev = dev; 222aa43953eSAnup Patel 223aa43953eSAnup Patel /* Setup mailbox client */ 224aa43953eSAnup Patel priv->client.dev = priv->dev; 225aa43953eSAnup Patel priv->client.rx_callback = NULL; 226aa43953eSAnup Patel priv->client.tx_block = false; 227aa43953eSAnup Patel priv->client.knows_txdone = true; 228aa43953eSAnup Patel priv->client.tx_tout = 0; 229aa43953eSAnup Patel 230aa43953eSAnup Patel /* Request mailbox channel */ 231aa43953eSAnup Patel priv->chan = mbox_request_channel(&priv->client, 0); 232aa43953eSAnup Patel if (IS_ERR(priv->chan)) 233aa43953eSAnup Patel return PTR_ERR(priv->chan); 234aa43953eSAnup Patel 235aa43953eSAnup Patel /* Get number of system MSIs */ 236aa43953eSAnup Patel rc = rpmi_sysmsi_get_num_msi(priv); 237aa43953eSAnup Patel if (rc < 1) { 238aa43953eSAnup Patel mbox_free_channel(priv->chan); 239aa43953eSAnup Patel if (rc) 240aa43953eSAnup Patel return dev_err_probe(dev, rc, "Failed to get number of system MSIs\n"); 241aa43953eSAnup Patel else 242aa43953eSAnup Patel return dev_err_probe(dev, -ENODEV, "No system MSIs found\n"); 243aa43953eSAnup Patel } 244aa43953eSAnup Patel priv->nr_irqs = rc; 245aa43953eSAnup Patel 246*4752b0cfSSunil V L fwnode = dev_fwnode(dev); 247*4752b0cfSSunil V L if (is_acpi_node(fwnode)) { 248*4752b0cfSSunil V L u32 nr_irqs; 249*4752b0cfSSunil V L 250*4752b0cfSSunil V L rc = riscv_acpi_get_gsi_info(fwnode, &priv->gsi_base, &id, 251*4752b0cfSSunil V L &nr_irqs, NULL); 252*4752b0cfSSunil V L if (rc) { 253*4752b0cfSSunil V L dev_err(dev, "failed to find GSI mapping\n"); 254*4752b0cfSSunil V L return rc; 255*4752b0cfSSunil V L } 256*4752b0cfSSunil V L 257*4752b0cfSSunil V L /* Update with actual GSI range */ 258*4752b0cfSSunil V L if (nr_irqs != priv->nr_irqs) 259*4752b0cfSSunil V L riscv_acpi_update_gsi_range(priv->gsi_base, priv->nr_irqs); 260*4752b0cfSSunil V L } 261*4752b0cfSSunil V L 262aa43953eSAnup Patel /* 263aa43953eSAnup Patel * The device MSI domain for platform devices on RISC-V architecture 264aa43953eSAnup Patel * is only available after the MSI controller driver is probed so, 265aa43953eSAnup Patel * explicitly configure here. 266aa43953eSAnup Patel */ 267aa43953eSAnup Patel if (!dev_get_msi_domain(dev)) { 268aa43953eSAnup Patel /* 269aa43953eSAnup Patel * The device MSI domain for OF devices is only set at the 270aa43953eSAnup Patel * time of populating/creating OF device. If the device MSI 271aa43953eSAnup Patel * domain is discovered later after the OF device is created 272aa43953eSAnup Patel * then we need to set it explicitly before using any platform 273aa43953eSAnup Patel * MSI functions. 274aa43953eSAnup Patel */ 275*4752b0cfSSunil V L if (is_of_node(fwnode)) { 276aa43953eSAnup Patel of_msi_configure(dev, dev_of_node(dev)); 277*4752b0cfSSunil V L } else if (is_acpi_device_node(fwnode)) { 278*4752b0cfSSunil V L struct irq_domain *msi_domain; 279*4752b0cfSSunil V L 280*4752b0cfSSunil V L msi_domain = irq_find_matching_fwnode(imsic_acpi_get_fwnode(dev), 281*4752b0cfSSunil V L DOMAIN_BUS_PLATFORM_MSI); 282*4752b0cfSSunil V L dev_set_msi_domain(dev, msi_domain); 283*4752b0cfSSunil V L } 284aa43953eSAnup Patel 285aa43953eSAnup Patel if (!dev_get_msi_domain(dev)) { 286aa43953eSAnup Patel mbox_free_channel(priv->chan); 287aa43953eSAnup Patel return -EPROBE_DEFER; 288aa43953eSAnup Patel } 289aa43953eSAnup Patel } 290aa43953eSAnup Patel 291aa43953eSAnup Patel if (!msi_create_device_irq_domain(dev, MSI_DEFAULT_DOMAIN, 292aa43953eSAnup Patel &rpmi_sysmsi_template, 293aa43953eSAnup Patel priv->nr_irqs, priv, priv)) { 294aa43953eSAnup Patel mbox_free_channel(priv->chan); 295aa43953eSAnup Patel return dev_err_probe(dev, -ENOMEM, "failed to create MSI irq domain\n"); 296aa43953eSAnup Patel } 297aa43953eSAnup Patel 298*4752b0cfSSunil V L #ifdef CONFIG_ACPI 299*4752b0cfSSunil V L struct acpi_device *adev = ACPI_COMPANION(dev); 300*4752b0cfSSunil V L 301*4752b0cfSSunil V L if (adev) 302*4752b0cfSSunil V L acpi_dev_clear_dependencies(adev); 303*4752b0cfSSunil V L #endif 304*4752b0cfSSunil V L 305aa43953eSAnup Patel dev_info(dev, "%u system MSIs registered\n", priv->nr_irqs); 306aa43953eSAnup Patel return 0; 307aa43953eSAnup Patel } 308aa43953eSAnup Patel 309aa43953eSAnup Patel static const struct of_device_id rpmi_sysmsi_match[] = { 310aa43953eSAnup Patel { .compatible = "riscv,rpmi-system-msi" }, 311aa43953eSAnup Patel {} 312aa43953eSAnup Patel }; 313aa43953eSAnup Patel 314*4752b0cfSSunil V L static const struct acpi_device_id acpi_rpmi_sysmsi_match[] = { 315*4752b0cfSSunil V L { "RSCV0006" }, 316*4752b0cfSSunil V L {} 317*4752b0cfSSunil V L }; 318*4752b0cfSSunil V L MODULE_DEVICE_TABLE(acpi, acpi_rpmi_sysmsi_match); 319*4752b0cfSSunil V L 320aa43953eSAnup Patel static struct platform_driver rpmi_sysmsi_driver = { 321aa43953eSAnup Patel .driver = { 322aa43953eSAnup Patel .name = "rpmi-sysmsi", 323aa43953eSAnup Patel .of_match_table = rpmi_sysmsi_match, 324*4752b0cfSSunil V L .acpi_match_table = acpi_rpmi_sysmsi_match, 325aa43953eSAnup Patel }, 326aa43953eSAnup Patel .probe = rpmi_sysmsi_probe, 327aa43953eSAnup Patel }; 328aa43953eSAnup Patel builtin_platform_driver(rpmi_sysmsi_driver); 329