1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (C) 2012 Regents of the University of California 4 * Copyright (C) 2017-2018 SiFive 5 * Copyright (C) 2020 Western Digital Corporation or its affiliates. 6 */ 7 8 #define pr_fmt(fmt) "riscv-intc: " fmt 9 #include <linux/acpi.h> 10 #include <linux/atomic.h> 11 #include <linux/bits.h> 12 #include <linux/cpu.h> 13 #include <linux/irq.h> 14 #include <linux/irqchip.h> 15 #include <linux/irqdomain.h> 16 #include <linux/interrupt.h> 17 #include <linux/module.h> 18 #include <linux/of.h> 19 #include <linux/smp.h> 20 #include <linux/soc/andes/irq.h> 21 22 #include <asm/hwcap.h> 23 24 static struct irq_domain *intc_domain; 25 static unsigned int riscv_intc_nr_irqs __ro_after_init = BITS_PER_LONG; 26 static unsigned int riscv_intc_custom_base __ro_after_init = BITS_PER_LONG; 27 static unsigned int riscv_intc_custom_nr_irqs __ro_after_init; 28 29 static asmlinkage void riscv_intc_irq(struct pt_regs *regs) 30 { 31 unsigned long cause = regs->cause & ~CAUSE_IRQ_FLAG; 32 33 if (generic_handle_domain_irq(intc_domain, cause)) 34 pr_warn_ratelimited("Failed to handle interrupt (cause: %ld)\n", cause); 35 } 36 37 static asmlinkage void riscv_intc_aia_irq(struct pt_regs *regs) 38 { 39 unsigned long topi; 40 41 while ((topi = csr_read(CSR_TOPI))) 42 generic_handle_domain_irq(intc_domain, topi >> TOPI_IID_SHIFT); 43 } 44 45 /* 46 * On RISC-V systems local interrupts are masked or unmasked by writing 47 * the SIE (Supervisor Interrupt Enable) CSR. As CSRs can only be written 48 * on the local hart, these functions can only be called on the hart that 49 * corresponds to the IRQ chip. 50 */ 51 52 static void riscv_intc_irq_mask(struct irq_data *d) 53 { 54 if (IS_ENABLED(CONFIG_32BIT) && d->hwirq >= BITS_PER_LONG) 55 csr_clear(CSR_IEH, BIT(d->hwirq - BITS_PER_LONG)); 56 else 57 csr_clear(CSR_IE, BIT(d->hwirq)); 58 } 59 60 static void riscv_intc_irq_unmask(struct irq_data *d) 61 { 62 if (IS_ENABLED(CONFIG_32BIT) && d->hwirq >= BITS_PER_LONG) 63 csr_set(CSR_IEH, BIT(d->hwirq - BITS_PER_LONG)); 64 else 65 csr_set(CSR_IE, BIT(d->hwirq)); 66 } 67 68 static void andes_intc_irq_mask(struct irq_data *d) 69 { 70 /* 71 * Andes specific S-mode local interrupt causes (hwirq) 72 * are defined as (256 + n) and controlled by n-th bit 73 * of SLIE. 74 */ 75 unsigned int mask = BIT(d->hwirq % BITS_PER_LONG); 76 77 if (d->hwirq < ANDES_SLI_CAUSE_BASE) 78 csr_clear(CSR_IE, mask); 79 else 80 csr_clear(ANDES_CSR_SLIE, mask); 81 } 82 83 static void andes_intc_irq_unmask(struct irq_data *d) 84 { 85 unsigned int mask = BIT(d->hwirq % BITS_PER_LONG); 86 87 if (d->hwirq < ANDES_SLI_CAUSE_BASE) 88 csr_set(CSR_IE, mask); 89 else 90 csr_set(ANDES_CSR_SLIE, mask); 91 } 92 93 static void riscv_intc_irq_eoi(struct irq_data *d) 94 { 95 /* 96 * The RISC-V INTC driver uses handle_percpu_devid_irq() flow 97 * for the per-HART local interrupts and child irqchip drivers 98 * (such as PLIC, SBI IPI, CLINT, APLIC, IMSIC, etc) implement 99 * chained handlers for the per-HART local interrupts. 100 * 101 * In the absence of irq_eoi(), the chained_irq_enter() and 102 * chained_irq_exit() functions (used by child irqchip drivers) 103 * will do unnecessary mask/unmask of per-HART local interrupts 104 * at the time of handling interrupts. To avoid this, we provide 105 * an empty irq_eoi() callback for RISC-V INTC irqchip. 106 */ 107 } 108 109 static struct irq_chip riscv_intc_chip = { 110 .name = "RISC-V INTC", 111 .irq_mask = riscv_intc_irq_mask, 112 .irq_unmask = riscv_intc_irq_unmask, 113 .irq_eoi = riscv_intc_irq_eoi, 114 }; 115 116 static struct irq_chip andes_intc_chip = { 117 .name = "RISC-V INTC", 118 .irq_mask = andes_intc_irq_mask, 119 .irq_unmask = andes_intc_irq_unmask, 120 .irq_eoi = riscv_intc_irq_eoi, 121 }; 122 123 static int riscv_intc_domain_map(struct irq_domain *d, unsigned int irq, 124 irq_hw_number_t hwirq) 125 { 126 struct irq_chip *chip = d->host_data; 127 128 irq_set_percpu_devid(irq); 129 irq_domain_set_info(d, irq, hwirq, chip, NULL, handle_percpu_devid_irq, 130 NULL, NULL); 131 132 return 0; 133 } 134 135 static int riscv_intc_domain_alloc(struct irq_domain *domain, 136 unsigned int virq, unsigned int nr_irqs, 137 void *arg) 138 { 139 int i, ret; 140 irq_hw_number_t hwirq; 141 unsigned int type = IRQ_TYPE_NONE; 142 struct irq_fwspec *fwspec = arg; 143 144 ret = irq_domain_translate_onecell(domain, fwspec, &hwirq, &type); 145 if (ret) 146 return ret; 147 148 /* 149 * Only allow hwirq for which we have corresponding standard or 150 * custom interrupt enable register. 151 */ 152 if ((hwirq >= riscv_intc_nr_irqs && hwirq < riscv_intc_custom_base) || 153 (hwirq >= riscv_intc_custom_base + riscv_intc_custom_nr_irqs)) 154 return -EINVAL; 155 156 for (i = 0; i < nr_irqs; i++) { 157 ret = riscv_intc_domain_map(domain, virq + i, hwirq + i); 158 if (ret) 159 return ret; 160 } 161 162 return 0; 163 } 164 165 static const struct irq_domain_ops riscv_intc_domain_ops = { 166 .map = riscv_intc_domain_map, 167 .xlate = irq_domain_xlate_onecell, 168 .alloc = riscv_intc_domain_alloc 169 }; 170 171 static struct fwnode_handle *riscv_intc_hwnode(void) 172 { 173 return intc_domain->fwnode; 174 } 175 176 static int __init riscv_intc_init_common(struct fwnode_handle *fn, struct irq_chip *chip) 177 { 178 int rc; 179 180 intc_domain = irq_domain_create_tree(fn, &riscv_intc_domain_ops, chip); 181 if (!intc_domain) { 182 pr_err("unable to add IRQ domain\n"); 183 return -ENXIO; 184 } 185 186 if (riscv_isa_extension_available(NULL, SxAIA)) 187 rc = set_handle_irq(&riscv_intc_aia_irq); 188 else 189 rc = set_handle_irq(&riscv_intc_irq); 190 if (rc) { 191 pr_err("failed to set irq handler\n"); 192 return rc; 193 } 194 195 riscv_set_intc_hwnode_fn(riscv_intc_hwnode); 196 197 pr_info("%d local interrupts mapped%s\n", 198 riscv_isa_extension_available(NULL, SxAIA) ? 64 : riscv_intc_nr_irqs, 199 riscv_isa_extension_available(NULL, SxAIA) ? " using AIA" : ""); 200 if (riscv_intc_custom_nr_irqs) 201 pr_info("%d custom local interrupts mapped\n", riscv_intc_custom_nr_irqs); 202 203 return 0; 204 } 205 206 static int __init riscv_intc_init(struct device_node *node, 207 struct device_node *parent) 208 { 209 struct irq_chip *chip = &riscv_intc_chip; 210 unsigned long hartid; 211 int rc; 212 213 rc = riscv_of_parent_hartid(node, &hartid); 214 if (rc < 0) { 215 pr_warn("unable to find hart id for %pOF\n", node); 216 return 0; 217 } 218 219 /* 220 * The DT will have one INTC DT node under each CPU (or HART) 221 * DT node so riscv_intc_init() function will be called once 222 * for each INTC DT node. We only need to do INTC initialization 223 * for the INTC DT node belonging to boot CPU (or boot HART). 224 */ 225 if (riscv_hartid_to_cpuid(hartid) != smp_processor_id()) { 226 /* 227 * The INTC nodes of each CPU are suppliers for downstream 228 * interrupt controllers (such as PLIC, IMSIC and APLIC 229 * direct-mode) so we should mark an INTC node as initialized 230 * if we are not creating IRQ domain for it. 231 */ 232 fwnode_dev_initialized(of_fwnode_handle(node), true); 233 return 0; 234 } 235 236 if (of_device_is_compatible(node, "andestech,cpu-intc")) { 237 riscv_intc_custom_base = ANDES_SLI_CAUSE_BASE; 238 riscv_intc_custom_nr_irqs = ANDES_RV_IRQ_LAST; 239 chip = &andes_intc_chip; 240 } 241 242 return riscv_intc_init_common(of_node_to_fwnode(node), chip); 243 } 244 245 IRQCHIP_DECLARE(riscv, "riscv,cpu-intc", riscv_intc_init); 246 IRQCHIP_DECLARE(andes, "andestech,cpu-intc", riscv_intc_init); 247 248 #ifdef CONFIG_ACPI 249 250 static int __init riscv_intc_acpi_init(union acpi_subtable_headers *header, 251 const unsigned long end) 252 { 253 struct fwnode_handle *fn; 254 struct acpi_madt_rintc *rintc; 255 256 rintc = (struct acpi_madt_rintc *)header; 257 258 /* 259 * The ACPI MADT will have one INTC for each CPU (or HART) 260 * so riscv_intc_acpi_init() function will be called once 261 * for each INTC. We only do INTC initialization 262 * for the INTC belonging to the boot CPU (or boot HART). 263 */ 264 if (riscv_hartid_to_cpuid(rintc->hart_id) != smp_processor_id()) 265 return 0; 266 267 fn = irq_domain_alloc_named_fwnode("RISCV-INTC"); 268 if (!fn) { 269 pr_err("unable to allocate INTC FW node\n"); 270 return -ENOMEM; 271 } 272 273 return riscv_intc_init_common(fn, &riscv_intc_chip); 274 } 275 276 IRQCHIP_ACPI_DECLARE(riscv_intc, ACPI_MADT_TYPE_RINTC, NULL, 277 ACPI_MADT_RINTC_VERSION_V1, riscv_intc_acpi_init); 278 #endif 279