xref: /linux/drivers/irqchip/irq-renesas-rzg2l.c (revision be239684b18e1cdcafcf8c7face4a2f562c745ad) 
1 // SPDX-License-Identifier: GPL-2.0
2 /*
3  * Renesas RZ/G2L IRQC Driver
4  *
5  * Copyright (C) 2022 Renesas Electronics Corporation.
6  *
7  * Author: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
8  */
9 
10 #include <linux/bitfield.h>
11 #include <linux/clk.h>
12 #include <linux/err.h>
13 #include <linux/io.h>
14 #include <linux/irqchip.h>
15 #include <linux/irqdomain.h>
16 #include <linux/of_address.h>
17 #include <linux/of_platform.h>
18 #include <linux/pm_runtime.h>
19 #include <linux/reset.h>
20 #include <linux/spinlock.h>
21 #include <linux/syscore_ops.h>
22 
23 #define IRQC_IRQ_START			1
24 #define IRQC_IRQ_COUNT			8
25 #define IRQC_TINT_START			(IRQC_IRQ_START + IRQC_IRQ_COUNT)
26 #define IRQC_TINT_COUNT			32
27 #define IRQC_NUM_IRQ			(IRQC_TINT_START + IRQC_TINT_COUNT)
28 
29 #define ISCR				0x10
30 #define IITSR				0x14
31 #define TSCR				0x20
32 #define TITSR(n)			(0x24 + (n) * 4)
33 #define TITSR0_MAX_INT			16
34 #define TITSEL_WIDTH			0x2
35 #define TSSR(n)				(0x30 + ((n) * 4))
36 #define TIEN				BIT(7)
37 #define TSSEL_SHIFT(n)			(8 * (n))
38 #define TSSEL_MASK			GENMASK(7, 0)
39 #define IRQ_MASK			0x3
40 
41 #define TSSR_OFFSET(n)			((n) % 4)
42 #define TSSR_INDEX(n)			((n) / 4)
43 
44 #define TITSR_TITSEL_EDGE_RISING	0
45 #define TITSR_TITSEL_EDGE_FALLING	1
46 #define TITSR_TITSEL_LEVEL_HIGH		2
47 #define TITSR_TITSEL_LEVEL_LOW		3
48 
49 #define IITSR_IITSEL(n, sense)		((sense) << ((n) * 2))
50 #define IITSR_IITSEL_LEVEL_LOW		0
51 #define IITSR_IITSEL_EDGE_FALLING	1
52 #define IITSR_IITSEL_EDGE_RISING	2
53 #define IITSR_IITSEL_EDGE_BOTH		3
54 #define IITSR_IITSEL_MASK(n)		IITSR_IITSEL((n), 3)
55 
56 #define TINT_EXTRACT_HWIRQ(x)		FIELD_GET(GENMASK(15, 0), (x))
57 #define TINT_EXTRACT_GPIOINT(x)		FIELD_GET(GENMASK(31, 16), (x))
58 
59 /**
60  * struct rzg2l_irqc_reg_cache - registers cache (necessary for suspend/resume)
61  * @iitsr: IITSR register
62  * @titsr: TITSR registers
63  */
64 struct rzg2l_irqc_reg_cache {
65 	u32	iitsr;
66 	u32	titsr[2];
67 };
68 
69 /**
70  * struct rzg2l_irqc_priv - IRQ controller private data structure
71  * @base:	Controller's base address
72  * @fwspec:	IRQ firmware specific data
73  * @lock:	Lock to serialize access to hardware registers
74  * @cache:	Registers cache for suspend/resume
75  */
76 static struct rzg2l_irqc_priv {
77 	void __iomem			*base;
78 	struct irq_fwspec		fwspec[IRQC_NUM_IRQ];
79 	raw_spinlock_t			lock;
80 	struct rzg2l_irqc_reg_cache	cache;
81 } *rzg2l_irqc_data;
82 
83 static struct rzg2l_irqc_priv *irq_data_to_priv(struct irq_data *data)
84 {
85 	return data->domain->host_data;
86 }
87 
88 static void rzg2l_irq_eoi(struct irq_data *d)
89 {
90 	unsigned int hw_irq = irqd_to_hwirq(d) - IRQC_IRQ_START;
91 	struct rzg2l_irqc_priv *priv = irq_data_to_priv(d);
92 	u32 bit = BIT(hw_irq);
93 	u32 iitsr, iscr;
94 
95 	iscr = readl_relaxed(priv->base + ISCR);
96 	iitsr = readl_relaxed(priv->base + IITSR);
97 
98 	/*
99 	 * ISCR can only be cleared if the type is falling-edge, rising-edge or
100 	 * falling/rising-edge.
101 	 */
102 	if ((iscr & bit) && (iitsr & IITSR_IITSEL_MASK(hw_irq)))
103 		writel_relaxed(iscr & ~bit, priv->base + ISCR);
104 }
105 
106 static void rzg2l_tint_eoi(struct irq_data *d)
107 {
108 	unsigned int hw_irq = irqd_to_hwirq(d) - IRQC_TINT_START;
109 	struct rzg2l_irqc_priv *priv = irq_data_to_priv(d);
110 	u32 bit = BIT(hw_irq);
111 	u32 reg;
112 
113 	reg = readl_relaxed(priv->base + TSCR);
114 	if (reg & bit)
115 		writel_relaxed(reg & ~bit, priv->base + TSCR);
116 }
117 
118 static void rzg2l_irqc_eoi(struct irq_data *d)
119 {
120 	struct rzg2l_irqc_priv *priv = irq_data_to_priv(d);
121 	unsigned int hw_irq = irqd_to_hwirq(d);
122 
123 	raw_spin_lock(&priv->lock);
124 	if (hw_irq >= IRQC_IRQ_START && hw_irq <= IRQC_IRQ_COUNT)
125 		rzg2l_irq_eoi(d);
126 	else if (hw_irq >= IRQC_TINT_START && hw_irq < IRQC_NUM_IRQ)
127 		rzg2l_tint_eoi(d);
128 	raw_spin_unlock(&priv->lock);
129 	irq_chip_eoi_parent(d);
130 }
131 
132 static void rzg2l_irqc_irq_disable(struct irq_data *d)
133 {
134 	unsigned int hw_irq = irqd_to_hwirq(d);
135 
136 	if (hw_irq >= IRQC_TINT_START && hw_irq < IRQC_NUM_IRQ) {
137 		struct rzg2l_irqc_priv *priv = irq_data_to_priv(d);
138 		u32 offset = hw_irq - IRQC_TINT_START;
139 		u32 tssr_offset = TSSR_OFFSET(offset);
140 		u8 tssr_index = TSSR_INDEX(offset);
141 		u32 reg;
142 
143 		raw_spin_lock(&priv->lock);
144 		reg = readl_relaxed(priv->base + TSSR(tssr_index));
145 		reg &= ~(TSSEL_MASK << TSSEL_SHIFT(tssr_offset));
146 		writel_relaxed(reg, priv->base + TSSR(tssr_index));
147 		raw_spin_unlock(&priv->lock);
148 	}
149 	irq_chip_disable_parent(d);
150 }
151 
152 static void rzg2l_irqc_irq_enable(struct irq_data *d)
153 {
154 	unsigned int hw_irq = irqd_to_hwirq(d);
155 
156 	if (hw_irq >= IRQC_TINT_START && hw_irq < IRQC_NUM_IRQ) {
157 		unsigned long tint = (uintptr_t)irq_data_get_irq_chip_data(d);
158 		struct rzg2l_irqc_priv *priv = irq_data_to_priv(d);
159 		u32 offset = hw_irq - IRQC_TINT_START;
160 		u32 tssr_offset = TSSR_OFFSET(offset);
161 		u8 tssr_index = TSSR_INDEX(offset);
162 		u32 reg;
163 
164 		raw_spin_lock(&priv->lock);
165 		reg = readl_relaxed(priv->base + TSSR(tssr_index));
166 		reg |= (TIEN | tint) << TSSEL_SHIFT(tssr_offset);
167 		writel_relaxed(reg, priv->base + TSSR(tssr_index));
168 		raw_spin_unlock(&priv->lock);
169 	}
170 	irq_chip_enable_parent(d);
171 }
172 
173 static int rzg2l_irq_set_type(struct irq_data *d, unsigned int type)
174 {
175 	unsigned int hw_irq = irqd_to_hwirq(d) - IRQC_IRQ_START;
176 	struct rzg2l_irqc_priv *priv = irq_data_to_priv(d);
177 	u16 sense, tmp;
178 
179 	switch (type & IRQ_TYPE_SENSE_MASK) {
180 	case IRQ_TYPE_LEVEL_LOW:
181 		sense = IITSR_IITSEL_LEVEL_LOW;
182 		break;
183 
184 	case IRQ_TYPE_EDGE_FALLING:
185 		sense = IITSR_IITSEL_EDGE_FALLING;
186 		break;
187 
188 	case IRQ_TYPE_EDGE_RISING:
189 		sense = IITSR_IITSEL_EDGE_RISING;
190 		break;
191 
192 	case IRQ_TYPE_EDGE_BOTH:
193 		sense = IITSR_IITSEL_EDGE_BOTH;
194 		break;
195 
196 	default:
197 		return -EINVAL;
198 	}
199 
200 	raw_spin_lock(&priv->lock);
201 	tmp = readl_relaxed(priv->base + IITSR);
202 	tmp &= ~IITSR_IITSEL_MASK(hw_irq);
203 	tmp |= IITSR_IITSEL(hw_irq, sense);
204 	writel_relaxed(tmp, priv->base + IITSR);
205 	raw_spin_unlock(&priv->lock);
206 
207 	return 0;
208 }
209 
210 static int rzg2l_tint_set_edge(struct irq_data *d, unsigned int type)
211 {
212 	struct rzg2l_irqc_priv *priv = irq_data_to_priv(d);
213 	unsigned int hwirq = irqd_to_hwirq(d);
214 	u32 titseln = hwirq - IRQC_TINT_START;
215 	u8 index, sense;
216 	u32 reg;
217 
218 	switch (type & IRQ_TYPE_SENSE_MASK) {
219 	case IRQ_TYPE_EDGE_RISING:
220 		sense = TITSR_TITSEL_EDGE_RISING;
221 		break;
222 
223 	case IRQ_TYPE_EDGE_FALLING:
224 		sense = TITSR_TITSEL_EDGE_FALLING;
225 		break;
226 
227 	default:
228 		return -EINVAL;
229 	}
230 
231 	index = 0;
232 	if (titseln >= TITSR0_MAX_INT) {
233 		titseln -= TITSR0_MAX_INT;
234 		index = 1;
235 	}
236 
237 	raw_spin_lock(&priv->lock);
238 	reg = readl_relaxed(priv->base + TITSR(index));
239 	reg &= ~(IRQ_MASK << (titseln * TITSEL_WIDTH));
240 	reg |= sense << (titseln * TITSEL_WIDTH);
241 	writel_relaxed(reg, priv->base + TITSR(index));
242 	raw_spin_unlock(&priv->lock);
243 
244 	return 0;
245 }
246 
247 static int rzg2l_irqc_set_type(struct irq_data *d, unsigned int type)
248 {
249 	unsigned int hw_irq = irqd_to_hwirq(d);
250 	int ret = -EINVAL;
251 
252 	if (hw_irq >= IRQC_IRQ_START && hw_irq <= IRQC_IRQ_COUNT)
253 		ret = rzg2l_irq_set_type(d, type);
254 	else if (hw_irq >= IRQC_TINT_START && hw_irq < IRQC_NUM_IRQ)
255 		ret = rzg2l_tint_set_edge(d, type);
256 	if (ret)
257 		return ret;
258 
259 	return irq_chip_set_type_parent(d, IRQ_TYPE_LEVEL_HIGH);
260 }
261 
262 static int rzg2l_irqc_irq_suspend(void)
263 {
264 	struct rzg2l_irqc_reg_cache *cache = &rzg2l_irqc_data->cache;
265 	void __iomem *base = rzg2l_irqc_data->base;
266 
267 	cache->iitsr = readl_relaxed(base + IITSR);
268 	for (u8 i = 0; i < 2; i++)
269 		cache->titsr[i] = readl_relaxed(base + TITSR(i));
270 
271 	return 0;
272 }
273 
274 static void rzg2l_irqc_irq_resume(void)
275 {
276 	struct rzg2l_irqc_reg_cache *cache = &rzg2l_irqc_data->cache;
277 	void __iomem *base = rzg2l_irqc_data->base;
278 
279 	/*
280 	 * Restore only interrupt type. TSSRx will be restored at the
281 	 * request of pin controller to avoid spurious interrupts due
282 	 * to invalid PIN states.
283 	 */
284 	for (u8 i = 0; i < 2; i++)
285 		writel_relaxed(cache->titsr[i], base + TITSR(i));
286 	writel_relaxed(cache->iitsr, base + IITSR);
287 }
288 
289 static struct syscore_ops rzg2l_irqc_syscore_ops = {
290 	.suspend	= rzg2l_irqc_irq_suspend,
291 	.resume		= rzg2l_irqc_irq_resume,
292 };
293 
294 static const struct irq_chip irqc_chip = {
295 	.name			= "rzg2l-irqc",
296 	.irq_eoi		= rzg2l_irqc_eoi,
297 	.irq_mask		= irq_chip_mask_parent,
298 	.irq_unmask		= irq_chip_unmask_parent,
299 	.irq_disable		= rzg2l_irqc_irq_disable,
300 	.irq_enable		= rzg2l_irqc_irq_enable,
301 	.irq_get_irqchip_state	= irq_chip_get_parent_state,
302 	.irq_set_irqchip_state	= irq_chip_set_parent_state,
303 	.irq_retrigger		= irq_chip_retrigger_hierarchy,
304 	.irq_set_type		= rzg2l_irqc_set_type,
305 	.irq_set_affinity	= irq_chip_set_affinity_parent,
306 	.flags			= IRQCHIP_MASK_ON_SUSPEND |
307 				  IRQCHIP_SET_TYPE_MASKED |
308 				  IRQCHIP_SKIP_SET_WAKE,
309 };
310 
311 static int rzg2l_irqc_alloc(struct irq_domain *domain, unsigned int virq,
312 			    unsigned int nr_irqs, void *arg)
313 {
314 	struct rzg2l_irqc_priv *priv = domain->host_data;
315 	unsigned long tint = 0;
316 	irq_hw_number_t hwirq;
317 	unsigned int type;
318 	int ret;
319 
320 	ret = irq_domain_translate_twocell(domain, arg, &hwirq, &type);
321 	if (ret)
322 		return ret;
323 
324 	/*
325 	 * For TINT interrupts ie where pinctrl driver is child of irqc domain
326 	 * the hwirq and TINT are encoded in fwspec->param[0].
327 	 * hwirq for TINT range from 9-40, hwirq is embedded 0-15 bits and TINT
328 	 * from 16-31 bits. TINT from the pinctrl driver needs to be programmed
329 	 * in IRQC registers to enable a given gpio pin as interrupt.
330 	 */
331 	if (hwirq > IRQC_IRQ_COUNT) {
332 		tint = TINT_EXTRACT_GPIOINT(hwirq);
333 		hwirq = TINT_EXTRACT_HWIRQ(hwirq);
334 
335 		if (hwirq < IRQC_TINT_START)
336 			return -EINVAL;
337 	}
338 
339 	if (hwirq > (IRQC_NUM_IRQ - 1))
340 		return -EINVAL;
341 
342 	ret = irq_domain_set_hwirq_and_chip(domain, virq, hwirq, &irqc_chip,
343 					    (void *)(uintptr_t)tint);
344 	if (ret)
345 		return ret;
346 
347 	return irq_domain_alloc_irqs_parent(domain, virq, nr_irqs, &priv->fwspec[hwirq]);
348 }
349 
350 static const struct irq_domain_ops rzg2l_irqc_domain_ops = {
351 	.alloc = rzg2l_irqc_alloc,
352 	.free = irq_domain_free_irqs_common,
353 	.translate = irq_domain_translate_twocell,
354 };
355 
356 static int rzg2l_irqc_parse_interrupts(struct rzg2l_irqc_priv *priv,
357 				       struct device_node *np)
358 {
359 	struct of_phandle_args map;
360 	unsigned int i;
361 	int ret;
362 
363 	for (i = 0; i < IRQC_NUM_IRQ; i++) {
364 		ret = of_irq_parse_one(np, i, &map);
365 		if (ret)
366 			return ret;
367 		of_phandle_args_to_fwspec(np, map.args, map.args_count,
368 					  &priv->fwspec[i]);
369 	}
370 
371 	return 0;
372 }
373 
374 static int rzg2l_irqc_init(struct device_node *node, struct device_node *parent)
375 {
376 	struct irq_domain *irq_domain, *parent_domain;
377 	struct platform_device *pdev;
378 	struct reset_control *resetn;
379 	int ret;
380 
381 	pdev = of_find_device_by_node(node);
382 	if (!pdev)
383 		return -ENODEV;
384 
385 	parent_domain = irq_find_host(parent);
386 	if (!parent_domain) {
387 		dev_err(&pdev->dev, "cannot find parent domain\n");
388 		return -ENODEV;
389 	}
390 
391 	rzg2l_irqc_data = devm_kzalloc(&pdev->dev, sizeof(*rzg2l_irqc_data), GFP_KERNEL);
392 	if (!rzg2l_irqc_data)
393 		return -ENOMEM;
394 
395 	rzg2l_irqc_data->base = devm_of_iomap(&pdev->dev, pdev->dev.of_node, 0, NULL);
396 	if (IS_ERR(rzg2l_irqc_data->base))
397 		return PTR_ERR(rzg2l_irqc_data->base);
398 
399 	ret = rzg2l_irqc_parse_interrupts(rzg2l_irqc_data, node);
400 	if (ret) {
401 		dev_err(&pdev->dev, "cannot parse interrupts: %d\n", ret);
402 		return ret;
403 	}
404 
405 	resetn = devm_reset_control_get_exclusive(&pdev->dev, NULL);
406 	if (IS_ERR(resetn))
407 		return PTR_ERR(resetn);
408 
409 	ret = reset_control_deassert(resetn);
410 	if (ret) {
411 		dev_err(&pdev->dev, "failed to deassert resetn pin, %d\n", ret);
412 		return ret;
413 	}
414 
415 	pm_runtime_enable(&pdev->dev);
416 	ret = pm_runtime_resume_and_get(&pdev->dev);
417 	if (ret < 0) {
418 		dev_err(&pdev->dev, "pm_runtime_resume_and_get failed: %d\n", ret);
419 		goto pm_disable;
420 	}
421 
422 	raw_spin_lock_init(&rzg2l_irqc_data->lock);
423 
424 	irq_domain = irq_domain_add_hierarchy(parent_domain, 0, IRQC_NUM_IRQ,
425 					      node, &rzg2l_irqc_domain_ops,
426 					      rzg2l_irqc_data);
427 	if (!irq_domain) {
428 		dev_err(&pdev->dev, "failed to add irq domain\n");
429 		ret = -ENOMEM;
430 		goto pm_put;
431 	}
432 
433 	register_syscore_ops(&rzg2l_irqc_syscore_ops);
434 
435 	return 0;
436 
437 pm_put:
438 	pm_runtime_put(&pdev->dev);
439 pm_disable:
440 	pm_runtime_disable(&pdev->dev);
441 	reset_control_assert(resetn);
442 	return ret;
443 }
444 
445 IRQCHIP_PLATFORM_DRIVER_BEGIN(rzg2l_irqc)
446 IRQCHIP_MATCH("renesas,rzg2l-irqc", rzg2l_irqc_init)
447 IRQCHIP_PLATFORM_DRIVER_END(rzg2l_irqc)
448 MODULE_AUTHOR("Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>");
449 MODULE_DESCRIPTION("Renesas RZ/G2L IRQC Driver");
450