1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Renesas RZ/G2L IRQC Driver 4 * 5 * Copyright (C) 2022 Renesas Electronics Corporation. 6 * 7 * Author: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> 8 */ 9 10 #include <linux/bitfield.h> 11 #include <linux/clk.h> 12 #include <linux/err.h> 13 #include <linux/io.h> 14 #include <linux/irqchip.h> 15 #include <linux/irqdomain.h> 16 #include <linux/of_address.h> 17 #include <linux/of_platform.h> 18 #include <linux/pm_runtime.h> 19 #include <linux/reset.h> 20 #include <linux/spinlock.h> 21 #include <linux/syscore_ops.h> 22 23 #define IRQC_IRQ_START 1 24 #define IRQC_IRQ_COUNT 8 25 #define IRQC_TINT_START (IRQC_IRQ_START + IRQC_IRQ_COUNT) 26 #define IRQC_TINT_COUNT 32 27 #define IRQC_NUM_IRQ (IRQC_TINT_START + IRQC_TINT_COUNT) 28 29 #define ISCR 0x10 30 #define IITSR 0x14 31 #define TSCR 0x20 32 #define TITSR(n) (0x24 + (n) * 4) 33 #define TITSR0_MAX_INT 16 34 #define TITSEL_WIDTH 0x2 35 #define TSSR(n) (0x30 + ((n) * 4)) 36 #define TIEN BIT(7) 37 #define TSSEL_SHIFT(n) (8 * (n)) 38 #define TSSEL_MASK GENMASK(7, 0) 39 #define IRQ_MASK 0x3 40 41 #define TSSR_OFFSET(n) ((n) % 4) 42 #define TSSR_INDEX(n) ((n) / 4) 43 44 #define TITSR_TITSEL_EDGE_RISING 0 45 #define TITSR_TITSEL_EDGE_FALLING 1 46 #define TITSR_TITSEL_LEVEL_HIGH 2 47 #define TITSR_TITSEL_LEVEL_LOW 3 48 49 #define IITSR_IITSEL(n, sense) ((sense) << ((n) * 2)) 50 #define IITSR_IITSEL_LEVEL_LOW 0 51 #define IITSR_IITSEL_EDGE_FALLING 1 52 #define IITSR_IITSEL_EDGE_RISING 2 53 #define IITSR_IITSEL_EDGE_BOTH 3 54 #define IITSR_IITSEL_MASK(n) IITSR_IITSEL((n), 3) 55 56 #define TINT_EXTRACT_HWIRQ(x) FIELD_GET(GENMASK(15, 0), (x)) 57 #define TINT_EXTRACT_GPIOINT(x) FIELD_GET(GENMASK(31, 16), (x)) 58 59 /** 60 * struct rzg2l_irqc_reg_cache - registers cache (necessary for suspend/resume) 61 * @iitsr: IITSR register 62 * @titsr: TITSR registers 63 */ 64 struct rzg2l_irqc_reg_cache { 65 u32 iitsr; 66 u32 titsr[2]; 67 }; 68 69 /** 70 * struct rzg2l_irqc_priv - IRQ controller private data structure 71 * @base: Controller's base address 72 * @fwspec: IRQ firmware specific data 73 * @lock: Lock to serialize access to hardware registers 74 * @cache: Registers cache for suspend/resume 75 */ 76 static struct rzg2l_irqc_priv { 77 void __iomem *base; 78 struct irq_fwspec fwspec[IRQC_NUM_IRQ]; 79 raw_spinlock_t lock; 80 struct rzg2l_irqc_reg_cache cache; 81 } *rzg2l_irqc_data; 82 83 static struct rzg2l_irqc_priv *irq_data_to_priv(struct irq_data *data) 84 { 85 return data->domain->host_data; 86 } 87 88 static void rzg2l_clear_irq_int(struct rzg2l_irqc_priv *priv, unsigned int hwirq) 89 { 90 unsigned int hw_irq = hwirq - IRQC_IRQ_START; 91 u32 bit = BIT(hw_irq); 92 u32 iitsr, iscr; 93 94 iscr = readl_relaxed(priv->base + ISCR); 95 iitsr = readl_relaxed(priv->base + IITSR); 96 97 /* 98 * ISCR can only be cleared if the type is falling-edge, rising-edge or 99 * falling/rising-edge. 100 */ 101 if ((iscr & bit) && (iitsr & IITSR_IITSEL_MASK(hw_irq))) { 102 writel_relaxed(iscr & ~bit, priv->base + ISCR); 103 /* 104 * Enforce that the posted write is flushed to prevent that the 105 * just handled interrupt is raised again. 106 */ 107 readl_relaxed(priv->base + ISCR); 108 } 109 } 110 111 static void rzg2l_clear_tint_int(struct rzg2l_irqc_priv *priv, unsigned int hwirq) 112 { 113 u32 bit = BIT(hwirq - IRQC_TINT_START); 114 u32 reg; 115 116 reg = readl_relaxed(priv->base + TSCR); 117 if (reg & bit) { 118 writel_relaxed(reg & ~bit, priv->base + TSCR); 119 /* 120 * Enforce that the posted write is flushed to prevent that the 121 * just handled interrupt is raised again. 122 */ 123 readl_relaxed(priv->base + TSCR); 124 } 125 } 126 127 static void rzg2l_irqc_eoi(struct irq_data *d) 128 { 129 struct rzg2l_irqc_priv *priv = irq_data_to_priv(d); 130 unsigned int hw_irq = irqd_to_hwirq(d); 131 132 raw_spin_lock(&priv->lock); 133 if (hw_irq >= IRQC_IRQ_START && hw_irq <= IRQC_IRQ_COUNT) 134 rzg2l_clear_irq_int(priv, hw_irq); 135 else if (hw_irq >= IRQC_TINT_START && hw_irq < IRQC_NUM_IRQ) 136 rzg2l_clear_tint_int(priv, hw_irq); 137 raw_spin_unlock(&priv->lock); 138 irq_chip_eoi_parent(d); 139 } 140 141 static void rzg2l_tint_irq_endisable(struct irq_data *d, bool enable) 142 { 143 unsigned int hw_irq = irqd_to_hwirq(d); 144 145 if (hw_irq >= IRQC_TINT_START && hw_irq < IRQC_NUM_IRQ) { 146 struct rzg2l_irqc_priv *priv = irq_data_to_priv(d); 147 u32 offset = hw_irq - IRQC_TINT_START; 148 u32 tssr_offset = TSSR_OFFSET(offset); 149 u8 tssr_index = TSSR_INDEX(offset); 150 u32 reg; 151 152 raw_spin_lock(&priv->lock); 153 reg = readl_relaxed(priv->base + TSSR(tssr_index)); 154 if (enable) 155 reg |= TIEN << TSSEL_SHIFT(tssr_offset); 156 else 157 reg &= ~(TIEN << TSSEL_SHIFT(tssr_offset)); 158 writel_relaxed(reg, priv->base + TSSR(tssr_index)); 159 raw_spin_unlock(&priv->lock); 160 } 161 } 162 163 static void rzg2l_irqc_irq_disable(struct irq_data *d) 164 { 165 rzg2l_tint_irq_endisable(d, false); 166 irq_chip_disable_parent(d); 167 } 168 169 static void rzg2l_irqc_irq_enable(struct irq_data *d) 170 { 171 rzg2l_tint_irq_endisable(d, true); 172 irq_chip_enable_parent(d); 173 } 174 175 static int rzg2l_irq_set_type(struct irq_data *d, unsigned int type) 176 { 177 struct rzg2l_irqc_priv *priv = irq_data_to_priv(d); 178 unsigned int hwirq = irqd_to_hwirq(d); 179 u32 iitseln = hwirq - IRQC_IRQ_START; 180 bool clear_irq_int = false; 181 u16 sense, tmp; 182 183 switch (type & IRQ_TYPE_SENSE_MASK) { 184 case IRQ_TYPE_LEVEL_LOW: 185 sense = IITSR_IITSEL_LEVEL_LOW; 186 break; 187 188 case IRQ_TYPE_EDGE_FALLING: 189 sense = IITSR_IITSEL_EDGE_FALLING; 190 clear_irq_int = true; 191 break; 192 193 case IRQ_TYPE_EDGE_RISING: 194 sense = IITSR_IITSEL_EDGE_RISING; 195 clear_irq_int = true; 196 break; 197 198 case IRQ_TYPE_EDGE_BOTH: 199 sense = IITSR_IITSEL_EDGE_BOTH; 200 clear_irq_int = true; 201 break; 202 203 default: 204 return -EINVAL; 205 } 206 207 raw_spin_lock(&priv->lock); 208 tmp = readl_relaxed(priv->base + IITSR); 209 tmp &= ~IITSR_IITSEL_MASK(iitseln); 210 tmp |= IITSR_IITSEL(iitseln, sense); 211 if (clear_irq_int) 212 rzg2l_clear_irq_int(priv, hwirq); 213 writel_relaxed(tmp, priv->base + IITSR); 214 raw_spin_unlock(&priv->lock); 215 216 return 0; 217 } 218 219 static u32 rzg2l_disable_tint_and_set_tint_source(struct irq_data *d, struct rzg2l_irqc_priv *priv, 220 u32 reg, u32 tssr_offset, u8 tssr_index) 221 { 222 u32 tint = (u32)(uintptr_t)irq_data_get_irq_chip_data(d); 223 u32 tien = reg & (TIEN << TSSEL_SHIFT(tssr_offset)); 224 225 /* Clear the relevant byte in reg */ 226 reg &= ~(TSSEL_MASK << TSSEL_SHIFT(tssr_offset)); 227 /* Set TINT and leave TIEN clear */ 228 reg |= tint << TSSEL_SHIFT(tssr_offset); 229 writel_relaxed(reg, priv->base + TSSR(tssr_index)); 230 231 return reg | tien; 232 } 233 234 static int rzg2l_tint_set_edge(struct irq_data *d, unsigned int type) 235 { 236 struct rzg2l_irqc_priv *priv = irq_data_to_priv(d); 237 unsigned int hwirq = irqd_to_hwirq(d); 238 u32 titseln = hwirq - IRQC_TINT_START; 239 u32 tssr_offset = TSSR_OFFSET(titseln); 240 u8 tssr_index = TSSR_INDEX(titseln); 241 u8 index, sense; 242 u32 reg, tssr; 243 244 switch (type & IRQ_TYPE_SENSE_MASK) { 245 case IRQ_TYPE_EDGE_RISING: 246 sense = TITSR_TITSEL_EDGE_RISING; 247 break; 248 249 case IRQ_TYPE_EDGE_FALLING: 250 sense = TITSR_TITSEL_EDGE_FALLING; 251 break; 252 253 default: 254 return -EINVAL; 255 } 256 257 index = 0; 258 if (titseln >= TITSR0_MAX_INT) { 259 titseln -= TITSR0_MAX_INT; 260 index = 1; 261 } 262 263 raw_spin_lock(&priv->lock); 264 tssr = readl_relaxed(priv->base + TSSR(tssr_index)); 265 tssr = rzg2l_disable_tint_and_set_tint_source(d, priv, tssr, tssr_offset, tssr_index); 266 reg = readl_relaxed(priv->base + TITSR(index)); 267 reg &= ~(IRQ_MASK << (titseln * TITSEL_WIDTH)); 268 reg |= sense << (titseln * TITSEL_WIDTH); 269 writel_relaxed(reg, priv->base + TITSR(index)); 270 rzg2l_clear_tint_int(priv, hwirq); 271 writel_relaxed(tssr, priv->base + TSSR(tssr_index)); 272 raw_spin_unlock(&priv->lock); 273 274 return 0; 275 } 276 277 static int rzg2l_irqc_set_type(struct irq_data *d, unsigned int type) 278 { 279 unsigned int hw_irq = irqd_to_hwirq(d); 280 int ret = -EINVAL; 281 282 if (hw_irq >= IRQC_IRQ_START && hw_irq <= IRQC_IRQ_COUNT) 283 ret = rzg2l_irq_set_type(d, type); 284 else if (hw_irq >= IRQC_TINT_START && hw_irq < IRQC_NUM_IRQ) 285 ret = rzg2l_tint_set_edge(d, type); 286 if (ret) 287 return ret; 288 289 return irq_chip_set_type_parent(d, IRQ_TYPE_LEVEL_HIGH); 290 } 291 292 static int rzg2l_irqc_irq_suspend(void) 293 { 294 struct rzg2l_irqc_reg_cache *cache = &rzg2l_irqc_data->cache; 295 void __iomem *base = rzg2l_irqc_data->base; 296 297 cache->iitsr = readl_relaxed(base + IITSR); 298 for (u8 i = 0; i < 2; i++) 299 cache->titsr[i] = readl_relaxed(base + TITSR(i)); 300 301 return 0; 302 } 303 304 static void rzg2l_irqc_irq_resume(void) 305 { 306 struct rzg2l_irqc_reg_cache *cache = &rzg2l_irqc_data->cache; 307 void __iomem *base = rzg2l_irqc_data->base; 308 309 /* 310 * Restore only interrupt type. TSSRx will be restored at the 311 * request of pin controller to avoid spurious interrupts due 312 * to invalid PIN states. 313 */ 314 for (u8 i = 0; i < 2; i++) 315 writel_relaxed(cache->titsr[i], base + TITSR(i)); 316 writel_relaxed(cache->iitsr, base + IITSR); 317 } 318 319 static struct syscore_ops rzg2l_irqc_syscore_ops = { 320 .suspend = rzg2l_irqc_irq_suspend, 321 .resume = rzg2l_irqc_irq_resume, 322 }; 323 324 static const struct irq_chip irqc_chip = { 325 .name = "rzg2l-irqc", 326 .irq_eoi = rzg2l_irqc_eoi, 327 .irq_mask = irq_chip_mask_parent, 328 .irq_unmask = irq_chip_unmask_parent, 329 .irq_disable = rzg2l_irqc_irq_disable, 330 .irq_enable = rzg2l_irqc_irq_enable, 331 .irq_get_irqchip_state = irq_chip_get_parent_state, 332 .irq_set_irqchip_state = irq_chip_set_parent_state, 333 .irq_retrigger = irq_chip_retrigger_hierarchy, 334 .irq_set_type = rzg2l_irqc_set_type, 335 .irq_set_affinity = irq_chip_set_affinity_parent, 336 .flags = IRQCHIP_MASK_ON_SUSPEND | 337 IRQCHIP_SET_TYPE_MASKED | 338 IRQCHIP_SKIP_SET_WAKE, 339 }; 340 341 static int rzg2l_irqc_alloc(struct irq_domain *domain, unsigned int virq, 342 unsigned int nr_irqs, void *arg) 343 { 344 struct rzg2l_irqc_priv *priv = domain->host_data; 345 unsigned long tint = 0; 346 irq_hw_number_t hwirq; 347 unsigned int type; 348 int ret; 349 350 ret = irq_domain_translate_twocell(domain, arg, &hwirq, &type); 351 if (ret) 352 return ret; 353 354 /* 355 * For TINT interrupts ie where pinctrl driver is child of irqc domain 356 * the hwirq and TINT are encoded in fwspec->param[0]. 357 * hwirq for TINT range from 9-40, hwirq is embedded 0-15 bits and TINT 358 * from 16-31 bits. TINT from the pinctrl driver needs to be programmed 359 * in IRQC registers to enable a given gpio pin as interrupt. 360 */ 361 if (hwirq > IRQC_IRQ_COUNT) { 362 tint = TINT_EXTRACT_GPIOINT(hwirq); 363 hwirq = TINT_EXTRACT_HWIRQ(hwirq); 364 365 if (hwirq < IRQC_TINT_START) 366 return -EINVAL; 367 } 368 369 if (hwirq > (IRQC_NUM_IRQ - 1)) 370 return -EINVAL; 371 372 ret = irq_domain_set_hwirq_and_chip(domain, virq, hwirq, &irqc_chip, 373 (void *)(uintptr_t)tint); 374 if (ret) 375 return ret; 376 377 return irq_domain_alloc_irqs_parent(domain, virq, nr_irqs, &priv->fwspec[hwirq]); 378 } 379 380 static const struct irq_domain_ops rzg2l_irqc_domain_ops = { 381 .alloc = rzg2l_irqc_alloc, 382 .free = irq_domain_free_irqs_common, 383 .translate = irq_domain_translate_twocell, 384 }; 385 386 static int rzg2l_irqc_parse_interrupts(struct rzg2l_irqc_priv *priv, 387 struct device_node *np) 388 { 389 struct of_phandle_args map; 390 unsigned int i; 391 int ret; 392 393 for (i = 0; i < IRQC_NUM_IRQ; i++) { 394 ret = of_irq_parse_one(np, i, &map); 395 if (ret) 396 return ret; 397 of_phandle_args_to_fwspec(np, map.args, map.args_count, 398 &priv->fwspec[i]); 399 } 400 401 return 0; 402 } 403 404 static int rzg2l_irqc_init(struct device_node *node, struct device_node *parent) 405 { 406 struct irq_domain *irq_domain, *parent_domain; 407 struct platform_device *pdev; 408 struct reset_control *resetn; 409 int ret; 410 411 pdev = of_find_device_by_node(node); 412 if (!pdev) 413 return -ENODEV; 414 415 parent_domain = irq_find_host(parent); 416 if (!parent_domain) { 417 dev_err(&pdev->dev, "cannot find parent domain\n"); 418 return -ENODEV; 419 } 420 421 rzg2l_irqc_data = devm_kzalloc(&pdev->dev, sizeof(*rzg2l_irqc_data), GFP_KERNEL); 422 if (!rzg2l_irqc_data) 423 return -ENOMEM; 424 425 rzg2l_irqc_data->base = devm_of_iomap(&pdev->dev, pdev->dev.of_node, 0, NULL); 426 if (IS_ERR(rzg2l_irqc_data->base)) 427 return PTR_ERR(rzg2l_irqc_data->base); 428 429 ret = rzg2l_irqc_parse_interrupts(rzg2l_irqc_data, node); 430 if (ret) { 431 dev_err(&pdev->dev, "cannot parse interrupts: %d\n", ret); 432 return ret; 433 } 434 435 resetn = devm_reset_control_get_exclusive(&pdev->dev, NULL); 436 if (IS_ERR(resetn)) 437 return PTR_ERR(resetn); 438 439 ret = reset_control_deassert(resetn); 440 if (ret) { 441 dev_err(&pdev->dev, "failed to deassert resetn pin, %d\n", ret); 442 return ret; 443 } 444 445 pm_runtime_enable(&pdev->dev); 446 ret = pm_runtime_resume_and_get(&pdev->dev); 447 if (ret < 0) { 448 dev_err(&pdev->dev, "pm_runtime_resume_and_get failed: %d\n", ret); 449 goto pm_disable; 450 } 451 452 raw_spin_lock_init(&rzg2l_irqc_data->lock); 453 454 irq_domain = irq_domain_add_hierarchy(parent_domain, 0, IRQC_NUM_IRQ, 455 node, &rzg2l_irqc_domain_ops, 456 rzg2l_irqc_data); 457 if (!irq_domain) { 458 dev_err(&pdev->dev, "failed to add irq domain\n"); 459 ret = -ENOMEM; 460 goto pm_put; 461 } 462 463 register_syscore_ops(&rzg2l_irqc_syscore_ops); 464 465 return 0; 466 467 pm_put: 468 pm_runtime_put(&pdev->dev); 469 pm_disable: 470 pm_runtime_disable(&pdev->dev); 471 reset_control_assert(resetn); 472 return ret; 473 } 474 475 IRQCHIP_PLATFORM_DRIVER_BEGIN(rzg2l_irqc) 476 IRQCHIP_MATCH("renesas,rzg2l-irqc", rzg2l_irqc_init) 477 IRQCHIP_PLATFORM_DRIVER_END(rzg2l_irqc) 478 MODULE_AUTHOR("Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>"); 479 MODULE_DESCRIPTION("Renesas RZ/G2L IRQC Driver"); 480