1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Renesas RZ/A1 IRQC Driver 4 * 5 * Copyright (C) 2019 Glider bvba 6 */ 7 8 #include <linux/err.h> 9 #include <linux/init.h> 10 #include <linux/interrupt.h> 11 #include <linux/io.h> 12 #include <linux/irqdomain.h> 13 #include <linux/irq.h> 14 #include <linux/module.h> 15 #include <linux/of_irq.h> 16 #include <linux/platform_device.h> 17 #include <linux/slab.h> 18 19 #include <dt-bindings/interrupt-controller/arm-gic.h> 20 21 #define IRQC_NUM_IRQ 8 22 23 #define ICR0 0 /* Interrupt Control Register 0 */ 24 25 #define ICR0_NMIL BIT(15) /* NMI Input Level (0=low, 1=high) */ 26 #define ICR0_NMIE BIT(8) /* Edge Select (0=falling, 1=rising) */ 27 #define ICR0_NMIF BIT(1) /* NMI Interrupt Request */ 28 29 #define ICR1 2 /* Interrupt Control Register 1 */ 30 31 #define ICR1_IRQS(n, sense) ((sense) << ((n) * 2)) /* IRQ Sense Select */ 32 #define ICR1_IRQS_LEVEL_LOW 0 33 #define ICR1_IRQS_EDGE_FALLING 1 34 #define ICR1_IRQS_EDGE_RISING 2 35 #define ICR1_IRQS_EDGE_BOTH 3 36 #define ICR1_IRQS_MASK(n) ICR1_IRQS((n), 3) 37 38 #define IRQRR 4 /* IRQ Interrupt Request Register */ 39 40 41 struct rza1_irqc_priv { 42 struct device *dev; 43 void __iomem *base; 44 struct irq_chip chip; 45 struct irq_domain *irq_domain; 46 struct of_phandle_args map[IRQC_NUM_IRQ]; 47 }; 48 49 static struct rza1_irqc_priv *irq_data_to_priv(struct irq_data *data) 50 { 51 return data->domain->host_data; 52 } 53 54 static void rza1_irqc_eoi(struct irq_data *d) 55 { 56 struct rza1_irqc_priv *priv = irq_data_to_priv(d); 57 u16 bit = BIT(irqd_to_hwirq(d)); 58 u16 tmp; 59 60 tmp = readw_relaxed(priv->base + IRQRR); 61 if (tmp & bit) 62 writew_relaxed(GENMASK(IRQC_NUM_IRQ - 1, 0) & ~bit, 63 priv->base + IRQRR); 64 65 irq_chip_eoi_parent(d); 66 } 67 68 static int rza1_irqc_set_type(struct irq_data *d, unsigned int type) 69 { 70 struct rza1_irqc_priv *priv = irq_data_to_priv(d); 71 unsigned int hw_irq = irqd_to_hwirq(d); 72 u16 sense, tmp; 73 74 switch (type & IRQ_TYPE_SENSE_MASK) { 75 case IRQ_TYPE_LEVEL_LOW: 76 sense = ICR1_IRQS_LEVEL_LOW; 77 break; 78 79 case IRQ_TYPE_EDGE_FALLING: 80 sense = ICR1_IRQS_EDGE_FALLING; 81 break; 82 83 case IRQ_TYPE_EDGE_RISING: 84 sense = ICR1_IRQS_EDGE_RISING; 85 break; 86 87 case IRQ_TYPE_EDGE_BOTH: 88 sense = ICR1_IRQS_EDGE_BOTH; 89 break; 90 91 default: 92 return -EINVAL; 93 } 94 95 tmp = readw_relaxed(priv->base + ICR1); 96 tmp &= ~ICR1_IRQS_MASK(hw_irq); 97 tmp |= ICR1_IRQS(hw_irq, sense); 98 writew_relaxed(tmp, priv->base + ICR1); 99 return 0; 100 } 101 102 static int rza1_irqc_alloc(struct irq_domain *domain, unsigned int virq, 103 unsigned int nr_irqs, void *arg) 104 { 105 struct rza1_irqc_priv *priv = domain->host_data; 106 struct irq_fwspec *fwspec = arg; 107 unsigned int hwirq = fwspec->param[0]; 108 struct irq_fwspec spec; 109 unsigned int i; 110 int ret; 111 112 ret = irq_domain_set_hwirq_and_chip(domain, virq, hwirq, &priv->chip, 113 priv); 114 if (ret) 115 return ret; 116 117 spec.fwnode = &priv->dev->of_node->fwnode; 118 spec.param_count = priv->map[hwirq].args_count; 119 for (i = 0; i < spec.param_count; i++) 120 spec.param[i] = priv->map[hwirq].args[i]; 121 122 return irq_domain_alloc_irqs_parent(domain, virq, nr_irqs, &spec); 123 } 124 125 static int rza1_irqc_translate(struct irq_domain *domain, 126 struct irq_fwspec *fwspec, unsigned long *hwirq, 127 unsigned int *type) 128 { 129 if (fwspec->param_count != 2 || fwspec->param[0] >= IRQC_NUM_IRQ) 130 return -EINVAL; 131 132 *hwirq = fwspec->param[0]; 133 *type = fwspec->param[1]; 134 return 0; 135 } 136 137 static const struct irq_domain_ops rza1_irqc_domain_ops = { 138 .alloc = rza1_irqc_alloc, 139 .translate = rza1_irqc_translate, 140 }; 141 142 static int rza1_irqc_parse_map(struct rza1_irqc_priv *priv, 143 struct device_node *gic_node) 144 { 145 struct device *dev = priv->dev; 146 unsigned int imaplen, i, j; 147 struct device_node *ipar; 148 const __be32 *imap; 149 u32 intsize; 150 int ret; 151 152 imap = of_get_property(dev->of_node, "interrupt-map", &imaplen); 153 if (!imap) 154 return -EINVAL; 155 156 for (i = 0; i < IRQC_NUM_IRQ; i++) { 157 if (imaplen < 3) 158 return -EINVAL; 159 160 /* Check interrupt number, ignore sense */ 161 if (be32_to_cpup(imap) != i) 162 return -EINVAL; 163 164 ipar = of_find_node_by_phandle(be32_to_cpup(imap + 2)); 165 if (ipar != gic_node) { 166 of_node_put(ipar); 167 return -EINVAL; 168 } 169 170 imap += 3; 171 imaplen -= 3; 172 173 ret = of_property_read_u32(ipar, "#interrupt-cells", &intsize); 174 of_node_put(ipar); 175 if (ret) 176 return ret; 177 178 if (imaplen < intsize) 179 return -EINVAL; 180 181 priv->map[i].args_count = intsize; 182 for (j = 0; j < intsize; j++) 183 priv->map[i].args[j] = be32_to_cpup(imap++); 184 185 imaplen -= intsize; 186 } 187 188 return 0; 189 } 190 191 static int rza1_irqc_probe(struct platform_device *pdev) 192 { 193 struct device *dev = &pdev->dev; 194 struct device_node *np = dev->of_node; 195 struct irq_domain *parent = NULL; 196 struct device_node *gic_node; 197 struct rza1_irqc_priv *priv; 198 int ret; 199 200 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); 201 if (!priv) 202 return -ENOMEM; 203 204 platform_set_drvdata(pdev, priv); 205 priv->dev = dev; 206 207 priv->base = devm_platform_ioremap_resource(pdev, 0); 208 if (IS_ERR(priv->base)) 209 return PTR_ERR(priv->base); 210 211 gic_node = of_irq_find_parent(np); 212 if (gic_node) 213 parent = irq_find_host(gic_node); 214 215 if (!parent) { 216 dev_err(dev, "cannot find parent domain\n"); 217 ret = -ENODEV; 218 goto out_put_node; 219 } 220 221 ret = rza1_irqc_parse_map(priv, gic_node); 222 if (ret) { 223 dev_err(dev, "cannot parse %s: %d\n", "interrupt-map", ret); 224 goto out_put_node; 225 } 226 227 priv->chip.name = "rza1-irqc"; 228 priv->chip.irq_mask = irq_chip_mask_parent; 229 priv->chip.irq_unmask = irq_chip_unmask_parent; 230 priv->chip.irq_eoi = rza1_irqc_eoi; 231 priv->chip.irq_retrigger = irq_chip_retrigger_hierarchy; 232 priv->chip.irq_set_type = rza1_irqc_set_type; 233 priv->chip.flags = IRQCHIP_MASK_ON_SUSPEND | IRQCHIP_SKIP_SET_WAKE; 234 235 priv->irq_domain = irq_domain_create_hierarchy(parent, 0, IRQC_NUM_IRQ, dev_fwnode(dev), 236 &rza1_irqc_domain_ops, priv); 237 if (!priv->irq_domain) { 238 dev_err(dev, "cannot initialize irq domain\n"); 239 ret = -ENOMEM; 240 } 241 242 out_put_node: 243 of_node_put(gic_node); 244 return ret; 245 } 246 247 static void rza1_irqc_remove(struct platform_device *pdev) 248 { 249 struct rza1_irqc_priv *priv = platform_get_drvdata(pdev); 250 251 irq_domain_remove(priv->irq_domain); 252 } 253 254 static const struct of_device_id rza1_irqc_dt_ids[] = { 255 { .compatible = "renesas,rza1-irqc" }, 256 {}, 257 }; 258 MODULE_DEVICE_TABLE(of, rza1_irqc_dt_ids); 259 260 static struct platform_driver rza1_irqc_device_driver = { 261 .probe = rza1_irqc_probe, 262 .remove = rza1_irqc_remove, 263 .driver = { 264 .name = "renesas_rza1_irqc", 265 .of_match_table = rza1_irqc_dt_ids, 266 } 267 }; 268 269 static int __init rza1_irqc_init(void) 270 { 271 return platform_driver_register(&rza1_irqc_device_driver); 272 } 273 postcore_initcall(rza1_irqc_init); 274 275 static void __exit rza1_irqc_exit(void) 276 { 277 platform_driver_unregister(&rza1_irqc_device_driver); 278 } 279 module_exit(rza1_irqc_exit); 280 281 MODULE_AUTHOR("Geert Uytterhoeven <geert+renesas@glider.be>"); 282 MODULE_DESCRIPTION("Renesas RZ/A1 IRQC Driver"); 283