1 // SPDX-License-Identifier: (GPL-2.0 OR MIT) 2 /* 3 * Microsemi Ocelot IRQ controller driver 4 * 5 * Copyright (c) 2017 Microsemi Corporation 6 */ 7 #include <linux/bitops.h> 8 #include <linux/irq.h> 9 #include <linux/of_address.h> 10 #include <linux/of_irq.h> 11 #include <linux/irqchip.h> 12 #include <linux/irqchip/chained_irq.h> 13 #include <linux/interrupt.h> 14 15 #define ICPU_CFG_INTR_DST_INTR_IDENT(_p, x) ((_p)->reg_off_ident + 0x4 * (x)) 16 #define ICPU_CFG_INTR_INTR_TRIGGER(_p, x) ((_p)->reg_off_trigger + 0x4 * (x)) 17 18 #define FLAGS_HAS_TRIGGER BIT(0) 19 #define FLAGS_NEED_INIT_ENABLE BIT(1) 20 21 struct chip_props { 22 u8 flags; 23 u8 reg_off_sticky; 24 u8 reg_off_ena; 25 u8 reg_off_ena_clr; 26 u8 reg_off_ena_set; 27 u8 reg_off_ident; 28 u8 reg_off_trigger; 29 u8 reg_off_ena_irq0; 30 u8 n_irq; 31 }; 32 33 static struct chip_props ocelot_props = { 34 .flags = FLAGS_HAS_TRIGGER, 35 .reg_off_sticky = 0x10, 36 .reg_off_ena = 0x18, 37 .reg_off_ena_clr = 0x1c, 38 .reg_off_ena_set = 0x20, 39 .reg_off_ident = 0x38, 40 .reg_off_trigger = 0x4, 41 .n_irq = 24, 42 }; 43 44 static struct chip_props serval_props = { 45 .flags = FLAGS_HAS_TRIGGER, 46 .reg_off_sticky = 0xc, 47 .reg_off_ena = 0x14, 48 .reg_off_ena_clr = 0x18, 49 .reg_off_ena_set = 0x1c, 50 .reg_off_ident = 0x20, 51 .reg_off_trigger = 0x4, 52 .n_irq = 24, 53 }; 54 55 static struct chip_props luton_props = { 56 .flags = FLAGS_NEED_INIT_ENABLE, 57 .reg_off_sticky = 0, 58 .reg_off_ena = 0x4, 59 .reg_off_ena_clr = 0x8, 60 .reg_off_ena_set = 0xc, 61 .reg_off_ident = 0x18, 62 .reg_off_ena_irq0 = 0x14, 63 .n_irq = 28, 64 }; 65 66 static struct chip_props jaguar2_props = { 67 .flags = FLAGS_HAS_TRIGGER, 68 .reg_off_sticky = 0x10, 69 .reg_off_ena = 0x18, 70 .reg_off_ena_clr = 0x1c, 71 .reg_off_ena_set = 0x20, 72 .reg_off_ident = 0x38, 73 .reg_off_trigger = 0x4, 74 .n_irq = 29, 75 }; 76 77 static void ocelot_irq_unmask(struct irq_data *data) 78 { 79 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(data); 80 struct irq_domain *d = data->domain; 81 struct chip_props *p = d->host_data; 82 struct irq_chip_type *ct = irq_data_get_chip_type(data); 83 unsigned int mask = data->mask; 84 u32 val; 85 86 guard(raw_spinlock)(&gc->lock); 87 /* 88 * Clear sticky bits for edge mode interrupts. 89 * Serval has only one trigger register replication, but the adjacent 90 * register is always read as zero, so there's no need to handle this 91 * case separately. 92 */ 93 val = irq_reg_readl(gc, ICPU_CFG_INTR_INTR_TRIGGER(p, 0)) | 94 irq_reg_readl(gc, ICPU_CFG_INTR_INTR_TRIGGER(p, 1)); 95 if (!(val & mask)) 96 irq_reg_writel(gc, mask, p->reg_off_sticky); 97 98 *ct->mask_cache &= ~mask; 99 irq_reg_writel(gc, mask, p->reg_off_ena_set); 100 } 101 102 static void ocelot_irq_handler(struct irq_desc *desc) 103 { 104 struct irq_chip *chip = irq_desc_get_chip(desc); 105 struct irq_domain *d = irq_desc_get_handler_data(desc); 106 struct chip_props *p = d->host_data; 107 struct irq_chip_generic *gc = irq_get_domain_generic_chip(d, 0); 108 u32 reg = irq_reg_readl(gc, ICPU_CFG_INTR_DST_INTR_IDENT(p, 0)); 109 110 chained_irq_enter(chip, desc); 111 112 while (reg) { 113 u32 hwirq = __fls(reg); 114 115 generic_handle_domain_irq(d, hwirq); 116 reg &= ~(BIT(hwirq)); 117 } 118 119 chained_irq_exit(chip, desc); 120 } 121 122 static int __init vcoreiii_irq_init(struct device_node *node, 123 struct device_node *parent, 124 struct chip_props *p) 125 { 126 struct irq_domain *domain; 127 struct irq_chip_generic *gc; 128 int parent_irq, ret; 129 130 parent_irq = irq_of_parse_and_map(node, 0); 131 if (!parent_irq) 132 return -EINVAL; 133 134 domain = irq_domain_create_linear(of_fwnode_handle(node), p->n_irq, 135 &irq_generic_chip_ops, NULL); 136 if (!domain) { 137 pr_err("%pOFn: unable to add irq domain\n", node); 138 return -ENOMEM; 139 } 140 141 ret = irq_alloc_domain_generic_chips(domain, p->n_irq, 1, 142 "icpu", handle_level_irq, 143 0, 0, 0); 144 if (ret) { 145 pr_err("%pOFn: unable to alloc irq domain gc\n", node); 146 goto err_domain_remove; 147 } 148 149 gc = irq_get_domain_generic_chip(domain, 0); 150 gc->reg_base = of_iomap(node, 0); 151 if (!gc->reg_base) { 152 pr_err("%pOFn: unable to map resource\n", node); 153 ret = -ENOMEM; 154 goto err_gc_free; 155 } 156 157 gc->chip_types[0].chip.irq_ack = irq_gc_ack_set_bit; 158 gc->chip_types[0].regs.ack = p->reg_off_sticky; 159 if (p->flags & FLAGS_HAS_TRIGGER) { 160 gc->chip_types[0].regs.mask = p->reg_off_ena_clr; 161 gc->chip_types[0].chip.irq_unmask = ocelot_irq_unmask; 162 gc->chip_types[0].chip.irq_mask = irq_gc_mask_set_bit; 163 } else { 164 gc->chip_types[0].regs.enable = p->reg_off_ena_set; 165 gc->chip_types[0].regs.disable = p->reg_off_ena_clr; 166 gc->chip_types[0].chip.irq_mask = irq_gc_mask_disable_reg; 167 gc->chip_types[0].chip.irq_unmask = irq_gc_unmask_enable_reg; 168 } 169 170 /* Mask and ack all interrupts */ 171 irq_reg_writel(gc, 0, p->reg_off_ena); 172 irq_reg_writel(gc, 0xffffffff, p->reg_off_sticky); 173 174 /* Overall init */ 175 if (p->flags & FLAGS_NEED_INIT_ENABLE) 176 irq_reg_writel(gc, BIT(0), p->reg_off_ena_irq0); 177 178 domain->host_data = p; 179 irq_set_chained_handler_and_data(parent_irq, ocelot_irq_handler, 180 domain); 181 182 return 0; 183 184 err_gc_free: 185 irq_free_generic_chip(gc); 186 187 err_domain_remove: 188 irq_domain_remove(domain); 189 190 return ret; 191 } 192 193 static int __init ocelot_irq_init(struct device_node *node, 194 struct device_node *parent) 195 { 196 return vcoreiii_irq_init(node, parent, &ocelot_props); 197 } 198 199 IRQCHIP_DECLARE(ocelot_icpu, "mscc,ocelot-icpu-intr", ocelot_irq_init); 200 201 static int __init serval_irq_init(struct device_node *node, 202 struct device_node *parent) 203 { 204 return vcoreiii_irq_init(node, parent, &serval_props); 205 } 206 207 IRQCHIP_DECLARE(serval_icpu, "mscc,serval-icpu-intr", serval_irq_init); 208 209 static int __init luton_irq_init(struct device_node *node, 210 struct device_node *parent) 211 { 212 return vcoreiii_irq_init(node, parent, &luton_props); 213 } 214 215 IRQCHIP_DECLARE(luton_icpu, "mscc,luton-icpu-intr", luton_irq_init); 216 217 static int __init jaguar2_irq_init(struct device_node *node, 218 struct device_node *parent) 219 { 220 return vcoreiii_irq_init(node, parent, &jaguar2_props); 221 } 222 223 IRQCHIP_DECLARE(jaguar2_icpu, "mscc,jaguar2-icpu-intr", jaguar2_irq_init); 224