1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2015 Endless Mobile, Inc. 4 * Author: Carlo Caione <carlo@endlessm.com> 5 * Copyright (c) 2016 BayLibre, SAS. 6 * Author: Jerome Brunet <jbrunet@baylibre.com> 7 */ 8 9 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 10 11 #include <linux/io.h> 12 #include <linux/module.h> 13 #include <linux/irq.h> 14 #include <linux/irqdomain.h> 15 #include <linux/irqchip.h> 16 #include <linux/of.h> 17 #include <linux/of_address.h> 18 19 #define MAX_NUM_CHANNEL 64 20 #define MAX_INPUT_MUX 256 21 22 #define REG_EDGE_POL 0x00 23 #define REG_PIN_03_SEL 0x04 24 #define REG_PIN_47_SEL 0x08 25 #define REG_FILTER_SEL 0x0c 26 27 /* use for A1 like chips */ 28 #define REG_PIN_A1_SEL 0x04 29 30 /* 31 * Note: The S905X3 datasheet reports that BOTH_EDGE is controlled by 32 * bits 24 to 31. Tests on the actual HW show that these bits are 33 * stuck at 0. Bits 8 to 15 are responsive and have the expected 34 * effect. 35 */ 36 #define REG_EDGE_POL_EDGE(params, x) BIT((params)->edge_single_offset + (x)) 37 #define REG_EDGE_POL_LOW(params, x) BIT((params)->pol_low_offset + (x)) 38 #define REG_BOTH_EDGE(params, x) BIT((params)->edge_both_offset + (x)) 39 #define REG_EDGE_POL_MASK(params, x) ( \ 40 REG_EDGE_POL_EDGE(params, x) | \ 41 REG_EDGE_POL_LOW(params, x) | \ 42 REG_BOTH_EDGE(params, x)) 43 #define REG_PIN_SEL_SHIFT(x) (((x) % 4) * 8) 44 #define REG_FILTER_SEL_SHIFT(x) ((x) * 4) 45 46 struct meson_gpio_irq_controller; 47 static void meson8_gpio_irq_sel_pin(struct meson_gpio_irq_controller *ctl, 48 unsigned int channel, unsigned long hwirq); 49 static void meson_gpio_irq_init_dummy(struct meson_gpio_irq_controller *ctl); 50 static void meson_a1_gpio_irq_sel_pin(struct meson_gpio_irq_controller *ctl, 51 unsigned int channel, 52 unsigned long hwirq); 53 static void meson_a1_gpio_irq_init(struct meson_gpio_irq_controller *ctl); 54 static int meson8_gpio_irq_set_type(struct meson_gpio_irq_controller *ctl, 55 unsigned int type, u32 *channel_hwirq); 56 static int meson_s4_gpio_irq_set_type(struct meson_gpio_irq_controller *ctl, 57 unsigned int type, u32 *channel_hwirq); 58 59 struct irq_ctl_ops { 60 void (*gpio_irq_sel_pin)(struct meson_gpio_irq_controller *ctl, 61 unsigned int channel, unsigned long hwirq); 62 void (*gpio_irq_init)(struct meson_gpio_irq_controller *ctl); 63 int (*gpio_irq_set_type)(struct meson_gpio_irq_controller *ctl, 64 unsigned int type, u32 *channel_hwirq); 65 }; 66 67 struct meson_gpio_irq_params { 68 unsigned int nr_hwirq; 69 unsigned int nr_channels; 70 bool support_edge_both; 71 unsigned int edge_both_offset; 72 unsigned int edge_single_offset; 73 unsigned int edge_pol_reg; 74 unsigned int pol_low_offset; 75 unsigned int pin_sel_mask; 76 struct irq_ctl_ops ops; 77 }; 78 79 #define INIT_MESON_COMMON(irqs, init, sel, type) \ 80 .nr_hwirq = irqs, \ 81 .ops = { \ 82 .gpio_irq_init = init, \ 83 .gpio_irq_sel_pin = sel, \ 84 .gpio_irq_set_type = type, \ 85 }, 86 87 #define INIT_MESON8_COMMON_DATA(irqs) \ 88 INIT_MESON_COMMON(irqs, meson_gpio_irq_init_dummy, \ 89 meson8_gpio_irq_sel_pin, \ 90 meson8_gpio_irq_set_type) \ 91 .edge_single_offset = 0, \ 92 .pol_low_offset = 16, \ 93 .pin_sel_mask = 0xff, \ 94 .nr_channels = 8, \ 95 96 #define INIT_MESON_A1_COMMON_DATA(irqs) \ 97 INIT_MESON_COMMON(irqs, meson_a1_gpio_irq_init, \ 98 meson_a1_gpio_irq_sel_pin, \ 99 meson8_gpio_irq_set_type) \ 100 .support_edge_both = true, \ 101 .edge_both_offset = 16, \ 102 .edge_single_offset = 8, \ 103 .pol_low_offset = 0, \ 104 .pin_sel_mask = 0x7f, \ 105 .nr_channels = 8, \ 106 107 #define INIT_MESON_A4_AO_COMMON_DATA(irqs) \ 108 INIT_MESON_COMMON(irqs, meson_a1_gpio_irq_init, \ 109 meson_a1_gpio_irq_sel_pin, \ 110 meson_s4_gpio_irq_set_type) \ 111 .support_edge_both = true, \ 112 .edge_both_offset = 0, \ 113 .edge_single_offset = 12, \ 114 .edge_pol_reg = 0x8, \ 115 .pol_low_offset = 0, \ 116 .pin_sel_mask = 0xff, \ 117 .nr_channels = 2, \ 118 119 #define INIT_MESON_S4_COMMON_DATA(irqs) \ 120 INIT_MESON_COMMON(irqs, meson_a1_gpio_irq_init, \ 121 meson_a1_gpio_irq_sel_pin, \ 122 meson_s4_gpio_irq_set_type) \ 123 .support_edge_both = true, \ 124 .edge_both_offset = 0, \ 125 .edge_single_offset = 12, \ 126 .edge_pol_reg = 0x1c, \ 127 .pol_low_offset = 0, \ 128 .pin_sel_mask = 0xff, \ 129 .nr_channels = 12, \ 130 131 static const struct meson_gpio_irq_params meson8_params = { 132 INIT_MESON8_COMMON_DATA(134) 133 }; 134 135 static const struct meson_gpio_irq_params meson8b_params = { 136 INIT_MESON8_COMMON_DATA(119) 137 }; 138 139 static const struct meson_gpio_irq_params gxbb_params = { 140 INIT_MESON8_COMMON_DATA(133) 141 }; 142 143 static const struct meson_gpio_irq_params gxl_params = { 144 INIT_MESON8_COMMON_DATA(110) 145 }; 146 147 static const struct meson_gpio_irq_params axg_params = { 148 INIT_MESON8_COMMON_DATA(100) 149 }; 150 151 static const struct meson_gpio_irq_params sm1_params = { 152 INIT_MESON8_COMMON_DATA(100) 153 .support_edge_both = true, 154 .edge_both_offset = 8, 155 }; 156 157 static const struct meson_gpio_irq_params a1_params = { 158 INIT_MESON_A1_COMMON_DATA(62) 159 }; 160 161 static const struct meson_gpio_irq_params a4_params = { 162 INIT_MESON_S4_COMMON_DATA(81) 163 }; 164 165 static const struct meson_gpio_irq_params a4_ao_params = { 166 INIT_MESON_A4_AO_COMMON_DATA(8) 167 }; 168 169 static const struct meson_gpio_irq_params a5_params = { 170 INIT_MESON_S4_COMMON_DATA(99) 171 }; 172 173 static const struct meson_gpio_irq_params s4_params = { 174 INIT_MESON_S4_COMMON_DATA(82) 175 }; 176 177 static const struct meson_gpio_irq_params s6_params = { 178 INIT_MESON_S4_COMMON_DATA(100) 179 }; 180 181 static const struct meson_gpio_irq_params s7_params = { 182 INIT_MESON_S4_COMMON_DATA(84) 183 }; 184 185 static const struct meson_gpio_irq_params c3_params = { 186 INIT_MESON_S4_COMMON_DATA(55) 187 }; 188 189 static const struct meson_gpio_irq_params t7_params = { 190 INIT_MESON_S4_COMMON_DATA(157) 191 }; 192 193 static const struct of_device_id meson_irq_gpio_matches[] __maybe_unused = { 194 { .compatible = "amlogic,meson8-gpio-intc", .data = &meson8_params }, 195 { .compatible = "amlogic,meson8b-gpio-intc", .data = &meson8b_params }, 196 { .compatible = "amlogic,meson-gxbb-gpio-intc", .data = &gxbb_params }, 197 { .compatible = "amlogic,meson-gxl-gpio-intc", .data = &gxl_params }, 198 { .compatible = "amlogic,meson-axg-gpio-intc", .data = &axg_params }, 199 { .compatible = "amlogic,meson-g12a-gpio-intc", .data = &axg_params }, 200 { .compatible = "amlogic,meson-sm1-gpio-intc", .data = &sm1_params }, 201 { .compatible = "amlogic,meson-a1-gpio-intc", .data = &a1_params }, 202 { .compatible = "amlogic,meson-s4-gpio-intc", .data = &s4_params }, 203 { .compatible = "amlogic,a4-gpio-ao-intc", .data = &a4_ao_params }, 204 { .compatible = "amlogic,a4-gpio-intc", .data = &a4_params }, 205 { .compatible = "amlogic,a5-gpio-intc", .data = &a5_params }, 206 { .compatible = "amlogic,s6-gpio-intc", .data = &s6_params }, 207 { .compatible = "amlogic,s7-gpio-intc", .data = &s7_params }, 208 { .compatible = "amlogic,s7d-gpio-intc", .data = &s7_params }, 209 { .compatible = "amlogic,c3-gpio-intc", .data = &c3_params }, 210 { .compatible = "amlogic,t7-gpio-intc", .data = &t7_params }, 211 { } 212 }; 213 214 struct meson_gpio_irq_controller { 215 const struct meson_gpio_irq_params *params; 216 void __iomem *base; 217 u32 channel_irqs[MAX_NUM_CHANNEL]; 218 DECLARE_BITMAP(channel_map, MAX_NUM_CHANNEL); 219 raw_spinlock_t lock; 220 }; 221 222 static void meson_gpio_irq_update_bits(struct meson_gpio_irq_controller *ctl, 223 unsigned int reg, u32 mask, u32 val) 224 { 225 unsigned long flags; 226 u32 tmp; 227 228 raw_spin_lock_irqsave(&ctl->lock, flags); 229 230 tmp = readl_relaxed(ctl->base + reg); 231 tmp &= ~mask; 232 tmp |= val; 233 writel_relaxed(tmp, ctl->base + reg); 234 235 raw_spin_unlock_irqrestore(&ctl->lock, flags); 236 } 237 238 static void meson_gpio_irq_init_dummy(struct meson_gpio_irq_controller *ctl) 239 { 240 } 241 242 static void meson8_gpio_irq_sel_pin(struct meson_gpio_irq_controller *ctl, 243 unsigned int channel, unsigned long hwirq) 244 { 245 unsigned int reg_offset; 246 unsigned int bit_offset; 247 248 reg_offset = (channel < 4) ? REG_PIN_03_SEL : REG_PIN_47_SEL; 249 bit_offset = REG_PIN_SEL_SHIFT(channel); 250 251 meson_gpio_irq_update_bits(ctl, reg_offset, 252 ctl->params->pin_sel_mask << bit_offset, 253 hwirq << bit_offset); 254 } 255 256 static void meson_a1_gpio_irq_sel_pin(struct meson_gpio_irq_controller *ctl, 257 unsigned int channel, 258 unsigned long hwirq) 259 { 260 unsigned int reg_offset; 261 unsigned int bit_offset; 262 263 bit_offset = ((channel % 2) == 0) ? 0 : 16; 264 reg_offset = REG_PIN_A1_SEL + ((channel / 2) << 2); 265 266 meson_gpio_irq_update_bits(ctl, reg_offset, 267 ctl->params->pin_sel_mask << bit_offset, 268 hwirq << bit_offset); 269 } 270 271 /* For a1 or later chips like a1 there is a switch to enable/disable irq */ 272 static void meson_a1_gpio_irq_init(struct meson_gpio_irq_controller *ctl) 273 { 274 meson_gpio_irq_update_bits(ctl, REG_EDGE_POL, BIT(31), BIT(31)); 275 } 276 277 static int 278 meson_gpio_irq_request_channel(struct meson_gpio_irq_controller *ctl, 279 unsigned long hwirq, 280 u32 **channel_hwirq) 281 { 282 unsigned long flags; 283 unsigned int idx; 284 285 raw_spin_lock_irqsave(&ctl->lock, flags); 286 287 /* Find a free channel */ 288 idx = find_first_zero_bit(ctl->channel_map, ctl->params->nr_channels); 289 if (idx >= ctl->params->nr_channels) { 290 raw_spin_unlock_irqrestore(&ctl->lock, flags); 291 pr_err("No channel available\n"); 292 return -ENOSPC; 293 } 294 295 /* Mark the channel as used */ 296 set_bit(idx, ctl->channel_map); 297 298 raw_spin_unlock_irqrestore(&ctl->lock, flags); 299 300 /* 301 * Setup the mux of the channel to route the signal of the pad 302 * to the appropriate input of the GIC 303 */ 304 ctl->params->ops.gpio_irq_sel_pin(ctl, idx, hwirq); 305 306 /* 307 * Get the hwirq number assigned to this channel through 308 * a pointer the channel_irq table. The added benefit of this 309 * method is that we can also retrieve the channel index with 310 * it, using the table base. 311 */ 312 *channel_hwirq = &(ctl->channel_irqs[idx]); 313 314 pr_debug("hwirq %lu assigned to channel %d - irq %u\n", 315 hwirq, idx, **channel_hwirq); 316 317 return 0; 318 } 319 320 static unsigned int 321 meson_gpio_irq_get_channel_idx(struct meson_gpio_irq_controller *ctl, 322 u32 *channel_hwirq) 323 { 324 return channel_hwirq - ctl->channel_irqs; 325 } 326 327 static void 328 meson_gpio_irq_release_channel(struct meson_gpio_irq_controller *ctl, 329 u32 *channel_hwirq) 330 { 331 unsigned int idx; 332 333 idx = meson_gpio_irq_get_channel_idx(ctl, channel_hwirq); 334 clear_bit(idx, ctl->channel_map); 335 } 336 337 static int meson8_gpio_irq_set_type(struct meson_gpio_irq_controller *ctl, 338 unsigned int type, u32 *channel_hwirq) 339 { 340 const struct meson_gpio_irq_params *params = ctl->params; 341 unsigned int idx; 342 u32 val = 0; 343 344 idx = meson_gpio_irq_get_channel_idx(ctl, channel_hwirq); 345 346 /* 347 * The controller has a filter block to operate in either LEVEL or 348 * EDGE mode, then signal is sent to the GIC. To enable LEVEL_LOW and 349 * EDGE_FALLING support (which the GIC does not support), the filter 350 * block is also able to invert the input signal it gets before 351 * providing it to the GIC. 352 */ 353 type &= IRQ_TYPE_SENSE_MASK; 354 355 /* 356 * New controller support EDGE_BOTH trigger. This setting takes 357 * precedence over the other edge/polarity settings 358 */ 359 if (type == IRQ_TYPE_EDGE_BOTH) { 360 if (!params->support_edge_both) 361 return -EINVAL; 362 363 val |= REG_BOTH_EDGE(params, idx); 364 } else { 365 if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING)) 366 val |= REG_EDGE_POL_EDGE(params, idx); 367 368 if (type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_EDGE_FALLING)) 369 val |= REG_EDGE_POL_LOW(params, idx); 370 } 371 372 meson_gpio_irq_update_bits(ctl, REG_EDGE_POL, 373 REG_EDGE_POL_MASK(params, idx), val); 374 375 return 0; 376 } 377 378 /* 379 * gpio irq relative registers for s4 380 * -PADCTRL_GPIO_IRQ_CTRL0 381 * bit[31]: enable/disable all the irq lines 382 * bit[12-23]: single edge trigger 383 * bit[0-11]: polarity trigger 384 * 385 * -PADCTRL_GPIO_IRQ_CTRL[X] 386 * bit[0-16]: 7 bits to choose gpio source for irq line 2*[X] - 2 387 * bit[16-22]:7 bits to choose gpio source for irq line 2*[X] - 1 388 * where X = 1-6 389 * 390 * -PADCTRL_GPIO_IRQ_CTRL[7] 391 * bit[0-11]: both edge trigger 392 */ 393 static int meson_s4_gpio_irq_set_type(struct meson_gpio_irq_controller *ctl, 394 unsigned int type, u32 *channel_hwirq) 395 { 396 const struct meson_gpio_irq_params *params = ctl->params; 397 unsigned int idx; 398 u32 val = 0; 399 400 idx = meson_gpio_irq_get_channel_idx(ctl, channel_hwirq); 401 402 type &= IRQ_TYPE_SENSE_MASK; 403 404 meson_gpio_irq_update_bits(ctl, params->edge_pol_reg, BIT(idx), 0); 405 406 if (type == IRQ_TYPE_EDGE_BOTH) { 407 val = BIT(ctl->params->edge_both_offset + idx); 408 meson_gpio_irq_update_bits(ctl, params->edge_pol_reg, val, val); 409 return 0; 410 } 411 412 if (type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_EDGE_FALLING)) 413 val |= BIT(ctl->params->pol_low_offset + idx); 414 415 if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING)) 416 val |= BIT(ctl->params->edge_single_offset + idx); 417 418 meson_gpio_irq_update_bits(ctl, params->edge_pol_reg, 419 BIT(idx) | BIT(12 + idx), val); 420 return 0; 421 }; 422 423 static unsigned int meson_gpio_irq_type_output(unsigned int type) 424 { 425 unsigned int sense = type & IRQ_TYPE_SENSE_MASK; 426 427 type &= ~IRQ_TYPE_SENSE_MASK; 428 429 /* 430 * The polarity of the signal provided to the GIC should always 431 * be high. 432 */ 433 if (sense & (IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW)) 434 type |= IRQ_TYPE_LEVEL_HIGH; 435 else 436 type |= IRQ_TYPE_EDGE_RISING; 437 438 return type; 439 } 440 441 static int meson_gpio_irq_set_type(struct irq_data *data, unsigned int type) 442 { 443 struct meson_gpio_irq_controller *ctl = data->domain->host_data; 444 u32 *channel_hwirq = irq_data_get_irq_chip_data(data); 445 int ret; 446 447 ret = ctl->params->ops.gpio_irq_set_type(ctl, type, channel_hwirq); 448 if (ret) 449 return ret; 450 451 return irq_chip_set_type_parent(data, 452 meson_gpio_irq_type_output(type)); 453 } 454 455 static struct irq_chip meson_gpio_irq_chip = { 456 .name = "meson-gpio-irqchip", 457 .irq_mask = irq_chip_mask_parent, 458 .irq_unmask = irq_chip_unmask_parent, 459 .irq_eoi = irq_chip_eoi_parent, 460 .irq_set_type = meson_gpio_irq_set_type, 461 .irq_retrigger = irq_chip_retrigger_hierarchy, 462 #ifdef CONFIG_SMP 463 .irq_set_affinity = irq_chip_set_affinity_parent, 464 #endif 465 .flags = IRQCHIP_SET_TYPE_MASKED, 466 }; 467 468 static int meson_gpio_irq_domain_translate(struct irq_domain *domain, 469 struct irq_fwspec *fwspec, 470 unsigned long *hwirq, 471 unsigned int *type) 472 { 473 if (is_of_node(fwspec->fwnode) && fwspec->param_count == 2) { 474 *hwirq = fwspec->param[0]; 475 *type = fwspec->param[1]; 476 return 0; 477 } 478 479 return -EINVAL; 480 } 481 482 static int meson_gpio_irq_allocate_gic_irq(struct irq_domain *domain, 483 unsigned int virq, 484 u32 hwirq, 485 unsigned int type) 486 { 487 struct irq_fwspec fwspec; 488 489 fwspec.fwnode = domain->parent->fwnode; 490 fwspec.param_count = 3; 491 fwspec.param[0] = 0; /* SPI */ 492 fwspec.param[1] = hwirq; 493 fwspec.param[2] = meson_gpio_irq_type_output(type); 494 495 return irq_domain_alloc_irqs_parent(domain, virq, 1, &fwspec); 496 } 497 498 static int meson_gpio_irq_domain_alloc(struct irq_domain *domain, 499 unsigned int virq, 500 unsigned int nr_irqs, 501 void *data) 502 { 503 struct irq_fwspec *fwspec = data; 504 struct meson_gpio_irq_controller *ctl = domain->host_data; 505 unsigned long hwirq; 506 u32 *channel_hwirq; 507 unsigned int type; 508 int ret; 509 510 if (WARN_ON(nr_irqs != 1)) 511 return -EINVAL; 512 513 ret = meson_gpio_irq_domain_translate(domain, fwspec, &hwirq, &type); 514 if (ret) 515 return ret; 516 517 ret = meson_gpio_irq_request_channel(ctl, hwirq, &channel_hwirq); 518 if (ret) 519 return ret; 520 521 ret = meson_gpio_irq_allocate_gic_irq(domain, virq, 522 *channel_hwirq, type); 523 if (ret < 0) { 524 pr_err("failed to allocate gic irq %u\n", *channel_hwirq); 525 meson_gpio_irq_release_channel(ctl, channel_hwirq); 526 return ret; 527 } 528 529 irq_domain_set_hwirq_and_chip(domain, virq, hwirq, 530 &meson_gpio_irq_chip, channel_hwirq); 531 532 return 0; 533 } 534 535 static void meson_gpio_irq_domain_free(struct irq_domain *domain, 536 unsigned int virq, 537 unsigned int nr_irqs) 538 { 539 struct meson_gpio_irq_controller *ctl = domain->host_data; 540 struct irq_data *irq_data; 541 u32 *channel_hwirq; 542 543 if (WARN_ON(nr_irqs != 1)) 544 return; 545 546 irq_domain_free_irqs_parent(domain, virq, 1); 547 548 irq_data = irq_domain_get_irq_data(domain, virq); 549 channel_hwirq = irq_data_get_irq_chip_data(irq_data); 550 551 meson_gpio_irq_release_channel(ctl, channel_hwirq); 552 } 553 554 static const struct irq_domain_ops meson_gpio_irq_domain_ops = { 555 .alloc = meson_gpio_irq_domain_alloc, 556 .free = meson_gpio_irq_domain_free, 557 .translate = meson_gpio_irq_domain_translate, 558 }; 559 560 static int meson_gpio_irq_parse_dt(struct device_node *node, struct meson_gpio_irq_controller *ctl) 561 { 562 const struct of_device_id *match; 563 int ret; 564 565 match = of_match_node(meson_irq_gpio_matches, node); 566 if (!match) 567 return -ENODEV; 568 569 ctl->params = match->data; 570 571 ret = of_property_read_variable_u32_array(node, 572 "amlogic,channel-interrupts", 573 ctl->channel_irqs, 574 ctl->params->nr_channels, 575 ctl->params->nr_channels); 576 if (ret < 0) { 577 pr_err("can't get %d channel interrupts\n", ctl->params->nr_channels); 578 return ret; 579 } 580 581 ctl->params->ops.gpio_irq_init(ctl); 582 583 return 0; 584 } 585 586 static int meson_gpio_irq_probe(struct platform_device *pdev, struct device_node *parent) 587 { 588 struct device_node *node = pdev->dev.of_node; 589 struct irq_domain *domain, *parent_domain; 590 struct meson_gpio_irq_controller *ctl; 591 int ret; 592 593 if (!parent) { 594 pr_err("missing parent interrupt node\n"); 595 return -ENODEV; 596 } 597 598 parent_domain = irq_find_host(parent); 599 if (!parent_domain) { 600 pr_err("unable to obtain parent domain\n"); 601 return -ENXIO; 602 } 603 604 ctl = kzalloc(sizeof(*ctl), GFP_KERNEL); 605 if (!ctl) 606 return -ENOMEM; 607 608 raw_spin_lock_init(&ctl->lock); 609 610 ctl->base = of_iomap(node, 0); 611 if (!ctl->base) { 612 ret = -ENOMEM; 613 goto free_ctl; 614 } 615 616 ret = meson_gpio_irq_parse_dt(node, ctl); 617 if (ret) 618 goto free_channel_irqs; 619 620 domain = irq_domain_create_hierarchy(parent_domain, 0, 621 ctl->params->nr_hwirq, 622 of_fwnode_handle(node), 623 &meson_gpio_irq_domain_ops, 624 ctl); 625 if (!domain) { 626 pr_err("failed to add domain\n"); 627 ret = -ENODEV; 628 goto free_channel_irqs; 629 } 630 631 pr_info("%d to %d gpio interrupt mux initialized\n", 632 ctl->params->nr_hwirq, ctl->params->nr_channels); 633 634 return 0; 635 636 free_channel_irqs: 637 iounmap(ctl->base); 638 free_ctl: 639 kfree(ctl); 640 641 return ret; 642 } 643 644 IRQCHIP_PLATFORM_DRIVER_BEGIN(meson_gpio_intc) 645 IRQCHIP_MATCH("amlogic,meson-gpio-intc", meson_gpio_irq_probe) 646 IRQCHIP_PLATFORM_DRIVER_END(meson_gpio_intc) 647 648 MODULE_AUTHOR("Jerome Brunet <jbrunet@baylibre.com>"); 649 MODULE_DESCRIPTION("Meson GPIO Interrupt Multiplexer driver"); 650 MODULE_LICENSE("GPL v2"); 651