1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (C) 2015 HiSilicon Limited, All Rights Reserved. 4 * Author: Jun Ma <majun258@huawei.com> 5 * Author: Yun Wu <wuyun.wu@huawei.com> 6 */ 7 8 #include <linux/acpi.h> 9 #include <linux/interrupt.h> 10 #include <linux/irqchip.h> 11 #include <linux/module.h> 12 #include <linux/msi.h> 13 #include <linux/of_address.h> 14 #include <linux/of_irq.h> 15 #include <linux/of_platform.h> 16 #include <linux/platform_device.h> 17 #include <linux/slab.h> 18 19 /* Interrupt numbers per mbigen node supported */ 20 #define IRQS_PER_MBIGEN_NODE 128 21 22 /* 64 irqs (Pin0-pin63) are reserved for each mbigen chip */ 23 #define RESERVED_IRQ_PER_MBIGEN_CHIP 64 24 25 /* The maximum IRQ pin number of mbigen chip(start from 0) */ 26 #define MAXIMUM_IRQ_PIN_NUM 1407 27 28 /* 29 * In mbigen vector register 30 * bit[21:12]: event id value 31 * bit[11:0]: device id 32 */ 33 #define IRQ_EVENT_ID_SHIFT 12 34 #define IRQ_EVENT_ID_MASK 0x3ff 35 36 /* register range of each mbigen node */ 37 #define MBIGEN_NODE_OFFSET 0x1000 38 39 /* offset of vector register in mbigen node */ 40 #define REG_MBIGEN_VEC_OFFSET 0x200 41 42 /* 43 * offset of clear register in mbigen node 44 * This register is used to clear the status 45 * of interrupt 46 */ 47 #define REG_MBIGEN_CLEAR_OFFSET 0xa000 48 49 /* 50 * offset of interrupt type register 51 * This register is used to configure interrupt 52 * trigger type 53 */ 54 #define REG_MBIGEN_TYPE_OFFSET 0x0 55 56 /** 57 * struct mbigen_device - holds the information of mbigen device. 58 * 59 * @pdev: pointer to the platform device structure of mbigen chip. 60 * @base: mapped address of this mbigen chip. 61 */ 62 struct mbigen_device { 63 struct platform_device *pdev; 64 void __iomem *base; 65 }; 66 67 static inline unsigned int get_mbigen_vec_reg(irq_hw_number_t hwirq) 68 { 69 unsigned int nid, pin; 70 71 hwirq -= RESERVED_IRQ_PER_MBIGEN_CHIP; 72 nid = hwirq / IRQS_PER_MBIGEN_NODE + 1; 73 pin = hwirq % IRQS_PER_MBIGEN_NODE; 74 75 return pin * 4 + nid * MBIGEN_NODE_OFFSET 76 + REG_MBIGEN_VEC_OFFSET; 77 } 78 79 static inline void get_mbigen_type_reg(irq_hw_number_t hwirq, 80 u32 *mask, u32 *addr) 81 { 82 unsigned int nid, irq_ofst, ofst; 83 84 hwirq -= RESERVED_IRQ_PER_MBIGEN_CHIP; 85 nid = hwirq / IRQS_PER_MBIGEN_NODE + 1; 86 irq_ofst = hwirq % IRQS_PER_MBIGEN_NODE; 87 88 *mask = 1 << (irq_ofst % 32); 89 ofst = irq_ofst / 32 * 4; 90 91 *addr = ofst + nid * MBIGEN_NODE_OFFSET 92 + REG_MBIGEN_TYPE_OFFSET; 93 } 94 95 static inline void get_mbigen_clear_reg(irq_hw_number_t hwirq, 96 u32 *mask, u32 *addr) 97 { 98 unsigned int ofst = (hwirq / 32) * 4; 99 100 *mask = 1 << (hwirq % 32); 101 *addr = ofst + REG_MBIGEN_CLEAR_OFFSET; 102 } 103 104 static void mbigen_eoi_irq(struct irq_data *data) 105 { 106 void __iomem *base = data->chip_data; 107 u32 mask, addr; 108 109 get_mbigen_clear_reg(data->hwirq, &mask, &addr); 110 111 writel_relaxed(mask, base + addr); 112 113 irq_chip_eoi_parent(data); 114 } 115 116 static int mbigen_set_type(struct irq_data *data, unsigned int type) 117 { 118 void __iomem *base = data->chip_data; 119 u32 mask, addr, val; 120 121 if (type != IRQ_TYPE_LEVEL_HIGH && type != IRQ_TYPE_EDGE_RISING) 122 return -EINVAL; 123 124 get_mbigen_type_reg(data->hwirq, &mask, &addr); 125 126 val = readl_relaxed(base + addr); 127 128 if (type == IRQ_TYPE_LEVEL_HIGH) 129 val |= mask; 130 else 131 val &= ~mask; 132 133 writel_relaxed(val, base + addr); 134 135 return 0; 136 } 137 138 static void mbigen_write_msi_msg(struct irq_data *d, struct msi_msg *msg) 139 { 140 void __iomem *base = d->chip_data; 141 u32 val; 142 143 if (!msg->address_lo && !msg->address_hi) 144 return; 145 146 base += get_mbigen_vec_reg(d->hwirq); 147 val = readl_relaxed(base); 148 149 val &= ~(IRQ_EVENT_ID_MASK << IRQ_EVENT_ID_SHIFT); 150 val |= (msg->data << IRQ_EVENT_ID_SHIFT); 151 152 /* The address of doorbell is encoded in mbigen register by default 153 * So,we don't need to program the doorbell address at here 154 */ 155 writel_relaxed(val, base); 156 } 157 158 static int mbigen_domain_translate(struct irq_domain *d, struct irq_fwspec *fwspec, 159 unsigned long *hwirq, unsigned int *type) 160 { 161 if (is_of_node(fwspec->fwnode) || is_acpi_device_node(fwspec->fwnode)) { 162 if (fwspec->param_count != 2) 163 return -EINVAL; 164 165 if ((fwspec->param[0] > MAXIMUM_IRQ_PIN_NUM) || 166 (fwspec->param[0] < RESERVED_IRQ_PER_MBIGEN_CHIP)) 167 return -EINVAL; 168 else 169 *hwirq = fwspec->param[0]; 170 171 /* If there is no valid irq type, just use the default type */ 172 if ((fwspec->param[1] == IRQ_TYPE_EDGE_RISING) || 173 (fwspec->param[1] == IRQ_TYPE_LEVEL_HIGH)) 174 *type = fwspec->param[1]; 175 else 176 return -EINVAL; 177 178 return 0; 179 } 180 return -EINVAL; 181 } 182 183 static void mbigen_domain_set_desc(msi_alloc_info_t *arg, struct msi_desc *desc) 184 { 185 arg->desc = desc; 186 arg->hwirq = (u32)desc->data.icookie.value; 187 } 188 189 static const struct msi_domain_template mbigen_msi_template = { 190 .chip = { 191 .name = "mbigen-v2", 192 .irq_mask = irq_chip_mask_parent, 193 .irq_unmask = irq_chip_unmask_parent, 194 .irq_eoi = mbigen_eoi_irq, 195 .irq_set_type = mbigen_set_type, 196 .irq_write_msi_msg = mbigen_write_msi_msg, 197 }, 198 199 .ops = { 200 .set_desc = mbigen_domain_set_desc, 201 .msi_translate = mbigen_domain_translate, 202 }, 203 204 .info = { 205 .bus_token = DOMAIN_BUS_WIRED_TO_MSI, 206 .flags = MSI_FLAG_USE_DEV_FWNODE, 207 }, 208 }; 209 210 static bool mbigen_create_device_domain(struct device *dev, unsigned int size, 211 struct mbigen_device *mgn_chip) 212 { 213 if (WARN_ON_ONCE(!dev->msi.domain)) 214 return false; 215 216 return msi_create_device_irq_domain(dev, MSI_DEFAULT_DOMAIN, 217 &mbigen_msi_template, size, 218 NULL, mgn_chip->base); 219 } 220 221 static int mbigen_of_create_domain(struct platform_device *pdev, 222 struct mbigen_device *mgn_chip) 223 { 224 struct platform_device *child; 225 struct device_node *np; 226 u32 num_pins; 227 int ret = 0; 228 229 for_each_child_of_node(pdev->dev.of_node, np) { 230 if (!of_property_read_bool(np, "interrupt-controller")) 231 continue; 232 233 child = of_platform_device_create(np, NULL, NULL); 234 if (!child) { 235 ret = -ENOMEM; 236 break; 237 } 238 239 if (of_property_read_u32(child->dev.of_node, "num-pins", 240 &num_pins) < 0) { 241 dev_err(&pdev->dev, "No num-pins property\n"); 242 ret = -EINVAL; 243 break; 244 } 245 246 if (!mbigen_create_device_domain(&child->dev, num_pins, mgn_chip)) { 247 ret = -ENOMEM; 248 break; 249 } 250 } 251 252 if (ret) 253 of_node_put(np); 254 255 return ret; 256 } 257 258 #ifdef CONFIG_ACPI 259 static const struct acpi_device_id mbigen_acpi_match[] = { 260 { "HISI0152", 0 }, 261 {} 262 }; 263 MODULE_DEVICE_TABLE(acpi, mbigen_acpi_match); 264 265 static int mbigen_acpi_create_domain(struct platform_device *pdev, 266 struct mbigen_device *mgn_chip) 267 { 268 u32 num_pins = 0; 269 int ret; 270 271 /* 272 * "num-pins" is the total number of interrupt pins implemented in 273 * this mbigen instance, and mbigen is an interrupt controller 274 * connected to ITS converting wired interrupts into MSI, so we 275 * use "num-pins" to alloc MSI vectors which are needed by client 276 * devices connected to it. 277 * 278 * Here is the DSDT device node used for mbigen in firmware: 279 * Device(MBI0) { 280 * Name(_HID, "HISI0152") 281 * Name(_UID, Zero) 282 * Name(_CRS, ResourceTemplate() { 283 * Memory32Fixed(ReadWrite, 0xa0080000, 0x10000) 284 * }) 285 * 286 * Name(_DSD, Package () { 287 * ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), 288 * Package () { 289 * Package () {"num-pins", 378} 290 * } 291 * }) 292 * } 293 */ 294 ret = device_property_read_u32(&pdev->dev, "num-pins", &num_pins); 295 if (ret || num_pins == 0) 296 return -EINVAL; 297 298 if (!mbigen_create_device_domain(&pdev->dev, num_pins, mgn_chip)) 299 return -ENOMEM; 300 301 return 0; 302 } 303 #else 304 static inline int mbigen_acpi_create_domain(struct platform_device *pdev, 305 struct mbigen_device *mgn_chip) 306 { 307 return -ENODEV; 308 } 309 #endif 310 311 static int mbigen_device_probe(struct platform_device *pdev) 312 { 313 struct mbigen_device *mgn_chip; 314 struct resource *res; 315 int err; 316 317 mgn_chip = devm_kzalloc(&pdev->dev, sizeof(*mgn_chip), GFP_KERNEL); 318 if (!mgn_chip) 319 return -ENOMEM; 320 321 mgn_chip->pdev = pdev; 322 323 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 324 if (!res) 325 return -EINVAL; 326 327 mgn_chip->base = devm_ioremap(&pdev->dev, res->start, 328 resource_size(res)); 329 if (!mgn_chip->base) { 330 dev_err(&pdev->dev, "failed to ioremap %pR\n", res); 331 return -ENOMEM; 332 } 333 334 if (IS_ENABLED(CONFIG_OF) && pdev->dev.of_node) 335 err = mbigen_of_create_domain(pdev, mgn_chip); 336 else if (ACPI_COMPANION(&pdev->dev)) 337 err = mbigen_acpi_create_domain(pdev, mgn_chip); 338 else 339 err = -EINVAL; 340 341 if (err) { 342 dev_err(&pdev->dev, "Failed to create mbi-gen irqdomain\n"); 343 return err; 344 } 345 346 platform_set_drvdata(pdev, mgn_chip); 347 return 0; 348 } 349 350 static const struct of_device_id mbigen_of_match[] = { 351 { .compatible = "hisilicon,mbigen-v2" }, 352 { /* END */ } 353 }; 354 MODULE_DEVICE_TABLE(of, mbigen_of_match); 355 356 static struct platform_driver mbigen_platform_driver = { 357 .driver = { 358 .name = "Hisilicon MBIGEN-V2", 359 .of_match_table = mbigen_of_match, 360 .acpi_match_table = ACPI_PTR(mbigen_acpi_match), 361 .suppress_bind_attrs = true, 362 }, 363 .probe = mbigen_device_probe, 364 }; 365 366 module_platform_driver(mbigen_platform_driver); 367 368 MODULE_AUTHOR("Jun Ma <majun258@huawei.com>"); 369 MODULE_AUTHOR("Yun Wu <wuyun.wu@huawei.com>"); 370 MODULE_DESCRIPTION("HiSilicon MBI Generator driver"); 371