xref: /linux/drivers/irqchip/irq-mbigen.c (revision 60a7a9a2493a10b408c00eb323fc479a3a292c17) 
1 /*
2  * Copyright (C) 2015 Hisilicon Limited, All Rights Reserved.
3  * Author: Jun Ma <majun258@huawei.com>
4  * Author: Yun Wu <wuyun.wu@huawei.com>
5  *
6  * This program is free software; you can redistribute it and/or modify
7  * it under the terms of the GNU General Public License version 2 as
8  * published by the Free Software Foundation.
9  *
10  * This program is distributed in the hope that it will be useful,
11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
13  * GNU General Public License for more details.
14  *
15  * You should have received a copy of the GNU General Public License
16  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
17  */
18 
19 #include <linux/acpi.h>
20 #include <linux/interrupt.h>
21 #include <linux/irqchip.h>
22 #include <linux/module.h>
23 #include <linux/msi.h>
24 #include <linux/of_address.h>
25 #include <linux/of_irq.h>
26 #include <linux/of_platform.h>
27 #include <linux/platform_device.h>
28 #include <linux/slab.h>
29 
30 /* Interrupt numbers per mbigen node supported */
31 #define IRQS_PER_MBIGEN_NODE		128
32 
33 /* 64 irqs (Pin0-pin63) are reserved for each mbigen chip */
34 #define RESERVED_IRQ_PER_MBIGEN_CHIP	64
35 
36 /* The maximum IRQ pin number of mbigen chip(start from 0) */
37 #define MAXIMUM_IRQ_PIN_NUM		1407
38 
39 /**
40  * In mbigen vector register
41  * bit[21:12]:	event id value
42  * bit[11:0]:	device id
43  */
44 #define IRQ_EVENT_ID_SHIFT		12
45 #define IRQ_EVENT_ID_MASK		0x3ff
46 
47 /* register range of each mbigen node */
48 #define MBIGEN_NODE_OFFSET		0x1000
49 
50 /* offset of vector register in mbigen node */
51 #define REG_MBIGEN_VEC_OFFSET		0x200
52 
53 /**
54  * offset of clear register in mbigen node
55  * This register is used to clear the status
56  * of interrupt
57  */
58 #define REG_MBIGEN_CLEAR_OFFSET		0xa000
59 
60 /**
61  * offset of interrupt type register
62  * This register is used to configure interrupt
63  * trigger type
64  */
65 #define REG_MBIGEN_TYPE_OFFSET		0x0
66 
67 /**
68  * struct mbigen_device - holds the information of mbigen device.
69  *
70  * @pdev:		pointer to the platform device structure of mbigen chip.
71  * @base:		mapped address of this mbigen chip.
72  */
73 struct mbigen_device {
74 	struct platform_device	*pdev;
75 	void __iomem		*base;
76 };
77 
78 static inline unsigned int get_mbigen_vec_reg(irq_hw_number_t hwirq)
79 {
80 	unsigned int nid, pin;
81 
82 	hwirq -= RESERVED_IRQ_PER_MBIGEN_CHIP;
83 	nid = hwirq / IRQS_PER_MBIGEN_NODE + 1;
84 	pin = hwirq % IRQS_PER_MBIGEN_NODE;
85 
86 	return pin * 4 + nid * MBIGEN_NODE_OFFSET
87 			+ REG_MBIGEN_VEC_OFFSET;
88 }
89 
90 static inline void get_mbigen_type_reg(irq_hw_number_t hwirq,
91 					u32 *mask, u32 *addr)
92 {
93 	unsigned int nid, irq_ofst, ofst;
94 
95 	hwirq -= RESERVED_IRQ_PER_MBIGEN_CHIP;
96 	nid = hwirq / IRQS_PER_MBIGEN_NODE + 1;
97 	irq_ofst = hwirq % IRQS_PER_MBIGEN_NODE;
98 
99 	*mask = 1 << (irq_ofst % 32);
100 	ofst = irq_ofst / 32 * 4;
101 
102 	*addr = ofst + nid * MBIGEN_NODE_OFFSET
103 		+ REG_MBIGEN_TYPE_OFFSET;
104 }
105 
106 static inline void get_mbigen_clear_reg(irq_hw_number_t hwirq,
107 					u32 *mask, u32 *addr)
108 {
109 	unsigned int ofst = (hwirq / 32) * 4;
110 
111 	*mask = 1 << (hwirq % 32);
112 	*addr = ofst + REG_MBIGEN_CLEAR_OFFSET;
113 }
114 
115 static void mbigen_eoi_irq(struct irq_data *data)
116 {
117 	void __iomem *base = data->chip_data;
118 	u32 mask, addr;
119 
120 	get_mbigen_clear_reg(data->hwirq, &mask, &addr);
121 
122 	writel_relaxed(mask, base + addr);
123 
124 	irq_chip_eoi_parent(data);
125 }
126 
127 static int mbigen_set_type(struct irq_data *data, unsigned int type)
128 {
129 	void __iomem *base = data->chip_data;
130 	u32 mask, addr, val;
131 
132 	if (type != IRQ_TYPE_LEVEL_HIGH && type != IRQ_TYPE_EDGE_RISING)
133 		return -EINVAL;
134 
135 	get_mbigen_type_reg(data->hwirq, &mask, &addr);
136 
137 	val = readl_relaxed(base + addr);
138 
139 	if (type == IRQ_TYPE_LEVEL_HIGH)
140 		val |= mask;
141 	else
142 		val &= ~mask;
143 
144 	writel_relaxed(val, base + addr);
145 
146 	return 0;
147 }
148 
149 static struct irq_chip mbigen_irq_chip = {
150 	.name =			"mbigen-v2",
151 	.irq_mask =		irq_chip_mask_parent,
152 	.irq_unmask =		irq_chip_unmask_parent,
153 	.irq_eoi =		mbigen_eoi_irq,
154 	.irq_set_type =		mbigen_set_type,
155 	.irq_set_affinity =	irq_chip_set_affinity_parent,
156 };
157 
158 static void mbigen_write_msg(struct msi_desc *desc, struct msi_msg *msg)
159 {
160 	struct irq_data *d = irq_get_irq_data(desc->irq);
161 	void __iomem *base = d->chip_data;
162 	u32 val;
163 
164 	if (!msg->address_lo && !msg->address_hi)
165 		return;
166 
167 	base += get_mbigen_vec_reg(d->hwirq);
168 	val = readl_relaxed(base);
169 
170 	val &= ~(IRQ_EVENT_ID_MASK << IRQ_EVENT_ID_SHIFT);
171 	val |= (msg->data << IRQ_EVENT_ID_SHIFT);
172 
173 	/* The address of doorbell is encoded in mbigen register by default
174 	 * So,we don't need to program the doorbell address at here
175 	 */
176 	writel_relaxed(val, base);
177 }
178 
179 static int mbigen_domain_translate(struct irq_domain *d,
180 				    struct irq_fwspec *fwspec,
181 				    unsigned long *hwirq,
182 				    unsigned int *type)
183 {
184 	if (is_of_node(fwspec->fwnode) || is_acpi_device_node(fwspec->fwnode)) {
185 		if (fwspec->param_count != 2)
186 			return -EINVAL;
187 
188 		if ((fwspec->param[0] > MAXIMUM_IRQ_PIN_NUM) ||
189 			(fwspec->param[0] < RESERVED_IRQ_PER_MBIGEN_CHIP))
190 			return -EINVAL;
191 		else
192 			*hwirq = fwspec->param[0];
193 
194 		/* If there is no valid irq type, just use the default type */
195 		if ((fwspec->param[1] == IRQ_TYPE_EDGE_RISING) ||
196 			(fwspec->param[1] == IRQ_TYPE_LEVEL_HIGH))
197 			*type = fwspec->param[1];
198 		else
199 			return -EINVAL;
200 
201 		return 0;
202 	}
203 	return -EINVAL;
204 }
205 
206 static int mbigen_irq_domain_alloc(struct irq_domain *domain,
207 					unsigned int virq,
208 					unsigned int nr_irqs,
209 					void *args)
210 {
211 	struct irq_fwspec *fwspec = args;
212 	irq_hw_number_t hwirq;
213 	unsigned int type;
214 	struct mbigen_device *mgn_chip;
215 	int i, err;
216 
217 	err = mbigen_domain_translate(domain, fwspec, &hwirq, &type);
218 	if (err)
219 		return err;
220 
221 	err = platform_msi_domain_alloc(domain, virq, nr_irqs);
222 	if (err)
223 		return err;
224 
225 	mgn_chip = platform_msi_get_host_data(domain);
226 
227 	for (i = 0; i < nr_irqs; i++)
228 		irq_domain_set_hwirq_and_chip(domain, virq + i, hwirq + i,
229 				      &mbigen_irq_chip, mgn_chip->base);
230 
231 	return 0;
232 }
233 
234 static const struct irq_domain_ops mbigen_domain_ops = {
235 	.translate	= mbigen_domain_translate,
236 	.alloc		= mbigen_irq_domain_alloc,
237 	.free		= irq_domain_free_irqs_common,
238 };
239 
240 static int mbigen_of_create_domain(struct platform_device *pdev,
241 				   struct mbigen_device *mgn_chip)
242 {
243 	struct device *parent;
244 	struct platform_device *child;
245 	struct irq_domain *domain;
246 	struct device_node *np;
247 	u32 num_pins;
248 
249 	for_each_child_of_node(pdev->dev.of_node, np) {
250 		if (!of_property_read_bool(np, "interrupt-controller"))
251 			continue;
252 
253 		parent = platform_bus_type.dev_root;
254 		child = of_platform_device_create(np, NULL, parent);
255 		if (!child)
256 			return -ENOMEM;
257 
258 		if (of_property_read_u32(child->dev.of_node, "num-pins",
259 					 &num_pins) < 0) {
260 			dev_err(&pdev->dev, "No num-pins property\n");
261 			return -EINVAL;
262 		}
263 
264 		domain = platform_msi_create_device_domain(&child->dev, num_pins,
265 							   mbigen_write_msg,
266 							   &mbigen_domain_ops,
267 							   mgn_chip);
268 		if (!domain)
269 			return -ENOMEM;
270 	}
271 
272 	return 0;
273 }
274 
275 #ifdef CONFIG_ACPI
276 static int mbigen_acpi_create_domain(struct platform_device *pdev,
277 				     struct mbigen_device *mgn_chip)
278 {
279 	struct irq_domain *domain;
280 	u32 num_pins = 0;
281 	int ret;
282 
283 	/*
284 	 * "num-pins" is the total number of interrupt pins implemented in
285 	 * this mbigen instance, and mbigen is an interrupt controller
286 	 * connected to ITS  converting wired interrupts into MSI, so we
287 	 * use "num-pins" to alloc MSI vectors which are needed by client
288 	 * devices connected to it.
289 	 *
290 	 * Here is the DSDT device node used for mbigen in firmware:
291 	 *	Device(MBI0) {
292 	 *		Name(_HID, "HISI0152")
293 	 *		Name(_UID, Zero)
294 	 *		Name(_CRS, ResourceTemplate() {
295 	 *			Memory32Fixed(ReadWrite, 0xa0080000, 0x10000)
296 	 *		})
297 	 *
298 	 *		Name(_DSD, Package () {
299 	 *			ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
300 	 *			Package () {
301 	 *				Package () {"num-pins", 378}
302 	 *			}
303 	 *		})
304 	 *	}
305 	 */
306 	ret = device_property_read_u32(&pdev->dev, "num-pins", &num_pins);
307 	if (ret || num_pins == 0)
308 		return -EINVAL;
309 
310 	domain = platform_msi_create_device_domain(&pdev->dev, num_pins,
311 						   mbigen_write_msg,
312 						   &mbigen_domain_ops,
313 						   mgn_chip);
314 	if (!domain)
315 		return -ENOMEM;
316 
317 	return 0;
318 }
319 #else
320 static inline int mbigen_acpi_create_domain(struct platform_device *pdev,
321 					    struct mbigen_device *mgn_chip)
322 {
323 	return -ENODEV;
324 }
325 #endif
326 
327 static int mbigen_device_probe(struct platform_device *pdev)
328 {
329 	struct mbigen_device *mgn_chip;
330 	struct resource *res;
331 	int err;
332 
333 	mgn_chip = devm_kzalloc(&pdev->dev, sizeof(*mgn_chip), GFP_KERNEL);
334 	if (!mgn_chip)
335 		return -ENOMEM;
336 
337 	mgn_chip->pdev = pdev;
338 
339 	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
340 	if (!res)
341 		return -EINVAL;
342 
343 	mgn_chip->base = devm_ioremap(&pdev->dev, res->start,
344 				      resource_size(res));
345 	if (!mgn_chip->base) {
346 		dev_err(&pdev->dev, "failed to ioremap %pR\n", res);
347 		return -ENOMEM;
348 	}
349 
350 	if (IS_ENABLED(CONFIG_OF) && pdev->dev.of_node)
351 		err = mbigen_of_create_domain(pdev, mgn_chip);
352 	else if (ACPI_COMPANION(&pdev->dev))
353 		err = mbigen_acpi_create_domain(pdev, mgn_chip);
354 	else
355 		err = -EINVAL;
356 
357 	if (err) {
358 		dev_err(&pdev->dev, "Failed to create mbi-gen@%p irqdomain",
359 			mgn_chip->base);
360 		return err;
361 	}
362 
363 	platform_set_drvdata(pdev, mgn_chip);
364 	return 0;
365 }
366 
367 static const struct of_device_id mbigen_of_match[] = {
368 	{ .compatible = "hisilicon,mbigen-v2" },
369 	{ /* END */ }
370 };
371 MODULE_DEVICE_TABLE(of, mbigen_of_match);
372 
373 static const struct acpi_device_id mbigen_acpi_match[] = {
374 	{ "HISI0152", 0 },
375 	{}
376 };
377 MODULE_DEVICE_TABLE(acpi, mbigen_acpi_match);
378 
379 static struct platform_driver mbigen_platform_driver = {
380 	.driver = {
381 		.name		= "Hisilicon MBIGEN-V2",
382 		.of_match_table	= mbigen_of_match,
383 		.acpi_match_table = ACPI_PTR(mbigen_acpi_match),
384 	},
385 	.probe			= mbigen_device_probe,
386 };
387 
388 module_platform_driver(mbigen_platform_driver);
389 
390 MODULE_AUTHOR("Jun Ma <majun258@huawei.com>");
391 MODULE_AUTHOR("Yun Wu <wuyun.wu@huawei.com>");
392 MODULE_LICENSE("GPL");
393 MODULE_DESCRIPTION("Hisilicon MBI Generator driver");
394