1caab277bSThomas Gleixner // SPDX-License-Identifier: GPL-2.0-only 2717c3dbcSMa Jun /* 364ec2ad3SHao Fang * Copyright (C) 2015 HiSilicon Limited, All Rights Reserved. 4717c3dbcSMa Jun * Author: Jun Ma <majun258@huawei.com> 5717c3dbcSMa Jun * Author: Yun Wu <wuyun.wu@huawei.com> 6717c3dbcSMa Jun */ 7717c3dbcSMa Jun 8f907c515SHanjun Guo #include <linux/acpi.h> 99650c60eSMa Jun #include <linux/interrupt.h> 109650c60eSMa Jun #include <linux/irqchip.h> 11717c3dbcSMa Jun #include <linux/module.h> 129650c60eSMa Jun #include <linux/msi.h> 13717c3dbcSMa Jun #include <linux/of_address.h> 14717c3dbcSMa Jun #include <linux/of_irq.h> 15717c3dbcSMa Jun #include <linux/of_platform.h> 16717c3dbcSMa Jun #include <linux/platform_device.h> 17717c3dbcSMa Jun #include <linux/slab.h> 18717c3dbcSMa Jun 199650c60eSMa Jun /* Interrupt numbers per mbigen node supported */ 209650c60eSMa Jun #define IRQS_PER_MBIGEN_NODE 128 219650c60eSMa Jun 229650c60eSMa Jun /* 64 irqs (Pin0-pin63) are reserved for each mbigen chip */ 239650c60eSMa Jun #define RESERVED_IRQ_PER_MBIGEN_CHIP 64 249650c60eSMa Jun 259650c60eSMa Jun /* The maximum IRQ pin number of mbigen chip(start from 0) */ 269650c60eSMa Jun #define MAXIMUM_IRQ_PIN_NUM 1407 279650c60eSMa Jun 28b9994883SRandy Dunlap /* 299650c60eSMa Jun * In mbigen vector register 309650c60eSMa Jun * bit[21:12]: event id value 319650c60eSMa Jun * bit[11:0]: device id 329650c60eSMa Jun */ 339650c60eSMa Jun #define IRQ_EVENT_ID_SHIFT 12 349650c60eSMa Jun #define IRQ_EVENT_ID_MASK 0x3ff 359650c60eSMa Jun 369650c60eSMa Jun /* register range of each mbigen node */ 379650c60eSMa Jun #define MBIGEN_NODE_OFFSET 0x1000 389650c60eSMa Jun 399650c60eSMa Jun /* offset of vector register in mbigen node */ 409650c60eSMa Jun #define REG_MBIGEN_VEC_OFFSET 0x200 419650c60eSMa Jun 42b9994883SRandy Dunlap /* 43a6c2f87bSMa Jun * offset of clear register in mbigen node 44a6c2f87bSMa Jun * This register is used to clear the status 45a6c2f87bSMa Jun * of interrupt 46a6c2f87bSMa Jun */ 47a6c2f87bSMa Jun #define REG_MBIGEN_CLEAR_OFFSET 0xa000 48a6c2f87bSMa Jun 49b9994883SRandy Dunlap /* 50a6c2f87bSMa Jun * offset of interrupt type register 51a6c2f87bSMa Jun * This register is used to configure interrupt 52a6c2f87bSMa Jun * trigger type 53a6c2f87bSMa Jun */ 54a6c2f87bSMa Jun #define REG_MBIGEN_TYPE_OFFSET 0x0 55a6c2f87bSMa Jun 56a6c2f87bSMa Jun /** 57717c3dbcSMa Jun * struct mbigen_device - holds the information of mbigen device. 58717c3dbcSMa Jun * 59717c3dbcSMa Jun * @pdev: pointer to the platform device structure of mbigen chip. 60717c3dbcSMa Jun * @base: mapped address of this mbigen chip. 61717c3dbcSMa Jun */ 62717c3dbcSMa Jun struct mbigen_device { 63717c3dbcSMa Jun struct platform_device *pdev; 64717c3dbcSMa Jun void __iomem *base; 65717c3dbcSMa Jun }; 66717c3dbcSMa Jun 679650c60eSMa Jun static inline unsigned int get_mbigen_vec_reg(irq_hw_number_t hwirq) 689650c60eSMa Jun { 699650c60eSMa Jun unsigned int nid, pin; 709650c60eSMa Jun 719650c60eSMa Jun hwirq -= RESERVED_IRQ_PER_MBIGEN_CHIP; 729650c60eSMa Jun nid = hwirq / IRQS_PER_MBIGEN_NODE + 1; 739650c60eSMa Jun pin = hwirq % IRQS_PER_MBIGEN_NODE; 749650c60eSMa Jun 759650c60eSMa Jun return pin * 4 + nid * MBIGEN_NODE_OFFSET 769650c60eSMa Jun + REG_MBIGEN_VEC_OFFSET; 779650c60eSMa Jun } 789650c60eSMa Jun 79a6c2f87bSMa Jun static inline void get_mbigen_type_reg(irq_hw_number_t hwirq, 80a6c2f87bSMa Jun u32 *mask, u32 *addr) 81a6c2f87bSMa Jun { 82a6c2f87bSMa Jun unsigned int nid, irq_ofst, ofst; 83a6c2f87bSMa Jun 84a6c2f87bSMa Jun hwirq -= RESERVED_IRQ_PER_MBIGEN_CHIP; 85a6c2f87bSMa Jun nid = hwirq / IRQS_PER_MBIGEN_NODE + 1; 86a6c2f87bSMa Jun irq_ofst = hwirq % IRQS_PER_MBIGEN_NODE; 87a6c2f87bSMa Jun 88a6c2f87bSMa Jun *mask = 1 << (irq_ofst % 32); 89a6c2f87bSMa Jun ofst = irq_ofst / 32 * 4; 90a6c2f87bSMa Jun 91a6c2f87bSMa Jun *addr = ofst + nid * MBIGEN_NODE_OFFSET 92a6c2f87bSMa Jun + REG_MBIGEN_TYPE_OFFSET; 93a6c2f87bSMa Jun } 94a6c2f87bSMa Jun 95a6c2f87bSMa Jun static inline void get_mbigen_clear_reg(irq_hw_number_t hwirq, 96a6c2f87bSMa Jun u32 *mask, u32 *addr) 97a6c2f87bSMa Jun { 989459a04bSMaJun unsigned int ofst = (hwirq / 32) * 4; 99a6c2f87bSMa Jun 100a6c2f87bSMa Jun *mask = 1 << (hwirq % 32); 101a6c2f87bSMa Jun *addr = ofst + REG_MBIGEN_CLEAR_OFFSET; 102a6c2f87bSMa Jun } 103a6c2f87bSMa Jun 104a6c2f87bSMa Jun static void mbigen_eoi_irq(struct irq_data *data) 105a6c2f87bSMa Jun { 106a6c2f87bSMa Jun void __iomem *base = data->chip_data; 107a6c2f87bSMa Jun u32 mask, addr; 108a6c2f87bSMa Jun 109a6c2f87bSMa Jun get_mbigen_clear_reg(data->hwirq, &mask, &addr); 110a6c2f87bSMa Jun 111a6c2f87bSMa Jun writel_relaxed(mask, base + addr); 112a6c2f87bSMa Jun 113a6c2f87bSMa Jun irq_chip_eoi_parent(data); 114a6c2f87bSMa Jun } 115a6c2f87bSMa Jun 116a6c2f87bSMa Jun static int mbigen_set_type(struct irq_data *data, unsigned int type) 117a6c2f87bSMa Jun { 118a6c2f87bSMa Jun void __iomem *base = data->chip_data; 119a6c2f87bSMa Jun u32 mask, addr, val; 120a6c2f87bSMa Jun 121a6c2f87bSMa Jun if (type != IRQ_TYPE_LEVEL_HIGH && type != IRQ_TYPE_EDGE_RISING) 122a6c2f87bSMa Jun return -EINVAL; 123a6c2f87bSMa Jun 124a6c2f87bSMa Jun get_mbigen_type_reg(data->hwirq, &mask, &addr); 125a6c2f87bSMa Jun 126a6c2f87bSMa Jun val = readl_relaxed(base + addr); 127a6c2f87bSMa Jun 128a6c2f87bSMa Jun if (type == IRQ_TYPE_LEVEL_HIGH) 129a6c2f87bSMa Jun val |= mask; 130a6c2f87bSMa Jun else 131a6c2f87bSMa Jun val &= ~mask; 132a6c2f87bSMa Jun 133a6c2f87bSMa Jun writel_relaxed(val, base + addr); 134a6c2f87bSMa Jun 135a6c2f87bSMa Jun return 0; 136a6c2f87bSMa Jun } 137a6c2f87bSMa Jun 138fbfe7e13SThomas Gleixner static void mbigen_write_msi_msg(struct irq_data *d, struct msi_msg *msg) 1399650c60eSMa Jun { 1409650c60eSMa Jun void __iomem *base = d->chip_data; 1419650c60eSMa Jun u32 val; 1429650c60eSMa Jun 143fca269f2SJianguo Chen if (!msg->address_lo && !msg->address_hi) 144fca269f2SJianguo Chen return; 145fca269f2SJianguo Chen 1469650c60eSMa Jun base += get_mbigen_vec_reg(d->hwirq); 1479650c60eSMa Jun val = readl_relaxed(base); 1489650c60eSMa Jun 1499650c60eSMa Jun val &= ~(IRQ_EVENT_ID_MASK << IRQ_EVENT_ID_SHIFT); 1509650c60eSMa Jun val |= (msg->data << IRQ_EVENT_ID_SHIFT); 1519650c60eSMa Jun 1529650c60eSMa Jun /* The address of doorbell is encoded in mbigen register by default 1539650c60eSMa Jun * So,we don't need to program the doorbell address at here 1549650c60eSMa Jun */ 1559650c60eSMa Jun writel_relaxed(val, base); 1569650c60eSMa Jun } 1579650c60eSMa Jun 158fbfe7e13SThomas Gleixner static int mbigen_domain_translate(struct irq_domain *d, struct irq_fwspec *fwspec, 159fbfe7e13SThomas Gleixner unsigned long *hwirq, unsigned int *type) 1609650c60eSMa Jun { 161f907c515SHanjun Guo if (is_of_node(fwspec->fwnode) || is_acpi_device_node(fwspec->fwnode)) { 1629650c60eSMa Jun if (fwspec->param_count != 2) 1639650c60eSMa Jun return -EINVAL; 1649650c60eSMa Jun 1659650c60eSMa Jun if ((fwspec->param[0] > MAXIMUM_IRQ_PIN_NUM) || 1669650c60eSMa Jun (fwspec->param[0] < RESERVED_IRQ_PER_MBIGEN_CHIP)) 1679650c60eSMa Jun return -EINVAL; 1689650c60eSMa Jun else 1699650c60eSMa Jun *hwirq = fwspec->param[0]; 1709650c60eSMa Jun 1719650c60eSMa Jun /* If there is no valid irq type, just use the default type */ 1729650c60eSMa Jun if ((fwspec->param[1] == IRQ_TYPE_EDGE_RISING) || 1739650c60eSMa Jun (fwspec->param[1] == IRQ_TYPE_LEVEL_HIGH)) 1749650c60eSMa Jun *type = fwspec->param[1]; 1759650c60eSMa Jun else 1769650c60eSMa Jun return -EINVAL; 1779650c60eSMa Jun 1789650c60eSMa Jun return 0; 1799650c60eSMa Jun } 1809650c60eSMa Jun return -EINVAL; 1819650c60eSMa Jun } 1829650c60eSMa Jun 183fbfe7e13SThomas Gleixner static void mbigen_domain_set_desc(msi_alloc_info_t *arg, struct msi_desc *desc) 184fbfe7e13SThomas Gleixner { 185fbfe7e13SThomas Gleixner arg->desc = desc; 186fbfe7e13SThomas Gleixner arg->hwirq = (u32)desc->data.icookie.value; 187fbfe7e13SThomas Gleixner } 188fbfe7e13SThomas Gleixner 189fbfe7e13SThomas Gleixner static const struct msi_domain_template mbigen_msi_template = { 190fbfe7e13SThomas Gleixner .chip = { 191fbfe7e13SThomas Gleixner .name = "mbigen-v2", 192fbfe7e13SThomas Gleixner .irq_mask = irq_chip_mask_parent, 193fbfe7e13SThomas Gleixner .irq_unmask = irq_chip_unmask_parent, 194fbfe7e13SThomas Gleixner .irq_eoi = mbigen_eoi_irq, 195fbfe7e13SThomas Gleixner .irq_set_type = mbigen_set_type, 196fbfe7e13SThomas Gleixner .irq_write_msi_msg = mbigen_write_msi_msg, 197fbfe7e13SThomas Gleixner }, 198fbfe7e13SThomas Gleixner 199fbfe7e13SThomas Gleixner .ops = { 200fbfe7e13SThomas Gleixner .set_desc = mbigen_domain_set_desc, 201fbfe7e13SThomas Gleixner .msi_translate = mbigen_domain_translate, 202fbfe7e13SThomas Gleixner }, 203fbfe7e13SThomas Gleixner 204fbfe7e13SThomas Gleixner .info = { 205fbfe7e13SThomas Gleixner .bus_token = DOMAIN_BUS_WIRED_TO_MSI, 206fbfe7e13SThomas Gleixner .flags = MSI_FLAG_USE_DEV_FWNODE, 207fbfe7e13SThomas Gleixner }, 208fbfe7e13SThomas Gleixner }; 209fbfe7e13SThomas Gleixner 210fbfe7e13SThomas Gleixner static bool mbigen_create_device_domain(struct device *dev, unsigned int size, 211fbfe7e13SThomas Gleixner struct mbigen_device *mgn_chip) 212fbfe7e13SThomas Gleixner { 213*752e021fSThomas Gleixner if (WARN_ON_ONCE(!dev->msi.domain)) 214fbfe7e13SThomas Gleixner return false; 215fbfe7e13SThomas Gleixner 216fbfe7e13SThomas Gleixner return msi_create_device_irq_domain(dev, MSI_DEFAULT_DOMAIN, 217fbfe7e13SThomas Gleixner &mbigen_msi_template, size, 218fbfe7e13SThomas Gleixner NULL, mgn_chip->base); 219fbfe7e13SThomas Gleixner } 220fbfe7e13SThomas Gleixner 22176e1f77fSKefeng Wang static int mbigen_of_create_domain(struct platform_device *pdev, 22276e1f77fSKefeng Wang struct mbigen_device *mgn_chip) 223717c3dbcSMa Jun { 224ed2a1002SMaJun struct platform_device *child; 225ed2a1002SMaJun struct device_node *np; 2269650c60eSMa Jun u32 num_pins; 227cddb536aSKefeng Wang int ret = 0; 228cddb536aSKefeng Wang 229ed2a1002SMaJun for_each_child_of_node(pdev->dev.of_node, np) { 230ed2a1002SMaJun if (!of_property_read_bool(np, "interrupt-controller")) 231ed2a1002SMaJun continue; 232ed2a1002SMaJun 233fb33a46cSChen Jun child = of_platform_device_create(np, NULL, NULL); 234321275f0SNishka Dasgupta if (!child) { 235cddb536aSKefeng Wang ret = -ENOMEM; 236cddb536aSKefeng Wang break; 237fea087fcSGreg Kroah-Hartman } 238ed2a1002SMaJun 239ed2a1002SMaJun if (of_property_read_u32(child->dev.of_node, "num-pins", 240ed2a1002SMaJun &num_pins) < 0) { 2419650c60eSMa Jun dev_err(&pdev->dev, "No num-pins property\n"); 242cddb536aSKefeng Wang ret = -EINVAL; 243cddb536aSKefeng Wang break; 2449650c60eSMa Jun } 2459650c60eSMa Jun 246fbfe7e13SThomas Gleixner if (!mbigen_create_device_domain(&child->dev, num_pins, mgn_chip)) { 247cddb536aSKefeng Wang ret = -ENOMEM; 248cddb536aSKefeng Wang break; 249ed2a1002SMaJun } 250321275f0SNishka Dasgupta } 2519650c60eSMa Jun 252cddb536aSKefeng Wang if (ret) 253cddb536aSKefeng Wang of_node_put(np); 254cddb536aSKefeng Wang 255cddb536aSKefeng Wang return ret; 25676e1f77fSKefeng Wang } 25776e1f77fSKefeng Wang 258f907c515SHanjun Guo #ifdef CONFIG_ACPI 259c96d6abbSYang Yingliang static const struct acpi_device_id mbigen_acpi_match[] = { 260c96d6abbSYang Yingliang { "HISI0152", 0 }, 261c96d6abbSYang Yingliang {} 262c96d6abbSYang Yingliang }; 263c96d6abbSYang Yingliang MODULE_DEVICE_TABLE(acpi, mbigen_acpi_match); 264c96d6abbSYang Yingliang 265f907c515SHanjun Guo static int mbigen_acpi_create_domain(struct platform_device *pdev, 266f907c515SHanjun Guo struct mbigen_device *mgn_chip) 267f907c515SHanjun Guo { 268f907c515SHanjun Guo u32 num_pins = 0; 269f907c515SHanjun Guo int ret; 270f907c515SHanjun Guo 271f907c515SHanjun Guo /* 272f907c515SHanjun Guo * "num-pins" is the total number of interrupt pins implemented in 273f907c515SHanjun Guo * this mbigen instance, and mbigen is an interrupt controller 274f907c515SHanjun Guo * connected to ITS converting wired interrupts into MSI, so we 275f907c515SHanjun Guo * use "num-pins" to alloc MSI vectors which are needed by client 276f907c515SHanjun Guo * devices connected to it. 277f907c515SHanjun Guo * 278f907c515SHanjun Guo * Here is the DSDT device node used for mbigen in firmware: 279f907c515SHanjun Guo * Device(MBI0) { 280f907c515SHanjun Guo * Name(_HID, "HISI0152") 281f907c515SHanjun Guo * Name(_UID, Zero) 282f907c515SHanjun Guo * Name(_CRS, ResourceTemplate() { 283f907c515SHanjun Guo * Memory32Fixed(ReadWrite, 0xa0080000, 0x10000) 284f907c515SHanjun Guo * }) 285f907c515SHanjun Guo * 286f907c515SHanjun Guo * Name(_DSD, Package () { 287f907c515SHanjun Guo * ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), 288f907c515SHanjun Guo * Package () { 289f907c515SHanjun Guo * Package () {"num-pins", 378} 290f907c515SHanjun Guo * } 291f907c515SHanjun Guo * }) 292f907c515SHanjun Guo * } 293f907c515SHanjun Guo */ 294f907c515SHanjun Guo ret = device_property_read_u32(&pdev->dev, "num-pins", &num_pins); 295f907c515SHanjun Guo if (ret || num_pins == 0) 296f907c515SHanjun Guo return -EINVAL; 297f907c515SHanjun Guo 298fbfe7e13SThomas Gleixner if (!mbigen_create_device_domain(&pdev->dev, num_pins, mgn_chip)) 299f907c515SHanjun Guo return -ENOMEM; 300f907c515SHanjun Guo 301f907c515SHanjun Guo return 0; 302f907c515SHanjun Guo } 303f907c515SHanjun Guo #else 304f907c515SHanjun Guo static inline int mbigen_acpi_create_domain(struct platform_device *pdev, 305f907c515SHanjun Guo struct mbigen_device *mgn_chip) 306f907c515SHanjun Guo { 307f907c515SHanjun Guo return -ENODEV; 308f907c515SHanjun Guo } 309f907c515SHanjun Guo #endif 310f907c515SHanjun Guo 31176e1f77fSKefeng Wang static int mbigen_device_probe(struct platform_device *pdev) 31276e1f77fSKefeng Wang { 31376e1f77fSKefeng Wang struct mbigen_device *mgn_chip; 31476e1f77fSKefeng Wang struct resource *res; 31576e1f77fSKefeng Wang int err; 31676e1f77fSKefeng Wang 31776e1f77fSKefeng Wang mgn_chip = devm_kzalloc(&pdev->dev, sizeof(*mgn_chip), GFP_KERNEL); 31876e1f77fSKefeng Wang if (!mgn_chip) 31976e1f77fSKefeng Wang return -ENOMEM; 32076e1f77fSKefeng Wang 32176e1f77fSKefeng Wang mgn_chip->pdev = pdev; 32276e1f77fSKefeng Wang 32376e1f77fSKefeng Wang res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 324ad7cc3c0SHanjun Guo if (!res) 325ad7cc3c0SHanjun Guo return -EINVAL; 326ad7cc3c0SHanjun Guo 3275ba9b0a1SHanjun Guo mgn_chip->base = devm_ioremap(&pdev->dev, res->start, 3285ba9b0a1SHanjun Guo resource_size(res)); 3295ba9b0a1SHanjun Guo if (!mgn_chip->base) { 3305ba9b0a1SHanjun Guo dev_err(&pdev->dev, "failed to ioremap %pR\n", res); 3315ba9b0a1SHanjun Guo return -ENOMEM; 3325ba9b0a1SHanjun Guo } 33376e1f77fSKefeng Wang 334f907c515SHanjun Guo if (IS_ENABLED(CONFIG_OF) && pdev->dev.of_node) 33576e1f77fSKefeng Wang err = mbigen_of_create_domain(pdev, mgn_chip); 336f907c515SHanjun Guo else if (ACPI_COMPANION(&pdev->dev)) 337f907c515SHanjun Guo err = mbigen_acpi_create_domain(pdev, mgn_chip); 338f907c515SHanjun Guo else 339f907c515SHanjun Guo err = -EINVAL; 340f907c515SHanjun Guo 341f907c515SHanjun Guo if (err) { 3420bdd0047SKefeng Wang dev_err(&pdev->dev, "Failed to create mbi-gen irqdomain\n"); 34376e1f77fSKefeng Wang return err; 344f907c515SHanjun Guo } 34576e1f77fSKefeng Wang 346717c3dbcSMa Jun platform_set_drvdata(pdev, mgn_chip); 347717c3dbcSMa Jun return 0; 348717c3dbcSMa Jun } 349717c3dbcSMa Jun 350717c3dbcSMa Jun static const struct of_device_id mbigen_of_match[] = { 351717c3dbcSMa Jun { .compatible = "hisilicon,mbigen-v2" }, 352717c3dbcSMa Jun { /* END */ } 353717c3dbcSMa Jun }; 354717c3dbcSMa Jun MODULE_DEVICE_TABLE(of, mbigen_of_match); 355717c3dbcSMa Jun 356717c3dbcSMa Jun static struct platform_driver mbigen_platform_driver = { 357717c3dbcSMa Jun .driver = { 358717c3dbcSMa Jun .name = "Hisilicon MBIGEN-V2", 359717c3dbcSMa Jun .of_match_table = mbigen_of_match, 360f907c515SHanjun Guo .acpi_match_table = ACPI_PTR(mbigen_acpi_match), 361d6152e6eSJohn Garry .suppress_bind_attrs = true, 362717c3dbcSMa Jun }, 363717c3dbcSMa Jun .probe = mbigen_device_probe, 364717c3dbcSMa Jun }; 365717c3dbcSMa Jun 366717c3dbcSMa Jun module_platform_driver(mbigen_platform_driver); 367717c3dbcSMa Jun 368717c3dbcSMa Jun MODULE_AUTHOR("Jun Ma <majun258@huawei.com>"); 369717c3dbcSMa Jun MODULE_AUTHOR("Yun Wu <wuyun.wu@huawei.com>"); 37064ec2ad3SHao Fang MODULE_DESCRIPTION("HiSilicon MBI Generator driver"); 371