1 /* 2 * Freescale SCFG MSI(-X) support 3 * 4 * Copyright (C) 2016 Freescale Semiconductor. 5 * 6 * Author: Minghuan Lian <Minghuan.Lian@nxp.com> 7 * 8 * This program is free software; you can redistribute it and/or modify 9 * it under the terms of the GNU General Public License version 2 as 10 * published by the Free Software Foundation. 11 */ 12 13 #include <linux/kernel.h> 14 #include <linux/module.h> 15 #include <linux/msi.h> 16 #include <linux/interrupt.h> 17 #include <linux/irq.h> 18 #include <linux/irqchip/chained_irq.h> 19 #include <linux/irqdomain.h> 20 #include <linux/of_irq.h> 21 #include <linux/of_pci.h> 22 #include <linux/of_platform.h> 23 #include <linux/spinlock.h> 24 25 #define MSI_IRQS_PER_MSIR 32 26 #define MSI_MSIR_OFFSET 4 27 28 #define MSI_LS1043V1_1_IRQS_PER_MSIR 8 29 #define MSI_LS1043V1_1_MSIR_OFFSET 0x10 30 31 struct ls_scfg_msi_cfg { 32 u32 ibs_shift; /* Shift of interrupt bit select */ 33 u32 msir_irqs; /* The irq number per MSIR */ 34 u32 msir_base; /* The base address of MSIR */ 35 }; 36 37 struct ls_scfg_msir { 38 struct ls_scfg_msi *msi_data; 39 unsigned int index; 40 unsigned int gic_irq; 41 unsigned int bit_start; 42 unsigned int bit_end; 43 unsigned int srs; /* Shared interrupt register select */ 44 void __iomem *reg; 45 }; 46 47 struct ls_scfg_msi { 48 spinlock_t lock; 49 struct platform_device *pdev; 50 struct irq_domain *parent; 51 struct irq_domain *msi_domain; 52 void __iomem *regs; 53 phys_addr_t msiir_addr; 54 struct ls_scfg_msi_cfg *cfg; 55 u32 msir_num; 56 struct ls_scfg_msir *msir; 57 u32 irqs_num; 58 unsigned long *used; 59 }; 60 61 static struct irq_chip ls_scfg_msi_irq_chip = { 62 .name = "MSI", 63 .irq_mask = pci_msi_mask_irq, 64 .irq_unmask = pci_msi_unmask_irq, 65 }; 66 67 static struct msi_domain_info ls_scfg_msi_domain_info = { 68 .flags = (MSI_FLAG_USE_DEF_DOM_OPS | 69 MSI_FLAG_USE_DEF_CHIP_OPS | 70 MSI_FLAG_PCI_MSIX), 71 .chip = &ls_scfg_msi_irq_chip, 72 }; 73 74 static int msi_affinity_flag = 1; 75 76 static int __init early_parse_ls_scfg_msi(char *p) 77 { 78 if (p && strncmp(p, "no-affinity", 11) == 0) 79 msi_affinity_flag = 0; 80 else 81 msi_affinity_flag = 1; 82 83 return 0; 84 } 85 early_param("lsmsi", early_parse_ls_scfg_msi); 86 87 static void ls_scfg_msi_compose_msg(struct irq_data *data, struct msi_msg *msg) 88 { 89 struct ls_scfg_msi *msi_data = irq_data_get_irq_chip_data(data); 90 91 msg->address_hi = upper_32_bits(msi_data->msiir_addr); 92 msg->address_lo = lower_32_bits(msi_data->msiir_addr); 93 msg->data = data->hwirq; 94 95 if (msi_affinity_flag) 96 msg->data |= cpumask_first(data->common->affinity); 97 } 98 99 static int ls_scfg_msi_set_affinity(struct irq_data *irq_data, 100 const struct cpumask *mask, bool force) 101 { 102 struct ls_scfg_msi *msi_data = irq_data_get_irq_chip_data(irq_data); 103 u32 cpu; 104 105 if (!msi_affinity_flag) 106 return -EINVAL; 107 108 if (!force) 109 cpu = cpumask_any_and(mask, cpu_online_mask); 110 else 111 cpu = cpumask_first(mask); 112 113 if (cpu >= msi_data->msir_num) 114 return -EINVAL; 115 116 if (msi_data->msir[cpu].gic_irq <= 0) { 117 pr_warn("cannot bind the irq to cpu%d\n", cpu); 118 return -EINVAL; 119 } 120 121 cpumask_copy(irq_data->common->affinity, mask); 122 123 return IRQ_SET_MASK_OK; 124 } 125 126 static struct irq_chip ls_scfg_msi_parent_chip = { 127 .name = "SCFG", 128 .irq_compose_msi_msg = ls_scfg_msi_compose_msg, 129 .irq_set_affinity = ls_scfg_msi_set_affinity, 130 }; 131 132 static int ls_scfg_msi_domain_irq_alloc(struct irq_domain *domain, 133 unsigned int virq, 134 unsigned int nr_irqs, 135 void *args) 136 { 137 struct ls_scfg_msi *msi_data = domain->host_data; 138 int pos, err = 0; 139 140 WARN_ON(nr_irqs != 1); 141 142 spin_lock(&msi_data->lock); 143 pos = find_first_zero_bit(msi_data->used, msi_data->irqs_num); 144 if (pos < msi_data->irqs_num) 145 __set_bit(pos, msi_data->used); 146 else 147 err = -ENOSPC; 148 spin_unlock(&msi_data->lock); 149 150 if (err) 151 return err; 152 153 irq_domain_set_info(domain, virq, pos, 154 &ls_scfg_msi_parent_chip, msi_data, 155 handle_simple_irq, NULL, NULL); 156 157 return 0; 158 } 159 160 static void ls_scfg_msi_domain_irq_free(struct irq_domain *domain, 161 unsigned int virq, unsigned int nr_irqs) 162 { 163 struct irq_data *d = irq_domain_get_irq_data(domain, virq); 164 struct ls_scfg_msi *msi_data = irq_data_get_irq_chip_data(d); 165 int pos; 166 167 pos = d->hwirq; 168 if (pos < 0 || pos >= msi_data->irqs_num) { 169 pr_err("failed to teardown msi. Invalid hwirq %d\n", pos); 170 return; 171 } 172 173 spin_lock(&msi_data->lock); 174 __clear_bit(pos, msi_data->used); 175 spin_unlock(&msi_data->lock); 176 } 177 178 static const struct irq_domain_ops ls_scfg_msi_domain_ops = { 179 .alloc = ls_scfg_msi_domain_irq_alloc, 180 .free = ls_scfg_msi_domain_irq_free, 181 }; 182 183 static void ls_scfg_msi_irq_handler(struct irq_desc *desc) 184 { 185 struct ls_scfg_msir *msir = irq_desc_get_handler_data(desc); 186 struct ls_scfg_msi *msi_data = msir->msi_data; 187 unsigned long val; 188 int pos, size, virq, hwirq; 189 190 chained_irq_enter(irq_desc_get_chip(desc), desc); 191 192 val = ioread32be(msir->reg); 193 194 pos = msir->bit_start; 195 size = msir->bit_end + 1; 196 197 for_each_set_bit_from(pos, &val, size) { 198 hwirq = ((msir->bit_end - pos) << msi_data->cfg->ibs_shift) | 199 msir->srs; 200 virq = irq_find_mapping(msi_data->parent, hwirq); 201 if (virq) 202 generic_handle_irq(virq); 203 } 204 205 chained_irq_exit(irq_desc_get_chip(desc), desc); 206 } 207 208 static int ls_scfg_msi_domains_init(struct ls_scfg_msi *msi_data) 209 { 210 /* Initialize MSI domain parent */ 211 msi_data->parent = irq_domain_add_linear(NULL, 212 msi_data->irqs_num, 213 &ls_scfg_msi_domain_ops, 214 msi_data); 215 if (!msi_data->parent) { 216 dev_err(&msi_data->pdev->dev, "failed to create IRQ domain\n"); 217 return -ENOMEM; 218 } 219 220 msi_data->msi_domain = pci_msi_create_irq_domain( 221 of_node_to_fwnode(msi_data->pdev->dev.of_node), 222 &ls_scfg_msi_domain_info, 223 msi_data->parent); 224 if (!msi_data->msi_domain) { 225 dev_err(&msi_data->pdev->dev, "failed to create MSI domain\n"); 226 irq_domain_remove(msi_data->parent); 227 return -ENOMEM; 228 } 229 230 return 0; 231 } 232 233 static int ls_scfg_msi_setup_hwirq(struct ls_scfg_msi *msi_data, int index) 234 { 235 struct ls_scfg_msir *msir; 236 int virq, i, hwirq; 237 238 virq = platform_get_irq(msi_data->pdev, index); 239 if (virq <= 0) 240 return -ENODEV; 241 242 msir = &msi_data->msir[index]; 243 msir->index = index; 244 msir->msi_data = msi_data; 245 msir->gic_irq = virq; 246 msir->reg = msi_data->regs + msi_data->cfg->msir_base + 4 * index; 247 248 if (msi_data->cfg->msir_irqs == MSI_LS1043V1_1_IRQS_PER_MSIR) { 249 msir->bit_start = 32 - ((msir->index + 1) * 250 MSI_LS1043V1_1_IRQS_PER_MSIR); 251 msir->bit_end = msir->bit_start + 252 MSI_LS1043V1_1_IRQS_PER_MSIR - 1; 253 } else { 254 msir->bit_start = 0; 255 msir->bit_end = msi_data->cfg->msir_irqs - 1; 256 } 257 258 irq_set_chained_handler_and_data(msir->gic_irq, 259 ls_scfg_msi_irq_handler, 260 msir); 261 262 if (msi_affinity_flag) { 263 /* Associate MSIR interrupt to the cpu */ 264 irq_set_affinity(msir->gic_irq, get_cpu_mask(index)); 265 msir->srs = 0; /* This value is determined by the CPU */ 266 } else 267 msir->srs = index; 268 269 /* Release the hwirqs corresponding to this MSIR */ 270 if (!msi_affinity_flag || msir->index == 0) { 271 for (i = 0; i < msi_data->cfg->msir_irqs; i++) { 272 hwirq = i << msi_data->cfg->ibs_shift | msir->index; 273 bitmap_clear(msi_data->used, hwirq, 1); 274 } 275 } 276 277 return 0; 278 } 279 280 static int ls_scfg_msi_teardown_hwirq(struct ls_scfg_msir *msir) 281 { 282 struct ls_scfg_msi *msi_data = msir->msi_data; 283 int i, hwirq; 284 285 if (msir->gic_irq > 0) 286 irq_set_chained_handler_and_data(msir->gic_irq, NULL, NULL); 287 288 for (i = 0; i < msi_data->cfg->msir_irqs; i++) { 289 hwirq = i << msi_data->cfg->ibs_shift | msir->index; 290 bitmap_set(msi_data->used, hwirq, 1); 291 } 292 293 return 0; 294 } 295 296 static struct ls_scfg_msi_cfg ls1021_msi_cfg = { 297 .ibs_shift = 3, 298 .msir_irqs = MSI_IRQS_PER_MSIR, 299 .msir_base = MSI_MSIR_OFFSET, 300 }; 301 302 static struct ls_scfg_msi_cfg ls1046_msi_cfg = { 303 .ibs_shift = 2, 304 .msir_irqs = MSI_IRQS_PER_MSIR, 305 .msir_base = MSI_MSIR_OFFSET, 306 }; 307 308 static struct ls_scfg_msi_cfg ls1043_v1_1_msi_cfg = { 309 .ibs_shift = 2, 310 .msir_irqs = MSI_LS1043V1_1_IRQS_PER_MSIR, 311 .msir_base = MSI_LS1043V1_1_MSIR_OFFSET, 312 }; 313 314 static const struct of_device_id ls_scfg_msi_id[] = { 315 /* The following two misspelled compatibles are obsolete */ 316 { .compatible = "fsl,1s1021a-msi", .data = &ls1021_msi_cfg}, 317 { .compatible = "fsl,1s1043a-msi", .data = &ls1021_msi_cfg}, 318 319 { .compatible = "fsl,ls1012a-msi", .data = &ls1021_msi_cfg }, 320 { .compatible = "fsl,ls1021a-msi", .data = &ls1021_msi_cfg }, 321 { .compatible = "fsl,ls1043a-msi", .data = &ls1021_msi_cfg }, 322 { .compatible = "fsl,ls1043a-v1.1-msi", .data = &ls1043_v1_1_msi_cfg }, 323 { .compatible = "fsl,ls1046a-msi", .data = &ls1046_msi_cfg }, 324 {}, 325 }; 326 MODULE_DEVICE_TABLE(of, ls_scfg_msi_id); 327 328 static int ls_scfg_msi_probe(struct platform_device *pdev) 329 { 330 const struct of_device_id *match; 331 struct ls_scfg_msi *msi_data; 332 struct resource *res; 333 int i, ret; 334 335 match = of_match_device(ls_scfg_msi_id, &pdev->dev); 336 if (!match) 337 return -ENODEV; 338 339 msi_data = devm_kzalloc(&pdev->dev, sizeof(*msi_data), GFP_KERNEL); 340 if (!msi_data) 341 return -ENOMEM; 342 343 msi_data->cfg = (struct ls_scfg_msi_cfg *) match->data; 344 345 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 346 msi_data->regs = devm_ioremap_resource(&pdev->dev, res); 347 if (IS_ERR(msi_data->regs)) { 348 dev_err(&pdev->dev, "failed to initialize 'regs'\n"); 349 return PTR_ERR(msi_data->regs); 350 } 351 msi_data->msiir_addr = res->start; 352 353 msi_data->pdev = pdev; 354 spin_lock_init(&msi_data->lock); 355 356 msi_data->irqs_num = MSI_IRQS_PER_MSIR * 357 (1 << msi_data->cfg->ibs_shift); 358 msi_data->used = devm_kcalloc(&pdev->dev, 359 BITS_TO_LONGS(msi_data->irqs_num), 360 sizeof(*msi_data->used), 361 GFP_KERNEL); 362 if (!msi_data->used) 363 return -ENOMEM; 364 /* 365 * Reserve all the hwirqs 366 * The available hwirqs will be released in ls1_msi_setup_hwirq() 367 */ 368 bitmap_set(msi_data->used, 0, msi_data->irqs_num); 369 370 msi_data->msir_num = of_irq_count(pdev->dev.of_node); 371 372 if (msi_affinity_flag) { 373 u32 cpu_num; 374 375 cpu_num = num_possible_cpus(); 376 if (msi_data->msir_num >= cpu_num) 377 msi_data->msir_num = cpu_num; 378 else 379 msi_affinity_flag = 0; 380 } 381 382 msi_data->msir = devm_kcalloc(&pdev->dev, msi_data->msir_num, 383 sizeof(*msi_data->msir), 384 GFP_KERNEL); 385 if (!msi_data->msir) 386 return -ENOMEM; 387 388 for (i = 0; i < msi_data->msir_num; i++) 389 ls_scfg_msi_setup_hwirq(msi_data, i); 390 391 ret = ls_scfg_msi_domains_init(msi_data); 392 if (ret) 393 return ret; 394 395 platform_set_drvdata(pdev, msi_data); 396 397 return 0; 398 } 399 400 static int ls_scfg_msi_remove(struct platform_device *pdev) 401 { 402 struct ls_scfg_msi *msi_data = platform_get_drvdata(pdev); 403 int i; 404 405 for (i = 0; i < msi_data->msir_num; i++) 406 ls_scfg_msi_teardown_hwirq(&msi_data->msir[i]); 407 408 irq_domain_remove(msi_data->msi_domain); 409 irq_domain_remove(msi_data->parent); 410 411 platform_set_drvdata(pdev, NULL); 412 413 return 0; 414 } 415 416 static struct platform_driver ls_scfg_msi_driver = { 417 .driver = { 418 .name = "ls-scfg-msi", 419 .of_match_table = ls_scfg_msi_id, 420 }, 421 .probe = ls_scfg_msi_probe, 422 .remove = ls_scfg_msi_remove, 423 }; 424 425 module_platform_driver(ls_scfg_msi_driver); 426 427 MODULE_AUTHOR("Minghuan Lian <Minghuan.Lian@nxp.com>"); 428 MODULE_DESCRIPTION("Freescale Layerscape SCFG MSI controller driver"); 429 MODULE_LICENSE("GPL v2"); 430