1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Loongson Extend I/O Interrupt Controller support
4 *
5 * Copyright (C) 2020-2022 Loongson Technology Corporation Limited
6 */
7
8 #define pr_fmt(fmt) "eiointc: " fmt
9
10 #include <linux/cpuhotplug.h>
11 #include <linux/interrupt.h>
12 #include <linux/irq.h>
13 #include <linux/irqchip.h>
14 #include <linux/irqdomain.h>
15 #include <linux/irqchip/chained_irq.h>
16 #include <linux/kernel.h>
17 #include <linux/syscore_ops.h>
18 #include <asm/numa.h>
19
20 #include "irq-loongson.h"
21
22 #define EIOINTC_REG_NODEMAP 0x14a0
23 #define EIOINTC_REG_IPMAP 0x14c0
24 #define EIOINTC_REG_ENABLE 0x1600
25 #define EIOINTC_REG_BOUNCE 0x1680
26 #define EIOINTC_REG_ISR 0x1800
27 #define EIOINTC_REG_ROUTE 0x1c00
28
29 #define VEC_REG_COUNT 4
30 #define VEC_COUNT_PER_REG 64
31 #define VEC_COUNT (VEC_REG_COUNT * VEC_COUNT_PER_REG)
32 #define VEC_REG_IDX(irq_id) ((irq_id) / VEC_COUNT_PER_REG)
33 #define VEC_REG_BIT(irq_id) ((irq_id) % VEC_COUNT_PER_REG)
34 #define EIOINTC_ALL_ENABLE 0xffffffff
35
36 #define MAX_EIO_NODES (NR_CPUS / CORES_PER_EIO_NODE)
37
38 static int nr_pics;
39
40 struct eiointc_priv {
41 u32 node;
42 u32 vec_count;
43 nodemask_t node_map;
44 cpumask_t cpuspan_map;
45 struct fwnode_handle *domain_handle;
46 struct irq_domain *eiointc_domain;
47 };
48
49 static struct eiointc_priv *eiointc_priv[MAX_IO_PICS];
50
eiointc_enable(void)51 static void eiointc_enable(void)
52 {
53 uint64_t misc;
54
55 misc = iocsr_read64(LOONGARCH_IOCSR_MISC_FUNC);
56 misc |= IOCSR_MISC_FUNC_EXT_IOI_EN;
57 iocsr_write64(misc, LOONGARCH_IOCSR_MISC_FUNC);
58 }
59
cpu_to_eio_node(int cpu)60 static int cpu_to_eio_node(int cpu)
61 {
62 return cpu_logical_map(cpu) / CORES_PER_EIO_NODE;
63 }
64
65 #ifdef CONFIG_SMP
eiointc_set_irq_route(int pos,unsigned int cpu,unsigned int mnode,nodemask_t * node_map)66 static void eiointc_set_irq_route(int pos, unsigned int cpu, unsigned int mnode, nodemask_t *node_map)
67 {
68 int i, node, cpu_node, route_node;
69 unsigned char coremap;
70 uint32_t pos_off, data, data_byte, data_mask;
71
72 pos_off = pos & ~3;
73 data_byte = pos & 3;
74 data_mask = ~BIT_MASK(data_byte) & 0xf;
75
76 /* Calculate node and coremap of target irq */
77 cpu_node = cpu_logical_map(cpu) / CORES_PER_EIO_NODE;
78 coremap = BIT(cpu_logical_map(cpu) % CORES_PER_EIO_NODE);
79
80 for_each_online_cpu(i) {
81 node = cpu_to_eio_node(i);
82 if (!node_isset(node, *node_map))
83 continue;
84
85 /* EIO node 0 is in charge of inter-node interrupt dispatch */
86 route_node = (node == mnode) ? cpu_node : node;
87 data = ((coremap | (route_node << 4)) << (data_byte * 8));
88 csr_any_send(EIOINTC_REG_ROUTE + pos_off, data, data_mask, node * CORES_PER_EIO_NODE);
89 }
90 }
91
92 static DEFINE_RAW_SPINLOCK(affinity_lock);
93
eiointc_set_irq_affinity(struct irq_data * d,const struct cpumask * affinity,bool force)94 static int eiointc_set_irq_affinity(struct irq_data *d, const struct cpumask *affinity, bool force)
95 {
96 unsigned int cpu;
97 unsigned long flags;
98 uint32_t vector, regaddr;
99 struct eiointc_priv *priv = d->domain->host_data;
100
101 raw_spin_lock_irqsave(&affinity_lock, flags);
102
103 cpu = cpumask_first_and_and(&priv->cpuspan_map, affinity, cpu_online_mask);
104 if (cpu >= nr_cpu_ids) {
105 raw_spin_unlock_irqrestore(&affinity_lock, flags);
106 return -EINVAL;
107 }
108
109 vector = d->hwirq;
110 regaddr = EIOINTC_REG_ENABLE + ((vector >> 5) << 2);
111
112 /* Mask target vector */
113 csr_any_send(regaddr, EIOINTC_ALL_ENABLE & (~BIT(vector & 0x1F)),
114 0x0, priv->node * CORES_PER_EIO_NODE);
115
116 /* Set route for target vector */
117 eiointc_set_irq_route(vector, cpu, priv->node, &priv->node_map);
118
119 /* Unmask target vector */
120 csr_any_send(regaddr, EIOINTC_ALL_ENABLE,
121 0x0, priv->node * CORES_PER_EIO_NODE);
122
123 irq_data_update_effective_affinity(d, cpumask_of(cpu));
124
125 raw_spin_unlock_irqrestore(&affinity_lock, flags);
126
127 return IRQ_SET_MASK_OK;
128 }
129 #endif
130
eiointc_index(int node)131 static int eiointc_index(int node)
132 {
133 int i;
134
135 for (i = 0; i < nr_pics; i++) {
136 if (node_isset(node, eiointc_priv[i]->node_map))
137 return i;
138 }
139
140 return -1;
141 }
142
eiointc_router_init(unsigned int cpu)143 static int eiointc_router_init(unsigned int cpu)
144 {
145 int i, bit;
146 uint32_t data;
147 uint32_t node = cpu_to_eio_node(cpu);
148 int index = eiointc_index(node);
149
150 if (index < 0) {
151 pr_err("Error: invalid nodemap!\n");
152 return -1;
153 }
154
155 if ((cpu_logical_map(cpu) % CORES_PER_EIO_NODE) == 0) {
156 eiointc_enable();
157
158 for (i = 0; i < eiointc_priv[0]->vec_count / 32; i++) {
159 data = (((1 << (i * 2 + 1)) << 16) | (1 << (i * 2)));
160 iocsr_write32(data, EIOINTC_REG_NODEMAP + i * 4);
161 }
162
163 for (i = 0; i < eiointc_priv[0]->vec_count / 32 / 4; i++) {
164 bit = BIT(1 + index); /* Route to IP[1 + index] */
165 data = bit | (bit << 8) | (bit << 16) | (bit << 24);
166 iocsr_write32(data, EIOINTC_REG_IPMAP + i * 4);
167 }
168
169 for (i = 0; i < eiointc_priv[0]->vec_count / 4; i++) {
170 /* Route to Node-0 Core-0 */
171 if (index == 0)
172 bit = BIT(cpu_logical_map(0));
173 else
174 bit = (eiointc_priv[index]->node << 4) | 1;
175
176 data = bit | (bit << 8) | (bit << 16) | (bit << 24);
177 iocsr_write32(data, EIOINTC_REG_ROUTE + i * 4);
178 }
179
180 for (i = 0; i < eiointc_priv[0]->vec_count / 32; i++) {
181 data = 0xffffffff;
182 iocsr_write32(data, EIOINTC_REG_ENABLE + i * 4);
183 iocsr_write32(data, EIOINTC_REG_BOUNCE + i * 4);
184 }
185 }
186
187 return 0;
188 }
189
eiointc_irq_dispatch(struct irq_desc * desc)190 static void eiointc_irq_dispatch(struct irq_desc *desc)
191 {
192 int i;
193 u64 pending;
194 bool handled = false;
195 struct irq_chip *chip = irq_desc_get_chip(desc);
196 struct eiointc_priv *priv = irq_desc_get_handler_data(desc);
197
198 chained_irq_enter(chip, desc);
199
200 for (i = 0; i < eiointc_priv[0]->vec_count / VEC_COUNT_PER_REG; i++) {
201 pending = iocsr_read64(EIOINTC_REG_ISR + (i << 3));
202
203 /* Skip handling if pending bitmap is zero */
204 if (!pending)
205 continue;
206
207 /* Clear the IRQs */
208 iocsr_write64(pending, EIOINTC_REG_ISR + (i << 3));
209 while (pending) {
210 int bit = __ffs(pending);
211 int irq = bit + VEC_COUNT_PER_REG * i;
212
213 generic_handle_domain_irq(priv->eiointc_domain, irq);
214 pending &= ~BIT(bit);
215 handled = true;
216 }
217 }
218
219 if (!handled)
220 spurious_interrupt();
221
222 chained_irq_exit(chip, desc);
223 }
224
eiointc_ack_irq(struct irq_data * d)225 static void eiointc_ack_irq(struct irq_data *d)
226 {
227 }
228
eiointc_mask_irq(struct irq_data * d)229 static void eiointc_mask_irq(struct irq_data *d)
230 {
231 }
232
eiointc_unmask_irq(struct irq_data * d)233 static void eiointc_unmask_irq(struct irq_data *d)
234 {
235 }
236
237 static struct irq_chip eiointc_irq_chip = {
238 .name = "EIOINTC",
239 .irq_ack = eiointc_ack_irq,
240 .irq_mask = eiointc_mask_irq,
241 .irq_unmask = eiointc_unmask_irq,
242 #ifdef CONFIG_SMP
243 .irq_set_affinity = eiointc_set_irq_affinity,
244 #endif
245 };
246
eiointc_domain_alloc(struct irq_domain * domain,unsigned int virq,unsigned int nr_irqs,void * arg)247 static int eiointc_domain_alloc(struct irq_domain *domain, unsigned int virq,
248 unsigned int nr_irqs, void *arg)
249 {
250 int ret;
251 unsigned int i, type;
252 unsigned long hwirq = 0;
253 struct eiointc_priv *priv = domain->host_data;
254
255 ret = irq_domain_translate_onecell(domain, arg, &hwirq, &type);
256 if (ret)
257 return ret;
258
259 for (i = 0; i < nr_irqs; i++) {
260 irq_domain_set_info(domain, virq + i, hwirq + i, &eiointc_irq_chip,
261 priv, handle_edge_irq, NULL, NULL);
262 }
263
264 return 0;
265 }
266
eiointc_domain_free(struct irq_domain * domain,unsigned int virq,unsigned int nr_irqs)267 static void eiointc_domain_free(struct irq_domain *domain, unsigned int virq,
268 unsigned int nr_irqs)
269 {
270 int i;
271
272 for (i = 0; i < nr_irqs; i++) {
273 struct irq_data *d = irq_domain_get_irq_data(domain, virq + i);
274
275 irq_set_handler(virq + i, NULL);
276 irq_domain_reset_irq_data(d);
277 }
278 }
279
280 static const struct irq_domain_ops eiointc_domain_ops = {
281 .translate = irq_domain_translate_onecell,
282 .alloc = eiointc_domain_alloc,
283 .free = eiointc_domain_free,
284 };
285
acpi_set_vec_parent(int node,struct irq_domain * parent,struct acpi_vector_group * vec_group)286 static void acpi_set_vec_parent(int node, struct irq_domain *parent, struct acpi_vector_group *vec_group)
287 {
288 int i;
289
290 for (i = 0; i < MAX_IO_PICS; i++) {
291 if (node == vec_group[i].node) {
292 vec_group[i].parent = parent;
293 return;
294 }
295 }
296 }
297
acpi_get_vec_parent(int node,struct acpi_vector_group * vec_group)298 static struct irq_domain *acpi_get_vec_parent(int node, struct acpi_vector_group *vec_group)
299 {
300 int i;
301
302 for (i = 0; i < MAX_IO_PICS; i++) {
303 if (node == vec_group[i].node)
304 return vec_group[i].parent;
305 }
306 return NULL;
307 }
308
eiointc_suspend(void)309 static int eiointc_suspend(void)
310 {
311 return 0;
312 }
313
eiointc_resume(void)314 static void eiointc_resume(void)
315 {
316 eiointc_router_init(0);
317 }
318
319 static struct syscore_ops eiointc_syscore_ops = {
320 .suspend = eiointc_suspend,
321 .resume = eiointc_resume,
322 };
323
pch_pic_parse_madt(union acpi_subtable_headers * header,const unsigned long end)324 static int __init pch_pic_parse_madt(union acpi_subtable_headers *header,
325 const unsigned long end)
326 {
327 struct acpi_madt_bio_pic *pchpic_entry = (struct acpi_madt_bio_pic *)header;
328 unsigned int node = (pchpic_entry->address >> 44) & 0xf;
329 struct irq_domain *parent = acpi_get_vec_parent(node, pch_group);
330
331 if (parent)
332 return pch_pic_acpi_init(parent, pchpic_entry);
333
334 return 0;
335 }
336
pch_msi_parse_madt(union acpi_subtable_headers * header,const unsigned long end)337 static int __init pch_msi_parse_madt(union acpi_subtable_headers *header,
338 const unsigned long end)
339 {
340 struct irq_domain *parent;
341 struct acpi_madt_msi_pic *pchmsi_entry = (struct acpi_madt_msi_pic *)header;
342 int node;
343
344 if (cpu_has_flatmode)
345 node = early_cpu_to_node(eiointc_priv[nr_pics - 1]->node * CORES_PER_EIO_NODE);
346 else
347 node = eiointc_priv[nr_pics - 1]->node;
348
349 parent = acpi_get_vec_parent(node, msi_group);
350
351 if (parent)
352 return pch_msi_acpi_init(parent, pchmsi_entry);
353
354 return 0;
355 }
356
acpi_cascade_irqdomain_init(void)357 static int __init acpi_cascade_irqdomain_init(void)
358 {
359 int r;
360
361 r = acpi_table_parse_madt(ACPI_MADT_TYPE_BIO_PIC, pch_pic_parse_madt, 0);
362 if (r < 0)
363 return r;
364
365 if (cpu_has_avecint)
366 return 0;
367
368 r = acpi_table_parse_madt(ACPI_MADT_TYPE_MSI_PIC, pch_msi_parse_madt, 1);
369 if (r < 0)
370 return r;
371
372 return 0;
373 }
374
eiointc_init(struct eiointc_priv * priv,int parent_irq,u64 node_map)375 static int __init eiointc_init(struct eiointc_priv *priv, int parent_irq,
376 u64 node_map)
377 {
378 int i;
379
380 node_map = node_map ? node_map : -1ULL;
381 for_each_possible_cpu(i) {
382 if (node_map & (1ULL << (cpu_to_eio_node(i)))) {
383 node_set(cpu_to_eio_node(i), priv->node_map);
384 cpumask_or(&priv->cpuspan_map, &priv->cpuspan_map,
385 cpumask_of(i));
386 }
387 }
388
389 priv->eiointc_domain = irq_domain_create_linear(priv->domain_handle,
390 priv->vec_count,
391 &eiointc_domain_ops,
392 priv);
393 if (!priv->eiointc_domain) {
394 pr_err("loongson-extioi: cannot add IRQ domain\n");
395 return -ENOMEM;
396 }
397
398 eiointc_priv[nr_pics++] = priv;
399 eiointc_router_init(0);
400 irq_set_chained_handler_and_data(parent_irq, eiointc_irq_dispatch, priv);
401
402 if (nr_pics == 1) {
403 register_syscore_ops(&eiointc_syscore_ops);
404 cpuhp_setup_state_nocalls(CPUHP_AP_IRQ_EIOINTC_STARTING,
405 "irqchip/loongarch/eiointc:starting",
406 eiointc_router_init, NULL);
407 }
408
409 return 0;
410 }
411
eiointc_acpi_init(struct irq_domain * parent,struct acpi_madt_eio_pic * acpi_eiointc)412 int __init eiointc_acpi_init(struct irq_domain *parent,
413 struct acpi_madt_eio_pic *acpi_eiointc)
414 {
415 int parent_irq, ret;
416 struct eiointc_priv *priv;
417 int node;
418
419 priv = kzalloc(sizeof(*priv), GFP_KERNEL);
420 if (!priv)
421 return -ENOMEM;
422
423 priv->domain_handle = irq_domain_alloc_named_id_fwnode("EIOPIC",
424 acpi_eiointc->node);
425 if (!priv->domain_handle) {
426 pr_err("Unable to allocate domain handle\n");
427 goto out_free_priv;
428 }
429
430 priv->vec_count = VEC_COUNT;
431 priv->node = acpi_eiointc->node;
432
433 parent_irq = irq_create_mapping(parent, acpi_eiointc->cascade);
434
435 ret = eiointc_init(priv, parent_irq, acpi_eiointc->node_map);
436 if (ret < 0)
437 goto out_free_handle;
438
439 if (cpu_has_flatmode)
440 node = early_cpu_to_node(acpi_eiointc->node * CORES_PER_EIO_NODE);
441 else
442 node = acpi_eiointc->node;
443 acpi_set_vec_parent(node, priv->eiointc_domain, pch_group);
444 acpi_set_vec_parent(node, priv->eiointc_domain, msi_group);
445
446 ret = acpi_cascade_irqdomain_init();
447 if (ret < 0)
448 goto out_free_handle;
449
450 return ret;
451
452 out_free_handle:
453 irq_domain_free_fwnode(priv->domain_handle);
454 priv->domain_handle = NULL;
455 out_free_priv:
456 kfree(priv);
457
458 return -ENOMEM;
459 }
460
eiointc_of_init(struct device_node * of_node,struct device_node * parent)461 static int __init eiointc_of_init(struct device_node *of_node,
462 struct device_node *parent)
463 {
464 int parent_irq, ret;
465 struct eiointc_priv *priv;
466
467 priv = kzalloc(sizeof(*priv), GFP_KERNEL);
468 if (!priv)
469 return -ENOMEM;
470
471 parent_irq = irq_of_parse_and_map(of_node, 0);
472 if (parent_irq <= 0) {
473 ret = -ENODEV;
474 goto out_free_priv;
475 }
476
477 ret = irq_set_handler_data(parent_irq, priv);
478 if (ret < 0)
479 goto out_free_priv;
480
481 /*
482 * In particular, the number of devices supported by the LS2K0500
483 * extended I/O interrupt vector is 128.
484 */
485 if (of_device_is_compatible(of_node, "loongson,ls2k0500-eiointc"))
486 priv->vec_count = 128;
487 else
488 priv->vec_count = VEC_COUNT;
489
490 priv->node = 0;
491 priv->domain_handle = of_node_to_fwnode(of_node);
492
493 ret = eiointc_init(priv, parent_irq, 0);
494 if (ret < 0)
495 goto out_free_priv;
496
497 return 0;
498
499 out_free_priv:
500 kfree(priv);
501 return ret;
502 }
503
504 IRQCHIP_DECLARE(loongson_ls2k0500_eiointc, "loongson,ls2k0500-eiointc", eiointc_of_init);
505 IRQCHIP_DECLARE(loongson_ls2k2000_eiointc, "loongson,ls2k2000-eiointc", eiointc_of_init);
506