1 /* 2 * Copyright (C) 2009-2010, Lars-Peter Clausen <lars@metafoo.de> 3 * JZ4740 platform IRQ support 4 * 5 * This program is free software; you can redistribute it and/or modify it 6 * under the terms of the GNU General Public License as published by the 7 * Free Software Foundation; either version 2 of the License, or (at your 8 * option) any later version. 9 * 10 * You should have received a copy of the GNU General Public License along 11 * with this program; if not, write to the Free Software Foundation, Inc., 12 * 675 Mass Ave, Cambridge, MA 02139, USA. 13 * 14 */ 15 16 #include <linux/errno.h> 17 #include <linux/init.h> 18 #include <linux/types.h> 19 #include <linux/interrupt.h> 20 #include <linux/ioport.h> 21 #include <linux/irqchip/ingenic.h> 22 #include <linux/of_address.h> 23 #include <linux/of_irq.h> 24 #include <linux/timex.h> 25 #include <linux/slab.h> 26 #include <linux/delay.h> 27 28 #include <asm/io.h> 29 #include <asm/mach-jz4740/irq.h> 30 31 #include "irqchip.h" 32 33 struct ingenic_intc_data { 34 void __iomem *base; 35 unsigned num_chips; 36 }; 37 38 #define JZ_REG_INTC_STATUS 0x00 39 #define JZ_REG_INTC_MASK 0x04 40 #define JZ_REG_INTC_SET_MASK 0x08 41 #define JZ_REG_INTC_CLEAR_MASK 0x0c 42 #define JZ_REG_INTC_PENDING 0x10 43 #define CHIP_SIZE 0x20 44 45 static irqreturn_t intc_cascade(int irq, void *data) 46 { 47 struct ingenic_intc_data *intc = irq_get_handler_data(irq); 48 uint32_t irq_reg; 49 unsigned i; 50 51 for (i = 0; i < intc->num_chips; i++) { 52 irq_reg = readl(intc->base + (i * CHIP_SIZE) + 53 JZ_REG_INTC_PENDING); 54 if (!irq_reg) 55 continue; 56 57 generic_handle_irq(__fls(irq_reg) + (i * 32) + JZ4740_IRQ_BASE); 58 } 59 60 return IRQ_HANDLED; 61 } 62 63 static void intc_irq_set_mask(struct irq_chip_generic *gc, uint32_t mask) 64 { 65 struct irq_chip_regs *regs = &gc->chip_types->regs; 66 67 writel(mask, gc->reg_base + regs->enable); 68 writel(~mask, gc->reg_base + regs->disable); 69 } 70 71 void ingenic_intc_irq_suspend(struct irq_data *data) 72 { 73 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(data); 74 intc_irq_set_mask(gc, gc->wake_active); 75 } 76 77 void ingenic_intc_irq_resume(struct irq_data *data) 78 { 79 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(data); 80 intc_irq_set_mask(gc, gc->mask_cache); 81 } 82 83 static struct irqaction intc_cascade_action = { 84 .handler = intc_cascade, 85 .name = "SoC intc cascade interrupt", 86 }; 87 88 static int __init ingenic_intc_of_init(struct device_node *node, 89 unsigned num_chips) 90 { 91 struct ingenic_intc_data *intc; 92 struct irq_chip_generic *gc; 93 struct irq_chip_type *ct; 94 struct irq_domain *domain; 95 int parent_irq, err = 0; 96 unsigned i; 97 98 intc = kzalloc(sizeof(*intc), GFP_KERNEL); 99 if (!intc) { 100 err = -ENOMEM; 101 goto out_err; 102 } 103 104 parent_irq = irq_of_parse_and_map(node, 0); 105 if (!parent_irq) { 106 err = -EINVAL; 107 goto out_free; 108 } 109 110 err = irq_set_handler_data(parent_irq, intc); 111 if (err) 112 goto out_unmap_irq; 113 114 intc->num_chips = num_chips; 115 intc->base = of_iomap(node, 0); 116 if (!intc->base) { 117 err = -ENODEV; 118 goto out_unmap_irq; 119 } 120 121 for (i = 0; i < num_chips; i++) { 122 /* Mask all irqs */ 123 writel(0xffffffff, intc->base + (i * CHIP_SIZE) + 124 JZ_REG_INTC_SET_MASK); 125 126 gc = irq_alloc_generic_chip("INTC", 1, 127 JZ4740_IRQ_BASE + (i * 32), 128 intc->base + (i * CHIP_SIZE), 129 handle_level_irq); 130 131 gc->wake_enabled = IRQ_MSK(32); 132 133 ct = gc->chip_types; 134 ct->regs.enable = JZ_REG_INTC_CLEAR_MASK; 135 ct->regs.disable = JZ_REG_INTC_SET_MASK; 136 ct->chip.irq_unmask = irq_gc_unmask_enable_reg; 137 ct->chip.irq_mask = irq_gc_mask_disable_reg; 138 ct->chip.irq_mask_ack = irq_gc_mask_disable_reg; 139 ct->chip.irq_set_wake = irq_gc_set_wake; 140 ct->chip.irq_suspend = ingenic_intc_irq_suspend; 141 ct->chip.irq_resume = ingenic_intc_irq_resume; 142 143 irq_setup_generic_chip(gc, IRQ_MSK(32), 0, 0, 144 IRQ_NOPROBE | IRQ_LEVEL); 145 } 146 147 domain = irq_domain_add_legacy(node, num_chips * 32, JZ4740_IRQ_BASE, 0, 148 &irq_domain_simple_ops, NULL); 149 if (!domain) 150 pr_warn("unable to register IRQ domain\n"); 151 152 setup_irq(parent_irq, &intc_cascade_action); 153 return 0; 154 155 out_unmap_irq: 156 irq_dispose_mapping(parent_irq); 157 out_free: 158 kfree(intc); 159 out_err: 160 return err; 161 } 162 163 static int __init intc_1chip_of_init(struct device_node *node, 164 struct device_node *parent) 165 { 166 return ingenic_intc_of_init(node, 1); 167 } 168 IRQCHIP_DECLARE(jz4740_intc, "ingenic,jz4740-intc", intc_1chip_of_init); 169 170 static int __init intc_2chip_of_init(struct device_node *node, 171 struct device_node *parent) 172 { 173 return ingenic_intc_of_init(node, 2); 174 } 175 IRQCHIP_DECLARE(jz4770_intc, "ingenic,jz4770-intc", intc_2chip_of_init); 176 IRQCHIP_DECLARE(jz4775_intc, "ingenic,jz4775-intc", intc_2chip_of_init); 177 IRQCHIP_DECLARE(jz4780_intc, "ingenic,jz4780-intc", intc_2chip_of_init); 178