1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * Copyright 2017 NXP 4 * Copyright (C) 2018 Pengutronix, Lucas Stach <kernel@pengutronix.de> 5 */ 6 7 #include <linux/clk.h> 8 #include <linux/interrupt.h> 9 #include <linux/irq.h> 10 #include <linux/irqchip/chained_irq.h> 11 #include <linux/irqdomain.h> 12 #include <linux/kernel.h> 13 #include <linux/of.h> 14 #include <linux/of_irq.h> 15 #include <linux/platform_device.h> 16 #include <linux/pm_runtime.h> 17 #include <linux/spinlock.h> 18 19 #define CTRL_STRIDE_OFF(_t, _r) (_t * 4 * _r) 20 #define CHANCTRL 0x0 21 #define CHANMASK(n, t) (CTRL_STRIDE_OFF(t, 0) + 0x4 * (n) + 0x4) 22 #define CHANSET(n, t) (CTRL_STRIDE_OFF(t, 1) + 0x4 * (n) + 0x4) 23 #define CHANSTATUS(n, t) (CTRL_STRIDE_OFF(t, 2) + 0x4 * (n) + 0x4) 24 #define CHAN_MINTDIS(t) (CTRL_STRIDE_OFF(t, 3) + 0x4) 25 #define CHAN_MASTRSTAT(t) (CTRL_STRIDE_OFF(t, 3) + 0x8) 26 27 #define CHAN_MAX_OUTPUT_INT 0x8 28 29 struct irqsteer_data { 30 void __iomem *regs; 31 struct clk *ipg_clk; 32 int irq[CHAN_MAX_OUTPUT_INT]; 33 int irq_count; 34 raw_spinlock_t lock; 35 int reg_num; 36 int channel; 37 struct irq_domain *domain; 38 u32 *saved_reg; 39 struct device *dev; 40 }; 41 42 static int imx_irqsteer_get_reg_index(struct irqsteer_data *data, 43 unsigned long irqnum) 44 { 45 return (data->reg_num - irqnum / 32 - 1); 46 } 47 48 static void imx_irqsteer_irq_unmask(struct irq_data *d) 49 { 50 struct irqsteer_data *data = d->chip_data; 51 int idx = imx_irqsteer_get_reg_index(data, d->hwirq); 52 unsigned long flags; 53 u32 val; 54 55 raw_spin_lock_irqsave(&data->lock, flags); 56 val = readl_relaxed(data->regs + CHANMASK(idx, data->reg_num)); 57 val |= BIT(d->hwirq % 32); 58 writel_relaxed(val, data->regs + CHANMASK(idx, data->reg_num)); 59 raw_spin_unlock_irqrestore(&data->lock, flags); 60 } 61 62 static void imx_irqsteer_irq_mask(struct irq_data *d) 63 { 64 struct irqsteer_data *data = d->chip_data; 65 int idx = imx_irqsteer_get_reg_index(data, d->hwirq); 66 unsigned long flags; 67 u32 val; 68 69 raw_spin_lock_irqsave(&data->lock, flags); 70 val = readl_relaxed(data->regs + CHANMASK(idx, data->reg_num)); 71 val &= ~BIT(d->hwirq % 32); 72 writel_relaxed(val, data->regs + CHANMASK(idx, data->reg_num)); 73 raw_spin_unlock_irqrestore(&data->lock, flags); 74 } 75 76 static void imx_irqsteer_irq_bus_lock(struct irq_data *d) 77 { 78 struct irqsteer_data *data = d->chip_data; 79 80 pm_runtime_get_sync(data->dev); 81 } 82 83 static void imx_irqsteer_irq_bus_sync_unlock(struct irq_data *d) 84 { 85 struct irqsteer_data *data = d->chip_data; 86 87 pm_runtime_put_autosuspend(data->dev); 88 } 89 90 static const struct irq_chip imx_irqsteer_irq_chip = { 91 .name = "irqsteer", 92 .irq_mask = imx_irqsteer_irq_mask, 93 .irq_unmask = imx_irqsteer_irq_unmask, 94 .irq_bus_lock = imx_irqsteer_irq_bus_lock, 95 .irq_bus_sync_unlock = imx_irqsteer_irq_bus_sync_unlock, 96 }; 97 98 static int imx_irqsteer_irq_map(struct irq_domain *h, unsigned int irq, 99 irq_hw_number_t hwirq) 100 { 101 irq_set_status_flags(irq, IRQ_LEVEL); 102 irq_set_chip_data(irq, h->host_data); 103 irq_set_chip_and_handler(irq, &imx_irqsteer_irq_chip, handle_level_irq); 104 105 return 0; 106 } 107 108 static const struct irq_domain_ops imx_irqsteer_domain_ops = { 109 .map = imx_irqsteer_irq_map, 110 .xlate = irq_domain_xlate_onecell, 111 }; 112 113 static int imx_irqsteer_get_hwirq_base(struct irqsteer_data *data, u32 irq) 114 { 115 int i; 116 117 for (i = 0; i < data->irq_count; i++) { 118 if (data->irq[i] == irq) 119 return i * 64; 120 } 121 122 return -EINVAL; 123 } 124 125 static void imx_irqsteer_irq_handler(struct irq_desc *desc) 126 { 127 struct irqsteer_data *data = irq_desc_get_handler_data(desc); 128 int hwirq; 129 int irq, i; 130 131 chained_irq_enter(irq_desc_get_chip(desc), desc); 132 133 irq = irq_desc_get_irq(desc); 134 hwirq = imx_irqsteer_get_hwirq_base(data, irq); 135 if (hwirq < 0) { 136 pr_warn("%s: unable to get hwirq base for irq %d\n", 137 __func__, irq); 138 return; 139 } 140 141 for (i = 0; i < 2; i++, hwirq += 32) { 142 int idx = imx_irqsteer_get_reg_index(data, hwirq); 143 unsigned long irqmap; 144 int pos; 145 146 if (hwirq >= data->reg_num * 32) 147 break; 148 149 irqmap = readl_relaxed(data->regs + 150 CHANSTATUS(idx, data->reg_num)); 151 152 for_each_set_bit(pos, &irqmap, 32) 153 generic_handle_domain_irq(data->domain, pos + hwirq); 154 } 155 156 chained_irq_exit(irq_desc_get_chip(desc), desc); 157 } 158 159 static int imx_irqsteer_probe(struct platform_device *pdev) 160 { 161 struct device_node *np = pdev->dev.of_node; 162 struct irqsteer_data *data; 163 u32 irqs_num; 164 int i, ret; 165 166 data = devm_kzalloc(&pdev->dev, sizeof(*data), GFP_KERNEL); 167 if (!data) 168 return -ENOMEM; 169 170 data->dev = &pdev->dev; 171 data->regs = devm_platform_ioremap_resource(pdev, 0); 172 if (IS_ERR(data->regs)) { 173 dev_err(&pdev->dev, "failed to initialize reg\n"); 174 return PTR_ERR(data->regs); 175 } 176 177 data->ipg_clk = devm_clk_get(&pdev->dev, "ipg"); 178 if (IS_ERR(data->ipg_clk)) 179 return dev_err_probe(&pdev->dev, PTR_ERR(data->ipg_clk), 180 "failed to get ipg clk\n"); 181 182 raw_spin_lock_init(&data->lock); 183 184 ret = of_property_read_u32(np, "fsl,num-irqs", &irqs_num); 185 if (ret) 186 return ret; 187 ret = of_property_read_u32(np, "fsl,channel", &data->channel); 188 if (ret) 189 return ret; 190 191 /* 192 * There is one output irq for each group of 64 inputs. 193 * One register bit map can represent 32 input interrupts. 194 */ 195 data->irq_count = DIV_ROUND_UP(irqs_num, 64); 196 data->reg_num = irqs_num / 32; 197 198 if (IS_ENABLED(CONFIG_PM)) { 199 data->saved_reg = devm_kzalloc(&pdev->dev, 200 sizeof(u32) * data->reg_num, 201 GFP_KERNEL); 202 if (!data->saved_reg) 203 return -ENOMEM; 204 } 205 206 ret = clk_prepare_enable(data->ipg_clk); 207 if (ret) { 208 dev_err(&pdev->dev, "failed to enable ipg clk: %d\n", ret); 209 return ret; 210 } 211 212 /* steer all IRQs into configured channel */ 213 writel_relaxed(BIT(data->channel), data->regs + CHANCTRL); 214 215 data->domain = irq_domain_add_linear(np, data->reg_num * 32, 216 &imx_irqsteer_domain_ops, data); 217 if (!data->domain) { 218 dev_err(&pdev->dev, "failed to create IRQ domain\n"); 219 ret = -ENOMEM; 220 goto out; 221 } 222 irq_domain_set_pm_device(data->domain, &pdev->dev); 223 224 if (!data->irq_count || data->irq_count > CHAN_MAX_OUTPUT_INT) { 225 ret = -EINVAL; 226 goto out; 227 } 228 229 for (i = 0; i < data->irq_count; i++) { 230 data->irq[i] = irq_of_parse_and_map(np, i); 231 if (!data->irq[i]) { 232 ret = -EINVAL; 233 goto out; 234 } 235 236 irq_set_chained_handler_and_data(data->irq[i], 237 imx_irqsteer_irq_handler, 238 data); 239 } 240 241 platform_set_drvdata(pdev, data); 242 243 pm_runtime_set_active(&pdev->dev); 244 pm_runtime_enable(&pdev->dev); 245 246 return 0; 247 out: 248 clk_disable_unprepare(data->ipg_clk); 249 return ret; 250 } 251 252 static void imx_irqsteer_remove(struct platform_device *pdev) 253 { 254 struct irqsteer_data *irqsteer_data = platform_get_drvdata(pdev); 255 int i; 256 257 for (i = 0; i < irqsteer_data->irq_count; i++) 258 irq_set_chained_handler_and_data(irqsteer_data->irq[i], 259 NULL, NULL); 260 261 irq_domain_remove(irqsteer_data->domain); 262 263 clk_disable_unprepare(irqsteer_data->ipg_clk); 264 } 265 266 #ifdef CONFIG_PM 267 static void imx_irqsteer_save_regs(struct irqsteer_data *data) 268 { 269 int i; 270 271 for (i = 0; i < data->reg_num; i++) 272 data->saved_reg[i] = readl_relaxed(data->regs + 273 CHANMASK(i, data->reg_num)); 274 } 275 276 static void imx_irqsteer_restore_regs(struct irqsteer_data *data) 277 { 278 int i; 279 280 writel_relaxed(BIT(data->channel), data->regs + CHANCTRL); 281 for (i = 0; i < data->reg_num; i++) 282 writel_relaxed(data->saved_reg[i], 283 data->regs + CHANMASK(i, data->reg_num)); 284 } 285 286 static int imx_irqsteer_suspend(struct device *dev) 287 { 288 struct irqsteer_data *irqsteer_data = dev_get_drvdata(dev); 289 290 imx_irqsteer_save_regs(irqsteer_data); 291 clk_disable_unprepare(irqsteer_data->ipg_clk); 292 293 return 0; 294 } 295 296 static int imx_irqsteer_resume(struct device *dev) 297 { 298 struct irqsteer_data *irqsteer_data = dev_get_drvdata(dev); 299 int ret; 300 301 ret = clk_prepare_enable(irqsteer_data->ipg_clk); 302 if (ret) { 303 dev_err(dev, "failed to enable ipg clk: %d\n", ret); 304 return ret; 305 } 306 imx_irqsteer_restore_regs(irqsteer_data); 307 308 return 0; 309 } 310 #endif 311 312 static const struct dev_pm_ops imx_irqsteer_pm_ops = { 313 SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, 314 pm_runtime_force_resume) 315 SET_RUNTIME_PM_OPS(imx_irqsteer_suspend, 316 imx_irqsteer_resume, NULL) 317 }; 318 319 static const struct of_device_id imx_irqsteer_dt_ids[] = { 320 { .compatible = "fsl,imx-irqsteer", }, 321 {}, 322 }; 323 324 static struct platform_driver imx_irqsteer_driver = { 325 .driver = { 326 .name = "imx-irqsteer", 327 .of_match_table = imx_irqsteer_dt_ids, 328 .pm = &imx_irqsteer_pm_ops, 329 }, 330 .probe = imx_irqsteer_probe, 331 .remove_new = imx_irqsteer_remove, 332 }; 333 builtin_platform_driver(imx_irqsteer_driver); 334